CN105977266A - TFT substrate and manufacturing method thereof - Google Patents
TFT substrate and manufacturing method thereof Download PDFInfo
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- CN105977266A CN105977266A CN201610566026.1A CN201610566026A CN105977266A CN 105977266 A CN105977266 A CN 105977266A CN 201610566026 A CN201610566026 A CN 201610566026A CN 105977266 A CN105977266 A CN 105977266A
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- data wire
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
Abstract
The invention provides a TFT substrate and a manufacturing method thereof. According to the manufacturing method of the TFT substrate, data lines, grid lines and a grid electrode are manufactured at the same layer so that a photomask can be saved, and multiple through holes and pixel electrodes in the TFT substrate are formed by adopting a halftone photomask so that a photomask can be saved, and thus two photomasks can be saved in comparison with the methods in the prior art, production cost can be reduced, manufacturing process time can be saved, the production efficiency can be enhanced, and no electrical damage is generated on a semiconductor layer in the manufacturing process. The TFT substrate is simple in manufacturing process and low in production cost and has great electrical properties.
Description
Technical field
The present invention relates to thin-film transistor technologies field, particularly relate to a kind of TFT substrate and preparation method thereof.
Background technology
Thin film transistor (TFT) (Thin Film Transistor is called for short TFT) is current liquid crystal indicator (Liquid
Crystal Display, is called for short LCD) and active matrix drive type organic electroluminescence display device and method of manufacturing same (Active
Matrix Organic Light-Emitting Diode, be called for short AMOLED) in main driving element, directly
Connect the developing direction being related to high performance flat display device.
Oxide semiconductor (Oxide Semiconductor), owing to having higher electron mobility, has
There is non crystalline structure, higher with non-crystalline silicon process compatibility, thus obtained widely in thin film transistor (TFT)
Application.The conduction band of oxide semiconductor thin-film transistor is to be formed by the S track of metal ion is overlapping, oxidation
The crystal formation (polycrystalline or amorphous) of thing quasiconductor is little on the impact of mobility.At present, oxide is partly led
Body thin film transistor commercially has extremely strong competitiveness, it could even be possible to replace current mainstream technology-
Silicon-based film transistor technology.
At present, the common structure of oxide semiconductor thin-film transistor is for having etch stop layer (Etching
Stop Layer, ESL) structure, but this structure itself exist some problems, as etching homogeneity be difficult to
Controlling, need to add one light shield and lithographic process, grid overlaps with source/drain, and storage electric capacity is relatively big,
It is difficult to reach high-resolution etc..
Relative to etching barrier layer structure, back of the body channel etching (Back Channel Etch, BCE) structure tool
There are the advantages such as preparation technology is simple, it has also become one of important technology method preparing oxide thin film transistor,
But in back of the body channel etching processing procedure, semiconductor layer can be damaged by source/drain etching at present, and impact electrically and is made
Journey is relatively complicated.
Summary of the invention
It is an object of the invention to provide the manufacture method of a kind of TFT substrate, it is possible to decrease production cost, save
Processing time, improves and semiconductor layer will not cause in production efficiency, and processing procedure electrically damage.
The present invention also aims to provide a kind of TFT substrate, processing procedure is simple, and production cost is low, and has
Good electric property.
For achieving the above object, present invention firstly provides the manufacture method of a kind of TFT substrate, including as follows
Step:
Step 1, provide a substrate, deposit a metal level on the substrate, use one light shield to described
Metal level is patterned process, obtains data wire, gate line and is connected to the grid of gate line side,
Described data wire intersects with gate line, and described gate line disconnects at infall, and the two ends of disconnection are respectively
It is positioned at the both sides of described data wire；
Step 2, on described data wire, gate line, grid and substrate depositing insulating layer, described absolutely
Form semiconductor layer in edge layer, use one light shield that described semiconductor layer is patterned process, obtain
Corresponding to the active layer above grid；
Step 3, on described active layer and insulating barrier formed passivation layer, on described passivation layer formed light
Resistance layer, uses one halftone mask be exposed described photoresist layer and develop, at described photoresist layer
Upper formation the first through hole, the second through hole, third through-hole, fourth hole and fifth hole, described first
Through hole is corresponding to the position of described active layer close on described data wire, described second through hole and third through-hole
Correspond respectively on described active layer on side and the described active layer of described data wire away from described number
According to the side of line, described fourth hole and fifth hole correspond respectively to the two ends that described gate line disconnects；
Formed on described photoresist layer simultaneously the first coating region, the second coating region and the 3rd coating region,
And the thick-layer region in addition to described first coating region, the second coating region and the 3rd coating region,
Described first coating region is between described first through hole and the second through hole；Described second coating region position
In the side of described third through-hole, described 3rd coating region be positioned at described fourth hole and fifth hole it
Between；
Step 4, along described first through hole, the second through hole, third through-hole, fourth hole and fifth hole
Described insulating barrier and passivation layer are carried out dry etch process, described insulating barrier with passivation layer is formed and is positioned at
On described data wire near described active layer position above the first via and be positioned at described gate line break
The 4th via above the two ends opened and the 5th via, formed on described passivation layer and be positioned at described active layer
Go up the second via above described data wire side and be positioned on described active layer away from described number
According to the 3rd via above line side；
Step 5, described photoresist layer is carried out ashing process, remove the first coating region on described photoresist layer,
Second coating region and the 3rd coating region, and thinning thick-layer region；At remaining photoresist layer and passivation layer
Upper formation conductive film；
Step 6, peel off remaining photoresist layer, remove simultaneously and be positioned at the conductive film above described photoresist layer,
The conductive film retained includes the first conductive tie layers, the second conductive tie layers and pixel electrode；
Described first conductive tie layers is connected to described data by described first via and the second via respectively
Line and active layer, described second conductive tie layers is connected to by described 4th via and the 5th via respectively
The two ends that described gate line disconnects, described pixel electrode is connected to described active layer by described 3rd via.
In described step 2, the material of described semiconductor layer is metal-oxide semiconductor (MOS)；In described step 5,
The material of described conductive film is transparent conductive metal oxide or Graphene.
The present invention also provides for a kind of TFT substrate, the data wire including substrate, being located on described substrate, grid
Polar curve and grid, the insulating barrier being located on described data wire, gate line, grid and substrate, it is located at
On described insulating barrier and corresponding to the active layer above described grid, it is located at described active layer and insulating barrier
On passivation layer and the first conductive tie layers being located on described passivation layer, the second conductive tie layers,
And pixel electrode；
Described grid is connected to gate line side, and described data wire intersects with gate line, and described grid
Line disconnects at infall, and the two ends of disconnection lay respectively at the both sides of described data wire；
Described insulating barrier and passivation layer are provided with and are positioned on described data wire on the position of described active layer
Side the first via and lay respectively at described gate line disconnect two ends above the 4th via and five faults in diagnosis and treatment
Hole, described passivation layer is provided with the second mistake being positioned on described active layer above described data wire side
Hole and be positioned on described active layer the 3rd via above away from described data wire side；
Described first conductive tie layers is connected to described data by described first via and the second via respectively
Line and active layer, described second conductive tie layers is connected to by described 4th via and the 5th via respectively
The two ends that described gate line disconnects, described pixel electrode is connected to described active layer by described 3rd via.
The material of described active layer is metal-oxide semiconductor (MOS)；Described first conductive tie layers, second lead
The material of electric connection layer and pixel electrode is transparent conductive metal oxide or Graphene.
The present invention also provides for the manufacture method of another kind of TFT substrate, comprises the steps:
Step 1, provide a substrate, deposit a metal level on the substrate, use one light shield to described
Metal level is patterned process, obtains data wire, gate line and is connected to the grid of gate line side,
Described data wire intersects with gate line, and described data wire disconnects at infall, and the two ends of disconnection are respectively
It is positioned at the both sides of described gate line；
Step 2, on described data wire, gate line, grid and substrate depositing insulating layer, described absolutely
Form semiconductor layer in edge layer, use one light shield that described semiconductor layer is patterned process, obtain
Corresponding to the active layer above grid；
Step 3, on described active layer and insulating barrier formed passivation layer, on described passivation layer formed light
Resistance layer, uses one halftone mask be exposed described photoresist layer and develop, at described photoresist layer
Upper formation the first through hole, the second through hole, third through-hole, fourth hole and fifth hole, described first
Through hole is corresponding to the position of described active layer close on described data wire, described second through hole and third through-hole
Correspond respectively on described active layer on side and the described active layer of described data wire away from described number
According to the side of line, described fourth hole and fifth hole correspond respectively to the two ends that described data wire disconnects；
Formed on described photoresist layer simultaneously the first coating region, the second coating region and the 3rd coating region,
And the thick-layer region in addition to described first coating region, the second coating region and the 3rd coating region,
Described first coating region is between described first through hole and the second through hole；Described second coating region position
In the side of described third through-hole, described 3rd coating region be positioned at described fourth hole and fifth hole it
Between；
Step 4, along described first through hole, the second through hole, third through-hole, fourth hole and fifth hole
Described insulating barrier and passivation layer are carried out dry etch process, described insulating barrier with passivation layer is formed and is positioned at
On described data wire near described active layer position above the first via and be positioned at described data wire break
The 4th via above the two ends opened and the 5th via, formed on described passivation layer and be positioned at described active layer
Go up the second via above described data wire side and be positioned on described active layer away from described number
According to the 3rd via above line side；
Step 5, described photoresist layer is carried out ashing process, remove described photoresist layer the first coating region,
Second coating region and the 3rd coating region, and thinning thick-layer region；At remaining photoresist layer and passivation layer
Upper formation conductive film；
Step 6, peel off remaining photoresist layer, remove simultaneously and be positioned at the conductive film above described photoresist layer,
The conductive film retained includes the first conductive tie layers, the second conductive tie layers and pixel electrode；
Described first conductive tie layers is connected to described data by described first via and the second via respectively
Line and active layer, described second conductive tie layers is connected to by described 4th via and the 5th via respectively
The two ends that described data wire disconnects, described pixel electrode is connected to described active layer by described 3rd via.
In described step 2, the material of described semiconductor layer is metal-oxide semiconductor (MOS)；In described step 5,
The material of described conductive film is transparent conductive metal oxide or Graphene.
Described first via and the 5th via are same via, described first conductive tie layers and the second conduction
Articulamentum is connected.
The present invention also provides for another kind of TFT substrate, the data wire including substrate, being located on described substrate,
Gate line and grid, the insulating barrier being located on described data wire, gate line, grid and substrate, set
On described insulating barrier and corresponding to the active layer above described grid, it is located at described active layer and insulation
Passivation layer on layer and the first conductive tie layers being located on described passivation layer, the second conductive tie layers,
And pixel electrode；
Described grid is connected to gate line side, and described data wire intersects with gate line, and described data
Line disconnects at infall, and the two ends of disconnection lay respectively at the both sides of described gate line；
Described insulating barrier and passivation layer are provided with and are positioned at described data wire above the position of described active layer
The first via and lay respectively at described data wire disconnect two ends above the 4th via and the 5th via,
Described passivation layer be provided be positioned on described active layer above the described data wire side the second via,
And it is positioned on described active layer the 3rd via above away from described data wire side；
Described first conductive tie layers is connected to described data by described first via and the second via respectively
Line and active layer, described second conductive tie layers is connected to by described 4th via and the 5th via respectively
The two ends that described data wire disconnects, described pixel electrode is connected to described active layer by described 3rd via.
The material of described active layer is metal-oxide semiconductor (MOS)；Described first conductive tie layers, second lead
The material of electric connection layer and pixel electrode is transparent conductive metal oxide or Graphene.
Described first via and the 5th via are same via, described first conductive tie layers and the second conduction
Articulamentum is connected.
Beneficial effects of the present invention: the manufacture method of a kind of TFT substrate that the present invention provides, by by data
Line, gate line and fabrication, in same layer, can save one light shield, by using one halftoning light
Multiple vias in hood-shaped one-tenth TFT substrate and pixel electrode, can save one light shield, thus and prior art
Comparing, the present invention can save twice light shield, reduces production cost, saves processing time, improves and produces effect
Semiconductor layer will not be caused electrically damage by rate, and processing procedure.A kind of TFT substrate that the present invention provides, system
Journey is simple, and production cost is low, and has good electric property.
In order to be able to be further understood that inventive feature and technology contents, refer to below in connection with the present invention
Detailed description and accompanying drawing, but accompanying drawing only provide with reference to and explanation use, not be used for the present invention is limited
System.
Accompanying drawing explanation
Below in conjunction with the accompanying drawings, by the detailed description of the invention of the present invention is described in detail, the skill of the present invention will be made
Art scheme and other beneficial effect are apparent.
In accompanying drawing,
Fig. 1 is the flow chart of the manufacture method of the first TFT substrate of the present invention；
Fig. 2-3 is the schematic diagram of the step 1 of the manufacture method of the first TFT substrate of the present invention, and Fig. 3
For profile along line A-A in Fig. 2；
Fig. 4-5 is the schematic diagram of the step 2 of the manufacture method of the first TFT substrate of the present invention, and Fig. 5
For profile along line A-A in Fig. 4；
Fig. 6-7 is the schematic diagram of the step 3 of the manufacture method of the first TFT substrate of the present invention；
Fig. 8-9 is the schematic diagram of step 4-5 of the manufacture method of the first TFT substrate of the present invention；
Figure 10-12 be the schematic diagram of the step 6 of the manufacture method of the first TFT substrate of the present invention and this
The structural representation of the first bright TFT substrate, and Figure 11 is profile along line A-A in Figure 10,
Figure 12 is the profile in Figure 10 along line B-B；
Figure 13 is the flow chart of the manufacture method of the second TFT substrate of the present invention；
Figure 14-15 is the schematic diagram of the step 1 of the manufacture method of the second TFT substrate of the present invention, and figure
15 is the profile in Figure 14 along A '-A ' line；
Figure 16-17 is the schematic diagram of the step 2 of the manufacture method of the second TFT substrate of the present invention, and figure
17 is the profile in Figure 16 along A '-A ' line；
Figure 18-19 is the schematic diagram of the step 3 of the manufacture method of the second TFT substrate of the present invention；
Figure 20-21 is the schematic diagram of step 4-5 of the manufacture method of the second TFT substrate of the present invention；
Figure 22-24 be the schematic diagram of the step 6 of the manufacture method of the second TFT substrate of the present invention and this
The structural representation of bright the second TFT substrate, and Figure 23 is profile along A '-A ' line in Figure 22,
Figure 24 is the profile in Figure 22 along B '-B ' line；
Figure 25 is a preferred embodiment of the step 6 of the manufacture method of the second TFT substrate of the present invention
Schematic diagram.
Detailed description of the invention
By further illustrating the technological means and effect thereof that the present invention taked, below in conjunction with the present invention's
Preferred embodiment and accompanying drawing thereof are described in detail.
Refer to Fig. 1, present invention firstly provides the manufacture method of a kind of TFT substrate, comprise the steps:
Step 1, refer to Fig. 2-3, it is provided that a substrate 10, described substrate 10 deposit a metal level 11,
Use one light shield that described metal level 11 is patterned process, obtain data wire 21, gate line 22 and
Being connected to the grid 23 of gate line 22 side, described data wire 21 intersects with gate line 22, and described grid
Line 22 disconnects at infall, and the two ends of disconnection lay respectively at the both sides of described data wire 21.
Concrete, described substrate 10 is glass substrate.
Concrete, described metal level 11 is single metal layer or multiple layer metal lamination.Preferably, described gold
Belong to composite bed or molybdenum layer and titanium (Ti) that layer 11 is single molybdenum (Mo) layer, molybdenum layer and aluminum (Al) layer
The composite bed of layer.
Step 2, refer to Fig. 4-5, on described data wire 21, gate line 22, grid 23 and substrate 10
Depositing insulating layer 40, forms semiconductor layer 31 on described insulating barrier 40, uses one light shield partly to lead described
Body layer 31 is patterned process, obtains the active layer 30 above corresponding to grid 23.
Concrete, in described step 2, the material of described semiconductor layer 31 is metal-oxide semiconductor (MOS), institute
Stating step 2 uses method for sputtering to form semiconductor layer 31.Preferably, described metal-oxide semiconductor (MOS) includes
Indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc tin oxide
(IGZTO) one in.
Concrete, the material of described insulating barrier 40 includes silicon oxide (SiOx) and silicon nitride (SiNxIn)
At least one.
Step 3, refer to Fig. 6-7, described active layer 30 and insulating barrier 40 are formed passivation layer 50,
Form photoresist layer 60 on described passivation layer 50, use one halftone mask that described photoresist layer 60 is exposed
Light and development, described photoresist layer 60 is formed first through hole the 61, second through hole 62, third through-hole 63,
Fourth hole 64 and fifth hole 65, described first through hole 61 is corresponding to close described on described data wire 21
The position of active layer 30, described second through hole 62 and third through-hole 63 correspond respectively to lean on described active layer 30
Away from the side of described data wire 21 on the side of nearly described data wire 21 and described active layer 30, the described 4th
Through hole 64 and fifth hole 65 correspond respectively to the two ends that described gate line 22 disconnects；
On described photoresist layer 60, form the first coating region the 71, second coating region 72 and the 3rd thin layer simultaneously
Region 73 and in addition to described first coating region the 71, second coating region 72 and the 3rd coating region 73
Thick-layer region 75, described first coating region 71 is between described first through hole 61 and the second through hole 62；
Described second coating region 72 is positioned at the side of described third through-hole 63, and described 3rd coating region 73 is positioned at institute
State between fourth hole 64 and fifth hole 65.
Concrete, the material of described passivation layer 50 includes silicon oxide and at least one in silicon nitride.
Step 4, refer to Fig. 8-9, along described first through hole the 61, second through hole 62, third through-hole 63,
Four through holes 64 and fifth hole 65 carry out dry etch process, described to described insulating barrier 40 with passivation layer 50
Formed on the position being positioned on described data wire 21 close described active layer 30 on insulating barrier 40 and passivation layer 50
Side the first via 51 and be positioned at described gate line 22 disconnect two ends above the 4th via 54 and five faults in diagnosis and treatment
Hole 55, is formed on described passivation layer 50 and is positioned on described active layer 30 above described data wire 21 side
The second via 52 and be positioned on described active layer 30 the 3rd mistake above away from described data wire 21 side
Hole 53.
Concrete, the etching gas that the dry ecthing procedure of described step 4 uses includes sulfur hexafluoride (SF6) with
Oxygen (O2)。
Step 5, refer to Fig. 8-9, described photoresist layer 60 is carried out ashing process, removes described photoresist layer 60
The first coating region the 71, second coating region 72 and the 3rd coating region 73, and thinning thick-layer region 75；
Remaining photoresist layer 60 and passivation layer 50 are formed conductive film 80.
Concrete, described step 5 uses oxygen that described photoresist layer 60 is carried out ashing process.
Preferably, in described step 5, the material of described conductive film 80 be transparent conductive metal oxide or
Graphene, preferably Graphene.
Step 6, refer to Figure 10-12, peel off remaining photoresist layer 60, remove simultaneously and be positioned at described photoresist layer
Conductive film 80 above in the of 60, the conductive film 80 of reservation includes that the first conductive tie layers 81, second conducts electricity even
Connect layer 82 and pixel electrode 83；
Described first conductive tie layers 81 is connected to institute by described first via 51 and the second via 52 respectively
Stating data wire 21 and active layer 30, described second conductive tie layers 82 is respectively by described 4th via 54 and the
Five vias 55 are connected to the two ends that described gate line 22 disconnects, and described pixel electrode 83 is by described 3rd via
53 are connected to described active layer 30.
Concrete, in described step 6, the method peeling off remaining photoresist layer 60 is: use organic solvent pair
Photoresist layer 60 dissolves, and removes and be positioned at the conductive thin above described photoresist layer 60 while stripping resistance layer 60
Film 80.Preferably, described organic solvent includes monoethanolamine (MEA) and dimethyl sulfoxide (DMSO),
Described monoethanolamine is 7:3 with the mass ratio of dimethyl sulfoxide.
Concrete, in described step 6, described first conductive tie layers 81 achieves described data wire 21 and has
The setting connecting and eliminating source electrode of active layer 30；Described second conductive tie layers 82 achieves described gate line
The connection at 22 two ends disconnected so that gate line 22 and data wire 21 may be located at same layer and non-phase mutual connection
Touch, therefore can be formed in same processing procedure, reduce production cost；Described pixel electrode 83 is direct with described
Semiconductor layer 31 is connected, and eliminates the setting of drain electrode.
The manufacture method of above-mentioned TFT substrate, by by data wire, gate line and fabrication in same layer,
One light shield can be saved, by using one halftone mask to form the multiple vias in TFT substrate and pixel
Electrode, can save one light shield, thus compared with prior art, the present invention can save twice light shield, fall
Low production cost, saves processing time, improves in production efficiency, and processing procedure and semiconductor layer will not be caused electricity
Property damage.
Referring to Figure 10-12, manufacture method based on above-mentioned TFT substrate, the present invention also provides for a kind of TFT base
Plate, the data wire 21 including substrate 10, being located on described substrate 10, gate line 22 and grid 23, is located at
Insulating barrier 40 on described data wire 21, gate line 22, grid 23 and substrate 10, it is located at described insulating barrier
On 40 and corresponding to the active layer 30 above described grid 23, it is located at described active layer 30 and insulating barrier 40
On passivation layer 50 and the first conductive tie layers 81 being located on described passivation layer 50, second be conductively connected
Layer 82 and pixel electrode 83；
Described grid 23 is connected to gate line 22 side, and described data wire 21 intersects with gate line 22, and institute
Stating gate line 22 to disconnect at infall, the two ends of disconnection lay respectively at the both sides of described data wire 21；
Described insulating barrier 40 is provided with passivation layer 50 and is positioned on described data wire 21 near described active layer 30
Position above the first via 51 and lay respectively at described gate line 22 disconnect two ends above the 4th mistake
Hole 54 and the 5th via 55, described passivation layer 50 is provided with and is positioned on described active layer 30 near described data wire
The second via 52 above 21 sides and being positioned on described active layer 30 away from described data wire 21 side
3rd via 53 of side；
Described first conductive tie layers 81 is connected to institute by described first via 51 and the second via 52 respectively
Stating data wire 21 and active layer 30, described second conductive tie layers 82 is respectively by described 4th via 54 and the
Five vias 55 are connected to the two ends that described gate line 22 disconnects, and described pixel electrode 83 is by described 3rd via
53 are connected to described active layer 30.
Concrete, described substrate 10 is glass substrate.
Concrete, described data wire 21, gate line 22 and grid 23 are single metal layer or multiple layer metal
Lamination.Preferably, described data wire 21, gate line 22 and grid 23 are monolayer molybdenum layer, molybdenum layer and aluminium lamination
Composite bed or the composite bed of molybdenum layer and titanium layer.
Concrete, the material of described active layer 30 is metal-oxide semiconductor (MOS).Preferably, described metal oxygen
Compound quasiconductor includes the one in indium gallium zinc oxide, indium zinc oxide, zinc oxide, indium gallium zinc tin oxide.
Concrete, described first conductive tie layers the 81, second conductive tie layers 82 and the material of pixel electrode 83
Material is transparent conductive metal oxide or Graphene, preferably Graphene.
Concrete, the material of described insulating barrier 40 and passivation layer 50 all includes in silicon oxide and silicon nitride at least
A kind of.
Referring to Figure 13, the present invention also provides for the manufacture method of another kind of TFT substrate, comprises the steps:
Step 1, refer to Figure 14-15, it is provided that a substrate 10 ', at described substrate 10 ' upper deposition one metal level
11 ', use one light shield that described metal level 11 ' is patterned process, obtain data wire 21 ', gate line
22 ' and be connected to the grid 23 ' of gate line 22 ' side, described data wire 21 ' intersects with gate line 22 ',
And described data wire 21 ' disconnects at infall, the two ends of disconnection lay respectively at the both sides of described gate line 22 '.
Concrete, described substrate 10 ' is glass substrate.
Concrete, described metal level 11 ' is single metal layer or multiple layer metal lamination.Preferably, described
Metal level 11 ' is the composite bed of monolayer molybdenum layer, the composite bed of molybdenum layer and aluminium lamination or molybdenum layer and titanium layer.
Step 2, refer to Figure 16-17, at described data wire 21 ', gate line 22 ', grid 23 ' and substrate
10 ' upper depositing insulating layers 40 ', at described insulating barrier 40 ' upper formation semiconductor layer 31 ', use one light shield pair
Described semiconductor layer 31 ' is patterned process, obtains the active layer 30 ' corresponding to grid 23 ' top.
Concrete, in described step 2, the material of described semiconductor layer 31 ' is metal-oxide semiconductor (MOS), institute
Stating step 2 uses method for sputtering to form semiconductor layer 31 '.Preferably, described metal-oxide semiconductor (MOS) includes
One in indium gallium zinc oxide, indium zinc oxide, zinc oxide, indium gallium zinc tin oxide.
Concrete, the material of described insulating barrier 40 ' includes silicon oxide and at least one in silicon nitride.
Step 3, refer to Figure 18-19, at described active layer 30 ' and insulating barrier 40 ' is upper forms passivation layer 50 ',
At described passivation layer 50 ' upper formation photoresist layer 60 ', use one halftone mask that described photoresist layer 60 ' is carried out
Exposure and development, at described photoresist layer 60 ' upper formation the first through hole 61 ', the second through hole 62 ', third through-hole
63 ', fourth hole 64 ' and fifth hole 65 ', described first through hole 61 ' is corresponding on described data wire 21 '
Near the position of described active layer 30 ', described second through hole 62 ' and third through-hole 63 ' correspond respectively to described in have
Away from described data wire 21 ' on the upper side near described data wire 21 ' of active layer 30 ' and described active layer 30 '
Side, described fourth hole 64 ' corresponds respectively to, with fifth hole 65 ', the two ends that described data wire 21 ' disconnects；
Simultaneously thin with the 3rd at upper the first coating region 71 ', the second coating region 72 ' of being formed of described photoresist layer 60 '
Layer region 73 ' and except described first coating region 71 ', the second coating region 72 ' and the 3rd coating region 73 '
Thick-layer region 75 ' in addition, described first coating region 71 ' is positioned at described first through hole 61 ' and the second through hole
Between 62 '；Described second coating region 72 ' is positioned at the side of described third through-hole 63 ', described 3rd thin layer district
Territory 73 ' is positioned between described fourth hole 64 ' and fifth hole 65 '.
Concrete, the material of described passivation layer 50 ' includes silicon oxide and at least one in silicon nitride.
Step 4, refer to Figure 20-21, along described first through hole 61 ', the second through hole 62 ', third through-hole 63 ',
Fourth hole 64 ' and fifth hole 65 ' carry out dry etch process to described insulating barrier 40 ' with passivation layer 50 ',
It is positioned at described data wire 21 ' upper near described active layer 30 ' in the formation upper with passivation layer 50 ' of described insulating barrier 40 '
Position above the first via 51 ' and be positioned at the 4th via above the two ends that described data wire 21 ' disconnects
54 ' and the 5th via 55 ', it is positioned at described active layer 30 ' in the described upper formation of passivation layer 50 ' upper near described number
According to the second via 52 ' above line 21 ' side and be positioned on described active layer 30 ' away from described data wire
The 3rd via 53 ' above 21 ' sides.
Concrete, the etching gas that the dry ecthing procedure of described step 4 uses includes sulfur hexafluoride and oxygen.
Step 5, refer to Figure 20-21, described photoresist layer 60 ' is carried out ashing process, removes described photoresistance
First coating region 71 ', the second coating region 72 ' and the 3rd coating region 73 ' of layer 60 ', and thinning thick-layer
Region 75 '；At remaining photoresist layer 60 ' and passivation layer 50 ' upper formation conductive film 80 '.
Concrete, described step 5 uses oxygen that described photoresist layer 60 ' is carried out ashing process.
Concrete, in described step 5, the material of described conductive film 80 ' be transparent conductive metal oxide or
Graphene, preferably Graphene.
Step 6, refer to Figure 22-24, peel off remaining photoresist layer 60 ', remove simultaneously and be positioned at described photoresistance
Layer 60 ' top conductive film 80 ', the conductive film 80 ' of reservation include the first conductive tie layers 81 ', second
Conductive tie layers 82 ' and pixel electrode 83 '；
Described first conductive tie layers 81 ' is connected to the second via 52 ' by described first via 51 ' respectively
Described data wire 21 ' and active layer 30 ', described second conductive tie layers 82 ' is respectively by described 4th via
54 ' and the 5th via 55 ' be connected to the two ends that described data wire 21 ' disconnects, described pixel electrode 83 ' passes through institute
State the 3rd via 53 ' and be connected to described active layer 30 '.
Concrete, in described step 6, the method peeling off remaining photoresist layer 60 ' is: use organic solvent pair
Photoresist layer 60 ' dissolves, and removes the conduction being positioned at described photoresist layer 60 ' top while stripping resistance layer 60 '
Thin film 80 '.Preferably, described organic solvent includes monoethanolamine and dimethyl sulfoxide, described monoethanolamine
It is 7:3 with the mass ratio of dimethyl sulfoxide.
Concrete, in described step 6, described first conductive tie layers 81 ' achieve described data wire 21 ' with
The setting connecting and eliminating source electrode of active layer 30 '；Described second conductive tie layers 82 ' achieves described number
Connection according to the two ends that line 21 ' disconnects so that gate line 22 ' may be located at same layer and non-phase with data wire 21 '
Contact, therefore can be formed in same processing procedure mutually, reduces production cost；Described pixel electrode 83 ' is directly
It is connected with described active layer 30 ', eliminates the setting of drain electrode.
Preferably, as shown in figure 25, described first via 51 ' and the 5th via 55 ' they are same via, due to
Described first conductive tie layers 81 ' and the second conductive tie layers 82 ' are respectively by the first via 51 ' and the 5th
Via 55 ' is connected with data wire 21 ', therefore, and described first conductive tie layers 81 ' and the second conductive tie layers
82 ' are connected.
The manufacture method of above-mentioned TFT substrate, by by data wire, gate line and fabrication in same layer,
One light shield can be saved, by using one halftone mask to form the multiple vias in TFT substrate and pixel
Electrode, can save one light shield, thus compared with prior art, the present invention can save twice light shield, fall
Low production cost, saves processing time, improves in production efficiency, and processing procedure and semiconductor layer will not be caused electricity
Property damage.
Referring to Figure 22-25, manufacture method based on above-mentioned TFT substrate, the present invention also provides for a kind of TFT base
Plate, the data wire 21 ' including substrate 10 ', being located on described substrate 10 ', gate line 22 ' and grid 23 ',
It is located at the insulating barrier 40 ' on described data wire 21 ', gate line 22 ', grid 23 ' and substrate 10 ', is located at institute
State that insulating barrier 40 ' is upper and active layer 30 ' corresponding to described grid 23 ' top, be located at described active layer 30 ',
And passivation layer 50 ' on insulating barrier 40 ' and the first conductive tie layers 81 ' being located on described passivation layer 50 ',
Second conductive tie layers 82 ' and pixel electrode 83 '；
Described grid 23 ' is connected to gate line 22 ' side, and described data wire 21 ' intersects with gate line 22 ',
And described data wire 21 ' disconnects at infall, the two ends of disconnection lay respectively at the both sides of described gate line 22 '；
Described insulating barrier 40 ' is provided with passivation layer 50 ' and is positioned at described data wire 21 ' near described active layer 30 '
Position above the first via 51 ' and lay respectively at the 4th above the two ends that described data wire 21 ' disconnects
Via 54 ' and the 5th via 55 ', described passivation layer 50 ' is provided with and is positioned at described active layer 30 ' above near described
The second via 52 ' above data wire 21 ' side and being positioned on described active layer 30 ' away from described data
The 3rd via 53 ' above line 21 ' side；
Described first conductive tie layers 81 ' is connected to the second via 52 ' by described first via 51 ' respectively
Described data wire 21 ' and active layer 30 ', described second conductive tie layers 82 ' is respectively by described 4th via
54 ' and the 5th via 55 ' be connected to the two ends that described data wire 21 ' disconnects, described pixel electrode 83 ' passes through institute
State the 3rd via 53 ' and be connected to described active layer 30 '.
Concrete, described substrate 10 ' is glass substrate.
Concrete, described data wire 21 ', gate line 22 ' and grid 23 ' they are single metal layer or multilamellar gold
Belong to lamination.Preferably, described data wire 21 ', gate line 22 ' and grid 23 ' be monolayer molybdenum layer, molybdenum layer with
The composite bed of the composite bed of aluminium lamination or molybdenum layer and titanium layer.
Concrete, the material of described active layer 30 ' is metal-oxide semiconductor (MOS).Preferably, described metal
Oxide semiconductor includes in indium gallium zinc oxide, indium zinc oxide, zinc oxide, indium gallium zinc tin oxide
Kind.
Concrete, described first conductive tie layers 81 ', the second conductive tie layers 82 ' and pixel electrode 83 '
Material be transparent conductive metal oxide or Graphene, preferably Graphene.
Preferably, as shown in figure 25, described first via 51 ' and the 5th via 55 ' are same via, described
First conductive tie layers 81 ' is connected with the second conductive tie layers 82 '.
Concrete, the material of described insulating barrier 40 ' and passivation layer 50 ' all includes in silicon oxide and silicon nitride extremely
Few one.
In sum, the present invention provides a kind of TFT substrate and preparation method thereof, the TFT substrate of the present invention
Manufacture method, by by data wire, gate line and fabrication in same layer, one light shield can be saved,
By using one halftone mask to form the multiple vias in TFT substrate and pixel electrode, can save together
Light shield, thus compared with prior art, the present invention can save twice light shield, reduces production cost, saves
Processing time, improves and semiconductor layer will not cause in production efficiency, and processing procedure electrically damage.The present invention's
TFT substrate, processing procedure is simple, and production cost is low, and has good electric property.
The above, for the person of ordinary skill of the art, can be according to the technical side of the present invention
Other various corresponding changes and deformation are made in case and technology design, and all these change and deformation are all answered
Belong to the protection domain of the claims in the present invention.
Claims (10)
1. the manufacture method of a TFT substrate, it is characterised in that comprise the steps:
Step 1, provide a substrate (10), at described substrate (10) upper deposition one metal level (11), adopt
With one light shield, described metal level (11) is patterned process, obtains data wire (21), gate line
And be connected to the grid (23) of gate line (22) side, described data wire (21) and grid (22)
Line (22) intersects, and described gate line (22) disconnects at infall, and the two ends of disconnection lay respectively at
The both sides of described data wire (21)；
Step 2, at described data wire (21), gate line (22), grid (23) and substrate (10)
Upper depositing insulating layer (40), forms semiconductor layer (31) on described insulating barrier (40), uses together
Light shield is patterned process to described semiconductor layer (31), obtains corresponding to grid (23) top
Active layer (30)；
Step 3, on described active layer (30) and insulating barrier (40), form passivation layer (50), in institute
State and on passivation layer (50), form photoresist layer (60), use one halftone mask to described photoresist layer (60)
Be exposed and develop, described photoresist layer (60) upper formed the first through hole (61), the second through hole (62),
Third through-hole (63), fourth hole (64) and fifth hole (65), described first through hole (61) is right
The upper position near described active layer (30) of data wire described in Ying Yu (21), described second through hole (62)
The upper close described data wire (21) of described active layer (30) is corresponded respectively to third through-hole (63)
Away from the side of described data wire (21), described fourth hole (64) on side and described active layer (30)
The two ends that described gate line (22) disconnects are corresponded respectively to fifth hole (65)；
Simultaneously at described photoresist layer (60) upper formation the first coating region (71), the second coating region (72)
With the 3rd coating region (73) and except described first coating region (71), the second coating region (72)
With the thick-layer region (75) beyond the 3rd coating region (73), described first coating region (71) is positioned at
Between described first through hole (61) and the second through hole (62)；Described second coating region (72) is positioned at
The side of described third through-hole (63), described 3rd coating region (73) is positioned at described fourth hole (64)
And between fifth hole (65)；
Step 4, along described first through hole (61), the second through hole (62), third through-hole (63), the 4th
Through hole (64) and fifth hole (65) carry out dry corrosion to described insulating barrier (40) and passivation layer (50)
Quarter processes, and is positioned at described data wire (21) in the upper formation of described insulating barrier (40) and passivation layer (50)
Go up the first via (51) above the position of described active layer (30) and be positioned at described gate line (22)
The 4th via (54) above two ends and the 5th via (55) disconnected, on described passivation layer (50)
Formation be positioned at upper the second via (52) above described data wire (21) side of described active layer (30),
And be positioned on described active layer (30) away from the 3rd via (53) above described data wire (21) side；
Step 5, described photoresist layer (60) is carried out ashing process, remove the of described photoresist layer (60)
A thin layer region (71), the second coating region (72) and the 3rd coating region (73), and thinning thick-layer
Region (75)；Remaining photoresist layer (60) and passivation layer (50) form conductive film (80)；
Step 6, peel off remaining photoresist layer (60), remove simultaneously and be positioned at described photoresist layer (60) top
Conductive film (80), the conductive film (80) of reservation include the first conductive tie layers (81), second
Conductive tie layers (82) and pixel electrode (83)；
Described first conductive tie layers (81) is respectively by described first via (51) and the second via (52)
Being connected to described data wire (21) and active layer (30), described second conductive tie layers (82) is led to respectively
Cross that described 4th via (54) and the 5th via (55) are connected to that described gate line (22) disconnects two
End, described pixel electrode (83) is connected to described active layer (30) by described 3rd via (53).
2. the manufacture method of TFT substrate as claimed in claim 1, it is characterised in that in described step 2,
The material of described semiconductor layer (31) is metal-oxide semiconductor (MOS)；In described step 5, described conductive thin
The material of film (80) is transparent conductive metal oxide or Graphene.
3. a TFT substrate, it is characterised in that include substrate (10), be located at described substrate (10)
On data wire (21), gate line (22) and grid (23), be located at described data wire (21), grid
Insulating barrier (40) on polar curve (22), grid (23) and substrate (10), it is located at described insulating barrier (40)
Upper and active layer (30) corresponding to described grid (23) top, be located at described active layer (30) and
Passivation layer (50) on insulating barrier (40) and the first conduction of being located on described passivation layer (50) are even
Connect layer (81), the second conductive tie layers (82) and pixel electrode (83)；
Described grid (23) is connected to gate line (22) side, described data wire (21) and gate line
(22) intersecting, and described gate line (22) disconnects at infall, the two ends of disconnection lay respectively at institute
State the both sides of data wire (21)；
Described insulating barrier (40) and passivation layer (50) are provided with that to be positioned at described data wire (21) upper the most close
The first via (51) above the position of described active layer (30) and lay respectively at described gate line (22)
The 4th via (54) above two ends and the 5th via (55) disconnected, described passivation layer sets on (50)
Have be positioned at upper the second via (52) above described data wire (21) side of described active layer (30),
And be positioned on described active layer (30) away from the 3rd via (53) above described data wire (21) side；
Described first conductive tie layers (81) is respectively by described first via (51) and the second via (52)
Being connected to described data wire (21) and active layer (30), described second conductive tie layers (82) is led to respectively
Cross that described 4th via (54) and the 5th via (55) are connected to that described gate line (22) disconnects two
End, described pixel electrode (83) is connected to described active layer (30) by described 3rd via (53).
4. TFT substrate as claimed in claim 3, it is characterised in that the material of described active layer (30)
Material is metal-oxide semiconductor (MOS)；Described first conductive tie layers (81), the second conductive tie layers (82),
And the material of pixel electrode (83) is transparent conductive metal oxide or Graphene.
5. the manufacture method of a TFT substrate, it is characterised in that comprise the steps:
Step 1, provide a substrate (10 '), at described substrate (10 ') upper deposition one metal level (11 '),
Use one light shield that described metal level (11 ') is patterned process, obtain data wire (21 '), grid
Polar curve (22 ') and be connected to the grid (23 ') of gate line (22 ') side, described data wire (21 ')
Intersect with gate line (22 '), and described data wire (21 ') disconnects at infall, the two ends of disconnection
Lay respectively at the both sides of described gate line (22 ')；
Step 2, at described data wire (21 '), gate line (22 '), grid (23 ') and substrate (10 ')
Upper depositing insulating layer (40 '), forms semiconductor layer (31 ') on described insulating barrier (40 '), uses one
Road light shield is patterned process to described semiconductor layer (31 '), obtains corresponding on grid (23 ')
The active layer (30 ') of side；
Step 3, on described active layer (30 ') and insulating barrier (40 '), form passivation layer (50 '),
Described passivation layer (50 ') forms photoresist layer (60 '), uses one halftone mask to described photoresistance
Layer (60 ') is exposed and develop, described photoresist layer (60 ') upper formation the first through hole (61 '),
Second through hole (62 '), third through-hole (63 '), fourth hole (64 ') and fifth hole (65 '),
Described first through hole (61 ') is corresponding to the upper close described active layer (30 ') of described data wire (21 ')
Position, described second through hole (62 ') and third through-hole (63 ') correspond respectively to described active layer (30 ')
Away from described data wire (21 ') on the upper side near described data wire (21 ') and described active layer (30 ')
Side, described fourth hole (64 ') and fifth hole (65 ') correspond respectively to described data wire (21 ')
The two ends disconnected；
Simultaneously at described photoresist layer (60 ') upper formation the first coating region (71 '), the second coating region (72 ')
With the 3rd coating region (73 ') and except described first coating region (71 '), the second coating region (72 ')
With the thick-layer region (75 ') beyond the 3rd coating region (73 '), described first coating region (71 ')
It is positioned between described first through hole (61 ') and the second through hole (62 ')；Described second coating region (72 ')
Being positioned at the side of described third through-hole (63 '), described 3rd coating region (73 ') is positioned at the described 4th
Between through hole (64 ') and fifth hole (65 ')；
Step 4, along described first through hole (61 '), the second through hole (62 '), third through-hole (63 '),
Described insulating barrier (40 ') is entered by four through holes (64 ') and fifth hole (65 ') with passivation layer (50 ')
Row dry etch process, is positioned at described data in the upper formation of described insulating barrier (40 ') and passivation layer (50 ')
Line (21 ') is gone up the first via (51 ') above the position of described active layer (30 ') and is positioned at
The 4th via (54 ') above two ends that described data wire (21 ') disconnects and the 5th via (55 '),
It is positioned at described active layer (30 ') upper near described data wire (21 ') in the upper formation of described passivation layer (50 ')
The second via (52 ') above side and being positioned on described active layer (30 ') away from described data
The 3rd via (53 ') above line (21 ') side；
Step 5, described photoresist layer (60 ') is carried out ashing process, remove described photoresist layer (60 ')
First coating region (71 '), the second coating region (72 ') and the 3rd coating region (73 '), and thinning
Thick-layer region (75 ')；Remaining photoresist layer (60 ') and passivation layer (50 ') form conductive film
(80’)；
Step 6, peel off remaining photoresist layer (60 '), remove simultaneously and be positioned on described photoresist layer (60 ')
Side conductive film (80 '), the conductive film (80 ') of reservation include the first conductive tie layers (81 '),
Second conductive tie layers (82 ') and pixel electrode (83 ')；
Described first conductive tie layers (81 ') is respectively by described first via (51 ') and the second via
(52 ') are connected to described data wire (21 ') and active layer (30 '), described second conductive tie layers (82 ')
It is connected to described data wire (21 ') respectively by described 4th via (54 ') and the 5th via (55 ')
Disconnect two ends, described pixel electrode (83 ') by described 3rd via (53 ') be connected to described in have
Active layer (30 ').
6. the manufacture method of TFT substrate as claimed in claim 5, it is characterised in that in described step 2,
The material of described semiconductor layer (31 ') is metal-oxide semiconductor (MOS)；In described step 5, described conduction
The material of thin film (80 ') is transparent conductive metal oxide or Graphene.
7. the manufacture method of TFT substrate as claimed in claim 5, it is characterised in that described first mistake
Hole (51 ') and the 5th via (55 ') are same via, described first conductive tie layers (81 ') and the
Two conductive tie layers (82 ') are connected.
8. a TFT substrate, it is characterised in that include substrate (10 '), be located at described substrate (10 ')
On data wire (21 '), gate line (22 ') and grid (23 '), be located at described data wire (21 '),
Insulating barrier (40 ') on gate line (22 '), grid (23 ') and substrate (10 '), be located at described absolutely
Edge layer (40 ') is upper and active layer (30 ') corresponding to described grid (23 ') top, be located at described in have
Passivation layer (50 ') in active layer (30 ') and insulating barrier (40 ') and be located at described passivation layer (50 ')
On the first conductive tie layers (81 '), the second conductive tie layers (82 ') and pixel electrode (83 ')；
Described grid (23 ') is connected to gate line (22 ') side, described data wire (21 ') and grid
Line (22 ') intersects, and described data wire (21 ') disconnects at infall, position respectively, the two ends of disconnection
Both sides in described gate line (22 ')；
Described insulating barrier (40 ') and passivation layer (50 ') are provided with that to be positioned at described data wire (21 ') close
The first via (51 ') above the position of described active layer (30 ') and lay respectively at described data wire
The 4th via (54 ') above the two ends that (21 ') disconnect and the 5th via (55 '), described passivation layer
(50 ') are provided with and are positioned at above upper close described data wire (the 21 ') side of described active layer (30 ')
Second via (52 ') and being positioned on described active layer (30 ') away from described data wire (21 ')
The 3rd via (53 ') above side；
Described first conductive tie layers (81 ') is respectively by described first via (51 ') and the second via
(52 ') are connected to described data wire (21 ') and active layer (30 '), described second conductive tie layers (82 ')
It is connected to described data wire (21 ') respectively by described 4th via (54 ') and the 5th via (55 ')
Disconnect two ends, described pixel electrode (83 ') by described 3rd via (53 ') be connected to described in have
Active layer (30 ').
9. TFT substrate as claimed in claim 8, it is characterised in that the material of described active layer (30 ')
Material is metal-oxide semiconductor (MOS)；Described first conductive tie layers (81 '), the second conductive tie layers (82 '),
And the material of pixel electrode (83 ') is transparent conductive metal oxide or Graphene.
10. TFT substrate as claimed in claim 8, it is characterised in that described first via (51 ')
Being same via with the 5th via (55 '), described first conductive tie layers (81 ') is with the second conduction even
Connect layer (82 ') to be connected.
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| CN103367248A (en) * | 2013-07-01 | 2013-10-23 | 京东方科技集团股份有限公司 | Array substrate, preparation method of array substrate and display device |
| CN104393000A (en) * | 2014-10-20 | 2015-03-04 | 上海天马微电子有限公司 | Array substrate and manufacturing method thereof, and display device |
| CN105097845A (en) * | 2015-08-24 | 2015-11-25 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof, and display device |
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| US5920083A (en) * | 1996-05-21 | 1999-07-06 | Samsung Electronics Co., Ltd. | Thin-film transistor display devices having coplanar gate and drain lines |
| CN103367248A (en) * | 2013-07-01 | 2013-10-23 | 京东方科技集团股份有限公司 | Array substrate, preparation method of array substrate and display device |
| CN104393000A (en) * | 2014-10-20 | 2015-03-04 | 上海天马微电子有限公司 | Array substrate and manufacturing method thereof, and display device |
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