CN105800549A - Metal nanodot array and method used for forming nanodot device - Google Patents

Metal nanodot array and method used for forming nanodot device Download PDF

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CN105800549A
CN105800549A CN 201610027870 CN201610027870A CN105800549A CN 105800549 A CN105800549 A CN 105800549A CN 201610027870 CN201610027870 CN 201610027870 CN 201610027870 A CN201610027870 A CN 201610027870A CN 105800549 A CN105800549 A CN 105800549A
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cavity
layer
initial
array
metal
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CN 201610027870
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CN105800549B (en )
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威尔伯·卡托贝
夏维仁
艾伯特·布吕格曼
姚杰森
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苏州工业园区纳米产业技术研究院有限公司
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    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82BNANOSTRUCTURES FORMED BY MANIPULATION OF INDIVIDUAL ATOMS, MOLECULES, OR LIMITED COLLECTIONS OF ATOMS OR MOLECULES AS DISCRETE UNITS; MANUFACTURE OR TREATMENT THEREOF
    • B82B1/00Nanostructures formed by manipulation of individual atoms or molecules, or limited collections of atoms or molecules as discrete units
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82BNANOSTRUCTURES FORMED BY MANIPULATION OF INDIVIDUAL ATOMS, MOLECULES, OR LIMITED COLLECTIONS OF ATOMS OR MOLECULES AS DISCRETE UNITS; MANUFACTURE OR TREATMENT THEREOF
    • B82B1/00Nanostructures formed by manipulation of individual atoms or molecules, or limited collections of atoms or molecules as discrete units
    • B82B1/002Devices comprising flexible or deformable elements
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82BNANOSTRUCTURES FORMED BY MANIPULATION OF INDIVIDUAL ATOMS, MOLECULES, OR LIMITED COLLECTIONS OF ATOMS OR MOLECULES AS DISCRETE UNITS; MANUFACTURE OR TREATMENT THEREOF
    • B82B3/00Manufacture or treatment of nanostructures by manipulation of individual atoms or molecules, or limited collections of atoms or molecules as discrete units
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82BNANOSTRUCTURES FORMED BY MANIPULATION OF INDIVIDUAL ATOMS, MOLECULES, OR LIMITED COLLECTIONS OF ATOMS OR MOLECULES AS DISCRETE UNITS; MANUFACTURE OR TREATMENT THEREOF
    • B82B3/00Manufacture or treatment of nanostructures by manipulation of individual atoms or molecules, or limited collections of atoms or molecules as discrete units
    • B82B3/0004Apparatus specially adapted for the manufacture or treatment of nanostructural devices or systems or methods for manufacturing the same
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82BNANOSTRUCTURES FORMED BY MANIPULATION OF INDIVIDUAL ATOMS, MOLECULES, OR LIMITED COLLECTIONS OF ATOMS OR MOLECULES AS DISCRETE UNITS; MANUFACTURE OR TREATMENT THEREOF
    • B82B3/00Manufacture or treatment of nanostructures by manipulation of individual atoms or molecules, or limited collections of atoms or molecules as discrete units
    • B82B3/0009Forming specific nanostructures
    • B82B3/0014Array or network of similar nanostructural elements
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82BNANOSTRUCTURES FORMED BY MANIPULATION OF INDIVIDUAL ATOMS, MOLECULES, OR LIMITED COLLECTIONS OF ATOMS OR MOLECULES AS DISCRETE UNITS; MANUFACTURE OR TREATMENT THEREOF
    • B82B3/00Manufacture or treatment of nanostructures by manipulation of individual atoms or molecules, or limited collections of atoms or molecules as discrete units
    • B82B3/0009Forming specific nanostructures
    • B82B3/0023Forming specific nanostructures comprising flexible or deformable elements
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y30/00Nanotechnology for materials or surface science, e.g. nanocomposites
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00Manufacture or treatment of nanostructures

Abstract

The invention discloses a nanodot array and an associated construction method. The nanodot array comprises a plurality of nanodots which are arranged on a substrate and used for further application.

Description

金属纳米点阵列和用于形成纳米点装置的方法 Metal nano dot array and a method for forming nano dots apparatus

技术领域 FIELD

[0001] 本文所描述的本发明公开了如制造在微小规模基板上的纳米点阵列。 [0001] The present invention described herein is disclosed as producing nano dot array on a microscopic scale substrate. 当用作等离子体传感器时,此种阵列具有广泛的应用性。 When used as a plasma sensor array having such wide applicability. 特别地,本文所公开的装置和方法描述了可应用于(但不局限于)生物传感器装置的纳米点阵列及构建方法。 In particular, the devices and methods disclosed herein described may be applied (but not limited to) an array of nanodots biosensor apparatus and construction methods. 而且,本发明针对成本有效的金纳米点阵列和构建方法。 Further, the present invention is directed to a cost effective method of constructing and gold dot array. 本文的原理也适用于其他纳米级别的制造技术,也适用于半导体封装和装置。 The principles herein are also applicable to other nanoscale fabrication techniques, and also applicable to a semiconductor device package.

背景技术 Background technique

[0002] 现有技术中,形成纳米点基板的方法是已知的。 Method [0002] In the prior art, the substrate is formed nanodots are known. 然而,所有的现有方法都遭受非常严重的限制性,使得成本显著增加,产生了不一致或非期望的结果。 However, all the conventional methods suffer from very serious restriction, such that a significant increase in cost, or produce inconsistent results desired. 一般来说,纳米点是测量起来仅有几个纳米跨度的表面,且为了以合理或甚至是成本有效的价格制造一致和高质量的纳米点阵列,甚至对最高质量的机器和最先进的技术提出了挑战。 In general, the surface of nanodots is only a few nanometers up measurement span, and for reasonable or even cost-effective manufacture consistent price and quality nano dot array, even for the highest quality and the most advanced technology machines challenges.

[0003] 虽然并不限于此,此种纳米点的一个特别有用的应用是:表面等离子体和生物技术统一。 [0003] While not limited thereto, one particularly useful application of this nanodots are: surface plasmon and biotechnology unification. 在一种这样的方法中,生物学活性分子可附于纳米点阵列,然后纳米点阵列可用以传导所附分子的非常精细和异常敏感的生物活性测量。 In one such method, the biologically active molecule may be attached to the nano dot array, and then the nano dot array can be used to conduct the following very fine molecular biological activity and abnormal sensitivity measurement. 几种非限制性实例应用包括将抗体附于此种纳米点阵列的纳米点。 Several non-limiting examples of applications include an antibody attached to such nanodots nano dot array. 随后阵列暴露至样品或诊断介质,可用于确定样品中是否存在指定的抗原。 The array is then exposed to the sample or diagnostic media, it can be used to determine whether there is a specified antigen in a sample. 在另一种有关的应用中,DNA、RNA或任何核酸可与纳米点阵列的纳米点结合,然后阵列可暴露至样品或诊断介质,样品或诊断介质可与结合有核酸的纳米点混杂,以确定所选择的互补链的存在。 In another related application, DNA, RNA, or any nucleic acid may be combined with the nano dot nano dot array, then the array may be exposed to sample or diagnostic media, diagnostic media, or mixed sample with the nucleic acid bound nanodots to determining the presence of the selected complementary strand. 在另一种应用中,选择的多肽可与纳米点结合,并暴露至样品或诊断介质,以检查反应物质的存在或不存在。 In another application, the selected polypeptide may be combined with the nano-dots, and exposed to the sample or diagnostic media, to check the reaction of the presence or absence of the substance. 这些应用仅仅是大量可能性中的几种。 These applications are just a few of a large number of possibilities.

[0004] 然而,以一致、可重复且成本有效方式来制造此种纳米点的均匀阵列已被证明是难以捉摸的。 [0004] However, in a consistent, reproducible and cost-effective way to manufacture such a uniform array of nanodots it has proven to be elusive. 而且,构建此种阵列可能所需要的机器是特别昂贵的,大约几千万到几亿美JL· 〇 Moreover, the construction of such an array may require special machines are expensive, about tens of millions to hundreds of millions of US JL · billion

[0005] 在O.Vasquez-Mena等(以下称为"Vasquez")的论文"Fabrication of Metallic Nanodots by StenciILithograpy for Localized Surface Plasmon Resonance Biosensing"中论述了一种纳米点阵列构建方法。 [0005] "of Metallic Nanodots by StenciILithograpy for Localized Surface Plasmon Resonance Biosensing Fabrication" discussed a nano dot array O.Vasquez-Mena et al. (Hereinafter referred to as "Vasquez") paper construction method. Vasquez方法是形成由非常薄的膜制成的型板,该膜具有形成在其中的精细孔图案。 Vasquez is formed by a plate made of a very thin film, the film having a fine pattern of holes formed therein. 该膜经受穿过型板中的孔的金属沉积,以将金属图案转移至基板(纳米点阵列)。 The film is subjected to metal deposition through an aperture in the plate to transfer the pattern to the substrate metal (nano dot array). 在一些应用中,其工作的也还好。 In some applications, it is also good work. 然而,为了形成有恰当的图案并具有所需的公差,该型板是极其昂贵的。 However, in order to form a pattern with a proper and having the required tolerances, the plate is extremely expensive. 更糟糕的是,在仅仅使用几次后,型板变得堵塞,基本上无法使用,因此其总体上不适用任何有用的应用。 Worse, after only a few uses, plate becomes clogged, basically you can not use, so it does not apply any useful application as a whole.

[0006] 在另一种方法中,在Sunghoon Kwon等(以下称为"Kwon")的劳伦斯-伯克利国家实验室发表的论文"Fabrication of Metallic Nanodots in Large-Area Arrays by Mold-toMold CrossImprinting(MTMCI)"中论述了另一种纳米点阵列构建法。 [0006] In another method, Sunghoon Kwon et Lawrence (hereinafter referred to as "Kwon") - the Berkeley National Laboratory published a paper "Fabrication of Metallic Nanodots in Large-Area Arrays by Mold-toMold CrossImprinting (MTMCI) "another discussed nano dot array Construction method. Kwon方法是形成带有柱(纳米级)阵列的模,柱阵列从该模伸出。 Kwon mold is formed (nanometer) with a column of the array, the array columns extending from the mold. 该模被按压以与具有柔软表面的基板表面材料相接触,以使得一旦应用压力,柱使柔软表面凹陷以形成孔。 The mold is pressed to contact with the surface of the substrate material has a soft surface, such that upon application of pressure to the column so that the soft surface of the recess to form a hole. 金属沉积至存在于柔软材料中的孔中,以使得金属沉积在下面的基板的孔中。 Depositing a soft metal material present in the bore, so that the metal is deposited on the substrate below the hole. 移除柔软材料,金属纳米点阵列保留在下面的基板上。 Removal of soft material, metal nano dot array on the lower substrate retained. 这种方法因许多缺点和困难而受阻碍。 This method is due to a number of disadvantages and difficulties hampered. 其中之一为:形成合适的压印型板和其许多纳米柱是极其困难的、高成本的,且经受非常严重的一致性问题。 One of which is: Suitable embossing plate and forming a number of nano-pillars thereof extremely difficult, costly, and subjected to very serious consistency problems. 而且,所得的纳米点的形状、均匀分布或一致性不规则。 Further, the shape of the resulting nano dots, a uniform distribution or consistency irregular. 这对使用这种方法形成的纳米点阵列的应用具有剧烈的影响。 This has a dramatic impact on the application of nano dot array is formed using this method.

[0007] 在张元等(以下称为"张")的"Phasechange nanodots patterning using self-assembled polymer lithography and crystallization analysis" 中论述了另一种纳米点阵列方法。 [0007] "using self-assembled polymer lithography and crystallization analysis Phasechange nanodots patterning" in Zhang et al. (Hereinafter referred to as "sheets") are discussed in the nano dot array of another method. "张"方法经受了非常差的纳米点尺寸一致性和不规则的阵列形成,其中不同尺寸的纳米点随机分散在表面上,未形成此种纳米点的规则阵列。 "Zhang" method is subjected to an array of nanodots very poor dimensional consistency and irregular form, wherein the different sizes of randomly dispersed nanodots on the surface, such a regular array of nano dots are not formed.

[0008] 因此,用于生成纳米点阵列的现有制造方案远远不能满足需求,花费了大量的金钱,在纳米点和它们相关的阵列中不能提供一致的尺寸和间隔,且需要利用极其昂贵的的工具来制造。 [0008] Thus, the conventional fabrication scheme for generating the nano dot array can not meet demand, it takes a lot of money, do not provide uniform size and spacing of the nano-dots and their associated array, and the need to use very expensive the tools to manufacture.

[0009] 为了这些及其他原因,一种改进的纳米点阵列和其相关的构建方法在工业上将是非常有帮助的。 [0009] For these and other reasons, an improved nano dot array and its associated method of construction in the industry will be very helpful.

发明内容 SUMMARY

[0010] 根据本发明的原理,公开了纳米点阵列配置及其相关联的制造方法。 [0010] In accordance with the principles of the present invention, discloses a nano dot array configuration and associated method for manufacturing.

[0011] 在一个实施例中,本发明公开了一种纳米点阵列。 [0011] In one embodiment, the present invention discloses a nano dot array. 此种阵列包括一支撑件,该支撑件具有形成在其中的初始空腔阵列。 Such an array comprising a support member, the support member having a cavity formed in the initial array therein. 一修整件安置在空腔中,以使得经由修整件来使初始空腔的内侧壁变窄。 A trim member disposed in the cavity, so that the trim member via the inner side wall to the initial narrowing of the cavity. 内侧壁限定了具有期望宽度的变窄的空腔,该期望宽度在其中限定了纳米点布置位置。 The sidewall defining a cavity having a desired width is narrowed, the width of which defines the desired nano dot placement locations. 金属塞子形成在相关联的纳米点布置位置,以使得纳米点的暴露的上表面限定了具有多个纳米点的纳米点阵列。 Metal plugs are formed in the nano dot placement locations associated, so that the nano dots on the exposed surface defining a plurality of nano dot array with nano-dots. 在形成具有规则间隔和尺寸的纳米点,具有大约50纳米(nm)或更小的纳米点宽度的纳米点阵列方面,此种实施例是特别有用的。 Forming nano dots in regular intervals and having a size of about 50 nm dot array nanometers (nm) or less of the width of the nano dots, this embodiment is particularly useful embodiment.

[0012] 在另一个实施例中,公开了一种在基板中形成窄尺寸的方法。 [0012] In another embodiment, a method of forming a narrow dimension in the substrate. 此种方法包括在支撑件中形成多个初始空腔的步骤。 Such a method comprises the initial step of forming a plurality of cavities in the support. 其中所述初始空腔各自具有初始宽度。 Wherein each of the initial cavity has an initial width. 并且,还修整所述初始空腔的初始宽度,以使所述初始空腔变窄至期望尺寸,从而形成相关联的修整空腔,该修整空腔具有相对所述初始宽度变窄的修整宽度。 And further trimmed initial width of the initial cavity, so that the initial cavity narrows to a desired size, trimming to form an associated cavity, the cavity having a trim trimming of the initial width is relatively narrower width .

[0013] 在另一个实施例中,公开了一种形成纳米点阵列的方法。 [0013] In another embodiment, there is disclosed a method of forming a nano dot array. 此种方法包括在支撑件中形成多个初始空腔的步骤,其中所述初始空腔各自具有初始宽度。 Such a method comprises the initial step of forming a plurality of cavities in the support member, wherein each of the initial cavity has an initial width. 还包括以下步骤:将所述初始空腔的初始宽度修整至更窄的期望尺寸,从而形成具有比初始宽度更窄的修整宽度的修整空腔,从而限定了纳米点布置位置。 Further comprising the steps of: initially the initial cavity width narrower trimmed to a desired size, trimming to form a cavity having a width narrower than the initial width of the dressing, so as to define a nano dot placement locations. 还包括以下步骤:在纳米点布置位置处形成多个金属塞子,以使得纳米点远远比初始空腔限定的轮廓窄,从而使得能够形成具有多个纳米点的纳米点阵列。 Further comprising the steps of: forming a plurality of metal nano-dots are arranged at the stopper position, so that the nano dots far narrower than the initial contour defined cavity, so that the nano dots can be formed array having a plurality of nano dots.

[0014] 在另一个实施例中,公开了一种形成纳米点阵列的方法。 [0014] In another embodiment, there is disclosed a method of forming a nano dot array. 此种方法包括:提供具有第一机械弹性层的支撑件,该机械弹性层具有形成在其上的第二金属层。 Such a method comprises: providing a support member having a first mechanical elastic layer, the elastic layer having a second mechanical metal layer is formed thereon. 一第三介电层还形成在第二金属层上。 A third dielectric layer is further formed on the second metal layer. 多个初始宽度的初始空腔形成在支撑件中。 Initial plurality of cavities formed in the initial width of the support member. 然后,在修整步骤中对初始空腔进行修整,该修整步骤将初始空腔变窄至相对于初始宽度更窄的修整宽度,从而形成了限定纳米点布置位置的修整空腔。 Then, in the trimming step for trimming the initial cavity, the cavity is narrowed initial finishing step with respect to the initial width narrower width trimmed, thus forming a nano dot placement locations defining a cavity dressing. 还包括在修整空腔中形成多个金属塞子以实现所述形成的步骤。 Further comprising forming a plurality of metal plugs in the cavity to achieve the step of trimming said formed.

[0015] 在下文阐述的附图的以下具体实施方式中将更详细地描述本发明的这些及其他方面。 [0015] These and other aspects of the present invention will be described in the following specific embodiments set forth in the accompanying drawings in detail below.

附图说明 BRIEF DESCRIPTION

[0016] 结合附图将更容易理解以下具体实施方式,其中: [0016] The accompanying drawings will be more readily understood in conjunction with the following detailed description, wherein:

[0017] 图1是描绘用于根据本发明原理构建装置和基板的方法实施例的流程图。 [0017] FIG. 1 is a diagram depicting a method and apparatus for constructing a substrate according to the principles of the present invention, a flow diagram of the embodiment.

[0018]图2(a)_2(e)包括一基板的一系列剖视图,该基板如适用于根据本发明原理形成装置的纳米点阵列形成工艺中所加工的。 [0018] FIG. 2 (a) _2 (e) a series of cross-sectional view of a substrate comprising a nano dot array as applied to the substrate forming apparatus according to principles of the present invention, the processing of the forming process.

[0019] 图3(a)-3(b)包括一基板的一系列剖视图,该基板如适用于根据本发明原理形成装置的纳米点阵列形成工艺中所加工的。 (B) comprises a series of cross-sectional view of a substrate 3 [0019] FIG. 3 (a), the substrate forming process as applied to the processing of nano dot array forming apparatus according to the principles of the present invention.

[0020] 图4是描绘用于根据本发明原理构建设备和装置的一替代性方法实施例的另一流程图。 [0020] FIG. 4 is a diagram depicting an alternative method for constructing a device and apparatus according to another embodiment of the flow diagram according to the principles of the present invention.

[0021] 图5(a)_5(g)包括一基板的一系列剖视图,该基板如适用于根据本发明原理形成装置的纳米点阵列形成工艺中所加工的。 Nano dot array [0021] FIG. 5 (a) _5 (g) a series of cross-sectional view of a substrate including, as applicable to the substrate forming apparatus according to principles of the present invention, the processing of the forming process.

[0022] 图6是描绘用于根据本发明原理构建设备和装置的一替代性方法实施例的另一流程图。 [0022] FIG. 6 is a diagram depicting an alternative method for constructing a device and apparatus according to another embodiment of the flow diagram according to the principles of the present invention.

[0023]图7(a)_7(e)包括一基板的一系列剖视图,该基板如适用于根据本发明原理形成装置的另一种纳米点阵列形成工艺中所加工的。 Another nano dot array [0023] FIG. 7 (a) _7 (e) a series of cross-sectional view of a substrate including, as applicable to the substrate forming apparatus according to principles of the present invention, the processing of the forming process.

[0024]应理解的是,在附图中,相同的元件符号代表相同的结构元件。 [0024] It should be understood that, in the drawings, the same reference numbers represent the same structural elements. 而且应理解,图中的描绘不一定是按比例的。 And it should be understood that the figures are not necessarily depicted to scale.

具体实施方式 Detailed ways

[0025] 一般来说,本发明涉及纳米点阵列和它们的各种制造方法。 [0025] In general, the present invention relates to an array of nano-dots and their various manufacturing methods. 已相对特定实施例和其具体的特征特别地展示和描述了本发明。 It has been particularly shown and described relative to the present invention and the specific features of a particular embodiment. 本文中阐述的实施例应视为示例性的,而非限制性的。 Example embodiments set forth herein should be considered illustrative, and not restrictive. 对于本领域技术人员来说,显而易见的是:在未脱离本发明精神和范畴的情况下, 可作出形式和细节上的各种变化和修改。 For the skilled person, it is apparent: in the case of not departing from the spirit and scope of the invention, and that various changes may be made in the form and details of the modifications.

[0026] 如上文所指出的,在现有技术中存在在严重的限制:较差的纳米点一致性、严重的掩模降解问题、可重复困难、制造工艺不可靠、与最先进的制造工具的获得和操作有关的极其高的成本、不能使用旧的高度贬值的工具,以及在以商业可支持方式制造足够小的纳米点方面的简单挑战。 [0026] As noted above in the prior art present serious limitations: poor consistency nanodots, mask serious degradation problems, difficulties can be repeated, the manufacturing process is not reliable and the most advanced manufacturing tools simple challenge of obtaining and operating costs related to extremely high, you can not use the old height devaluation tool, as well as aspects of the nanodots in manufacturing small enough to support commercial way.

[0027] 本发明提供了一种形成极其小的纳米点阵列的能力,所述纳米点阵列具有低至20 纳米(nm)或更小的点尺寸、极其好的可重复性、优良的点均匀性、优良的点间隔均匀性、使用已证明技术的非常可靠的制造工艺,不需要新的工具套装和机器,从而使得厂商能够将旧机器用于制造前沿的纳米结构,并提供了一种商业上可行的装置和制造方法。 [0027] The present invention provides an ability to form extremely small nano dot array, said array having up to 20 nano dots nanometers (nm) or smaller dot size, extremely good reproducibility, excellent uniformity point , excellent uniformity of dot interval, use has proved very reliable manufacturing process technology, no new suite of tools and machines, so that the old machine manufacturers can be used to manufacture cutting edge of nanostructures, and provides a commercial feasible apparatus and method.

[0028] 在一个实施例中,将展示和描述一种装置及其相关联的制造方法。 [0028] In one embodiment, it will be shown and described an apparatus and a method for producing associated. 图1是图示了用于形成纳米点阵列的一个合适实施例的流程图。 FIG 1 is a flowchart illustrating a suitable embodiment for forming the nano dot array.

[0029]开始参阅图1和图2(a)来描述第一个实施例。 [0029] Referring to FIG. 1 and FIG Start 2 (a) to a first embodiment described. 提供或形成一支撑件(步骤101)。 Providing or forming a support member (step 101). 在一种可能的方法中,形成一支撑件200。 In one possible approach, a supporting member 200 is formed. 在一个示例性实施例中,支撑件可包括其上形成有第二层202的第一层201。 In one exemplary embodiment, the support member may comprise a first layer on which a second layer 202 201. 在大多数实施方式中,第一层201是机械弹性结构层,其可支撑将由该工艺形成的整个纳米点阵列。 In most embodiments, the first layer 201 is a mechanical structure of an elastic layer, which may be supported by the entire array of the nano dots formed by the process. 这种层201可由任何材料形成,但是许多材料由于低成本和/或容易制造而更具有吸引力。 Such a layer 201 may be formed of any material, but due to the many low cost materials and / or are easy to manufacture more attractive. 例如,有利地使用硼硅玻璃(BSG)、石英、石英玻璃和其他材料。 For example, it is advantageous to use a borosilicate glass (BSG), quartz, quartz glass, and other materials. 然而,实际上,也可容易地使用半导体加工中使用的任何材料。 However, in practice, any material that can be easily used in a semiconductor process used.

[0030] 在一个特别有利的实施例中,硅片可用作机械性坚固基板201。 [0030] In a particularly advantageous embodiment, the silicon substrate 201 can be used as mechanically robust. 此种硅片提供了随时可利用性、制造容易性和足够的强度。 Such a silicon wafer is provided ready availability, ease of manufacture and sufficient strength. 重要的是,如下文其他实施例中将图示的,金属层和层压多层材料可用于形成第一层201 (通常,以及此支撑件200)。 Importantly, as described in the other embodiments illustrated embodiment, the metal layer may be laminated multilayer material for forming the first layer 201 (generally, and this support member 200). 在任何情况下,此种层可用现有的晶片制造方法和工具使用标准的圆片尺寸来形成。 In any case, such layer may be a conventional wafer manufacturing methods and tools using standard wafer sizes are formed.

[0031] 作为进一步描述用,支撑件200还包括形成在第一层201上的第二层202。 [0031] As is further described by the support member 200 further includes a second layer 202 formed on the first layer 201. 在一个实施例中,此第二层202可由介电材料制成。 In one embodiment, this second layer 202 may be made of a dielectric material. 例如,可使用许多有机或无机材料中的任何一种, 也可使用许多各种不同的其他介电材料。 For example, using any one of a number of organic or inorganic materials, it may also be used a number of various other dielectric materials. 可以使用硅烷氧化物层,如可以使用二氧化硅层, 及其他介电材料。 A silane oxide layer, such as a silicon dioxide layer may be used, and other dielectric materials. 在一种合适的方法中,一种正硅酸四乙酯(TE0S)制造工艺可用以形成第二层202,在这种情况下,为期望的介电层202。 In one suitable method, a tetraethyl orthosilicate (TE0S) manufacturing process used to form second layer 202, in this case, a desired dielectric layer 202. 此外,特别指出的是,本发明不限于此。 Further, particularly it pointed out that the invention is not limited thereto. 可使用各种各样的其他工艺,包括(但不限于)热氧化,多种沉积技术,例如:等离子体增强化学汽相沉积(PECVD)、低压化学气相沉积(LPCVD)、低压等离子体增强化学气相沉积(LPPECVD),以及许多其他方法,这取决于期望的薄膜性质和所用的材料。 A wide variety of other processes, including (but not limited to) the thermal oxidation, a variety of deposition techniques, for example: a plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced low pressure chemical vapor deposition (LPPECVD), and many other methods, depending on the desired film properties and the materials used. 第二层材料可来自十分广泛的选择,虽然介电材料是一种优选的材料,还可以使用其他非导电材料。 The second layer of material may be selected from a very wide range, although the preferred material is a dielectric material, may also be used other nonconductive material. 此外, 取决于应用,甚至还可使用一些导电性材料,只要它们在化学上不同于纳米点材料。 Further, depending on the application, and even some of the conductive material may be used as long as they are chemically different from the nano dot material.

[0032] 此种薄膜通常形成大约100A(埃)至大约5000A(埃)的厚度。 [0032] Such films are typically formed to a thickness of about IOOA (Angstroms) to about 5000A (angstrom). 优选的范围是在大约1000A至大约3000A厚度之间,一个合适的实施例具有大约2000A的厚度。 A preferred range is between about 1000A to about 3000A thickness, a suitable embodiment of a thickness of about 2000A. 使用标准的半导体加工工具可容易地实现此种层。 Using standard semiconductor processing tool such layers can be easily realized.

[0033] 继续参阅图1以及图2(b'),初始空腔203形成在第二层202中(步骤103)。 [0033] Referring to FIG. 1 and FIG. 2 (b '), the initial cavity 203 is formed in the second layer 202 (step 103). 此种初始空腔限定了初期的纳米点位置。 Such nano initial cavity defines the initial position. 在一个实施例中,所述空腔203形成了规则间隔和相似尺寸的空腔203阵列。 In one embodiment, the cavity 203 includes a cavity 203 and an array of similarly sized regular intervals. 由于使用了半导体工艺,且初始空腔203的尺寸在普通半导体加工工具的工艺包迹内,可形成极其精确的图案,空腔203之间具有优良的规则性和间隔。 The use of the semiconductor process, and the initial size of the cavity 203 in the process of ordinary envelope semiconductor processing tool, extremely precise pattern can be formed, having excellent regularity and the spacing between the cavity 203. 这些孔的尺寸和轮廓可以被很好地控制。 Size and profile of the holes can be well controlled. 应指出,在一些实施例中,初始空腔203可形成在特定类型的第一层201中,从而完全避免需要第二层202。 It should be noted, in some embodiments, cavities 203 may be initially formed in the first layer 201 of a specific type, thereby completely avoiding the need for a second layer 202. 在任何情况下,甚至在工艺的早期阶段,本发明就解决和克服了至少一些上述提到的Vazquez、张和Kwon方法中成问题的争端。 In any case, even in the early stage of the process, the present invention is to address and overcome at least some of the above-mentioned Vazquez, Kwon and processes into sheets of disputes. 图案是规则的,空腔尺寸是均匀和精确的,且不依赖易腐败的可降解掩模。 Pattern is regular, and uniform cavity size is accurate, is not dependent perishable biodegradable mask.

[0034]另外,应指出,若需要,基板200可经配置以包括在基板200的不同部分具有变化尺寸的初始空腔阵列。 [0034] Further, it should be noted that, if desired, the substrate 200 may be configured to include an initial array of cavities of varying dimensions in different portions of substrate 200. 另外,根据需要,具有变化的图案方向和变化的空腔之间的间距的阵列可形成在相同基板上。 Further, if necessary, the spacing between the array pattern having a varying direction and varying the cavity may be formed on the same substrate.

[0035]在一个实施例中,掩模层可用于促进初始空腔203的形成。 [0035] In one embodiment, the mask layer may be used to facilitate the initial formation of the cavity 203. 例如,第二层202上可形成一掩模层,其上形成有一系列间隔的孔。 For example, a mask layer may be formed on the second layer 202, a series of spaced holes formed thereon. 在一个实施例中,掩模中的孔可以是规则间隔和均匀尺寸的,或根据需要可以是尺寸和间隔变化的图案。 In one embodiment, the mask apertures can be of uniform size and regular intervals, as needed, or may be a pattern of size and spacing variation. 例如,感光材料层形成在第二层202的上表面上,选择性地暴露至照明源以形成曝光图案,然后显影以在第二层202上形成光掩模。 For example, the photosensitive material layer is formed on the upper surface of the second layer 202 is selectively exposed to an illumination source to form an exposure pattern, and then developed to form a second layer 202 on the photomask. 取决于实施方式,这个感光材料层可以是可移除的,在有些实施例中,可以是永久性的。 Depending on the embodiment, the photosensitive material layer may be removable, in some embodiments, may be permanent. 另外,该感光材料层可包括各种各样的正反光阻材料,例如,本领域技术人员所知道的。 Further, the photosensitive material layer may comprise a wide variety of positive and negative photoresist materials, e.g., those skilled in the art will know.

[0036]然后,扫描仪或光刻机(或其他曝光工具)用来选择性地照明感光层,以在感光材料层中限定指定的光掩模图案。 [0036] Then, the scanner or lithography (or other exposure tool) is used to selectively illuminate a photosensitive layer to define the mask pattern specified in the photosensitive material layer. 在一个实施例中,图案的特定部分具有孔,孔基本相同且具有均匀间隔,以形成一种期望类型的光掩模层。 In one embodiment, a specific portion of the pattern having a hole having substantially the same and evenly spaced holes to form a desired type of mask layer. 在一种方法中,ASML 1250Twin扫描可用来对光阻材料成像,许多其他的也可以。 In one approach, ASML 1250Twin scanning may be used to image the photoresist material, it may be many other.

[0037]在一个实施例中,光掩模孔可以为大约90nm宽,且间隔大约90nm。 [0037] In one embodiment, the mask aperture may be approximately 90nm wide and spaced approximately 90nm. 然而,专利权人仔细考虑了结合任何期望尺寸或间隔的孔的实施例。 However, the patentee contemplates embodiments in combination with any desired pore size or spaced. 一般来说,这仅仅受到具体工具工艺包迹和最终纳米点阵列的尺寸需求的限制。 Generally, this is limited only by the size requirements of the specific process tool and the final envelope nano dot array. 因此,对于间隔和尺寸不存在真正的限制,这是可以用光感工具来实现的。 Therefore, for the spacing and size of the real limitation does not exist, it is possible to achieve a sense of light tool.

[0038]如上文所指出的,在许多实施例中较小的孔是有利的。 [0038] As noted above, the smaller pores in many embodiments is advantageous. 另外,虽然基板一般用成堆的相似尺寸的孔以指定的规则间距来形成图案,本发明允许此种限制的宽松的变化。 Further, although the substrate generally hole piles of similar size to the specified regular intervals to form a pattern, such restrictions the invention allows loose change. 换句话说,根据需要,基板可使用各种各样的孔间间隔(即,并非基板上的所有间隔必须是相同的)以及各种各样的孔尺寸来形成图案。 In other words, according to need, a wide variety of substrates may be used between the hole pitch (i.e., not all of the spacing on the substrate must be the same) and a variety of pore size to form the pattern. 因此,可在同一基板(例如,200)上制造许多不同阵列轮廓。 Thus, the same substrate (e.g., 200) for producing an array of a number of different contour.

[0039]继续地,一旦光掩模在应有的位置上且被适当地形成图案,支撑件200被加工以在支撑件的表面上形成孔。 [0039] Continuing, once in position the photomask and the pattern is properly formed, is processed to form on the surface of the support member 200 of the support member bore. 在一个具体实施例中,执行蚀刻以至少从第二层202选择性地移除材料。 In one particular embodiment, the etch is performed to remove material from the second layer of at least 202 selectively. 一般来说,第二层202经由掩模层中的孔来蚀刻,以形成初始空腔203的期望图案。 Generally, the second layer 202 via the hole in the mask layer is etched to form a desired pattern 203 of the initial cavity.

[0040] 在一个特别有利的实施例中,各向异性蚀刻用以蚀刻第二层202,以产生具有初始空腔203的期望的蚀刻图案,初始空腔203具有期望的蚀刻轮廓。 [0040] In a particularly advantageous embodiment, the anisotropic etching for etching the second layer 202 to generate an initial etch pattern having a desired cavity 203, cavity 203 has an initial desired etch profile. 如本文所图示的,形成了一种基本直立壁的初始空腔203。 As herein illustrated, the cavities 203 form a basic initial upstanding wall. 定向蚀刻方法通常用来实现期望的初始空腔203。 Directional etching method is usually used to achieve a desired initial cavity 203. 例如,可以使用等离子蚀刻、反应离子蚀刻(RIE)、深反应离子蚀刻(DRIE)和其他定向蚀刻技术。 For example, plasma etching, reactive ion etching (the RIE), deep reactive ion etching (the DRIE) and other directional etching techniques. 这种各向异性蚀刻可提供深而精确的初始空腔203。 This anisotropic etching may provide an accurate initial deep cavity 203. 在一个特定的实施例中,可以1:1的纵横比来形成初始空腔203,虽然也可以使用其他比例。 In a particular embodiment, it may be 1: 203 to form the original aspect ratio of the cavity 1, although other ratios may be used. 因此,在一个实施例中,空腔203被蚀刻至深度206,深度206至少与空腔的初始宽度204-样大。 Thus, in one embodiment, the cavity 203 is etched to a depth of 206, and the initial depth of at least 206 204- large as the width of the cavity. 然而,其可以是更深的。 However, it may be deeper. 应指出,可以一直向下蚀刻到下面的基板202,且在有些实施例中有明确的理由来这么做,正如在本发明下文中将要公开的。 It should be noted that it has been etched down to the underlying substrate 202, and a clear reason to do so in some embodiments, as will hereinafter be disclosed in the present invention. 向下蚀刻至基板的一个优点是:实现了横跨圆片且在圆片之间的更均匀的刻蚀深度。 One advantage is etched down to the substrate: and to achieve a more uniform across the wafer between the etching depth of the wafer. 蚀刻均匀性由第二层与下面的基板之间的蚀刻选择性来补偿。 Etch uniformity is compensated by an etch selectivity between the second layer and the underlying substrate. 或者,所述空腔可形成在基板自身中。 Alternatively, the cavity may be formed in the substrate itself. 另外,在一些实施方式中,可以使用较浅的空腔203。 Further, in some embodiments, the shallow cavity 203 may be used. 在这个特定的实施例中,空腔初始宽度204大约为90nm,但是,如上所解释的,可以为许多其他宽度。 In this particular embodiment, the cavity 204 is approximately an initial width of 90 nm, but, as explained above, may be a number of other widths.

[0041] 返回一具体(非限制性)实施例(例如,如图2(b)_2(b')中所图示的),第二层202可以是Si02材料(或其他硅氧化物),其在第一层201上形成2000 A的深度。 [0041] Returns a specific (non-limiting) embodiment (e.g., FIG. 2 (b) _2 (b ') as illustrated), a second Si02 layer 202 may be a material (silicon oxide or other), depth of 2000 a is formed on the first layer 201. RIE蚀刻可用来形成间隔205达90nm的一系列初始空腔203,以使得空腔203具有90nm的初始宽度204,其在此处与90nm的深度成1:1纵横比。 RIE etch used to form a series of initial interval 205 of the cavities 203 of 90nm, so that the cavity 203 having an initial width of 204 90nm, 90nm depth which is here to be 1: 1 aspect ratio. 本发明还考虑到了许多其他轮廓(包括那些具有不同的纵横比)、几何形状、间距和其他参数。 The present invention also contemplates many other profiles (including those having different aspect ratios), geometry, spacing, and other parameters.

[0042]具体地,应指出,所描述的初始空腔203具有90nm宽度204的开口,但是也可以从大约90nm宽至大约160nm宽的范围。 [0042] Particularly, it should be noted that the described initial cavity 203 having an opening 204 90nm width, but may be from about 90nm to about 160nm wide width range. 应特别指出的是:本领域技术人员应理解,本发明考虑到了更宽的范围和尺寸(更窄和更宽)。 It should be particularly pointed out that: the skilled artisan will appreciate that the present invention contemplates a wider scope and size (narrower and wider). 而且,本领域技术人员应理解,除了指定的1:1纵横比, 也可以使用更宽范围的纵横比来形成期望的初始空腔203。 Further, those skilled in the art will appreciate, in addition to specifying the 1: 1 aspect ratio, can also be formed using a desired initial aspect ratio of the cavities 203 wider range. 另外,进一步指出的是,本领域技术人员应理解,可以实现超过1:1(空腔宽度:空腔之间的间距)的更宽范围的间距(部件(空腔203)之间的间距)。 Further, is further noted that those skilled in the art will appreciate, more than one may be achieved: 1: (the distance between the member (cavity 203)) (spacing width of the cavity between the cavities) wider range of pitch . 主要的限制是工艺限制和用来形成此种空腔203的工具的分辨率。 The main limitation is the process for forming resolution and the limitations of such a cavity 203 of the tool.

[0043]本发明进一步考虑到将第二层202用作感光层,其可被简便地形成图案和显影,以获得期望的初始空腔203。 [0043] The present invention is further contemplated that the second layer 202 serves as a photosensitive layer, which pattern can be easily formed and developed to obtain a desired initial cavity 203. 在此种实施方式中,不必移除层202。 In such an embodiment, the layer 202 does not have to be removed.

[0044] 参阅图2(c)并继续参阅图1,在初始空腔203中形成修整层211,以调整空腔的宽度来形成修整空腔212(步骤105)。 [0044] Referring to Figure 2 (c) and continue to refer to FIG. 1, layer 211 is formed in the initial dressing cavity 203 in order to adjust the width of the cavity to form a dressing cavity 212 (step 105). 修整层211由薄的介电材料共形层形成,该介电材料共形层对下面的第二层202的材料具有良好的粘附性,或与下面的第二层202的材料兼容。 Layer 211 is trimmed by a thin conformal layer of dielectric material is formed, the conformal layer of dielectric material having a good adhesion to the underlying second material layer 202, or compatible with the material of the underlying second layer 202. 这个薄的共形层211用来选择性地窄化(或修整)初始空腔203的宽度。 The thin conformal layer 211 to selectively narrowed (or trim) the cavity 203 of the initial width. 此层211共形至介电层202的表面,且特别地,共形至初始空腔203的轮廓,因而形成在初始空腔203的内壁上。 This layer 211 is conformal to the surface of the dielectric layer 202, and in particular, the initial conformal to the contour of the cavity 203, thereby forming on the inner wall of the cavity 203 of the original. 重要的是, 沉积工艺是高度可控的,因此,可高度地控制层211的厚度,以能够形成高度均匀厚度的薄层211。 Importantly, the deposition process is highly controllable, and therefore, the thickness of the layer 211 may be highly controlled, to be able to form a thin layer 211 of highly uniform thickness. 重要的是,虽然此层可以是极其薄的,它们也可以形成更大的厚度,使得该工艺能够形成具有各种各样厚度的层211。 Importantly, although this layer may be extremely thin, they may also form a larger thickness, so that the process is capable of forming a layer 211 having various thicknesses.

[0045] 因此,层211共形地安置在初始空腔211内,以提供使空腔203变窄至期望宽度的修整件(即,侧壁),该期望宽度为随后形成的纳米点限定了宽度。 [0045] Thus, the layer 211 conformally disposed within the initial cavity 211 to provide that the cavity 203 is narrowed to the desired width of the trimmer (i.e., sidewall), which defines the desired width of the subsequently formed nanodots width. 因此,共形层211限定了安置在每个初始空腔203内的侧壁,以使得侧壁将初始宽度204变窄至具有修整宽度213的更窄的修整空腔212(也限定了纳米点布置位置212)。 Accordingly, conformal layer 211 defines a cavity disposed within each of the initial sidewall 203, so that the initial width of the sidewall 204 is narrowed to have a width 213 is narrower trimmed dressing cavity 212 (also defines nanodots arrangement position 212). 因此,随着修整层211制作的更厚,修整空腔212变的更窄(参见213)。 Thus, as the thicker layer 211 made of trimming, trimming becomes narrower cavity 212 (see 213).

[0046] 因此,该工艺(步骤105)包括形成覆盖了初始空腔203内壁共形的修整层211,基本均匀的修整层211从而形成了变窄的修整空腔212,修整空腔212限定了具有期望宽度213的纳米点布置位置212。 [0046] Accordingly, the process (step 105) comprises forming a finishing layer covering the inner walls of the cavities 203 initial conformal 211, substantially uniform trim layer 211 to form a narrowed dressing cavity 212, cavity 212 defines a dressing 213 having a desired width 212 nano dot placement locations. 此种修整空腔基于高度均匀的初始空腔202形状和尺寸,以形成更窄的修整空腔212,修整空腔212也具有对每个修整空腔来说基本相等的尺寸和形状。 Such dressing cavity 202 based on a highly uniform shape and size of the initial cavity to form a narrower dressing cavity 212, cavity 212 also has a trimming substantially equal to each cavity is sized and shaped dressing.

[0047] 可使用各种各样的工艺来获得期望的共形层211。 [0047] The various processes may be used to achieve the desired conformal layer 211. 甚至是可在高纵横比的初始空腔203中形成修整层211。 Even trim layer 211 may be formed in an initial high aspect ratio cavities 203 in. 在一个实施例中,PECVD工艺可用来将合适的材料沉积在初始空腔203的表面上,以形成共形层211。 In one embodiment, PECVD process can be used a suitable initial material is deposited on the surface of the cavity 203 to form a conformal layer 211. 例如,在一个实施例中,可使用二氧化硅修整层211。 For example, in one embodiment, may be trimmed using a silica layer 211. 因此, PECVD工艺可用来形成期望的Si02层211,以建立合适的修整空腔。 Thus, PECVD process is used to form the Si02 layer 211 is desired to establish a suitable dressing cavity. 在一个实例中,诺发的Vector Express PECVD平台可用来形成合适的薄膜。 In one example, Novellus Vector Express PECVD platform may be used to form a suitable film. 也可以使用其他的PECVD相关技术。 You can also use other PECVD technologies. 原子层沉积(ALD)也可以用来形成合适的层211。 Atomic layer deposition (ALD) may be used to form a suitable layer 211. 也可以使用高温氧化(ΗΤ0)工艺LPCVD,以及其他工艺。 High temperature oxidation may also be used (ΗΤ0) process LPCVD, and other processes. 具体地,本发明不限于实例性材料、机器或具体表达的工艺。 In particular, the present invention is not limited to the exemplary material, the machine or process specific expression.

[0048]在一个实例中,具有大约90nm初始宽度204的初始空腔203被加工,以在第二层202 上形成20nm厚的共形层211。 [0048] In one example, the initial cavity having an initial width of about 90nm 203 to 204 are processed to form on the second layer 202 20nm thick conformal layer 211. 因为这个相同的层211安置在初始空腔的侧壁上,修整空腔212 的宽度213变的更窄。 Because the same layer 211 disposed on a sidewall of the initial cavity 213 of trimming the width of the cavity 212 becomes narrower. 因此,在这个实例中,具有形成在其上的20nm厚修整层的90nm宽的初始空腔将开口变窄至50nm。 Thus, in this example, the cavity having an initial width 90nm 20nm thick layer is formed on the trim of the opening thereof is narrowed to 50nm. 因此,使用这个工艺可制得远远比通常可能情况更窄的空腔。 Thus, this process can be obtained using much narrower than the cavity may generally be the case. 此处,窄的50nm宽度213的修整空腔212被认为是非常有利的。 Here, 50nm narrow cavity dressing 213 212 is considered to be highly advantageous. 如上文所指出的,本发明进一步考虑到了具有甚至更窄的213的修整空腔212的实施例。 As noted above, the present invention further contemplates embodiments of the narrower cavity 213 of the dressing 212 having even.

[0049] 参阅图2(d)、2(e)和5(a)并继续参阅图1,在修整空腔212中形成填充层(214)(步骤107)。 [0049] Referring to Figure 2 (d), 2 (e) and 5 (a) and continue to refer to FIG. 1, a filling layer (214) (step 107) in the cavity 212 of the dressing. 有许多方法可用来形成这个层214。 There are many ways to form the layer 214. 在一种方法中,填充层214可通过沉积、无电沉积、电镀以及其他方法使用期望的填充材料来形成。 In one process, the filling layer 214 by deposition, using a desired filler electrodeposition, electroplating, and other methods to form. 此层214至少填充了空腔212的一部分。 This layer 214 at least a portion of the cavity 212 is filled. 经过随后选择性地移除填充层214的部分(参见,步骤109),可形成塞子215(这个视图中未图示)(参见,例如图3(a)-3(b)。因此,一般来说,层214应是共形的,且在修整空腔212中具有良好的覆盖率。特别有利的工艺是:在填充过程中,具有良好的台阶覆盖性,且不会使修整空腔212封闭。 After section (see step 109) the filling layer 214 is then selectively removed, the plug 215 may be formed (not shown in this view) (see, e.g. FIG. 3 (a) -3 (b). Accordingly, Generally He said conformal layer 214 should be, and has good coverage cavity 212 during the trimming process is particularly advantageous: during filling, a good step coverage, does not cause the dressing cavity 212 is closed .

[0050] 在几种合适的实施方式中,使用厚度大约为空腔212的深度的1.5-2.0倍的层来形成填充层214。 [0050] In several embodiments a suitable embodiment, the filling layer 214 is formed using 1.5-2.0 times the depth of the cavity 212 of a thickness of about. 许多不同的金属可用来形成层214。 Many different metal layer 214 may be used to form. 在等离子体实施方式中,提供良好响应的材料是优选的。 In the embodiment described plasma, a material to provide a good response is preferable. 实例包括,但不限于金(Au)、铂(Pt)、钯(Pd)以及其他。 Examples include, but are not limited to, gold (Au), platinum (Pt), palladium (Pd), and others. 在一个特定的实施例中,使用金层214是优选的。 In one particular embodiment, a layer 214 of gold is preferable. 在任何情况下,可使用许多不同的方法,将此种材料沉积在表面上,特别是沉积进修整空腔212。 In any case, a number of different methods can be used, such material is deposited on the surface, especially the whole training deposition cavity 212. 在一个实施例中,使用蒸发沉积工艺来沉积金材料。 In one embodiment, the evaporative deposition process used to deposit gold material. 此种工艺可抵抗"面包块(bread loafing)",以及可能妨碍一些其他技术的其他沉积限制。 Such a process may resistance "loaf (bread loafing)", and may interfere with other deposition techniques other limitations. 特别地指出,也可以使用许多其他方法,如上所述的,其中一个重要的特征是:获得良好的覆盖度, 且在修整空腔中形成的材料中不存在封闭空间,或至少此种空间被最小化。 Particularly he noted that many other methods may be used, as described above, one of the important features are: to achieve good coverage, and the absence of material in the closed space formed in the cavity in the trim, or at least such a space minimize.

[0051] 在另一个实施例中,参阅图2(e)描述,晶种层可用来促进该工艺。 [0051] In another embodiment, see FIG. 2 (e) is described, the seed layer may be used to facilitate this process. 例如,一旦形成晶种层213,电镀(或无电镀的)工艺可用来完成形成此种填充层214。 For example, once formed, the seed layer 213, plating (or electroless plating) process may be used to complete the filling layer 214 is formed such. 图2(e)简要地图示了布置在第二层202上的晶种层213。 FIG. 2 (e) schematically illustrates a seed layer 213 is disposed on the second layer 202. 可进一步选择此种晶种层213,以除了有利于形成填充层214外,还增强对下面的基板200及特别是空腔中的层211的粘附性。 May be further selected such seed layer 213, except to facilitate the formation of the filling layer 214, also enhance adhesion to the underlying and in particular the substrate 200 layer cavity 211. 合适的晶种层的非限制性实例包括镍(Ni)、钛(Ti)、铂(Pt)、钯(Pd)、金(Au)以及其他。 Suitable non-limiting examples of the seed layer comprises nickel (Ni), titanium (Ti), platinum (Pt), palladium (Pd), gold (Au), and other. 合金,或在某些情况下非常薄的层压板也可以使用。 An alloy, or in some cases a very thin laminates can also be used. 晶种层213通常形成的非常薄,大约几埃(A)到几纳米。 The seed layer 213 is generally formed of very thin, about several angstroms (A) to a few nanometers. 可使用许多层形成方法,包括但不限于:ALD、PECVD、蒸发沉积及其他方法。 The method of forming a plurality of layers may be used, including but not limited to: ALD, PECVD, evaporation deposition, and other methods. 特别指出的是,"晶种"层213可以简单地为一种粘附性增强材料,该粘附性增强材料与修整层211和填充材料214两者均具有良好的粘附性质。 In particular, the "seed" layer 213 may be simply as a reinforcing material adhesion, the adhesion reinforcing layer of finishing material and the filling material 214 and 211 both have good adhesion properties. 因此,其作为电镀晶种层的用途并非普遍化的,而是仅包括一种实施方式。 Thus, as a plating seed layer is not a generalized use, but comprising only one embodiment.

[0052] 在一个优选实施例中,大约5A厚的钛晶种层213形成在支撑件200上,特别是在修整层211的表面上。 [0052] In a preferred embodiment, a thickness of about 5A titanium seed layer 213 is formed on the support member 200, particularly on the surface modification layer 211. 如图2(e)所示,一旦在适当位置,然后填充层214可电镀至晶种层213上。 As shown in FIG 2 (e), once in place, and then the filling layer 214 may be electroplated onto the seed layer 213. 如上所述,也可以使用无电镀的工艺。 As described above, the electroless plating process may also be used. 在这个实施例中,填充材料可以是金材料,且具有厚度大约为空腔212深度1.5-2.0倍的层214。 In this embodiment, the filler material may be gold, and a layer 214 having a thickness of approximately 1.5-2.0 times the depth of the cavity 212. 在这个包括80nm深的空腔212的实例中,可以使用厚度范围在120-160nm的层214(虽然本发明考虑到了更宽的宽度范围)。 In this example comprises a cavity 212 of depth 80nm may be used in the layer thickness in the range of 214 120-160nm (although the present invention contemplates a wider width).

[0053]现返回图1的流程图,自填充层形成纳米点塞子(步骤109)。 [0053] Returning now to the flowchart of FIG. 1, is formed from the nano dot layer filling plug (step 109). 因此,一旦形成填充层214(例如,如图2(d)-2(e),从填充层214(在某些情况下为修整层211)选择性地移除材料, 以形成塞子215。可使用许多不同的方法来形成塞子215。所有方法都是用来形成塞子215阵列。 Thus, once the filling layer 214 (e.g., FIG. 2 (d) -2 (e), the filling layer 214 (and in some cases to trim layer 211) selectively removing material to form a plug 215. can to form a plug 215. a number of different methods are all methods for forming the stopper 215 array.

[0054] 在一种方法中,例如图3(a)(以及可应用于图2(d)和图2(e)所示实施例,以及其他附图)中所图示的,移除填充层214的上部,从而形成由相关联的空腔和修整层以精确可重复的尺寸限定的塞子315阵列。 [0054] In one method, for example in FIG. 3 (a) (Example, as well as other drawings, and may be applied to FIG. 2 (d) and 2 (e) illustrated embodiment) as illustrated, the filling is removed an upper layer 214, the stopper 315 so as to form an array of cavities and associated finishing layer in a precise repeatable defined size. 例如,在一个实施例中,移除填充层214的上部,直到至少修整层211的上部被暴露。 For example, in one embodiment, the upper fill layer 214 is removed, until at least the upper portion of the dressing layer 211 is exposed. 因而,形成了不连续的塞子315的阵列。 Thus, the formation of a discontinuous array of plug 315. 使用金填充层214的情况下, 金选择性的CMP工艺可用来移除期望量的填充材料214。 The case where the filler layer 214 of gold, gold selective CMP process used to remove the desired amount of filler material 214. 特别指出的是,可以使用其他材料移除工艺。 Of particular note is, you can use other material removal processes. 具体地,此种移除工艺高度依赖于塞子315材料、修整层211材料,以及(在某些情况下)第二层202的材料。 Specifically, such a removal process is highly dependent on the stopper material 315, 211 trim material layer, and (in some cases) of the second material layer 202. 应注意的是,在这个具体描述的工艺中,修整层211的剩余部分仍暴露在基板200的表面上,一般来说,在平坦表面上留下了多个规则间隔和规则尺寸的塞子315。 It is noted that, in this particular process described herein, the remaining portion of the dressing layer 211 is still exposed on the surface of the substrate 200, in general, it left on the flat surface 315 plugs regular intervals and a plurality of regular sizes. 重要的是,应认识到,由于修整工艺(与现有技术大不相同)的精确本质,塞子的尺寸和形状可以几乎是相等的。 Importantly, it is appreciated that, due to the trimming process (very different from the prior art) the exact nature, size and shape of the plug may be nearly equal. 同样重要的是,应认识到,部件(塞子315)之间的间距也可以是规则的且一致的(几乎相等)(也与现有技术大不相同)。 Equally important, it should be appreciated that the spacing between the members (the stopper 315) may be a regular and consistent (substantially equal) (also very different from the prior art).

[0055] 在另一种相关的方法中,除了移除填充层214的上部之外,可以移除整个修整层211 (或其部分)。 [0055] In another related method, in addition to the upper filling layer 214 is removed outside, can be trimmed to remove the entire layer 211 (or portion thereof). 另外,在一种相关的方法中,相似地,可移除支撑件200的一部分(例如,第二层202的上部)。 Further, In a related approach, similarly, part of the support member 200 may be removed (e.g., an upper portion of the second layer 202). 在一种实施方式中,可根据需要使用CMP工艺来移除填充材料以及其它材料。 In one embodiment, the filling material can be removed using a CMP process and other materials as needed. 因此,此外,移除材料直到形成不连续的分离的塞子315,该工艺可用来移除材料,直到上层202的一部分也被移除。 Thus, in addition, a discontinuous removal of material until a separate plug 315, the process used to remove material until the upper portion 202 is also removed. 另外,此种工艺通过暴露塞子315的一部分限定了精确、可重复的塞子。 Further, this process is performed by exposing a portion of the plug 315 defines a precise, repeatable plug.

[0056] 应指出的是,可以使用用于形成塞子315的其他方法,以使得表面和塞子具有不同的最终构造。 [0056] It should be noted that other methods may be used for forming the stopper 315, so that the surface of the plug having a different final configuration. 例如,如图2(e)、3(a)和图3(b)所图示的,可以释放上修整层211的剩余部分。 For example, FIG. 2 (e), 3 (a) and 3 (b) are illustrated, the remainder of the dressing may release layer 211. 因此,移除填充层的上部,以使得修整层不再连续。 Thus, the upper fill layer is removed, so that the dressing is no longer a continuous layer. 例如,使用金填充层(例如,图2(e)的214),金选择性CMP工艺可用来移除期望量的填充材料。 For example, gold filling layer (e.g., FIG. 2 (e) 214), the selective metal CMP process used to remove the desired amount of filler material. 如上文所指出的,此种移除工艺可能高度依赖于塞子215材料(即,填充层214),修整层211材料,以及(在有些情况下)第二层202的介电材料。 As noted above, this removal process may be highly dependent on the material of the stopper 215 (i.e., the filler layer 214), dressing material layer 211, and (in some cases) a second dielectric material layer 202. 此处,可执行金选择性CMP工艺,直到修整层211被从上层202完全或基本移除,留下金作为带有暴露侧壁315s的塞子315(图3(a))。 Here, gold perform selective CMP process until the dressing 202 from the upper layer 211 is substantially or completely removed, leaving the exposed metal with a sidewall 315s of the plug 315 (FIG. 3 (a)). 由于塞子在第二层202之上延伸,通过移除修整层211的上部,现塞子315包括凸起的表面。 Since the plug 202 extends over the second layer, trimming by removing the upper layer 211, the stopper 315 now comprises a convex surface. 因此,塞子侧壁315s被暴露。 Thus, the plug is exposed sidewall 315s. 在任何情况下,在塞子315上形成了稍微更大的暴露的塞子表面面积。 In any case, the stopper 315 is formed on the stopper slightly larger surface area exposed. 另外,塞子的尺寸和形状几乎是相等的(与现有技术大不相同)。 Further, the size and shape of the plug are nearly equal (with the prior art very different). 同样重要的是,应认识到,部件(塞子315)之间的间距也可以是规则的(几乎相等(也与现有技术大不相同))。 Equally important, it should be appreciated that the spacing between the members (the stopper 315) may also be regular (almost equal (also very different from the prior art)). 应指出的是,因为使用了不同的材料,可以使用不同的蚀刻剂、抛光剂和方法来获得期望的塞子315。 It is noted that, because of the use of different materials, different etchants can be used, a polishing agent and a method to achieve the desired plug 315.

[0057] 在另一个实施例中,展示和描述了其他装置和相关联的制造方法。 [0057] In another embodiment, shown and described a method of manufacturing and other associated apparatus. 图4是图示用于形成相关类型纳米点阵列的方法的流程图。 FIG 4 is a flowchart illustrating a method for forming the nano dot array associated type.

[0058] 参阅图4和图5(a),描述了第一个实施例。 [0058] Referring to FIG. 4 and FIG. 5 (a), first described embodiment. 如前文所述,提供或形成了一机械弹性支撑件(步骤401)。 As previously described, there is provided a mechanical or form a resilient support member (step 401). 此处,第一层501具有形成在其上的有图案的第二层502。 Here, the first layer 501 has formed thereon a patterned on the second layer 502. 另外,在大多数实施方式中,第一层501是可以支撑将由这个工艺形成的整个纳米点阵列的机械弹性结构层。 Further, in most embodiments, the first layer 501 is a mechanical support layer may be resilient structure formed by the whole of this process the nano dot array. 在一个实例中,可使用如上所述的实施例。 In one example, the embodiment described above may be used. 例如,第一层501可由任何合适的材料形成。 For example, the first layer 501 may be formed of any suitable material. 例如,可以使用硼硅玻璃(BSG)、石英、石英玻璃和其他材料。 For example, a borosilicate glass (BSG), quartz, quartz glass, and other materials. 然而,如前文所述,实际上,可以使用半导体加工中使用的任何材料。 However, as previously described, in fact, any material used in semiconductor processing. 一个特别有利的实施例使用硅片作为机械性坚固基板501。 A particularly advantageous embodiment uses a silicon wafer as a substrate 501 mechanically robust. 如上文(和其他处)所讨论的,金属层和层压多层材料可用来形成第一层501。 As described above (and elsewhere) in question, and a metal layer laminated multilayer material used to form the first layer 501. 在任何情况下,此种层可由现有的晶片制造方法和工具使用标准的晶片尺寸来形成。 In any case, such layer is formed by a conventional wafer manufacturing methods and tools using standard wafer sizes.

[0059]该支撑件包括形成在第一层501上的第二层502。 [0059] The support member 502 includes a second layer formed on the first layer 501. 如前文所述,第二层502可以是由许多有机或无机材料(例如,介电材料层)形成的电绝缘层。 As before, the second layer 502 may be an electrically insulating layer is made of many organic or inorganic material (e.g., dielectric material layer) is formed. 可以使用类似的材料,诸如那些用来形成如上所述的第二层202,以及许多其他材料,这取决于所期望的薄膜性质。 Similar materials may be used, such as those used to form 202, and many other second layer material as described above, depending on the desired film properties.

[0060] 如前文所述,第二层502可形成大约100A(埃)至大约5000A的厚度。 [0060] As previously described, the second layer 502 may be formed about IOOA (Angstroms) to a thickness of about 5000A. 一个优选的范围是在大约1000.A至大约3000A厚度,一个合适的实施例具有大约2000A的厚度。 A preferred range is from about 3000A to about 1000.A thickness, a suitable embodiment of a thickness of about 2000A.

[0061] 应指出的是,预形成的具有第一和第二层(501、502)的晶片可从第三方供应商获取,而不一定形成本发明的部分,但是可在可选的实施例中如此做。 [0061] It should be noted that the wafer having first and second layers (501, 502) is preformed available from third-party vendors, without necessarily forming part of the present invention, but in alternative embodiments may be in doing so.

[0062]继续参阅图4和图5(a),在第二层502中形成初始空腔503(步骤403)。 [0062] Referring to FIG 4 and FIG. 5 (a), the initial cavity 503 is formed (step 403) in the second layer 502. 在多数情况下,其不会是单独的空腔503,而是规则间隔和相似尺寸的空腔503的阵列,或者是变化的空腔尺寸和间距的图案。 In most cases, it does not separate the cavity 503, the cavity 503 of the array of regularly spaced and of similar size but of, or change in the cavity size and spacing of the pattern. 由于使用了半导体工艺,且初始空腔503的尺寸在常规加工工具的工艺包迹内,可形成极其精确的图案,空腔503之间具有优良的规则性和间隔。 The use of the semiconductor process, and the initial size of the cavity 503 within the process tool conventional processing envelope, extremely precise pattern can be formed, having excellent regularity and the spacing between the cavity 503.

[0063]如上所述,在一些实施例中,一掩模层可以被形成、照明和显影以在第二层502上形成光掩模图案。 [0063] As described above, in some embodiments, a mask layer may be formed, and developed to the illumination layer 502 is formed on the second mask pattern. 一般来说,该光掩模具有均匀尺寸的规则间隔开口的图案,以根据本领域技术人员所知的方法形成期望的掩模图案。 Generally, the rule photomask having an opening pattern of uniform size interval, to form a desired mask pattern in accordance with methods known to the skilled person. 因此,在一个实施例中,根据设计者的需要,该掩模可包括基本相同开口或以不同间距间隔的不同尺寸开口的规则图案。 Thus, in one embodiment, according to the designer's needs, the mask may comprise substantially the same as a regular pattern of openings of different sizes or to different pitch distance of the openings. 在这个实例中, 开口可间隔大约90nm,但是在尺寸和间距方面不存在限制。 In this example, the opening may be spaced approximately of 90 nm, but is not limited in the present aspect of the size and spacing.

[0064] 一旦形成图案,第二层502被处理以从第二层502移除材料来形成初始空腔503,初始空腔503-直向下延伸至下面的第一层501,第一层501包括一种与上述实施例的区别。 [0064] Once the pattern is formed, the second layer 502 is processed to be formed from the second material layer 502 is removed first layer 501 extends the initial cavity 503, the initial vertical cavity 503- to below, the first layer 501 comprising one difference from the above embodiment. 例如,各向异性蚀刻用来蚀刻第二层502以获得基本直立的壁的初始空腔503,初始空腔503 相对深地穿过第二层502以暴露在下面的第一层501。 For example, an anisotropic etch used to etch the second layer 502 to obtain an initial cavity substantially upright wall 503, an initial relatively deep cavity 503 through the second layer 502 to expose the underlying first layer 501. 因此,根据本发明的原理可获得非常大的高宽比。 Therefore, a very high aspect ratio according to the principles of the present invention. 例如,在一个非限制性实施例中,可以向下蚀刻90nm宽的开口至2000人(200nm)深的第一基板表面。 For example, in one non-limiting embodiment, may be etched down to 90nm wide opening 2000 (200 nm) of the depth of the first substrate surface. 当然,考虑到了许多其他轮廓,包括深的多的空腔,或者根据需要远没那么深的空腔(例如,如相对上述实施例解释的)。 Of course, considering the many other profile, comprising a plurality of deep cavities, or required far less deep cavity (e.g., with respect to the embodiment as explained above). 因此,如前文所述,定向蚀刻方法可用来实现期望的初始空腔503。 Thus, as previously described, directional etching method may be used to achieve the desired initial cavity 503. 例如如前文建议的,可以使用包括(但不限于)等离子蚀亥|J、RIE、DRIE和其他定向蚀刻技术的实例。 As previously suggested, for example, may be used include (but are not limited to) plasma etching Hai | Examples J, RIE, DRIE, and other directional etching techniques.

[0065] 诸如上文所讨论的轮廓、间距、纵横比、几何形状以及其他特征和参数可用于各种实施例中,以在第二层502中形成图案或形成初始空腔503。 [0065] such as an outline, as discussed above, the pitch, the aspect ratio, the geometry and other features and parameters may be used in various embodiments, to form a pattern in the second layer 502 or 503 forming an initial cavity.

[0066] 然后,如上文所述的执行修整工艺。 [0066] Then, as described above is performed trimming process. 因此,修整了初始空腔(步骤405)。 Thus, trimming the initial cavity (step 405). 参阅图5 (b),在初始空腔503中形成修整层511,以调整空腔503的宽度来形成修整空腔512。 Refer to FIG. 5 (b), layer 511 is formed in the initial dressing cavity 503 in order to adjust the width of the cavity 503 of the cavity 512 formed dressing. 共形的修整层511通常是薄的绝缘材料(例如,介电材料)共形层,其与下面的第二层502以及第一层501相兼容,并选择性地使得初始空腔503的宽度变窄。 Trimming conformal layer 511 is generally thin insulating material (e.g., dielectric material) conformal layer, which is compatible with the underlying second layer 502 and first layer 501, and selectively so that the initial cavity width 503 narrows. 如前文所述,层511的厚度可以被很好地控制,使得能够形成高度均匀厚度的层511,从而很好地限定修整空腔512的尺寸以及随后形成的纳米点的宽度。 As previously described, the thickness of the well layer 511 can be controlled, enabling the formation of a highly uniform thickness of layer 511, so that well-defined width dimension of the cavity 512 and the trimming nano dot subsequently formed. 类似的工艺可用来形成这个层511,如用来形成上述的共形层211。 Similar processes may be used to form the layer 511, as described above for forming a conformal layer 211. 因此,可使用各种各样的方法来形成第二层511,以形成合适的第二层511。 Thus, the second layer 511 may be formed using a variety of methods, suitable to form a second layer 511.

[0067] 一个示例性实施例包括具有大约90nm的初始宽度505和20nm厚度的共形层511的初始空腔503,从而限定了变窄至50nm的修整空腔512。 [0067] An exemplary embodiment includes a width 505 and having an initial thickness of about 20nm 90nm of a conformal layer of initial cavities 503,511 so as to define a narrowing of the cavity 512 to 50nm dressing. 如已经解释的,修整空腔可被形成许多不同尺寸,且可被制成窄的多。 As already explained, the trimming cavity may be formed in many different sizes, and can be made more narrow. 例如,可根据本发明的原理有利地形成20nm宽度505的空腔512(或更小)。 For example, a cavity may advantageously be 512 20nm width 505 in accordance with principles of the present invention (or less).

[0068]继续地,图5(b)和(c)象征性地图示了形成另一种修整层实施例的一个实例。 [0068] Continuing, FIG. 5 (b) and (c) a symbolically illustrates another example of forming the finishing layer of Example. 在这个实施例中,然后在修整层511上执行各向异性蚀刻531,以移除修整空腔512的底部,暴露修整空腔512中的下面的第一层501(步骤407)。 In this embodiment, the trimming is then performed on the layer 511 an anisotropic etch 531 to remove the bottom of the cavity 512 of trimming, trimming the exposed first layer 501 below the cavity 512 (step 407). 优选地,此种各向异性蚀刻531的定向本质在修整空腔的底部移除了修整层511的底部,而没有从空腔侧壁移除修整材料,从而暴露了机械弹性第一层501的上部。 Preferably, such an anisotropic etching oriented nature of the cavity 531 in the bottom of the dressing removal layer 511 of the bottom dressing, and the dressing without removing material from the sidewalls of the cavity, thereby exposing a first mechanical layer 501 is an elastic the upper part. 而且,可从第二层502的上表面移除修整层511,如图5(c)中所示的。 Further, layer 511 may be removed from the trimmed surface of the second layer 502, as shown in FIG. 5 (c) of.

[0069] 在一些非限制性实例中,这种定向蚀刻5 31可包括等离子蚀刻、反应离子蚀刻(RIE)、深反应离子蚀刻(DRIE)以及一系列其他定向蚀刻技术。 [0069] In some non-limiting examples, such a directional etch 531 may include plasma etching, reactive ion etching (the RIE), deep reactive ion etching (the DRIE) and a range of other directional etching techniques. 这种各向异性蚀刻531可提供一直向下至下面的基板501的深而精确的蚀刻(参见,例如,图5(c))。 This anisotropic etch 531 may be provided all the way down to the underlying substrate 501 is etched deep and accurate (see, e.g., FIG. 5 (c)).

[0070]在这一点上,可根据此种塞子形成工艺来将塞子材料沉积至修整空腔,如上文关于图2(d)_2(e)和图3(a)_3(b)所描述的。 [0070] In this regard, such a plug may be formed according to the process of the plug material is deposited to trim the cavity, as described above with respect to FIG. 2 (d) _2 (e) and 3 (a) _3 (b) described .

[0071]参阅图5(d)和5(e)并继续参阅图4来描述另一个实施例。 [0071] Referring to FIG. 5 (d) and 5 (e) and continues to refer to FIG. 4 illustrates another embodiment. 在一个示例性实施例中, 然后在修整空腔512内的修整壁表面511s上执行空腔成形工艺。 In one exemplary embodiment, the cavity forming process is then performed on the surface of the walls 511s finishing dressing cavity 512. 在一个这样的实施例中,执行该工艺,以形成修整侧壁511的轮廓。 In one such embodiment, the process is performed to form side walls 511 of the trimming profile. 在这个步骤中,执行各向同性蚀刻工艺521,以在修整侧壁511s中生成成形轮廓(参见,图5(e)(步骤409)。 In this step, an isotropic etch process 521, to generate the profiled contour trim sidewall 511s (see FIG. 5 (e) (step 409).

[0072] 在一种工艺中,针对侧壁511 s以变化的角度执行若干定向蚀刻步骤以创建一蚀刻图案,该蚀刻图案优选从侧壁的更中心部分51 lm蚀刻更多材料,而在靠近侧壁的底部51 lb 处更少地蚀刻,从而仔细地控制在已修整和成形的空腔515底部处的孔的尺寸。 [0072] In one process, the side wall 511 s for the angle change is performed in several steps to create a directional etch etching pattern, the etching pattern and more preferably from the center of the side wall portion 51 lm etched more material, and near the bottom side walls 51 lb less etched, thereby carefully controlling the size of the hole has been formed and trimmed at the bottom of the cavity 515. 由于此种蚀刻步骤的定向性质,修整空腔515的形状和尺寸可被高度地控制。 Since the nature of such directional etching step, trimming the shape and size of the cavity 515 can be highly controlled. 因此,此种各向同性蚀刻使空腔515成形,以使得已加工的侧壁具有弓形横截面,使得修整空腔的底部具有比侧壁的其他部分更小的横截面尺寸(例如,511m比511b更宽)。 Therefore, isotropic etching such that the cavity 515 shaped so that the processed side wall having an arcuate cross-section, so that the bottom of the cavity having a trim is smaller than the other portion of the sidewall cross-sectional dimension (e.g., more than 511M 511b wider). 因此,此种各向同性蚀刻在最终成形的侦幢515中形成了弓形轮廓。 Accordingly, such an isotropic etching investigation arcuate profile 515 final shaping of buildings. 因此,ϋ壁515的介电材料比底部的更厚(例如,如图5(e)中所图示的)。 Thus, the dielectric material ϋ thicker wall 515 (e.g., FIG. 5 (e) as illustrated) than the bottom. 弓形侧壁在结构成形中增加了柔韧性,可以潜在地提供锚定效应。 Arcuate sidewall configuration increases the flexibility in molding, may potentially provide an anchor effect.

[0073] 在一个实施例中,各向同性蚀刻可以通过改变角度执行为一系列定向蚀刻步骤521,在该角度处定向蚀刻侵蚀了修整侧壁511的材料。 [0073] In one embodiment, isotropic etching may be performed by changing the angle 521 as a series of directional etching step, eroding material trimmed directional etching in the side wall 511 at that angle. 此种变化的定向蚀刻被执行,以获得期望的最终侧壁(以及空腔515)形状。 Directional etching is performed such changes, to obtain the desired final side wall (515 and cavity) shape. 因此,在已修整和成形的空腔515处包括已限定和控制好的开口512,(在空腔515的底部)暴露了第一层501的一部分,以形成基板512a的暴露上部。 Thus, the cavity 515 has been trimmed and shaped comprising an opening defining a well 512 and a control, (the bottom of the cavity 515) exposing a portion of the first layer 501 to form an upper substrate 512a is exposed. 这种工艺可进一步用来根据需要从机械弹性第一层501的上部移除小量材料。 This process may further be used to remove small amounts of material from the upper portion of the mechanical elasticity of the first layer 501 as necessary.

[0074]参阅图5(f),在修整和成形的空腔515中形成纳米点填充层541。 [0074] Referring to FIG. 5 (f), the filling layer 541 is formed in the nano-dots trimming and forming of the cavity 515. 可使用许多不同的方法来形成纳米点填充层541。 Filling layer 541 may be formed using the nano-dots in many different ways. 实例工艺包括(但不限于)沉积和(伴随一些工艺调整)电镀一层纳米点填充材料。 Examples of the process include (but not limited to) the deposition and (with some processes adjustments) plating layer of nanodots filled material. 在任何情况下,虽然并非限制本发明的,纳米点填充层541的材料可沉积至空腔515内,以使得其依靠在成形的修整空腔515中的基板512a的暴露上部上。 In any case the material, although not limiting to the present invention, the nanodots filling layer 541 may be deposited to cavity 515, such that it relies on a substrate 512a of the cavity 515 formed in the trimming of the exposed upper portion.

[0075]在几种合适的实施方式中,填充层541被形成至大约丨〇〇-1000,4的期望的层厚度。 [0075] In several embodiments a suitable embodiment, the filling layer 541 is formed to a layer thickness of about 1000,4 Shu-thousand and desired. 许多不同金属可用来形成层541。 Many different metals used to form the layer 541. 如前文所述,实例可以包括,但不限于:金(Au)、铂(Pt )、钯(Pd)以及其他材料。 As described previously, examples may include, but are not limited to: gold (Au), platinum (Pt), palladium (Pd), and other materials. 在一个特定的实施例中,优选使用金层541。 In a particular embodiment, layer 541 is preferably gold. 由于蚀刻工艺(例如,步骤407和409)是如此可控,因而在第一基板501的暴露上部512a处可以获得极其好的尺寸和形状控制。 Since the etching process (e.g., steps 407 and 409) are so controlled, it is possible to obtain a very good control of size and shape of the upper portion 512a of the first substrate 501 is exposed. 这个位置512a可被容易且可预见地加工成大约10-100纳米范围。 This position 512a can be easily and predictably processed to range from about 10-100 nanometers.

[0076]在一个实例中,可使用许多不同的方法将填充材料541沉积至表面512a上。 [0076] In one example, a number of different methods may be used to fill material 541 is deposited onto the surface 512a. 例如, 可使用蒸发沉积工艺沉积金材料。 For example, a gold material evaporation deposition process. 成形的修整空腔515的大的敞开顶部被形成,以使得敞开的顶部被打开的足够宽以阻碍"面包块"和可能会妨碍填充层沉积技术的其他沉积限制。 Shaped open top dressing large cavity 515 is formed, so that the open top is wide enough to discourage open "loaf" and other deposition restrictions may prevent filling layer deposition techniques. 一般来说,填充材料541的层大约1 Onm至大约几百nm厚,优选大约50nm 〇 Generally, the filler material layer 541 is about 1 Onm to about hundreds of nm thick, preferably from about 50nm billion

[0077]在另一个实例中,可使用电镀(或无电镀)工艺来形成纳米点结构。 [0077] In another example, the nano dot structure may be formed using a plating (or electroless plating) process. 例如,一旦修整空腔被打开和成形,可在其中形成晶种层。 For example, once the trimming and molding cavity is opened, the seed layer may be formed therein.

[0078]继续地,参阅图4和图5,一旦已在空腔515中沉积纳米点填充材料541。 [0078] Continuing, FIG. 4 and FIG. 5, once it has been deposited in the cavity filling material nanodots 515 541. 可从表面移除第二层502,留下形成在第一层501表面上的纳米点542阵列(步骤413)。 The second layer 502 may be removed from the surface, leaving the array 542 is formed on the nanodots surface of the first layer 501 (step 413). 任何的构造或结构是可能的。 Any structure or structures are possible. 然而,在一种实施方式中,纳米点542的阵列包括一组规则间隔和尺寸的纳米点。 However, in one embodiment, the array 542 comprises nanodots nanodots a set of regularly spaced and sized.

[0079] 在一个实例中,通过CMP工艺可使得第二层502的移除更便利,CMP工艺在纳米点541材料和第二层502材料之间是有选择性的。 [0079] In one example, by a CMP process may remove the second layer 502 such that the more convenient, the CMP process at the point between 541 nanometers and the second material layer 502 is selective material. 执行此种工艺,直到第二层502基本或完全移除。 Such a process is performed, or until the second layer 502 is substantially completely removed. 移除第二层502的工艺可使用替代性工艺来执行,该替代性工艺可以选择性地移除第二层502的材料,而不会将纳米点材料移除至任何显著程度。 Removing the second layer 502 process may be used to perform alternative processes, the alternative process may selectively remove the second material layer 502, it will not remove the nano dot material to any significant degree. 也可以使用灰化和选择性蚀刻, 也可以使用用于选择性地移除第二层502的材料以在第一层501上留下规则间隔和尺寸的纳米点541的图案的方法,如图5(g)中大体所示的。 May also be used ashing and selective etching may also be used for the material of the second layer 502 is selectively removed to leave a method of nano dots 541 regularly spaced and the size of the pattern on the first layer 501, FIG. It is shown generally 5 (g) in.

[0080] 在另一个替代性实施例中,将展示和描述一种装置和相关的制造方法。 [0080] In another alternative embodiment, the shown and described an apparatus and associated method of manufacture. 图6是图示一种用于形成纳米点阵列的方法的流程图。 6 is a flowchart illustrating a method for forming a nano dot array.

[0081] 参阅图6和图7(a)_7(e),描述了下一个实施例。 [0081] Referring to FIG. 6 and FIG. 7 (a) _7 (e), described in the next embodiment. 开始,参阅图6和图7(a),支撑件被提供或形成(步骤601)。 Start, refer to FIG. 6 and FIG. 7 (a), the support member is provided or formed (step 601). 在一个一般性描述的实施例中,支撑件700被提供或形成。 In a general embodiment described, the support member 700 are provided or formed. 支撑件700包括第一层701,第二层702布置在其上,然后第三层703布置在第二层702上。 Support member 700 includes a first layer 701, second layer 702 disposed thereon, and a third layer 703 disposed on the second layer 702.

[0082]在大多数实施方式中,第一层701是可以支撑将由这个工艺形成的整个纳米点阵列的机械弹性结构层。 [0082] In most embodiments, the first layer 701 is a mechanical support layer may be resilient structure formed by the whole of this process the nano dot array. 第一层701可由任何材料形成,但是如上文所描述的,特定的材料比其他材料是更有利的。 The first layer 701 may be formed of any material, but as described above, the particular material is more advantageous than other materials. 例如,硼硅玻璃(BSG)、石英、石英玻璃和其他材料可被用作合适的第一层701。 For example, borosilicate glass (BSG), quartz, quartz glass, and other suitable materials may be used as the first layer 701. 如上,实际上,可以使用半导体加工中使用的任何材料。 As, in fact, any material used in semiconductor processing. 因此,如前文所述,硅片可用作第一层701的机械性坚固基板。 Thus, as previously described, may be used as the first silicon layer 701 is mechanically robust substrate. 重要的是,如将在下文的其他实例中所图示的,金属层和层压的多层材料也可用来形成第一层701。 Importantly, as will be illustrated below in other examples, the metal layer and the multilayer material may also be laminated to form the first layer 701. 在任何情况下,此种层可由现有的晶片制造方法和工具使用标准的晶片尺寸来形成。 In any case, such layer is formed by a conventional wafer manufacturing methods and tools using standard wafer sizes.

[0083]第二金属层702形成在第一层701上。 [0083] The second metal layer 702 formed on the first layer 701. 第二层702起作用以形成这种实施方式中使用的凹陷的纳米点。 The second layer 702 acts to form a recess nanodots used in this embodiment. 此种第二层702可以是形成在第一层701上的金属层。 Such a second layer 702 may be a metal layer formed on the first layer 701. 与上述纳米点所使用的相同的材料可用来形成金属层702。 The same material as used in the nano dot layer 702 may be used to form the metal. 因此,虽然可以使用许多此种金属层和金属层压结构,本发明还考虑到了以下材料,包括但不限于:镍(Ni)、钛(Ti)、金(Au)、铂(Pt)、钯(Pd) 以及其他合适的合金和层压板。 Thus, although many of these metals may be used, and a metal layer laminated structure, the present invention also contemplates the following materials, including, but not limited to: a nickel (Ni), titanium (Ti), gold (Au), platinum (Pt), palladium (Pd), and other suitable alloys and laminates. 如上所述,贵金属是优选的。 As described above, the noble metal is preferable.

[0084]在一个特定的实施例中,优选使用Pd第二层702。 [0084] In a particular embodiment, the second layer 702 is preferable to use Pd. 在任何情况下,可使用许多不同的方法将此种材料沉积到表面701上。 In any case, a number of different methods can be used to deposit such material onto the surface 701. 在一个实施例中,可使用本领域技术人员所知的许多方法来沉积Pd材料。 In one embodiment, using a number of methods known to those skilled in Pd deposited material. 在一个实例中,取决于产商的愿望、需要、成本和能力以及所使用的材料,可以使用许多物理气相沉积(PVD)类技术(以及其他技术)中的任何一种。 In one example, depending on the manufacturer's wishes, needs, capabilities, and costs and materials used, can be used many physical vapor deposition (PVD) technology-based (and other techniques) any of a. 在一个特定的实施例中,可以使用大约60nm至大约100nm厚的Pd层。 In a particular embodiment, it may be used from about 60nm to about 100nm thick Pd layer. 重要的是,应指出,本发明还考虑到了更宽的厚度范围,而不是限制性的。 Importantly, it should be noted, the present invention also contemplates a wider thickness range, and not restrictive.

[0085]然后在第二层702上形成了第三层703。 [0085] The third layer 703 is then formed on the second layer 702. 此种第三层703可以是由使用标准材料的许多有机或无机材料中的任何一种来形成的电绝缘层(例如,使用介电材料)。 Such a third layer 703 may be an electrically insulating layer (e.g., using a dielectric material) from any of a number of organic or inorganic materials using standard material to form. 可以使用硅烷氧化物层,可以使用二氧化硅层,及其他介电材料。 A silane oxide layer, a silicon dioxide layer, and other dielectric materials. 在一种合适的工艺中,可使用正硅酸四乙酯(TE0S)制造工艺来形成期望的介电层703。 In one suitable process may be used tetraethyl orthosilicate (TE0S) manufacturing process to form the desired dielectric layer 703. 然而,可以使用各种各样的其他工艺,包括热氧化,沉积技术,诸如标准化学气相沉积技术(CVD)、等离子体增强化学气相沉积(PECVD)、低压化学气相沉积(LPCVD)、低压等离子体增强化学气相沉积(LPPECVD)以及许多其他技术,这取决于期望的薄膜性质和所使用的材料。 However, a variety of other processes may be used, including thermal oxidation, deposition techniques, such as a standard chemical vapor deposition techniques (CVD), plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), low pressure plasma enhanced chemical vapor deposition (LPPECVD) and many other techniques, depending on the desired film properties and the materials used. 可以使用各种各样的硅氧化物层, 也可以使用与上述确定的TE0S工艺不同的各种方法。 Can use various silicon oxide layer, it may be used with the above identified process TE0S various different methods.

[0086] 第三层703通常被形成至大约20A(埃)至大约SOOOA的厚度。 [0086] The third layer 703 is typically formed to about 20A (Angstroms) to about the thickness of SOOOA. 一个优选的范围是大约20nm至大约50nm厚度之间,一个合适的实施例具有大约40nm厚度。 A preferred range is between about 20nm to about 50nm thickness, a suitable embodiment has a thickness of about 40nm. 使用标准的半导体加工工具可容易地实现此种层。 Using standard semiconductor processing tool such layers can be easily realized. 描述了本发明的方面的其他部分。 Other aspects of the description part of the present invention. 一旦三个层基板被形成或提供,可以执行其他步骤。 Once the three-layer substrate is formed or provided, other steps may be performed. 参阅图6、7(b)和图7(c),描述了一种用于选择性地暴露金属层702的一部分的工艺(步骤603)。 Referring to Figure 6,7 (b) and 7 (c), describes a process (step 603) a portion for selectively exposing the metal layer 702. 通常,这通过在第三层703中形成凹陷来完成。 Typically, this is done by forming a recess 703 in the third layer.

[0087] 在所描述的实施例中,使用掩模来选择性地移除材料,以暴露层702的部分。 [0087] In the embodiment described, using a mask material is selectively removed to expose portions of the layer 702. 因此, 图7(b)展示了一实施例,该实施例使用布置在下面的支撑件700(即,701、702和703)上的有图案的掩模层704。 Thus, FIG. 7 (b) shows an embodiment, this embodiment uses a support member disposed below 700 (i.e., 701, 702 and 703) with a mask layer pattern 704 on. 如上所述,掩模图案704可以包括一系列均匀尺寸的规则间隔的开口或变化的尺寸和间距图案。 As described above, the mask pattern 704 may include a series of openings of uniform size or varying in size and regularly spaced pitch pattern. 在本专利前文中已讨论过此种有图案的掩模的形成。 In this patent we have been discussed hereinbefore have such a mask pattern is formed. 如前所述,掩模704限定了纳米点布置位置705的阵列。 As described above, the mask 704 defining an array of dot placement locations 705 nanometers.

[0088]纳米点布置位置705的宽度可以与可能使用的掩模制造工具的分辨率相似。 [0088] The width of the nano dot placement locations 705 may be similar to the mask manufacturing tools may be used resolution. 例如, 使用173nm扫描仪,具有大约90nm宽度的纳米点布置位置的图案是相对简单的,其中较窄的公差和纳米点布置位置705也是可能的。 For example, using 173nm scanner, a pattern having a nano dot placement locations about 90nm width is relatively simple, wherein the narrow tolerances and nano dot placement locations 705 are also possible.

[0089]图6和7(c)展示了从纳米点位置705移除材料,以在支撑件700初始空腔中形成凹陷图案。 [0089] FIGS. 6 and 7 (c) shows a position removed from the nano-dots 705 material to form a pattern recess 700 of the support member in the initial cavity. 从而选择性地暴露下面的金属层702(步骤603),并在由掩模开口中布置的纳米点布置位置705限定的区域形成凹陷部707。 Thereby selectively exposing the underlying metal layer 702 (step 603), and a recess portion 707 is formed by the mask opening is arranged in the region of 705 nano dot placement locations defined. 在一个优选的实施例中,材料(例如,层703和702 的部分)被移除,以暴露在其中限定了凹陷部707的金属层702(此处为钯)。 In a preferred embodiment, the material (e.g., layer 703 and section 702) is removed to expose the metal layer 702 which defines a recessed portion 707 (here, Pd). 一些实施例一旦达到了金属层702便停止材料移除工艺,但是更优选的是,金属层702的一部分也被移除。 Some embodiments of the metal layer 702 is reached once the material removal process is stopped, but more preferably is part of the metal layer 702 is also removed. 通常,各向异性蚀刻用来形成凹陷707。 Typically, anisotropic etching is used to form the recess 707. 然而,本发明也考虑到了还使用各向同性蚀刻技术。 However, the present invention also contemplates the further use of an isotropic etching technique. 在这个实施例中,具有40nm厚度的第三层703,70nm深的凹陷部707被形成,贯穿第三层703,并进入第二金属层702-些距离,而没有穿过它。 In this embodiment, the third layer 703,70nm deep recess 707 having a thickness of 40nm is formed through the third layer 703, and into the 702- some distance from the second metal layer, without passing through it.

[0090] 在此,可移除光致抗蚀掩膜704。 [0090] Here, a removable photoresist mask 704. 因此,绝缘层703的上部被暴露。 Thus, an upper insulating layer 703 is exposed. 在一个普遍的实施例(如上文所讨论的)中,层703包括在其之间限定了凹陷部707的TE0S或硅烷层。 In one general embodiment (as discussed above), between layer 703 comprises a silane or TE0S defining layer 707 is recessed portion. 然而,可以使用许多绝缘和介电材料,包括上文讨论的那些以及其他材料。 However, the use of a plurality of insulating and dielectric materials, and other materials including those discussed above.

[0091] 图6和图7(d)涉及将共形修整层711添加到基板上(步骤405)。 [0091] FIG. 6 and FIG. 7 (d) relates to the conformal layer 711 is added to the trimmed (step 405) substrate. 具体地,用修整层711来处理层703的剩余部分和凹陷部707中的金属层702的暴露部分。 In particular, treated with a finishing layer 711 exposed portions of the metal layer 707 remaining portions 702 and recesses 703 of the layer. 因此,纳米点位置由覆盖它们的凹陷707和修整层711限定。 Thus, the nano dot position 711 is defined by the recess 707 and covered their finishing layer. 修整层711可以由如上关于其他修整层详细讨论的材料组成。 Trim layer 711 material can be trimmed as described above with respect to other layers of the composition are discussed in detail. 因此,此种修整层711起作用,以将凹陷部707变窄至期望轮廓。 Accordingly, such finishing layer 711 acts to the recess portion 707 is narrowed to a desired profile. 正如已经讨论的, 此种沉积工艺是极其可控的,且可用来很好地限定层711的厚度(以及因此的凹陷侧壁厚度713)。 As already discussed, such a deposition process is very controllable and is adapted to the thickness of the layer 711 (and thus the thickness of the side wall of the recess 713) is well defined. 例如,在形成和使用35nm厚度的修整层711,90nm宽凹陷707的情况下,形成了20nm宽的修整空腔714。 For example, in the case of forming and using 35nm layer thickness 711,90nm trimming width of the recess 707, forming a cavity 714 dressing 20nm wide. 这是完全可调节的,取决于所期望的最终纳米点尺寸。 This is fully adjustable, depending on the desired final size of nano dots. 此层711是共形的, 且可以具有任何期望的厚度。 This is a conformal layer 711, and may have any desired thickness. 此层711共形至层702、703的蚀刻后表面,且特别地共形至初始空腔707的轮廓,并因此形成在初始空腔707的内壁上。 This conformal layer 711 to the rear surface of the etching layer 702, 703, and in particular the initial conformal to the contour of the cavity 707, and thus the initial formed on inner walls of the cavity 707. 如上所述,层的厚度可以是高度可控制的,使能够形成高度均匀厚的层711。 As described above, the thickness of the layer can be highly controlled, capable of forming a highly uniform thickness of layer 711. 重要的是,此种层可以是极其薄的,但是也可以形成为大的多的厚度,使该工艺能够形成各种各样的厚度。 Importantly, this layer may be extremely thin, but may be formed as a plurality of large thickness, so that the process is capable of forming a wide variety of thicknesses.

[0092] 因此,修整层711可以是由使用标准材料的许多有机或无机材料中的任何一种形成的介电层。 [0092] Thus, the dressing layer is a dielectric layer 711 may be formed from any of a number of organic or inorganic materials used in the standard materials. 在一个特别有用的实施例中,层711包括与第三层703相同的材料,或与其具有良好粘附性和兼容性的材料。 In one particularly useful embodiment, the third layer 711 comprises a layer 703 of the same material, or in connection with good adhesion and material compatibility. 可以使用硅烷氧化物层,可以使用二氧化硅层,还可以使用其他介电材料。 A silane oxide layer, a silicon oxide layer, may also be used other dielectric materials. 在一种合适的工艺中,正硅酸四乙酯(TE0S)制造工艺可用来形成期望的介电层711。 In one suitable process, a tetraethyl orthosilicate (TE0S) manufacturing process used to form the desired dielectric layer 711. 当层703也由TE0S工艺形成时,此种工艺是特别兼容的。 When the layer 703 is also formed of TE0S process, such process is especially compatible. 但是,如上文所指出的,可以使用各种各样的其他工艺,包括热氧化、CVD、PECVD、LPCVD、LPPECVD以及许多其他工艺,这取决于期望的修整层711的薄膜性质。 However, as noted above, a variety of other processes may be used, including thermal oxidation, CVD, PECVD, LPCVD, LPPECVD and many other processes, depending on the desired properties of the film layer 711 is trimmed. 形成在剩余部分703上的层711的部分可包括牺牲层, 该牺牲层保护在下面的层703免于随后的蚀刻或其它处理。 Portions of layer 711 is formed on the remaining portion of the sacrificial layer 703 may comprise, the sacrificial layer protects the underlying layer 703 from subsequent etching or other processing.

[0093] 如上文所解释的,虽然此处以35nm厚度修整层711来讨论,但是此种薄膜普遍形成至大约20,4(埃)至大约5000入的厚度。 [0093] As explained above, although the discussion here to trim layer 711 to a thickness of 35nm, but such films generally are formed to about 20,4 (Angstroms) to about 5000 the thickness. 因此,使用3511111厚度的修整层711,以及9〇11111宽的凹陷707,所得的修整空腔714是20nm宽。 Therefore, the thickness of the finishing layer 711 3511111, and 9〇11111 wide recesses 707, the resulting dressing cavity 714 is 20nm wide. 一种非常小且非常有用的尺寸。 A very small size and very useful.

[0094]参阅图6和图7(e),在进一步处理中,可从凹陷714(以及就此而言的整个上水平面)移除修整层711的部分,以在修整空腔714的底部暴露金属层702的窄的部分。 [0094] Referring to FIG. 6 and FIG. 7 (e), in the further processing, the removable portion of the trimmed layer 711 from the recess 714 (and the entire upper level for that matter), to expose the metal in the bottom of the cavity 714 of the dressing the narrow portion of the layer 702. 通常,将使用各向异性蚀刻工艺。 Typically, using an anisotropic etch process. 这将形成一种蚀刻的修整层711e。 This will form the finishing layer 711e for etching. 但是,特别地,蚀刻工艺(步骤607)是用来在之前由凹陷707限定的区域暴露下面的金属702。 However, in particular, an etching process (step 607) is used to expose the underlying metal 702 in the region defined by the recess 707 before. 这个表面702η将是更窄的, 并限定了暴露的纳米点表面702η。 This surface 702η will be narrower, and defining the exposed surface of the nano-dots 702η.

[0095] 因此,在一个实施例中,修整层711被各向异性地蚀刻,以特别是在金属702之上空腔的底中部移除层711的部分。 [0095] Thus, in one embodiment, the dressing layer 711 is anisotropically etched, particularly in the central bottom cavity 702 above the metal layer 711 is partially removed. 在一些实施例中,基本上可以移除层711的所有水平表面。 In some embodiments, the layer may be removed substantially all horizontal surfaces 711. 甚至到这个程度:在一个实施例中,以至从层703之上的部分完全移除层711。 Even to this extent: In one embodiment, layer 703 from above as well as complete removal of portions of layer 711. 然而,大部分(如果不是全部)层703将仍在应有位置,以覆盖凹陷外区域中的在下面的金属702。 However, most (if not all) of the layer 703 is still proper position, so as to cover the recess in the outer metal region 702 below. 因此,位于凹陷区域707中金属702之上的薄的修整层711被移除,以暴露下面的金属702。 Thus, the recess is located in an area above 707 702 a thin metal layer 711 of the dressing is removed to expose the underlying metal 702. 具体地,在这个特定的实施例中,凸起的金属部分712之间的修整层711被移除,以限定暴露了下面的金属702的修整空腔,从而形成区域714中的所述暴露的纳米点702η。 Specifically, in this particular embodiment, the metal portion between the projections 712 trimmed layer 711 is removed to expose the underlying metal defining the cavity 702 of the trimming, to form the exposed region 714 nanodots 702η. 应记住,侧壁711s仍然基本上在应有位置,从而限定了纳米点702η的尺寸。 It should be remembered, sidewall 711s remains substantially in position, thereby defining the size of nano-dots 702η. 继续地,在一个特别有利的实施例中,层702由钯形成,而不是更昂贵的金。 Continuing, in a particularly advantageous embodiment, the layer 702 is formed of palladium, rather than the more expensive gold. 然而,本发明不限于任一种材料。 However, the present invention is not limited to any material.

[0096] 因此,在这个特定的实施例中,各向异性蚀刻蚀刻了修整层711,以使得其调整了初始空腔707中材料的宽度,以形成修整空腔714,且修整层711的剩余部分限定了纳米点702η的尺寸。 [0096] Thus, in this particular embodiment, the trimming etch anisotropic etch layer 711, so that the adjustment of the initial width of the material in the cavity 707, the cavity 714 to form a trim, and the trim layer 711 remaining 702η portion defines the size of nano-dots. 在这个特定的实施例中,层711包括薄的介电材料共形层(此处为与示例性层703的TE0S材料相同的TE0S材料),其与下面的第三层703相兼容。 In this particular embodiment, layer 711 includes a thin conformal layer of dielectric material (here the TE0S material layer 703 of the exemplary TE0S same material), which is compatible with the underlying third layer 703. 在一种可能的实施方式中,原有的光掩模层(参见,图7(c)的704)可留在应有位置,而修整层711形成在光掩模704 之上。 In one possible embodiment, the layer of the original photomask (see FIG. 7 (c) 704) may be left in position, the layer 711 is formed on the trim mask 704. 随后,可根据上文所讨论的实施例(以及其他实施例)来蚀刻上文引用的修整层711的部分,以移除修整层711的上部。 Subsequently, the etched portions may be trimmed layer 711 according to the above cited embodiment (and other embodiments) discussed above, to remove the upper layer 711 of the trim. 然后,可从表面移除光掩模704,以暴露第二层702。 It can then be removed from the surface of the photomask 704, 702 to expose the second layer.

[0097]在另一种任选的工艺中,可通过电镀(或无电镀)来建立纳米点702η,以用额外的纳米点材料(此处为钯)来填充空腔714。 [0097] In another optional process, can be established nanodots 702η by electroplating (or electroless plating), in order to fill the cavity 714 with additional nano dot material (here, Pd). 具体地,应指出的是,这是一种任选的工艺,而不是实施本发明所必须的。 Particularly, it should be noted that this is an optional process, but not necessary embodiment of the present invention.

[0098] 本发明人指出,这些工艺步骤中的许多步骤可以任何次序执行,或者一起执行。 [0098] The present invention is indicated, these process steps a number of steps may be performed in any order or performed together. 此种封装可展示出更高的装置密度,更短的互连距离,更好的热性能,以及更优的所得电气性能。 Such packages may exhibit a higher density of devices, shorter interconnect distance, better thermal performance and the better the resulting electrical performance.

[0099] 已针对特定优选实施例和其具体特征特别地展示和描述了本发明。 [0099] Preferred embodiments are specific embodiments thereof and specific features particularly shown and described with the present invention. 然而,应注意的是,上述实施例是用来描述本发明的原理,而非限制其范围。 However, it should be noted that the above embodiments are used to describe the principles of the present invention, without limiting its scope. 因此,对于本领域技术人员来说,很轻易地显而易见的是,可在形式和细节上作出各种变化和修改,而不会脱离如所附加权利要求阐述的本发明的精神和范畴。 Thus, the skilled artisan, easily be apparent that various changes and modifications may be made in form and detail without departing from the spirit and scope of the invention as set forth in the appended claims is claimed. 其他实施例和对所描述实施例的改变对本领域技术人员来说是显而易见的,且可被作出,而不会脱离以下权利要求中所限定的本发明的精神和范畴。 Other embodiments and variations of the described embodiments of the present embodiments will be apparent to those of skill, and can be made without departing from the spirit and scope of the invention as defined in the following claims to. 此外,除非明确指出,权利要求中以单数引用元件并不是用来意味着"一个且仅有一个",而是"一或多个"。 Moreover, unless explicitly stated in the claims recited in the singular is not intended to elements mean "one and only one", but rather "one or more." 此外,本文示例性公开的实施例可以被实施,而没有任何元件在本文中没有被具体地公开。 Further, the exemplary embodiments described herein may be implemented disclosed, without any element not specifically disclosed herein. 本发明人进一步指出,虽然以相继次序描述了工艺步骤、方法步骤、算法等等,然而此种工艺、方法和算法可配置成以轮流次序工作。 The present invention is further noted that, although described in a sequential order of process steps, method steps, algorithms or the like, however, such processes, methods and algorithms may be configured to work in alternate order. 换句话说,在这个专利申请中可能描述的任何步骤的顺序或者次序的内部和本身并没有表明需要这些步骤按照此次序执行。 In other words, any internal sequence or order of steps in this patent application and may be described in itself does not need to show these steps in this order. 所描述的工艺步骤可以任何实际次序来执行。 Described process steps may be performed in any order practical. 此外,可同时地执行一些步骤, 尽管描述或暗示为非同时发生的(例如,因为一个步骤是在另一步骤之后描述的)。 Further, some steps may be performed simultaneously, although described or implied non-simultaneously (e.g., because one step is described after the other step). 而且,通过在附图中描述的工艺图解并非意味着所图示的工艺是排除对其的其他变化和修改,并没有意味着所图示的工艺或其任何一个步骤为本发明的一或多个所必需的,且并非意味着所图示的工艺是优选的。 Further, as illustrated by the process illustrated in the accompanying drawings described process is not meant to exclude other variations and modifications thereto, does not imply that the illustrated process or any of the steps of the present invention, one or more of a necessary, and is not meant illustrated process is preferred.

Claims (24)

  1. 1. 一种纳米点阵列,包括: 一支撑件,其包括一阵列,所述阵列包括形成在其中的多个初始空腔; 一修整件,其设置在各个所述空腔内使得初始空腔的侧壁变窄至期望的宽度,以形成其中限定了纳米点布置位置的修整空腔; 金属塞子,其形成在相关联的纳米点布置位置,以使得纳米点暴露的上表面限定了包括多个纳米点的一纳米点阵列。 A nano dot array, comprising: a support member, which includes an array, the array comprising a plurality of initial cavities formed therein; a finishing member, which is disposed in each of the cavity so that the initial cavity the side wall is narrowed to a desired width to form a cavity which defines a nano dot arrangement trimming position; metal plugs, which are formed in the nano dot placement locations associated, so that the exposed upper surface of the nanodots include defining a plurality a nano dot array nanometers points.
  2. 2. 根据权利要求1所述的纳米点阵列,其中: 所述支撑件包括一支撑装置,所述支撑装置适于为初始空腔阵列提供机械弹性支撑; 所述修整件包括一变窄装置,所述变窄装置安置在初始空腔侧壁上,适用于将初始空腔变窄以形成其中限定了纳米点布置位置的修整空腔; 形成在纳米点布置位置的金属塞子包括用于包括所述多个纳米点的一金属装置。 The nano dot array according to claim 1, wherein: the support member comprises a support means, said support means is adapted to provide mechanical support for the elastic initial array of cavities; said finishing member comprises a narrowing device, means disposed on said narrowed initial sidewalls of the cavity, the cavity adapted to initially narrowed to form a cavity which defines a nano dot arrangement trimming position; plug formed in the metal nano dot placement locations comprises means for including the said apparatus a plurality of metal nano-dots.
  3. 3. 根据权利要求1所述的纳米点阵列,其中:所述阵列包括具有基本相同尺寸和形状的纳米点的基本规则的阵列。 According to claim 1, said array of nanodots, wherein: said array comprises a substantially regular array of nano dots having substantially the same size and shape.
  4. 4. 根据权利要求3所述的纳米点阵列,其中:所述纳米点具有大约50纳米或更小的宽度。 4. The nano dot array according to claim 3, wherein: said nano dots or less has a width of about 50 nanometers.
  5. 5. 根据权利要求3所述的纳米点阵列,其中:所述纳米点具有大约20纳米的宽度。 The nano dot array according to claim 3, wherein: said nano dots having a width of about 20 nanometers.
  6. 6. 根据权利要求1所述的纳米点阵列,其中:所述支撑件包括一基板,所述基板包括形成在其上的介电材料层,初始空腔的阵列包括形成在所述介电材料层中的规则间隔和尺寸的初始空腔的有图案的阵列;且其中所述修整空腔的内表面包括一金属晶种层,所述金属塞子安置在所述金属晶种层上。 According to claim 1, said array of nanodots, wherein: the support member comprises a substrate, said substrate comprising a layer of dielectric material is formed thereon, the array comprises an initial cavity formed in the dielectric material the initial layer of the cavity size and are regularly spaced array pattern; and wherein said inner surface of the cavity dressing comprises a metal seed layer, the metal plug disposed on the metal seed layer.
  7. 7. 根据权利要求6所述的纳米点阵列,其中:所述初始空腔贯穿所述介电材料层,以暴露下面的基板;且其中,所述金属晶种层安置在所述修整空腔的内侧壁上,且安置在下面的基板的暴露部分上。 The nano dot array according to claim 6, wherein: the initial cavity through said dielectric material layer to expose the underlying substrate; and wherein the metal seed layer disposed in the cavity dressing the inner side wall, and disposed on the exposed portion of the substrate below.
  8. 8. 根据权利要求1所述纳米点阵列,其中所述金属塞子由金、铂、钯和钛中的至少一种制成。 According to claim 1 nano dot array, wherein the metal plug made of gold, platinum, palladium, titanium and at least one is made.
  9. 9. 一种纳米点阵列,其包括:一支撑件,所述支撑件包括形成在其上的规则间隔的金属纳米点阵列,以使得所述纳米点基本呈相同形状和尺寸,且具有大约30纳米或更小的宽度。 A nano dot array, comprising: a support member, said support member comprises a metal nano dot array is formed on its regular intervals, so that the nano dots substantially same shape and size, and has approximately 30 nanometers or less in width.
  10. 10. -种在基板上形成窄尺寸的方法,包括以下步骤: 在一支撑件中形成多个初始空腔,其中所述初始空腔各自具有初始宽度; 修整所述初始空腔的初始宽度,使所述初始空腔变窄至期望尺寸,从而形成相关联的修整空腔,所述修整空腔包括相对所述初始宽度变窄的修整宽度。 10. - Method narrow dimension species formed on a substrate, comprising the steps of: forming a plurality of cavities initial support member, wherein each of the initial cavity having an initial width; initial trimming the initial width of the cavity, the initial cavity narrows to a desired size, trimming to form an associated cavity, said cavity comprises opposed trimming the trimmed initial width becomes narrower.
  11. 11. 根据权利要求10所述的方法,其中:所述方法进一步能够形成纳米点阵列, 其中,形成修整空腔的所述修整界定了由修整空腔的修整宽度限定的纳米点布置位置进一步包括以下步骤:在修整空腔限定的纳米点布置位置形成多个金属塞子,使得能够形成包括多个纳米点的纳米点阵列。 11. The method according to claim 10, wherein: said method further capable of forming a nano dot array, wherein the conditioning cavities are formed by trimming the trimming width of the trimming defined cavity defined nano dot placement locations further comprises the steps of: forming a plurality of metal plugs in the cavity defined by the trimming nano dot placement locations, making it possible to form a nano dot array comprising a plurality of nano dots.
  12. 12. 根据权利要求11所述的方法,其中,所述纳米点阵列的纳米点包括50纳米或更小的宽度。 12. The method of claim 11, wherein said array of nanodots include nanodots or smaller width of 50 nm.
  13. 13. 根据权利要求11所述的方法,其中: 形成多个初始空腔的步骤包括用于在所述支撑件中形成多个初始空腔的一装置; 修整所述初始空腔的初始宽度的步骤包括一装置,所述装置用于修整所述空腔的初始宽度,以将所述空腔变窄至所述期望尺寸而形成所述修整空腔,从而限定了所述修整空腔中的纳米点布置位置;且形成多个金属塞子的步骤包括一装置,所述装置用于在修整空腔的纳米点布置位置形成金属塞子,以能够形成纳米点阵列。 13. The method of claim 11, wherein: the initial step of forming a plurality of cavities forming apparatus comprising a plurality of initial cavities for the support member; trimming the initial width of the initial cavity step includes a means, said means for trimming the initial width of the cavity to form the conditioning cavity to the cavity is narrowed to the desired size, so as to define a cavity in the dresser nano dot placement locations; and the step of forming a plurality of metal plugs comprise means, said means for forming a metal plug in the cavity dressing nano dot placement locations, to be able to form a nano dot array.
  14. 14. 根据权利要求11所述的方法,其中: 在一支撑件中形成所述初始空腔的步骤包括:自所述支撑件各向异性地蚀刻材料,以形成基本相似尺寸和形状的初始空腔的规则间隔的阵列;且修整所述初始空腔的初始宽度的步骤包括:形成安置在所述初始空腔内的一共形层直到所述共形层获得期望的厚度,从而根据期望的最终宽度精确地限定修整空腔的最终宽度。 14. The method of claim 11, wherein: the initial step of forming a cavity in the support member comprising: a supporting member from the material is anisotropically etched to form a substantially similar size and shape of the initial blank a regular array of spaced cavities; and the step of trimming the initial width of the initial cavity comprising: forming initial disposed in the cavity until the total thickness of the conformal layer to obtain the desired conformal layer, such as desired final precisely defined width finishing final width of the cavity.
  15. 15. 根据权利要求14所述的方法,其中,在一支撑件中形成多个初始空腔的步骤包括: 在一机械弹性基板上形成一介电层;及从所述支撑件各向异性地蚀刻材料,以形成所述初始空腔的规则间隔的阵列,各空腔具有基本相同的尺寸和形成,各自具有所述初始宽度。 Step 15. The method according to claim 14, wherein a plurality of initial cavities formed on a support member comprising: forming a dielectric layer on a substrate, mechanical resilience; from the support member and anisotropically etching an array of material to form the initial regularly spaced cavities, each cavity having substantially the same size and are formed, each having the initial width.
  16. 16. 根据权利要求15所述的方法,其中:从所述支撑件各向异性地蚀刻材料的步骤包括:各向异性地蚀刻所述介电层以暴露下面的机械弹性基板。 16. The method according to claim 15, wherein: the support member from the step of anisotropically etching said material comprising: anisotropically etching the dielectric layer to expose the underlying substrate mechanical resilience.
  17. 17. 根据权利要求15所述的方法,其中,形成所述金属塞子的步骤包括:形成延伸至修整空腔的一晶种层,以使得其安置在修整空腔的侧壁和底面上;且所述金属塞子通过将金属电镀至填充修整空腔的晶种层上来形成。 17. The method according to claim 15, wherein said forming metal plugs comprises: forming a seed layer extending to the cavity trimming, trimming so disposed in the side walls and the bottom surface of the cavity; and the metal plugs filled by metal plating to the dressing onto the seed layer formed cavity.
  18. 18. 根据权利要求17所述的方法,其中:所述金属塞子由包括金、铂、钯和钛中的至少一种的材料制成。 18. The method according to claim 17, wherein: said plug is made of at least one metal materials include gold, platinum, palladium, and titanium.
  19. 19. 根据权利要求17所述的方法,其中:形成金属塞子的步骤进一步包括:从所述介电层的顶面上移除至少一部分共形层。 19. The method according to claim 17, wherein: the step of forming a metal plug further comprising: removing at least a portion of the top surface of the conformal layer from the dielectric layer.
  20. 20. 根据权利要求19所述的方法,其中,所述移除包括:从所述介电层的顶面移除所有共形层材料,以使得所述塞子包括在所述介电层之上延伸的凸起部分,从而形成凸起的纳米点的阵列。 20. The method according to claim 19, wherein said removing comprises: removing all of the conformal layer material from the top surface of the dielectric layer, such that the plug comprises a dielectric layer over the raised portion extending projections so as to form an array of nanodots.
  21. 21. 根据权利要求11所述的方法,其中在所述支撑件中形成所述多个初始空腔的步骤包括: 在一机械弹性基板上形成一介电层;及从所述支撑件各向异性地蚀刻材料,以形成所述初始空腔的规则间隔的阵列,各空腔具有基本相同的尺寸和形状,各自具有所述初始宽度;且修整包括形成在其上的共形层的所述初始空腔的初始宽度的步骤进一步包括: 执行一第一修整蚀刻,其包括各向异性地蚀刻共形层,以暴露下面的机械弹性基板; 执行一第二修整蚀刻,包括各向同性地蚀刻共形层的侧壁,从而在侧壁中形成弓形轮廓,以使得侧壁轮廓至少比修整空腔的底部更窄; 形成多个金属塞子的步骤包括:在修整空腔内的机械弹性基板的暴露部分上沉积金属材料;且进一步包括以下步骤:移除所述介电层,留下布置在机械弹性基板表面上的多个纳米点,从而形成纳米点 Step 21. The method of claim 11, wherein said plurality of initial cavities formed in said support member comprising: forming a dielectric layer on a substrate, mechanical resilience; and a support member from each of the said and said trimming comprises a conformal layer is formed thereon; an array of anisotropically etching the material to form the initial regular intervals cavity, each cavity having substantially the same size and shape, each having a width of the initial the initial step of the initial width of the cavity further comprises: performing a first trim etch, which comprises anisotropically etching the conformal layer to expose the underlying substrate mechanical resilience; performing a second etch trimming, comprising isotropically etching conformal layer of the sidewall, so as to form an arcuate profile in the side wall, so that the contour of at least the side walls is narrower than the bottom of the cavity dressing; the step of forming a plurality of metal plugs comprising: an elastic substrate in a mechanical finishing of the cavity depositing a metal material on the exposed portion; and further comprising the step of: removing said dielectric layer, leaving a plurality of nanodots are arranged on a surface of the mechanical elasticity of the substrate, thereby forming nanodots 列,以使得纳米点是规则间隔的且具有基本相同的形状和尺寸。 Column, so that the nanodots are regularly spaced and have substantially the same shape and size.
  22. 22. 根据权利要求21所述的方法,其中纳米点在大约20-50纳米的宽度范围内。 22. The method of claim 21, wherein the nanodots in the range of about 20-50 nm width.
  23. 23. 根据权利要求14所述的方法,其中,在一支撑件中形成多个初始空腔的步骤包括: 提供一机械弹性基板,所述机械弹性基板包括形成在其上的一金属基底层,一介电层布置在所述金属基底层上;且从所述支撑件各向异性地蚀刻材料包括:从介电层各向异性地蚀刻材料,以暴露下面的金属基底层,从而形成与所述纳米点布置位置相关联的所述初始空腔的规则间隔的阵列;且进一步包括:各向异性地蚀刻所述共形层以暴露下面的金属层,从而限定多个纳米点, 各纳米点与一相关联的纳米点布置位置相关联,所述纳米点包括所述最终宽度。 23. A method according to claim 14, wherein a plurality of initial cavities formed on a support member comprising: providing a mechanical elastic substrate, the mechanical elastic metal substrate comprises a base layer formed thereon, a dielectric layer disposed on the metal base layer; from the support member and anisotropically etching the material comprising: from dielectric material is anisotropically etched to expose the underlying metal substrate layer, thereby forming the the regular array of said nano dot placement locations associated with the initial cavity spaced; and further comprising: anisotropically etching the conformal layer to expose the underlying metal layer, thereby defining a plurality of nanodots, each nanodots nano dot placement locations associated with an associated, comprising the nanodots the final width.
  24. 24. 根据权利要求23所述的方法,其中:用金属材料电镀暴露的下面的金属层以增强所述纳米点。 24. The method according to claim 23, wherein: the metal layer underneath the exposed plated metallic material to enhance the nanodots.
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