CN105760285B - A kind of typical embedding assembly machine architecture efficiency evaluation method - Google Patents
A kind of typical embedding assembly machine architecture efficiency evaluation method Download PDFInfo
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Abstract
A kind of typical embedding assembly machine architecture efficiency evaluation method of the present invention, includes the following steps, 1. establish embedded computer efficiency evaluation index system；According to the demand that embedded system information is handled, efficiency evaluation index system is established, and determine the scale and quantification gradation of the test method and each evaluation index of evaluation index；2. obtaining the ballot weight of each evaluation index in efficiency evaluation index system by Experts consultation method, evaluation index normalized weight coefficient in efficiency evaluation index system is determined by assignment method two-by-two；3. by the comprehensive multi-index measuring and evaluation matrix for obtaining efficiency evaluation index system based on the not determining architecture evaluation model estimated；4. Utilization assessment index normalized weight coefficient obtains comprehensive multi-index measure evaluation vector with comprehensive multi-index measuring and evaluation matrix；5. according to comprehensive multi-index measure evaluation vector, differentiate to obtain the opinion rating of the architecture adaptability by established confidence level and criterion of identification.
Description
Technical field
The present invention relates to embedded computer system structure exploitation and design evaluatio field, specially a kind of typical insertion
Formula Computer Architecture efficiency evaluation method.
Background technology
As embedded computer task is increased sharply, it is desirable that system for computer structure becomes increasingly complex, high-performance embedded
Computer Architecture enters the multinuclear epoch, and has also appeared proprietary coprocessor, is provided quickly for information processing system
The hardware platform of calculating, especially processing capacity, memory capacity, bus transfer rate etc..But the effect of embedded system
Quantitative and believable conclusion can be not yet received, there is an urgent need to establish to be directed to embedded computer efficiency evaluation method, in conjunction with being
The policy information stream that each stage decision of uniting forms, is effectively estimated and is evaluated to the overall efficiency of system, and according to evaluation
As a result adjusting and optimizing strategy is further corrected, so that systems stay optimization and resource distribution is planned as a whole, to meet multitask high-performance
Processing embedded computer architecture Design provides technical support in real time.
In the prior art, in order to realize that the particular characteristic of different embedded systems, embedded computer are all to be determined mostly
System, the design of different product function performances realizes that not only variant but also there are general character.As embedded system is to real-time etc.
An urgent demand of aspect needs the design of the architecture of hardware system more to optimize, especially processing capacity, memory capacity,
Bus bandwidth etc..But estimate and evaluate shortage means for the efficiency of embedding assembly machine architecture.
Invention content
For problems of the prior art, the present invention provides a kind of typical embedding assembly machine architecture efficiency
Evaluation method, by defining the test method of each evaluation index of embedding assembly machine architecture efficiency evaluation index system, mark
Degree and quantification gradation establish based on the not determining embedded architecture evaluation model estimated, and set confidence level and know
Other criterion can provide Appreciation gist for the optimization design of embedded architecture.
A kind of typical embedding assembly machine architecture efficiency evaluation method, includes the following steps,
Step 1, embedded computer efficiency evaluation index system is established；According to embedded system information handle demand,
It disclosure satisfy that the characteristic parameter involved by defined performance requirement extracts after embedding assembly machine architecture is implemented, build
It is vertical a set of to occupy comprising task responding ability, host processor resources occupation rate, coprocessor FPGA resource occupation rate, storage resource
The embedded computer system knot that rate, transfer resource occupation rate, data throughout and task seven evaluation indexes of delay are constituted
Structure efficiency evaluation index system, and determine the scale and quantification gradation of the test method and each evaluation index of evaluation index；
Step 2, the ballot of each evaluation index in efficiency evaluation index system is obtained in a manner of voting by Experts consultation method
Weight, and evaluation index normalized weight coefficient in efficiency evaluation index system is determined by assignment method two-by-two；
Step 3, by based on not determining that the architecture evaluation model estimated obtains more fingers of efficiency evaluation index system
Mark Synthetic Measurement evaluations matrix；
Step 4, it is comprehensive with comprehensive multi-index measuring and evaluation matrix to obtain multi objective for Utilization assessment index normalized weight coefficient
Close measure evaluation vector；
Step 5, according to comprehensive multi-index measure evaluation vector, differentiate to obtain by established confidence level and criterion of identification
The opinion rating of the architecture adaptability.
Preferably, in step 1, the test method of evaluation index is as follows in efficiency evaluation index system：With x1Expression task
Responding ability is defined as completing the ability of predetermined processing task at the appointed time, handles what task was completed by test data
Time is denoted as the test result of response time with the ratio between actual finish time and stipulated time；With x2Indicate host processor resources
Occupation rate is defined as the service condition of the internal resource of primary processor in data handling procedure, by testing making for its ram in slice
With quantity and external expansible program and data space usage quantity account for used chip homegrown resource number, provided with some
The peak use rate that source occupies charges to test result；With x3It indicates coprocessor FPGA resource occupation rate, is defined as data processing
The service condition of FPGA internal resources in the process, by testing accounting for for FPGA clocks, logic, memory resource and computing resource
With rate, test result is charged to the peak use rate that some resource occupies；With x4It indicates storage resource occupation rate, is defined as data
The service condition of storage resource in processing procedure charges to survey by testing the memory physical memory space with memory capacity ratio
Test result；With x5It indicates transfer resource occupation rate, is defined as the service condition of transfer resource in data handling procedure, passes through test
Actual transfer rate charges to test result with design interface rate ratio；With x6It indicates data throughout, is defined as data in list
The ability that interaction is set up in the time of position charges to test result by test data operation total amount and the practical time ratios that calculate；With
x7Expression task be delayed, be defined as data and reach to the time of start to process, by test data reach to start calculate when
Between ratio charge to test result.
Further, the quantification gradation of each evaluation index is divided into 9 grades, be respectively it is special it is good, fine, good, preferable, general, poor,
Poor, very poor and spy is poor, and introduces the quantification gradation that 1~9 scale realizes Comparative indices；
The scale of each index is divided into 9 grades in efficiency evaluation index system, and the 1st grade of scale is special good, is denoted as c1It is expressed as each
The limiting value of evaluation index；5th grade of scale is general, is denoted as c5It is expressed as only disclosure satisfy that each evaluation that user performance requires refers to
Scale 5 and 1 difference of scale are divided into 4 parts and obtain the increment size of scale by target calculated value；
2nd grade of scale is fine, is denoted as c2Be expressed as scale 1 and increment size and；3rd level scale preferably, is denoted as c3It indicates
For scale 2 and increment size and；4th grade of scale is preferable, is denoted as c3Be expressed as scale 3 and increment size and；6th grade of scale be
It is poor, it is denoted as c6Be expressed as scale 5 and increment size and；7th grade of scale is poor, is denoted as c7It is expressed as scale 6 and increment size
With；8th grade of scale is very poor, is denoted as c8Be expressed as scale 7 and increment size and；9th grade of scale is special poor, is denoted as c9It is expressed as
Scale 8 and increment size and；Thus obtained scale space is denoted as U={ c1, c2..., c9}；And in efficiency evaluation index system
The test value hits of each evaluation index should be greater than the quantification gradation number 9 equal to evaluation index.
Preferably, it in step 2, when using Experts consultation method, chooses and is no less than four expert consultings, wherein expert limits and grinds
Field is studied carefully for Embedded System Design and academic title is not less than senior engineer.
Preferably, step 2 is as follows,
Step 2.1, the expert of consulting carries out weight votes to each evaluation index respectively, obtains in efficiency evaluation index system
The ballot weight of each evaluation index；
Step 2.2, arithmetic average is carried out to the ballot weight ratio of each consultant expert according to following formula, as a result evaluation
The arithmetic average matrix of index ballot weight, is denoted as bI, j(j≤7 1≤i ＜)；
Wherein, the ballot weight ratio of k-th of expert is denoted asL is expert's number, andwiIt is k-th of expert for the ballot weight of i-th of evaluation index；wjFor
Ballot weight of k-th of expert for j-th of evaluation index；
bR, q(1≤r≤7,2≤q≤7,）With bQ, s(2≤q≤7,2≤s≤7) extracted in the result of step 2.2 respectively
It obtains；The 1st row result of statistical average matrix of evaluation index ballot weight is equal to the arithmetic average square of evaluation index ballot weight
The result of the 1st row of battle array；
Step 2.4, the result of step 2.3 is normalized according to following formula to obtain efficiency evaluation index system
Normalized weight coefficient, be denoted as
Wherein, i=1,2 ..., 7, j=1,2 ..., 7；WithRespectively in step
It extracts and obtains in 2.3 result.
Further, step 3 specifically comprises the following steps,
Step 3.1, with task responding ability, host processor resources occupation rate, coprocessor FPGA resource occupation rate, storage
Resources occupation rate, transfer resource occupation rate, data throughout and task 7 evaluation indexes of delay are established and are estimated based on determination
Embedded architecture efficiency evaluation model；Formed includes that all evaluation indexes correspond to the space of test data and are denoted as X=
{x1,x2,…,x7}；Wherein, xi(1≤i≤7) indicate the test value of i-th of evaluation index；
Step 3.2, have 1~9 quantitatively evaluating grade for each evaluation index in efficiency evaluation index system, it is special it is good,
Very well, good, preferable, general, poor, poor, very poor and spy is poor, corresponding 9 scale c1, c2..., c9, scale space is denoted as U=
{c1, c2..., c9}；Wherein ctIndicate t grades of scales, then t grades of scales are better than t+1 grades of scales, and scale space U is ordered into segmentation
Class；I-th of evaluation index test value x is calculated by following formulaiBelong to t-th of opinion rating ctDegree be denoted as,
μit=μ (xi∈ct)；
0≤μ(xi∈ct)≤1,
μ(xi∈ U)≤1,
Wherein i=1,2 ..., 7, t=1,2 ..., 9.
It is step 3.3, as follows by the result of step 3.2 structure comprehensive multi-index measuring and evaluation matrix,
Wherein, i=1,2 ..., 7, t=1,2 ..., 9.
Wherein,I=1,2 ..., 7, t=1,2 ..., 9,It is taken out in the result of step 2.4
Take acquisition, μitIt extracts and obtains in the result of step 3.3.
Further, in step 5, confidence level λ=0.7 and criterion of identification are determined, ifThen the opinion rating of embedding assembly machine architecture is ρ0；If ρ0
=1 opinion rating is good, the ρ of spy0=2 opinion ratings are fine, ρ0=3 opinion ratings preferably, ρ0=4 opinion ratings are preferable, ρ0
=5 opinion ratings are general, ρ0=6 opinion ratings are poor, ρ0=7 opinion ratings are poor, ρ0=8 opinion ratings be it is very poor and
ρ0=9 opinion ratings are special poor；0≤τ≤ρ, ρ=1,2 are extracted in the result of step 4 ... 9.
Compared with prior art, the present invention has technique effect beneficial below：
The present invention proposes a kind of typical embedding assembly machine architecture efficiency evaluation method, passes through characteristic index system
With the foundation of efficiency evaluation model, architecture attribute can be embodied, can accurately reflect that the efficiency of embedded computer is wanted
The quality of element and architecture Design.It is on this basis design alternative and improved basis to the evaluation of architecture.According to
The efficiency evaluation method of the present invention can be applied to embedded body by what embedding assembly machine architecture efficiency evaluation instantiated
Architecture is designed and developed, and realizes that preceding 100% evaluation is implemented in design, and it is accurate that the design research and development to optimize balanced architecture provide
Foundation.
Description of the drawings
Fig. 1 is the flow diagram of method described in present example.
Specific implementation mode
With reference to specific embodiment, the present invention is described in further detail, it is described be explanation of the invention and
It is not to limit.
The present invention is to be achieved through the following technical solutions：1. establishing embedded computer efficiency evaluation index system；Root
According to the demand that embedded system information is handled, defined performance requirement disclosure satisfy that after embedding assembly machine architecture is implemented
Involved characteristic parameter is extracted, and is established a set of comprising task response-time, host processor resources occupation rate, coprocessor
FPGA resource occupation rate, storage resource occupation rate, transfer resource occupation rate, data throughout and task 7 evaluations of delay refer to
Mark constitute embedding assembly machine architecture efficiency evaluation index system, and determine evaluation index test method with each comment
The scale and quantification gradation of valence index；2. obtaining respectively evaluating in efficiency evaluation index system in a manner of voting by Experts consultation method
The ballot weight of index, and evaluation index normalized weight coefficient in efficiency evaluation index system is determined by assignment method two-by-two；
3. being commented by showing that the comprehensive multi-index of efficiency evaluation index system is estimated based on the not determining architecture evaluation model estimated
Valence matrix；Estimate 4. Utilization assessment index normalized weight coefficient obtains comprehensive multi-index with comprehensive multi-index measuring and evaluation matrix
Evaluation vector；5. according to comprehensive multi-index measure evaluation vector, this is differentiated by established confidence level and criterion of identification
The opinion rating of architecture adaptability.
Specifically, the present invention includes the following steps：
Step 1：Establish embedded computer efficiency evaluation index system.
With x1Expression task responding ability is defined as completing the ability of predetermined processing task at the appointed time, passes through survey
It tries the time that data processing task is completed, the test result of response time to be denoted as with the ratio between actual finish time and stipulated time；
With x2It indicates host processor resources occupation rate, is defined as the service condition of the internal resource of primary processor in data handling procedure,
Used chip is accounted for by the usage quantity and external expansible program and data space usage quantity of testing its ram in slice certainly
The number for having resource, test result is charged to the peak use rate that some resource occupies.With x3Indicate coprocessor FPGA resource
Occupation rate is defined as the service condition of FPGA internal resources in data handling procedure, by testing FPGA clocks, logic, storage
The occupancy of device resource and computing resource charges to test result with the peak use rate that some resource occupies.With x4Expression is deposited
Resources occupation rate is stored up, the service condition of storage resource in data handling procedure is defined as, it is empty by testing memory actual storage
Between with memory capacity ratio charge to test result.With x5It indicates transfer resource occupation rate, is defined as passing in data handling procedure
The service condition of defeated resource charges to test result by testing actual transfer rate with design interface rate ratio.With x6It indicates
Data throughout is defined as the data ability that interaction is set up within the unit interval, is counted with practical by test data operation total amount
Evaluation time ratio charges to test result.With x7Expression task is delayed, and is defined as data and reaches to the time of start to process, passes through survey
Examination data, which reach to the time ratios for starting to calculate, charges to test result.The quantification gradation of each evaluation index is divided into 9 grades, is respectively
Spy is good, fine, good, preferable, general, poor, poor, very poor and spy is poor, and introduces the quantization etc. that 1~9 scale realizes Comparative indices
Grade.The scale of each index is divided into 9 grades in efficiency evaluation index system, and the 1st grade of scale (special good) is denoted as c1Each evaluation is expressed as to refer to
Target limiting value, the 5th grade of scale (general) are denoted as c5It is expressed as the meter for each evaluation index that only disclosure satisfy that user performance requires
Scale 5 and 1 difference of scale are divided into 4 parts and obtain the increment size of scale by calculation value.2nd grade of scale (fine) is denoted as c2Table
Be shown as scale 1 and increment size and.3rd level scale (good) is denoted as c3Be expressed as scale 2 and increment size and.4th grade of scale (compared with
It is good) it is denoted as c3Be expressed as scale 3 and increment size and.6th grade of scale (poor) is denoted as c6Be expressed as scale 5 and increment size and.
7th grade of scale (poor) is denoted as c7Be expressed as scale 6 and increment size and.8th grade of scale (very poor) is denoted as c8Be expressed as scale 7 with
The sum of increment size.9th grade of scale (special poor) is denoted as c9Be expressed as scale 8 and increment size and.Thus obtained scale space note
For U={ c1, c2..., c9}；And the test value hits of each evaluation index should be greater than being equal to evaluation in efficiency evaluation index system
The quantification gradation number 9 of index.
Step 2：The ballot of each evaluation index in efficiency evaluation index system is obtained in a manner of voting by Experts consultation method
Weight, and evaluation index normalized weight coefficient in efficiency evaluation index system is determined by assignment method two-by-two；
Step 2.1, the expert of consulting carries out weight votes to each evaluation index respectively, obtains in efficiency evaluation index system
The ballot weight of each evaluation index.It is shown in Table 1.wiIt is k-th of expert for the ballot weight of i-th of evaluation index.Wherein (1≤i
≤ 7), (1≤k≤l), l are expert's number.
Ballot weight tabular form of the 1 Embedded System Design expert of table to each evaluation index.
Step 2.2, arithmetic average is carried out to the ballot weight ratio of each consultant expert according to following formula, as a result evaluation
The arithmetic average matrix of index ballot weight, is denoted as bI, j(j≤7 1≤i ＜).
Wherein, the ballot weight ratio of k-th of expert is denoted as1≤k≤l, l are expert's number, andwiIt is k-th of expert for the ballot weight of i-th of evaluation index.wjFor
Ballot weight of k-th of expert for j-th of evaluation index.
bR, q(1≤r≤7,2≤q≤7) and bQ, s(2≤q≤7,2≤s≤7) extracted in the result of step 2.2 respectively
It obtains.The 1st row result of statistical average matrix of evaluation index ballot weight is equal to the arithmetic average square of evaluation index ballot weight
The result of the 1st row of battle array.
Step 2.4, the result of step 2.3 is normalized according to following formula to obtain efficiency evaluation index system
Normalized weight coefficient, be denoted as
Wherein, i=1,2 ... 7, j=1,2 ... 7.WithRespectively in step
It extracts and obtains in 2.3 result.
Step 3：By the more fingers for obtaining efficiency evaluation index system based on the not determining architecture evaluation model estimated
Mark Synthetic Measurement evaluations matrix；
Step 3.1, with response time, host processor resources occupation rate, coprocessor FPGA resource occupation rate, storage resource
Occupation rate, transfer resource occupation rate, data throughout and task be delayed 7 evaluation indexes establish based on do not determine estimate it is embedding
Enter formula architecture efficiency evaluation model；Formed includes that all evaluation indexes correspond to the space of test data and are denoted as X={ x1,
x2,…,x7}；Wherein, xi(1≤i≤7) indicate the test value of i-th of evaluation index；
Step 3.2, have 1~9 quantitatively evaluating grade for each evaluation index in efficiency evaluation index system, it is special it is good,
Very well, good, preferable, general, poor, poor, very poor and spy is poor, corresponding 9 scale c1, c2..., c9, scale space is denoted as U=
{c1, c2..., c9}；Wherein ctIndicate t grades of scales, then t grades of scales are better than t+1 grades of scales, and scale space U is ordered into segmentation
Class；I-th of evaluation index test value x is calculated by following formulaiBelong to t-th of opinion rating ctDegree be denoted as,
μit=μ (xi∈ct)；
0≤μ(xi∈ct)≤1,
μ(xi∈ U)≤1, (formula 4)
Wherein i=1,2 ..., 7, t=1,2 ..., 9.
It is step 3.3, as follows by the result of step 3.2 structure comprehensive multi-index measuring and evaluation matrix,
Wherein, i=1,2 ..., 7, t=1,2 ..., 9.
Wherein i=1,2 ..., 7, t=1,2 ..., 9,It extracts and obtains in the result of step 2.4,In step
It extracts and obtains in 3.3 result.
Step 5：According to comprehensive multi-index measure evaluation vector, sentenced by established confidence level and criterion of identification
The opinion rating of the architecture adaptability is not obtained.Determine confidence level λ=0.7 and criterion of identification, ifThen the opinion rating of embedding assembly machine architecture is ρ0.If ρ0
=1 opinion rating is good, the ρ of spy0=2 opinion ratings are fine, ρ0=3 opinion ratings preferably, ρ0=4 opinion ratings are preferable, ρ0
=5 opinion ratings are general, ρ0=6 opinion ratings are poor, ρ0=7 opinion ratings are poor, ρ0=8 opinion ratings be it is very poor and
ρ0=9 opinion ratings are special poor.0≤τ≤ρ, ρ=1,2 ... 9 extract in the result of step 4.
Specifically, being made with the development and design of the quick processing system of agile remote sensing images based on software and hardware integration platform
Prototype is verified for the instantiation of this method.It is to find to be suitble to the hardware-accelerated of typical remote sensing image processing algorithm that it, which designs core,
Architectural framework and with the task balanced design strategy on this.The hardware plan is accelerated single using " DSP+FPGA " as specialized hardware
The algorithm performs mechanism of member, is responsible for the Hardware processing work of remote sensing images algorithm, and hardware composition includes mainly：DSP、FPGA、
RAM, Flash, clock module and power module etc., actual measurement task processing speed-up ratio reach 10 times.
Step 1, embedded computer efficiency evaluation index system is established, including task response-time, host processor resources
Occupation rate, coprocessor FPGA resource occupation rate, storage resource occupation rate, transfer resource occupation rate, data throughout and appoint
9 groups of sampling test datas of business 7 evaluation indexes of delay are as shown in table 2.
Each evaluation index test data of 2 efficiency evaluation index system of table.
The quantification gradation of each evaluation index is divided into 9 grades, is special good, fine, good, preferable, general, poor, poor, very poor respectively
It is poor with spy, and introduce the quantification gradation that 1~9 scale realizes Comparative indices.The corresponding scale of 9 grades of quantification gradations of each evaluation index
It is as follows：
The scale of task response-time={ 0.2,0.4,0.6,0.8,1,1.2,1.4,1.6,1.8 }；
The scale of host processor resources occupation rate={ 1,0.9,0.8,0.7,0.6,0.5,0.4,0.3,0.2 }；
The scale of coprocessor FPGA resource occupation rate={ 1,0.9,0.8,0.7,0.6,0.5,0.4,0.3,0.2 }；
The scale of storage resource occupation rate={ 1,0.9,0.8,0.7,0.6,0.5,0.4,0.3,0.2 }；
The scale of transfer resource occupation rate={ 1,0.9,0.8,0.7,0.6,0.5,0.4,0.3,0.2 }；
The scale of data throughout={ 2400,2200,2000,1800,1600,1400,1200,1000,800 }；
Scale={ 0,0.2,0.4,0.6,0.8,1,1.2,1.4,1.6 } of task delay；
Step 2：The ballot of each evaluation index in efficiency evaluation index system is obtained in a manner of voting by Experts consultation method
Weight, and evaluation index normalized weight coefficient in efficiency evaluation index system is determined by assignment method two-by-two；
Step 2.1,5 experts of embedded computer system design field to each evaluation index of efficiency evaluation index system into
Row weight votes are shown in Table 3.
Ballot weight of the 3 Embedded System Design expert of table to each evaluation index.
Step 2.2, arithmetic average is carried out to the ballot weight ratio of each consultant expert according to (formula 1), as a result evaluation
The arithmetic average matrix of index ballot weight is as follows：
Step 2.3, statistical average is carried out to the result of step 2.2 according to (formula 2), as a result evaluation index franchise
The statistical average matrix of weight is as follows：
Step 2.4, the result of step 2.2 is normalized according to (formula 3) to obtain efficiency evaluation index system
Normalized weight coefficient it is as follows：
Step 3：By the more fingers for obtaining efficiency evaluation index system based on the not determining architecture evaluation model estimated
Mark Synthetic Measurement evaluations matrix；
Step 3.1, with task responding ability, host processor resources occupation rate, coprocessor FPGA resource occupation rate, storage
Resources occupation rate, transfer resource occupation rate, data throughout and task 7 evaluation indexes of delay are established and are estimated based on determination
Embedded architecture efficiency evaluation model；Form the space that 7 evaluation indexes correspond to test data under 9 kinds of processing tasks
X is as follows：
Step 3.2：The test data that each evaluation index is established by (formula 4) is corresponded in 1~9 grade of quantification gradation in scale
Degree.With task response-time x1It corresponds to for the degree in scale calculates and illustrates in 1~9 grade of quantification gradation, 9 kinds are appointed
The test data of business is 0.42,0.04,0.26,0.38,0.15,0.2,0.46,0.52,0.83.The scale of task response-time
={ 0.2,0.4,0.6,0.8,1,1.2,1.4,1.6,1.8 } respectively it is corresponding special it is good, fine, good, preferable, general, poor, poor,
Very poor and spy is poor, and number of the task response-time less than or equal to 0.2 is 3, this scale degree of correspondence is 3/9；Task response-time
Number more than 0.2 less than or equal to 0.4 is 2, this scale degree of correspondence is 2/9；Task response-time is less than or equal to more than 0.4
0.6 number is 3, and the corresponding degree of this scale is 3/9；It is 0 that task response-time, which is more than 0.6 number less than or equal to 0.8, this
The corresponding degree of scale is 0；It is 1 that task response-time, which is more than 0.8 number less than or equal to 1, this scale degree of correspondence is 1/9；
It is 0 that task response-time, which is more than 1 number less than or equal to 1.2, this scale degree of correspondence is 0；It is small that task response-time is more than 1.2
It is 0 in the number equal to 1.4, this scale degree of correspondence is 0；It is 0 that task response-time, which is more than 1.4 number less than or equal to 1.6,
This scale degree of correspondence is 0；It is 0 that task response-time, which is more than 1.6 number less than or equal to 1.8, this scale degree of correspondence is 0；
Step 3.3, to obtain comprehensive multi-index measuring and evaluation matrix by the result of step 3.2 and (formula 5) as follows：
Step 4, by multi objective measuring and evaluation matrix and index weights vector, it is comprehensive that multi objective is calculated by (formula 6)
It is as follows to close measure evaluation vector
Step 5, confidence level and criterion of identification are established and calculates the embedded architecture evaluation grade.Take confidence level λ=
0.7, had by the result of step 4：
If ρ0=1,0.1587 ＜ 0.7；
If ρ0=2,0.1587+0.2423=0A010 ＜ 0.7；
If ρ0=3,0.1587+0.2423+0.3703=0.7713 ＞ 0.7；
Work as ρ as a result,0Comprehensive multi-index measure evaluation vector is more than confidence level 0.7 when=3, can differentiate the embedded body
Architecture Adaptability Evaluation grade is 3 grades, and corresponding quantification gradation is；This shows the embedded architecture overall evaluation
Preferably, and at least 0.7713 confidence level is not less than.This assessment result is consistent with the hardware-accelerated ratio for surveying 10 times.
Claims (7)
1. a kind of typical embedding assembly machine architecture efficiency evaluation method, which is characterized in that include the following steps,
Step 1, embedded computer efficiency evaluation index system is established；It, will be embedding according to the demand that embedded system information is handled
Enter after formula Computer Architecture is implemented and disclosure satisfy that the characteristic parameter involved by defined performance requirement is extracted, establishes one
Set is by task responding ability, host processor resources occupation rate, coprocessor FPGA resource occupation rate, storage resource occupation rate, biography
The embedding assembly machine architecture efficiency that defeated resources occupation rate, data throughout and task seven evaluation indexes of delay are constituted
Assessment indicator system, and determine the scale and quantification gradation of the test method and each evaluation index of evaluation index；
Step 2, the ballot weight of each evaluation index in efficiency evaluation index system is obtained in a manner of voting by Experts consultation method,
And evaluation index normalized weight coefficient in efficiency evaluation index system is determined by assignment method two-by-two；
Step 3, by showing that the multi objective of efficiency evaluation index system is comprehensive based on the not determining architecture evaluation model estimated
Close measuring and evaluation matrix；
Step 4, Utilization assessment index normalized weight coefficient obtains comprehensive multi-index survey with comprehensive multi-index measuring and evaluation matrix
Spend evaluation vector；
Step 5, according to comprehensive multi-index measure evaluation vector, differentiate to obtain the body by established confidence level and criterion of identification
The opinion rating of architecture adaptability；
In step 1, the test method of evaluation index is as follows in efficiency evaluation index system：With x1Expression task responding ability, definition
To complete the ability of predetermined processing task at the appointed time, the time that task is completed is handled by test data, with practical complete
The test result of response time is denoted as at the ratio between time and stipulated time；With x2It indicates host processor resources occupation rate, is defined as
The service condition of the internal resource of primary processor in data handling procedure, by testing the usage quantity of its ram in slice and outer
The expansible program and data space usage quantity in portion accounts for the number of used chip homegrown resource, the maximum occupied with some resource
Utilization rate charges to test result；With x3It indicates coprocessor FPGA resource occupation rate, is defined as in data handling procedure in FPGA
The service condition of portion's resource, by testing the occupancy of FPGA clocks, logic, memory resource and computing resource, with some
The peak use rate that resource occupies charges to test result；With x4It indicates storage resource occupation rate, is defined as in data handling procedure
The service condition of storage resource charges to test result by testing the memory physical memory space with memory capacity ratio；With
x5It indicates transfer resource occupation rate, is defined as the service condition of transfer resource in data handling procedure, by testing actual transmissions
Rate charges to test result with design interface rate ratio；With x6It indicates data throughout, is defined as data within the unit interval
The ability that interaction is set up charges to test result by test data operation total amount and the practical time ratios that calculate；With x7It indicates to appoint
Business delay, is defined as data and reaches to the time of start to process, is reached to the time ratios for starting to calculate by test data and is remembered
Enter test result.
2. a kind of typical embedding assembly machine architecture efficiency evaluation method according to claim 1, feature exist
In the quantification gradation of each evaluation index is divided into 9 grades, is special good, fine, good, preferable, general, poor, poor, very poor and special respectively
Difference, and introduce the quantification gradation that 1~9 scale realizes Comparative indices；
The scale of each index is divided into 9 grades in efficiency evaluation index system, and the 1st grade of scale is special good, is denoted as c1Each evaluation is expressed as to refer to
Target limiting value；5th grade of scale is general, is denoted as c5It is expressed as the meter for each evaluation index that only disclosure satisfy that user performance requires
Scale 5 and 1 difference of scale are divided into 4 parts and obtain the increment size of scale by calculation value；
2nd grade of scale is fine, is denoted as c2Be expressed as scale 1 and increment size and；3rd level scale preferably, is denoted as c3It is expressed as marking
Degree 2 with increment size and；4th grade of scale is preferable, is denoted as c3Be expressed as scale 3 and increment size and；6th grade of scale be compared with
Difference is denoted as c6Be expressed as scale 5 and increment size and；7th grade of scale is poor, is denoted as c7Be expressed as scale 6 and increment size and；
8th grade of scale is very poor, is denoted as c8Be expressed as scale 7 and increment size and；9th grade of scale is special poor, is denoted as c9It is expressed as scale
8 with increment size and；Thus obtained scale space is denoted as U={ c1, c2..., c9}；And it is respectively commented in efficiency evaluation index system
The test value hits of valence index should be greater than the quantification gradation number 9 equal to evaluation index.
3. a kind of typical embedding assembly machine architecture efficiency evaluation method according to claim 1, feature exist
In in step 2, when using Experts consultation method, selection is no less than four expert consultings, and wherein expert limits research field as insertion
Formula system designs and academic title is not less than senior engineer.
4. a kind of typical embedding assembly machine architecture efficiency evaluation method according to claim 1, feature exist
In, step 2 is as follows,
Step 2.1, the expert of consulting carries out weight votes to each evaluation index respectively, obtains respectively commenting in efficiency evaluation index system
The ballot weight of valence index；
Step 2.2, arithmetic average is carried out to the ballot weight ratio of each consultant expert according to following formula, as a result evaluation index
The arithmetic average matrix of ballot weight, is denoted as bI, j(j≤7 1≤i ＜)；
Wherein, the ballot weight ratio of k-th of expert is denoted asL is expert's number, andwiIt is k-th of expert for the ballot weight of i-th of evaluation index；wjFor
Ballot weight of k-th of expert for j-th of evaluation index；
Step 2.3, according to following formula to the ballot weight of each consultant expert than arithmetic average matrix carry out statistical average,
As a result it is the statistical average matrix of evaluation index ballot weight, is denoted as
Wherein,
bR, q(1≤r≤7,2≤q≤7) and bQ, s(2≤q≤7,2≤s≤7) extract obtain in the result of step 2.2 respectively
；The 1st row result of statistical average matrix of evaluation index ballot weight is equal to the arithmetic average matrix of evaluation index ballot weight
The result of 1st row；
Step 2.4, the result of step 2.3 is normalized according to following formula to obtain returning for efficiency evaluation index system
One changes weight coefficient, is denoted as
Wherein, i=1,2 ..., 7, j=1,2 ..., 7；WithRespectively in step 2.3
As a result it extracts and obtains in.
5. a kind of typical embedding assembly machine architecture efficiency evaluation method according to claim 4, feature exist
In, step 3 specifically comprises the following steps,
Step 3.1, with task responding ability, host processor resources occupation rate, coprocessor FPGA resource occupation rate, storage resource
Occupation rate, transfer resource occupation rate, data throughout and task be delayed 7 evaluation indexes establish based on do not determine estimate it is embedding
Enter formula architecture efficiency evaluation model；Formed includes that all evaluation indexes correspond to the space of test data and are denoted as X={ x1,
x2,…,x7}；Wherein, xi(1≤i≤7) indicate the test value of i-th of evaluation index；
Step 3.2, have 1~9 quantitatively evaluating grade for each evaluation index in efficiency evaluation index system, it is special it is good, fine,
Good, preferable, general, poor, poor, very poor and spy is poor, corresponding 9 scale c1, c2..., c9, scale space is denoted as U={ c1,
c2..., c9}；Wherein ctIndicate t grades of scales, then t grades of scales are better than t+1 grades of scales, and scale space U is ordered into segmentation class；It is logical
It crosses following formula and i-th of evaluation index test value x is calculatediBelong to t-th of opinion rating ctDegree be denoted as,
μit=μ (xi∈ct)；
0≤μ(xi∈ct)≤1,
μ(xi∈ U)≤1,
Wherein i=1,2 ..., 7, t=1,2 ..., 9；
It is step 3.3, as follows by the result of step 3.2 structure comprehensive multi-index measuring and evaluation matrix,
Wherein, i=1,2 ..., 7, t=1,2 ..., 9.
6. a kind of typical embedding assembly machine architecture efficiency evaluation method according to claim 5, feature exist
In in step 4, Utilization assessment index normalized weight coefficient and comprehensive multi-index measuring and evaluation matrix pass through following formula meter
Calculation obtains comprehensive multi-index measure evaluation vector, is denoted as
Wherein,I=1,2 ..., 7, t=1,2 ..., 9,It extracts and obtains in the result of step 2.4,
μitIt extracts and obtains in the result of step 3.3.
7. a kind of typical embedding assembly machine architecture efficiency evaluation method according to claim 6, feature exist
In, in step 5, determine confidence level λ=0.7 and criterion of identification, ifThen
The opinion rating of embedding assembly machine architecture is ρ0；If ρ0=1 opinion rating is good, the ρ of spy0=2 opinion ratings are very
Good, ρ0=3 opinion ratings preferably, ρ0=4 opinion ratings are preferable, ρ0=5 opinion ratings are general, ρ0=6 opinion ratings be compared with
Difference, ρ0=7 opinion ratings are poor, ρ0=8 opinion ratings are very poor and ρ0=9 opinion ratings are special poor；In the result of step 4
Middle extraction 0≤τ≤ρ, ρ=1,2 ... 9.
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