CN105743327A - Control circuit and control method for switched capacitor converter - Google Patents

Control circuit and control method for switched capacitor converter Download PDF

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CN105743327A
CN105743327A CN201610202792.XA CN201610202792A CN105743327A CN 105743327 A CN105743327 A CN 105743327A CN 201610202792 A CN201610202792 A CN 201610202792A CN 105743327 A CN105743327 A CN 105743327A
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signal
switch
reset
control
output
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CN105743327B (en
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杨磊
张晓斌
蔡沛
吴斌
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西北工业大学
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    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00Details of apparatus for conversion
    • H02M1/08Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00Details of apparatus for conversion
    • H02M2001/0003Details of control, feedback and regulation circuits

Abstract

The invention discloses a control circuit and a control method for a switched capacitor converter and aims at solving the technical problem of a complicated control circuit of an existing switched capacitor converter. According to the technical scheme, the control circuit comprises three subtracters, two resettable integral circuit units, two comparator units and two RS trigger units. Due to the action of the resettable integral circuit units, feedback signal modulation of a single-cycle control circuit is only concerned with an input voltage feedback state and an output voltage feedback state of the currentcycle and is irrelevant to the historical state; and inhibition on external input and output voltage disturbance is finished within one cycle. In addition, an input voltage signal and an output voltage signal are both in the feedback loop, so that disturbance on the input voltage and the output load is instantaneously fed back to the control circuit. The dynamic reaction speed is high; the input range and the output range are wide; and the control logic circuit is simple in structure and easy to implement in engineering.

Description

开关电容变换器控制电路及控制方法 Switched capacitor converter control circuit and control method

技术领域 FIELD

[0001] 本发明设及一种控制电路,特别设及一种开关电容变换器控制电路。 [0001] The present invention is provided, and one control circuit, and a switched capacitor provided particularly converter control circuit. 还设及一种开关电容变换器控制电路的控制方法。 The method is further provided a control circuit and a switched capacitor converter control.

背景技术 Background technique

[0002] 参照图8。 [0002] Referring to FIG. 文献l''Siew-化ong 化]!,Sevetlana Bronstein,Moshe Nur,YMLai, etal,Nonlinear control of switched-capacitor converter using sliding mode control approach[C],Power Electronics Specialists Conference(PESC)pp.372-377, 2008"和文献2"Siew-畑ong !"Sn,Sevetlana 化onstein,Moshe Nu;r,YM丄ai ,Variable Structure Modeling and Design of Switched-Capacitor Converters, IEEE Transactions on Circuits and Systems I: Regular Papers,2009,Vol56(9),pp:2132-2142"公开了一种应用于两相开关电容变换器的非线性定频滑模控制方法及控制电路。 Document l' 'Siew- of ong of] !, Sevetlana Bronstein, Moshe Nur, YMLai, etal, Nonlinear control of switched-capacitor converter using sliding mode control approach [C], Power Electronics Specialists Conference (PESC) pp.372-377 , 2008 "and Document 2" Siew- Hata ong "Sn, Sevetlana of onstein, Moshe Nu; r, YM Shang ai, Variable Structure Modeling and Design of Switched-Capacitor Converters, IEEE Transactions on Circuits and Systems I:! Regular Papers, 2009, Vol56 (9), pp: 2132-2142 "discloses a two-phase switched-capacitor converter is applied to a nonlinear sliding mode control method and a fixed frequency control circuit. 该控制方法基于开关电容变换器输出滤波电容能量守恒原则,得出了存储电容准确的实时充电输入电流和实时放电输出电流之间的关系,用于建立在充电和放电过程中的大信号模型。 The switched-capacitor converter control method of conservation of energy based on the principle of the output filter capacitor, the relationship between the derived accurate real time charging the storage capacitor and the input current discharge output current real time, the large-signal model for establishing the charging and discharging process. 在此基础上,根据确定的开关函数并采用W比例-积分(PI)滑模面,建立了一种滑模控制模型。 On this basis, according to the determined switching function and a W proportional - integral (PI) sliding surface, sliding mode control establishes a model. 其控制电路采用与传统的电压模式PWM控制电路相同的结构,在此基础上增加了额外的反馈电路检测元件:输出电流实时检测传感器,用于形成控制信号;输入电压信号传感器W及存储电容电压信号传感器,用于控制斜坡信号的幅度。 And a control circuit which uses a conventional voltage mode PWM control of the same circuit configuration on the basis of a feedback circuit adds an additional detection element: an output current detecting sensor in real time, for forming a control signal; W input voltage signal of the sensor and the storage capacitor voltage a sensor signal for controlling the amplitude of the ramp signal. 运些额外增加的元器件使得反馈回路具有非线性的特点。 Transport some additional components so that the feedback loop is non-linear. 该反馈控制电路具有良好的动态和稳态性能。 The feedback control circuit has good dynamic and static performance. 滑模控制方法及其控制电路的缺点是:1)滑模控制方法需要满足可达性,存在性和稳定性的条件,其输入电压和输出负载需要限制在一定范围之内,所W其应用具有一定的局限性;2)滑模控制电路需要经过多个周期才能有效抑制外界扰动,扰动调节时间较长;3)在滑模控制电路中需要电流信号传感器W及斜坡信号发生器等多种成本较高的元器件,其控制电路较为复杂, 在实际应用中很难实现。 Disadvantage of sliding mode control method and a control circuit are: 1) The sliding mode control method needs to satisfy the reachability, stability and the presence of the input voltage and the output load needs to be limited within a certain range of its applications W It has certain limitations; 2) sliding mode control circuit to go through a plurality of cycles to effectively suppress external disturbance, the disturbance adjusted longer; 3) in the sliding mode control circuit requires a current sensor signal and a ramp signal generator, W and other high cost components, which control circuit is complicated, difficult to implement in practice.

[0003] 参照图9。 [0003] Referring to FIG. 文献2"专利号是齡.52784901(65〇16 1日51116(1167,〇]16-巧。16〇〇]1化〇116(1 switching ci;rcuits[P],USpatent application Ser."公开了一种开关电源变换器的单周期控制电路(OCC),其控制电路主要采用可复位的有源运算放大电路积分器,比较器和基于边沿触发的Reset-Set(RS)触发器。在每个周期开始时,高电平时钟化OCK信号使得RS 触发器置位,其Q端输出高电平,开关电源变换器主电路开关管导通;同时,RS触发器巧端输出低电平,控制电路可复位积分器的复位开关管断开,输入信号x(t)通过可复位积分器开始积分。当输入信号积分值Vint达到参考电压值Vref时,控制电路比较器输出高电平,RS触发器复位,其Q端输出低电平,开关电源变换器主电路开关管断开;同时,RS触发器巧端输出高电平,控制电路可复位积分器的复位开关管导通,可复位积分器置零。在该专利的控制方法中 Document 2 "is age Patent No. .52784901 (65〇16 the 1st 51116 (1167 square] 16- Qiao .16〇〇] 1 of 〇116 (1 switching ci;. Rcuits [P], USpatent application Ser" discloses a single-cycle of a power converter control circuit (the OCC), which can reset the control circuit mainly active integrator operational amplifier circuit, a comparator, and based on reset-Set (RS) flip-flop trigged. each at the beginning of the cycle, so that the high-level clock signal OCK of RS flip-flop is set, its Q output high, the inverter main circuit switching power supply switch is turned on; the same time, RS flip-flop output low end clever control reset circuit may switch the integrator off, the input signal x (t) can be reset by the integrator starts integration. when the input signal integration value Vint reaches the reference voltage Vref, the control circuit the comparator output high, RS trigger reset, its Q terminal outputs a low level, the inverter main circuit switching power OFF switch; simultaneously, RS flip-flop output high coincidence, the control circuit resets resettable integrator switch is turned on, the resettable integrator It is set to zero. in the control method of patent ,输出信号y(t)和参考电压信号Vref保持线性平衡关系。其控制电路能够单周期抑制外界输入信号和负载扰动。该专利控制电路的缺点是可复位的有源运算放大电路积分器成本局,电路较为复杂。 , The output signal y (t) and the reference voltage signal Vref to maintain the balance between the linear its single-cycle control circuit can be suppressed and external load disturbance input signal disadvantage of this patent is an active control circuit of the operational amplifier circuit resettable integrator cost Board , the circuit is more complex.

发明内容 SUMMARY

[0004] 为了克服现有开关电容变换器控制电路复杂的不足,本发明提供一种开关电容变换器控制电路及控制方法。 [0004] In order to overcome the conventional switched capacitor converter control circuit complex deficiency, the present invention provides a switched capacitor converter control circuit and control method. 控制电路包括=个减法器、两个可复位积分器、两个比较器和两个RS触发器W及一些其它线性元件。 The control circuit comprises a = subtractors, two resettable integrators, two comparators and two RS flip-flop W and other linear element. 由于可复位积分器的作用,单周期控制电路的反馈信号调制仅与本周期输入电压和输出电压反馈状态有关而与历史状态无关,在一个周期内完成对外界输入和输出电压扰动的抑制。 Due resettable integrator, single-cycle modulation control circuit of the feedback signal is only present cycle of the input voltage and the output voltage feedback about the status regardless of historical state, complete suppression of external disturbance input and output voltages in one cycle. 另外,因为输入电压和输出电压信号都在反馈回路中,所W输入电压和输出负载上的扰动被瞬时反馈到控制电路中。 Further, since the input voltage and output voltage signals in the feedback loop, the perturbation W input voltage and the output load is instantaneously fed back to the control circuit. 动态反应速度快,输入和输出范围宽,逻辑控制电路结构简单,在工程上易于实现。 Dynamic response speed, wide input and output ranges, the control logic circuit configuration is simple, easy to implement engineering.

[0005] 本发明解决其技术问题所采用的技术方案是:一种开关电容变换器控制电路,其特点是:包括减法器101、减法器102、减法器103、可复位积分器104、可复位积分器105、比较器106、比较器107、RS触发器108和RS触发器109。 [0005] aspect of the present invention to solve the technical problem is: A switched capacitor converter control circuit, characterized by: a subtracter 101, a subtractor 102, subtractor 103, integrator 104 may be reset, reset an integrator 105, a comparator 106, a comparator 107, RS flip-flop 108 and RS flip-flop 109.

[0006] 所述减法器101的同向输入端接收反馈的输入信号Vin,反向输入端接收反馈的存储电容Cl电压信号Vcl(t),其输出信号是第一差值信号(Vin-Vciw),并作为可复位积分器104 的输入信号。 Receive the same [0006] The subtractor 101 is fed back to the signal input terminal Vin, an inverting input signal voltage of the storage capacitor Cl Vcl (t) receives feedback, the output signal of the first difference signal (Vin-Vciw ), and resettable integrator 104 as an input signal.

[0007] 所述减法器102的同向输入端接收反馈的输入信号Vin,反向输入端接收反馈的存储电容C2电压信号Vc2(t),其输出信号是第二差值信号(Vin-Vc2(t)),并作为可复位积分器105 的输入信号。 Receive the same [0007] The subtractor 102 is fed back to the signal input terminal Vin, an inverting input voltage of the storage capacitor C2 signal Vc2 (t) of the terminal receiving feedback, the output signal is the second difference signal (Vin-Vc2 (t)), and a resettable integrator input signal 105.

[0008] 所述减法器103的同向输入端接收输出电压参考信号Vref,反向输入端接收反馈的输出电压信号V。 With [0008] The subtracter 103 receives the output voltage reference signal Vref to the input terminal, an inverting input terminal receiving an output voltage feedback signal V. ,其输出信号是第立差值信号Ve = K(Vref-Vn), K是常数,第立差值信号Ve作为比较器106的反向输入端的输入信号。 , The output signal of the first vertical difference signal Ve = K (Vref-Vn), K is a constant, the first vertical difference signal Ve input of the inverting input of the comparator 106 signal.

[0009] 所述可复位积分器104由电阻化和电容C3组成。 [0009] The integrator 104 may be reset by a resistor and capacitor C3. 所述电阻Ri的一端作为输入端接收第一差值信号(Vin-VcKt)),电阻Rl的另一端与所述电容C3相连,共同作为所述可复位积分器104输出端,电容C3另一端与地线相连; One end of the resistor Ri receiving the first difference signal as an input terminal (Vin-VcKt)), the other end of the resistor Rl and the capacitor C3 is connected to a common output terminal of the resettable integrator 104, the other end of the capacitor C3 connected with the ground;

[0010] 复位开关Wi并联在所述电容C3两端。 [0010] Wi reset switch is connected in parallel to the capacitor C3.

[0011] 所述可复位积分器104对第一差值信号(Vin-VcKt))进行积分,生成并输出第一积分信号Vintl。 [0011] The resettable integrator 104 may be a first difference signal (Vin-VcKt)) is integrated, generates and outputs a first integrated signal Vintl.

[0012] 所述可复位积分器105由电阻R2和电容C4组成。 [0012] The integrator 105 may be reset by the resistor R2 and the capacitor C4. 所述电阻R2的一端作为输入端接收第二差值信号(Vin-Vc2(t)),电阻R2的另一端与所述电容C4相连,共同作为所述可复位积分器105输出端,电容C4另一端与地线相连; One end of the resistor R2 receiving a second difference signal (Vin-Vc2 (t)), the other end of the resistor R2 and the capacitor C4 is connected together as a resettable integrator output terminal 105 as an input, capacitor C4 the other end is connected to the ground;

[0013] 复位开关W2并联在所述电容C4两端。 [0013] W2 reset switch connected in parallel at both ends of the capacitor C4.

[0014] 所述可复位积分器105对第二差值信号(Vin-Vc2(t))进行积分,生成并输出第二积分信号Vint2。 [0014] The resettable integrator 105 may be a second difference signal (Vin-Vc2 (t)) is integrated, generates and outputs a second integrated signal Vint2.

[0015] 所述比较器106的同向输入端接收第一积分信号Vintl,反向输入端接收第S差值信号Ve。 The [0015] Comparator 106 receives a first integrated signal Vintl input terminal, an inverting input terminal S receives the first difference signal Ve. 所述比较器106生成并输出数字电平形式的比较结果信号Ucnml。 The comparator 106 generates and outputs a digital level comparison result signal in the form of Ucnml.

[0016] 所述比较器107的同向输入端接收第二积分信号Vintv,反向输入端接收第=差值信号Ve。 The [0016] Comparator 107 receives the same Vintv second integrated signal input terminal, an inverting input receiving a first difference signal = Ve. 所述比较器107生成并输出数字电平形式的比较结果信号Ucnm2。 The comparator 107 generates and outputs a digital level comparison result signal in the form of Ucnm2.

[0017] 所述RS触发器108的R输入端接收所述比较结果信号Uenml,S输入端接收外部周期时钟信号CLK1。 The [0017] RS flip-flop 108 is an input terminal R receives the comparison result signal Uenml, S input for receiving an external clock signal cycle CLK1. 所述RS触发器108的Q输出端生成控制信号化1并送入外部驱动电路,控制开关电容变换器开关管Si的导通和关断,廷输出端生成所述复位信号Uwi,控制所述可复位积分器104复位开关Wi的导通和关断。 The Q output of the RS flip-flop 108 generates a control signal of 1 and sent to an external driving circuit, a control switch Si switched capacitor converter ON and OFF, the output terminal ting uwi generating said reset signal, said control resettable integrator reset switch 104 is turned on and a Wi off.

[0018] 所述RS触发器109的R输入端接收所述比较结果信号Uenm2, S输入端接收外部周期时钟信号CLK2。 R input [0018] The RS flip-flop 109 receives the comparison result signal Uenm2, S input for receiving an external clock signal cycle CLK2. 所述RS触发器109的Q输出端生成控制信号化3并送入外部驱动电路,控制开关电容变换器开关管S3的导通和关断,巧输出端生成所述复位信号机2,控制所述可复位积分器105复位开关W2的导通和关断。 The Q output of RS flip-flop 109 generates a control signal for 3 and sent to an external driving circuit, switched capacitor converter controls the switch S3 is turned on and off, generating a coincidence output of the reset signal 2, the control said resettable integrator reset switch 105 is turned on and W2 is turned off.

[0019] -种适用于上述开关电容变换器控制电路的控制方法,其特点是包括W下步骤: [0019] - species suitable for the above method of controlling a switched capacitor converter control circuit, characterized by comprising the steps of W:

[0020] 步骤一、设定开关管S2和S4的控制信号为占空比恒为0.5,相位相差180°的两组方波信号。 [0020] Step one, two square-wave signal setting switch S2 and the control signal S4 is a constant duty ratio is 0.5, the phase difference of 180 °. 其中,开关管S2的控制信号和开关管S3的控制信号同步;开关管S4的控制信号与开关管Sl的控制信号同步。 Wherein the switch S2 and the control signals synchronizing switch S3; the control signals Sl and switch S4 is synchronized switching.

[0021] 步骤二、对存储电容Cl和存储电容C2的充放电过程分别建立改进的单周期控制模型,控制公式分别为式(1)和式(2): [0021] Step II of the process of charging and discharging the storage capacitance of the storage capacitor Cl and C2, respectively, to establish an improved single-cycle control model, control formulas are formulas (1) and (2):

Figure CN105743327AD00061

[0022] (1) [0022] (1)

[0023] (2) [0023] (2)

[0024] 其中,Kl,K2和K都是常数,Vin是输入电压,Vo是输出电压,Vref是输出参考电压, Vcl(t)是充电状态下存储电容Cl的电压,Vc2(t)是充电状态下存储电容C2的电压,DlTs是存储电容Cl的充电时间,化Ts是存储电容C2的充电时间。 [0024] wherein, Kl, K2 and K are constants, Vin is the input voltage, Vo is the output voltage, Vref is a reference voltage output, Vcl (t) is the voltage of the storage capacitor Cl is charged state, Vc2 (t) is the charge voltage of the storage capacitor C2 in the state, the storage capacitor Cl is DLTS charging time, charging time Ts of the storage capacitor C2.

[0025] 核屯、控制公式(1)和(2)所生成的控制信号分别实时调节控制开关管Si和开关管S3 的导通和关断。 [0025] Nuclear Tun, control formula (1) and (2) the generated control signals are adjusted in real-time control switch Si and the switch S3 is turned on and off.

[0026] 步骤S、可复位积分器104在RS触发器108置位(Q=l,巧=0)即在开关管Si导通时间内,连续的对第一差值信号(Vin-Vciw)进行积分,得到第一积分信号Vintl。 [0026] Step S, resettable integrator 104 in the RS flip-flop 108 is set (Q = l, Qiao = 0) i.e. the switch Si conduction time, continuous first difference signal (Vin-Vciw) integrating, to obtain a first integrated signal Vintl. 并实时的与第S差值信号Ve进行比较。 Real time is compared with the second difference signal S Ve. 当第一积分信号Vintl小于第S差值信号Ve时,比较器106保持低电平,开关管Sl继续导通,RS触发器108维持置位;当第一积分信号Vintl等于或者大于第=差值信号Ve时,比较器106变为高电平,开关管Si关断,RS触发器108复位(Q = O,巧=1)。 When the first integrated signal difference signal S Vintl smaller than Ve, the comparator 106 remains low, switch Sl is turned on continues, RS flip-flop 108 is maintained set; when the first integral signal is equal to or greater than the Vintl difference = when the value of the signal Ve, the comparator 106 goes high, the switch Si oFF, RS flip-flop 108 is reset (Q = O, Qiao = 1). 可复位积分器104的复位开关Wi导通,可复位积分器104置零并准备接收下一个周期的第一差值信号(Vin-Vcl(t))。 Resettable integrator reset switch 104 is turned on Wi, the integrator 104 may be reset to zero and ready for the next signal reception period a first difference (Vin-Vcl (t)).

[0027] 可复位积分器105在RS触发器109置位(Q=IQ = 0)即在开关管S3导通时间内,连续的对第二差值信号(Vin-Vt2(t))进行积分,得到第二积分信号Vint2,并实时地与第S差值信号Ve进行比较。 [0027] resettable integrator 105 RS flip-flop 109 is set (Q = IQ = 0) i.e. the time the switch S3 is turned on, a continuous second difference signal (Vin-Vt2 (t)) is integrated , to obtain a second integrated signal Vint2, and real time comparison with the first difference signal S Ve. 当第二积分信号Vint2小于第立差值信号Ve时,比较器107保持低电平,开关管S3继续导通,RS触发器109维持置位;当第二积分信号Vint2等于或者大于第S差值信号Ve时, 比较器107变为高电平,开关管S3关断,RS触发器109复位(Q = O,巧=1)。 When the second integrated signal Vint2 smaller than the vertical difference signal Ve, the comparator 107 remains low, the switch S3 is turned on continues, RS flip-flop 109 is set to maintain; Vint2 when the second integrated signal S is equal to or greater than the difference when the value of the signal Ve, the comparator 107 goes high, the switch S3 is turned off, RS flip-flop 109 is reset (Q = O, Qiao = 1). 可复位积分器105 的复位开关W2导通,可复位积分器105置零并准备接收下一个周期的第二差值信号(Vin- Vc2(t)) O Resettable integrator reset switch 105 is turned W2, the integrator 105 may be reset to zero and ready to receive the next cycle of the second difference signal (Vin- Vc2 (t)) O

[00%]本发明的有益效果是:控制电路仅由=个减法器、两个可复位积分器、两个比较器和两个无源RS触发器和一些其它线性元件组成。 [00%] Advantageous effects of the present invention is: a = control circuit only subtractors, two resettable integrators, two comparators and two RS flip-flops and other passive linear elements. 其控制电路简单且成本较低。 A control circuit which is simple and low cost. 由于可复位积分器的作用,此发明的控制电路的反馈信号调制仅与本周期输入信号和输出信号反馈状态有而与历史状态无关。 Due resettable integrator, the feedback signal modulation control circuit of this invention only to this cycle of the input signal and the output signal regardless of the state in which the feedback state history. 本发明控制方法可在一个时钟周期内完成对外界输入信号扰动和负载扰动的抑制,且不受输入电压范围和负载范围的影响。 Control method of the present invention can suppress the influence of the external input signal and the disturbance load disturbance, and is not input voltage range and load range of one clock cycle. 相对于滑模变结构控制,其动态反应速度较快,输入电压和负载范围较宽。 With respect to the sliding mode control, the dynamic response speed, wide input voltage and load range.

[0029] 下面结合具体实施方式对本发明作详细说明。 [0029] DETAILED DESCRIPTION The following embodiments of the present invention will be described in detail.

附图说明 BRIEF DESCRIPTION

[0030] 图1是本发明开关电容变换器控制电路结构图。 [0030] FIG. 1 is a switched capacitor converter control circuit configuration diagram of the present invention.

[0031 ]图2是图1中部分元器件的波形图。 [0031] FIG. 2 is a waveform diagram of a portion of the components of FIG.

[0032] 图3是图1控制电路对输入电压扰动抑制波形图。 [0032] FIG. 3 is a control circuit of Figure 1 the input voltage waveform diagram suppressing disturbance.

[0033] 图4是图1控制电路对负载扰动抑制波形图。 [0033] FIG. 4 is a load control circuit of FIG waveform disturbance suppression FIG.

[0034] 图5是本发明实施例两相开关电容变换器的主功率电路。 [0034] FIG 5 is a main power circuit according to a two-phase switched capacitor converter embodiment of the present invention.

[0035] 图6是图5主功率电路的开关管驱动信号波形图。 [0035] FIG. 6 is a waveform diagram of a gate driver signal to the main power circuit 5 in FIG.

[0036] 图7是图5主功率电路的状态运行图。 [0036] FIG. 7 is a state diagram of the main power circuit 5 in FIG.

[0037] 图8是背景技术文献1公开的开关电容变换器滑模控制电路。 [0037] FIG. 8 is a background art document 1 discloses a switched capacitor converter sliding mode control circuit.

[0038] 图9是背景技术文献2公开的开关电源变换器单周期控制电路。 [0038] FIG. 9 is a background art document 2 discloses a single-cycle control of switching power converter circuit.

具体实施方式 Detailed ways

[0039] 参照图1-7。 [0039] Referring to FIG 1-7. 本发明是针对开关电容变换器提出的,因此为清楚地描述本发明提出的控制电路和控制方法,需要W两相互补对称开关电容变换器作为实施例阐述具体的实现方式。 The present invention is proposed for the switched capacitor converter, so as to clearly describe the control circuit and a control method proposed by the present invention requires two complementary symmetrical W switched capacitor converter as set forth in Example specific implementation.

[0040] 为更清楚地阐述技术方案,首先概述开关电容变换器的特点。 [0040] The technical solution to more clearly set forth, first outlines the characteristics of the switched capacitor converter. 所述开关电容变换器由四个开关管Si,开关管S2,开关管S3和开关管S4、存储电容Cl和存储电容C2、一个输出电容Co和负载电阻化组成。 The switched-capacitor converter comprises four switch Si, switch S2, the switch switches S3 and S4, the storage capacitor Cl and a storage capacitor C2, an output capacitor Co and a load resistance of the composition. 所述开关电容变换器采用互补对称结构(存储电容Cl和C2的充放电过程是互补的),通过控制存储电容Cl和存储电容C2的充放电W控制开关电容变换器的输出电压。 The switched capacitor converter using complementary symmetry structure (storage capacitors Cl and C2 during charging and discharging is complementary), by controlling the storage capacitor Cl and C2 is charging and discharging the storage capacitance W control the output voltage of the switched-capacitor converter. 开关管存储电容Cl的充电由开关管Sl决定,放电由开关管S2决定;存储电容C2的充电由开关管S3决定,放电由开关管S4决定。 Charging the storage capacitor Cl switch is determined by the switch Sl, the discharge is determined by the switch S2; charge storage capacitor C2 is determined by the switch S3, the discharge is determined by the switch S4. 所述开关电容变换器充放电有四个状态过程。 The switched capacitor converter has four states during charging and discharging. 状态1,开关管Sl和开关管S4导通,开关管S2和开关管S3关断,电源对存储电容Cl充电,存储电容C2 对输出电容和负载放电;状态2,开关管S4保持导通,开关管Si、开关管S2和开关管S3关断,电源对存储电容Cl停止充电,存储电容C2对输出电容Co和负载继续放电;状态3,与状态1互补, 开关S2和S3导通,开关管Sl和开关管S4关断,电源对存储电容C2充电,存储电容Cl对输出电容Co和负载化放电;状态4,与状态2互补,开关管S2保持导通,开关管Si、开关管S3和开关管S4关断,电源对存储电容C2停止充电,存储电容Cl对输出电容Co和负载化继续放电。 State 1, the switch Sl and the switch S4 is turned on, the switch S2 and the switch S3 is turned off, the power storage capacitor Cl charged, the storage capacitor C2 to the output capacitor and load discharge; state 2, switch S4 remains turned on, switch Si, switch S2 and the switch S3 is turned off, the power supply stops charging the storage capacitor Cl, the storage capacitor C2 the output capacitor Co and the load continues to be discharged; state 3, state 1 is complementary, switches S2 and S3 is turned on, the switch tube Sl and S4 is turned off, the power storage capacitor C2 is charged, the storage capacitor Cl to the output capacitor Co and a load of discharge; state 4, state 2 is complementary to the switch S2 remains turned on, the switch Si, switch S3 and the switch S4 is turned off, the power supply stops charging the storage capacitor C2, a storage capacitor Cl to the output capacitor Co and the load of the discharge continues.

[0041] 所述两相开关电容变换器作为主功率电路,主要由存储电容Cl和存储电容C2及开关管Si、开关管S2、开关管S3和开关管S4组成。 [0041] The two-phase transformer as the main power switch capacitor circuits, mainly by the storage capacitor and the storage capacitor C2 and Cl switch Si, switch S2, switches S3 and S4 composition. 其中,开关管Sl和开关管S3参数一致且不能同时导通,分别控制存储电容Cl和存储电容C2的充电,开关管S2和开关管S4参数一致且不能同时导通,分别控制存储电容Cl和存储电容C2的放电。 Wherein the same switch Sl and the switch S3 parameters and can not simultaneously turned on, control the charge storage capacitor Cl and a storage capacitor C2, the same switch S2 and S4 parameters and can not simultaneously turned on, control the storage capacitor Cl and discharging the storage capacitor C2. 存储电容Cl和存储电容C2在一周期Ts内相继充放电,在前半个周期存储电容Cl充电时间维持DTs,存储电容C2放电时间维持0.5TS。 Storage capacitors Cl and C2 successive charging and discharging the storage capacitance in a period Ts of, sustain DTs half cycle preceding the charging time of the storage capacitor Cl, the storage capacitor C2 discharge time maintained 0.5TS. 在后半个周期,存储电容C2充电时间维持DTs,存储电容Cl放电时间维持0.5Ts。 In the latter half cycle, the storage capacitor C2 is charged to maintain the DTs time, the discharge time of the storage capacitor Cl is maintained 0.5Ts.

[0042] 具体的,因所述主功率电路的互补对称性,限定开关管S2的控制信号化2和开关管S4的控制信号化4均为占空比0.5、相位相差180°的方波信号,无需调制。 [0042] Specifically, because of the complementary symmetry of the main power circuit, and defining a control signal of the control signal 2 of the switch S4 the switch S2 are the duty ratio of 0.5 4, 180 ° out of phase square wave signals without modulation.

[0043] 所述控制电路仅对开关管Si的控制信号化I和开关管S3的控制信号化3进行调制W 调节输出电压。 [0043] The switch control circuit only to a control signal of the control signal I and the switch S3 Si, W 3 modulated output voltage. 其中,控制信号化3和控制信号化袖位相差180%占空比相同。 Wherein the control signal of the sleeve 3 and the control signal of the same bit by 180% duty cycle.

[0044] 所述主功率电路存在四种运行状态。 [0044] There are four operating state of the main power circuit. 状态1表征开关管Si和开关管S4导通,开关管S2和开关管S3关断,使存储电容Cl充电,同时使存储电容C2放电。 Characterization of a state Si and the switch S4 is turned on the switch, the switch S2 and the switch S3 is turned off, charging of the storage capacitor Cl, while the storage capacitor C2 is discharged. 状态2表征开关管Si、开关管S沸开关管S3关断,开关管S4维持导通,使存储电容Cl停止充电,存储电容C2继续放电。 Characterization of the switch state 2 Si, switch S boiling switch S3 is turned off, the switch S4 is turned on is maintained, so that the storage capacitor Cl stops charging the storage capacitor C2 continues to discharge. 状态3 表征开关管S2和开关管S3导通,开关管Sl和开关管S4关断,使存储电容C2充电,同时使存储电容Cl放电。 3 Characterization state switch S2 and the switch S3 is turned on, the switch Sl and the switch S4 is turned off, so that the storage capacitor C2 is charged while the storage capacitor Cl is discharged. 状态4表征开关管Si、开关管S3和开关管S4关断,开关管S2维持导通,使存储电容C2 停止充电,存储电容Cl继续放电。 Characterization state switch 4 Si, switches S3 and S4 is turned off, the switch S2 is turned on is maintained, so that the storage capacitor C2 stops charging the storage capacitor Cl continues to discharge.

[0045] 本发明设及一种开关电容变换器的控制电路,包括减法器101、减法器102、减法器103、可复位积分器104、可复位积分器105、比较器106、比较器107、RS触发器108和RS触发器109。 [0045] The present invention is provided and a control circuit for a switched capacitor converter, comprises a subtractor 101, subtractor 102, subtractor 103, integrator 104 may be reset, resettable integrator 105, comparator 106, comparator 107, RS flip-flop 108 and RS flip-flop 109.

[0046] 具体的,所述减法器101的同向输入端接收反馈的输入信号Vin,反向输入端接收反馈的存储电容Cl电压信号Vcl(t),其输出信号是第一差值信号(Vin-VclW),并作为可复位积分器104的输入信号。 [0046] Specifically, the subtractor 101 receive the same input signal Vin is fed back to the input terminal, an inverting input signal voltage of the storage capacitor Cl Vcl (t) receives feedback, the output signal of the first difference signal ( Vin-VclW), and the input signal as a resettable integrator 104.

[0047] 具体的,所述减法器102的同向输入端接收反馈的输入信号Vin,反向输入端接收反馈的存储电容C2电压信号Vc2(t),其输出信号是第二差值信号(Vin-Vc2(t)),并作为可复位积分器105的输入信号。 [0047] Specifically, the subtractor 102 receive the same input signal Vin is fed back to the input terminal, the storage capacitor C2 inverting input terminal voltage Vc2 receiving feedback signal (T), which is an output signal of the second difference signal ( Vin-Vc2 (t)), and as the input signal of the resettable integrator 105.

[0048] 具体的,所述减法器103的同向输入端接收输出电压参考信号Vref,反向输入端接收反馈的输出电压信号V。 [0048] Specifically, the subtractor 103 with the input terminal receives an output voltage reference signal Vref, an inverting input terminal receiving an output voltage feedback signal V. ,其输出信号是第S差值信号Ve = K(Vref-Vn), K是常数,第S差值信号Ve作为比较器106和比较器107的反向输入端的输入信号。 , Which is the output signal of the difference signal S Ve = K (Vref-Vn), K is a constant, S as a difference signal Ve inverting input of comparator 106 and the comparator 107 is an input signal.

[0049] 具体的,所述可复位积分器104包括积分网络。 [0049] Specifically, the resettable integrator 104 includes an integrating network. 所述积分网络为一阶低通RC电路, 由电阻化和电容C3组成。 The integrated network is a first order low-pass RC circuit consisting of a resistor and capacitor C3. 所述电阻化的一端作为输入端接收第一差值信号(Vin-VcKt)),电阻Ri的另一端与所述电容C3相连,共同作为所述可复位积分器104输出端,电容C3另一端与地线相连; The receiving end of the resistor of the first difference signal as an input terminal (Vin-VcKt)), the other end of the resistor Ri and the capacitor C3 is connected to a common output terminal of the resettable integrator 104, the other end of the capacitor C3 connected with the ground;

[0050] 复位开关Wi。 [0050] The reset switch Wi. 所述复位开关Wi并联在所述电容C3两端。 Wi said reset switch in parallel with both ends of the capacitor C3. 所述复位开关Wi为N沟道MOSFET,源极接地,漏极接所述电容C3非接地端,栅极接收所述复位信号化1; Wi is the N-channel reset switch the MOSFET, the source is grounded, a drain connected to the non-grounded terminal of the capacitor C3, the gate receiving a reset signal of 1;

[0051] 所述可复位积分器104接收第一差值信号(Vin-VelW)并对其进行积分,生成并输出第一积分信号Vintl。 [0051] The resettable integrator 104 receives a first difference signal (Vin-VelW) and subjected to integration, and generates and outputs a first integrated signal Vintl.

[0052] 具体的,所述可复位积分器105包括积分网络。 [0052] Specifically, the resettable integrator 105 includes an integrating network. 所述积分网络为一阶低通RC电路, 由电阻化和电容C4组成。 The integrated network is a first order low-pass RC circuit consisting of a resistor and capacitor C4. 所述电阻R2的一端作为输入端接收第二差值信号(Vin-Vc2(t)),电阻R2的另一端与所述电容C4相连,共同作为所述可复位积分器105输出端,电容C4另一端与地线相连; One end of the resistor R2 receiving a second difference signal (Vin-Vc2 (t)), the other end of the resistor R2 and the capacitor C4 is connected together as a resettable integrator output terminal 105 as an input, capacitor C4 the other end is connected to the ground;

[0053] 复位开关W2。 [0053] The reset switch W2. 所述复位开关W2并联在所述电容C4两端。 The reset switch W2 in parallel with both ends of the capacitor C4. 所述复位开关W2为N沟道MOSFET,源极接地,漏极接所述电容C4非接地端,栅极接收所述复位信号帕2; The reset switch W2 of the MOSFET N-channel, source grounded, and a drain connected to the non-grounded terminal of the capacitor C4, a gate receiving said reset signal 2 Pa;

[0054] 所述可复位积分器105接收第二差值信号(Vin-Ve2(t))并对其进行积分,生成并输出第二积分信号Vint2。 [0054] The resettable integrator 105 receives the second difference signal (Vin-Ve2 (t)) and integrated in, generates and outputs a second integrated signal Vint2.

[0055] 具体的,所述比较器106的同向输入端接收第一积分信号Vintl,反向输入端接收第=差值信号Ve。 [0055] Specifically, with the comparator 106 receives a first integrated signal Vintl input terminal, an inverting input receiving a first difference signal = Ve. 所述比较器106生成并输出数字电平形式的比较结果信号Uccml。 The comparator 106 generates and outputs a digital level comparison result signal in the form of Uccml.

[0056] 具体的,所述比较器107的同向输入端接收第二积分信号Vint2,反向输入端接收第=差值信号Ve。 [0056] Specifically, the second integrator compares the received signal 107 in the same Vint2 input terminal, an inverting input receiving a first difference signal = Ve. 所述比较器107生成并输出数字电平形式的比较结果信号UcDm2。 The comparator 107 generates and outputs a digital level comparison result signal in the form of UcDm2.

[0057]具体的,所述RS触发器108包括时钟电路。 [0057] Specifically, the RS flip-flop circuit 108 comprises a clock. 所述时钟电路由外部时钟构成,提供周期时钟信号(CLKl); The clock circuit is constituted by an external clock, providing periodic clock signal (CLKl);

[005引RS触发器。 [Cited RS flip-flop 005. 所述RS触发器108的R输入端接收所述比较结果信号化。 The RS R input of flip flop 108 receives the signal of the comparison result. ml, S输入端接收外部周期时钟信号化K1。 ml, S input for receiving an external clock signal of period K1. 所述RS触发器108的Q输出端生成控制信号化1并送入外部驱动电路,控制开关电容变换器开关管Si的导通和关断,巧输出端生成所述复位信号化1,控制复位开关Wi的导通和关断。 The Q output of the RS flip-flop 108 generates a control signal of 1 and sent to an external driving circuit, a control switch Si switched capacitor converter ON and OFF, the output terminal of coincidence of said reset signal to generate a control reset Wi switch oN and oFF.

[0059] 具体的,所述RS触发器109包括时钟电路。 [0059] Specifically, the RS flip-flop circuit 109 comprises a clock. 所述时钟电路由外部时钟构成,提供周期时钟信号(CLK2); The clock circuit is constituted by an external clock, providing periodic clock signal (CLK2);

[0060] RS触发器。 [0060] RS flip-flop. 所述RS触发器109的R输入端接收所述比较结果信号化。 The RS R input of flip flop 109 receives the signal of the comparison result. m2,S输入端接收外部周期时钟信号化K2。 m2, S input for receiving an external clock signal of the period K2. 所述RS触发器109的Q输出端生成控制信号化3并送入外部驱动电路,控制开关电容变换器开关管S3的导通和关断,Q输出端生成所述复位信号化2,控制复位开关W2的导通和关断。 The Q output of RS flip-flop 109 generates a control signal for 3 and sent to an external driving circuit, switched capacitor converter controls the switch S3 is turned on and off, to generate the Q output of the reset signal 2, the reset control W2, and the switch is turned off.

[0061 ]所述控制电路具体工作过程为: [0061] The specific control operation of the circuit is:

[0062] 在前半个周期开始时,一个恒定频率的外部时钟信号CLK 1将RS触发器108置高(Q = l,Q = 〇),控制信号化1为高电平,使开关电容变换器的开关管Si导通,存储电容Cl开始充电,存储电容Cl的电压Vci(t)上升。 [0062] at the beginning of the former half cycle, the external clock signal of a constant frequency of the CLK 1 RS flip-flop 108 will be set high (Q = l, Q = square), a control signal of a high level, the switch capacitor converter the switch Si is turned on, the storage capacitor Cl begins to charge the storage capacitor Cl voltage Vci (t) rises. 复位信号Uwi为低电平,使可复位积分器104的复位开关Wi 关断,使能可复位积分器104。 Uwi reset signal is low, resettable integrator 104 to reset switches off Wi enable resettable integrator 104. 可复位积分器104对第一差值信号(Vin-VsKt))进行积分,得到第一积分信号Vintl。 Resettable integrator 104 may be a first difference signal (Vin-VsKt)) is integrated to obtain a first integrated signal Vintl.

[0063] 比较器106的反向输入端接收第S差值信号Ve,同向输入端接收第一积分信号Vintl 并对二者进行实时比较,二者的相对大小将决定RS触发器108的输出状态。 Inverting input terminal [0063] The comparator 106 receives the second difference signal Ve S, integral with the first received signal Vintl and compared in real time to both the input terminal, determines the relative size of the two outputs of the RS flip-flop 108 status.

[0064] 当第一积分信号Vintl小于第S差值信号Ve时,比较器106输出的比较结果信号化。 [0064] When the first integrated signal S Vintl smaller than the difference signal Ve, of the comparison result signal output from the comparator 106. ml 为低电平,RS触发器108的输出维持现有状态(Q=I,巧= 0)。 ml is low, the output of the RS flip-flop 108 to maintain the current state (Q = I, Qiao = 0). 因为当前控制信号化1为高电平,则控制信号化1保持高电平,开关管Si继续导通;因为当前复位信号Uwi为低电平,可复位积分器104的复位开关Wi继续保持关断,可复位积分器104不复位。 Because the current control signal of a high level, the holding control signal of a high level, the switch Si is still turned on; because this reset signal is turned Uwi Wi remain reset low, the integrator 104 may be reset switch off, resettable integrator 104 is not reset.

[0065] 当第一积分信号Vintl等于或大于第=差值信号Ve时,比较器106输出的比较结果信号化。 [0065] When the first integral signal is equal to or greater than the Vintl = difference signal Ve, of the comparison result signal output from the comparator 106. ml为高电平,RS触发器108复位(Q = O, Q二1)。 ml is high, RS flip-flop 108 is reset (Q = O, Q 1 two). 控制信号化1变成低电平,开关管Si关断, 存储电容Cl停止充电;复位信号Uwi为高电平,可复位积分器104的复位开关Wi导通,可复位积分器104置零并准备接收下一个周期的第一差值信号(Vin-Vsiw)。 1 becomes the low level of the control signal, the switch Si is off, to stop charging the storage capacitor Cl; Wi reset signal Uwi switch is turned on, resettable integrator 104 is reset to zero to high, resettable integrator 104 and ready to receive the first difference signal (Vin-Vsiw) of the next cycle. 当下一个周期的时钟信号CLKl到来时,可复位积分器104重新开始积分。 When the next cycle of a clock signal CLKl arrival, resettable integrator 104 restarts the integration.

[0066] 在后半个周期开始时,一个恒定频率的外部时钟信号CLK 2将RS触发器109置高(Q =1,巧= 0),控制信号化3为高电平,使开关电容变换器的开关管S3导通,存储电容C2开始充电,存储电容C2的电压Vc2(t)上升。 [0066] At the beginning of the latter half cycle, a constant frequency of the external clock signal CLK 2 of the RS flip-flop 109 will be set high (Q = 1, Qiao = 0), the control signal 3 is a high level of the switched capacitor conversion the switch S3 is turned on, the storage capacitor C2 starts charging, the voltage Vc2 (t) stored in the capacitor C2 rises. 复位信号机2为低电平,使可复位积分器105的复位开关化关断,使能可复位积分器105。 2 low level reset signal, the reset resettable integrator 105 of the switch is turned off, enabling resettable integrator 105. 可复位积分器105对第二差值信号(Vin-VsSW)进行积分,得到第二积分信号Vint2。 Resettable integrator 105 may be a second difference signal (Vin-VsSW) is integrated to obtain a second integrated signal Vint2.

[0067] 比较器107的反向输入端接收第S差值信号Ve,同向输入端接收第二积分信号Vint2 并对二者进行实时比较,二者的相对大小将决定RS触发器109的输出状态。 Inverting input terminal [0067] The comparator 107 receives the second difference signal Ve S, both receiving the same Vint2 second integrated signal and compared in real time to the input terminal, determines the relative size of the two outputs of the RS flip-flop 109 status.

[006引当第二积分信号Vint2小于第S差值信号Ve时,比较器107输出的比较结果信号化。 [006 cited Vint2 when the second integrated signal S is less than the first difference signal Ve, of the comparison result signal output from the comparator 107. m2 为低电平,RS触发器109的输出维持现有状态(Q = I,巧二O )。 m2 is low, the output of the RS flip-flop 109 to maintain the current state (Q = I, Qiao two O). 因为当前控制信号化3为高电平,则控制信号化3保持高电平,开关管S3继续导通;因为当前复位信号UW2为低电平,可复位积分器105的复位开关W2继续保持关断,可复位积分器105不复位。 3 because the current control signal of a high level, the control signal maintains a high level of 3, the switch S3 is turned on to continue; UW2 reset signal since the current is low, resettable integrator reset switch W2 105 is maintained OFF off, resettable integrator 105 is not reset.

[0069] 当第二积分信号Vint2等于或大于第S差值信号Ve时,比较器107输出的比较结果信号化。 [0069] When the second integrated signal is equal to or larger than S Vint2 difference signal Ve, of the comparison result signal output from the comparator 107. m2为高电平,RS触发器109复位(Q = O, Q = 1)。 m2 is high, RS flip-flop 109 is reset (Q = O, Q = 1). 控制信号帖变成低电平,开关管S3关断, 存储电容C2停止充电;复位信号机2为高电平,可复位积分器105的复位开关化导通,可复位积分器105置零并准备接收下一个周期的第二差值信号(Vin-VsSW)。 Posts control signal becomes low level, the switch S3 is turned off, to stop charging the storage capacitor C2; 2 high level reset signal, the reset resettable integrator 105 of the switch is turned on, the integrator 105 may be reset to zero and ready to receive a second difference signal (Vin-VsSW) of the next cycle. 当下一个周期的时钟信号CLK2到来时,可复位积分器105重新开始积分。 When the next cycle of a clock signal CLK2 arrives, the integrator 105 may be reset to restart integration.

[0070] 在前半个周期内,第一积分信号Vintl从零逐渐增大,控制信号化1持续保持高电平。 [0070] the first half cycle, the first integral signal Vintl gradually increased from zero, the control signal of a high level continuously maintained. 当第一积分信号Vintl达到第S差值信号Ve时,比较器106输出的比较结果信号Ucoml为高电平,使RS触发器108复位(Q = 0,Q =1),控制信号化1变为低电平,开关电容变换器开关管Si 关断,可复位积分器104的复位开关Wi导通,可复位积分器104置零。 When the first integral signal Vintl S reaches the second difference signal Ve, Ucoml comparison result signal output from the comparator 106 is high, the RS flip-flop 108 is reset (Q = 0, Q = 1), a variant of the control signal is low, Si switched capacitor converter switch off, resettable integrator 104 is reset switch is turned Wi, resettable integrator 104 to zero. 类似地,在后半个周期内,第二积分信号Vint2从零逐渐增大,控制信号化3持续保持高电平。 Similarly, in the latter half cycle, the second integral signal Vint2 is gradually increased from zero, the control signal remains high continuously for 3. 当第二积分信号Vint2达到第S差值信号Ve时,比较器107输出的比较结果信号Uc«2为高电平,使RS触发器109复位(Q =0,巧=1 ),控制信号化3变为低电平,开关电容变换器开关管S3关断,可复位积分器105的复位开关W2导通,可复位积分器105置零。 Vint2 when the second integrated signal reaches a first difference signal Ve S, the comparison result signal output by the comparator 107 Uc «2 is high, the RS flip-flop 109 is reset (Q = 0, Qiao = 1), of the control signal 3 goes low, the switch S3 is switched capacitor converter is turned off, resettable integrator reset switch 105 is turned W2, resettable integrator 105 to zero.

[0071] 单周期控制方法对输入电压扰动的抑制体现在:当输出负载保持不变,输入电压Vin出现阶跃。 [0071] The single-cycle control method for suppressing disturbance is reflected in the input voltage: When the output load remains unchanged, the input voltage Vin appears step. 由于输入电压Vin与第一积分信号Vintl和第二积分信号Vint2成正比,当输入电压Vin升高时,积分上升速度将会瞬时加快,而第=误差信号Ve保持不变。 Since the input signal voltage Vin and the first integrator and the second integrator signal proportional Vintl Vint2, when the input voltage Vin increases, the integral transient increase in speed will accelerate, and the first error signal Ve = unchanged. 因此,第一积分信号Vinti和第二积分信号Vint2上升到第S差值信号Ve的时间将会缩短,与上一个周期相比,开关管Sl的控制信号化谢开关管S3的控制信号化3的占空比将会减小。 Thus, the first integrator and the second integrator signal Vinti Vint2 signal up to the first difference signal Ve S time will be shorter, compared with the previous period, the control signal of the switch control signal Sl Xie the switch S3 3 the duty cycle will be reduced. 相反地,当输入电压Vin 减小时,开关管Sl的控制信号化1和开关管S3的控制信号化3的占空比将会增大。 Conversely, when the input voltage Vin decreases, the control signal of the switch control signal Sl 1 of the duty cycle of the switch S3 and 3 will increase.

[0072] 单周期控制方法对负载扰动的抑制体现在:当输入电压Vin保持不变,当负载增大时,即输出电流增大时,输出电压Vo有减小的趋势,第=差值信号Ve将会瞬时增大。 [0072] The single-cycle control method for suppressing disturbance is reflected in load: remains constant when the input voltage Vin, when the load increases, i.e. when the output current increases, the output voltage Vo has a decreasing trend, the difference signal = Ve will instantaneously increase. 又由于第一积分信号Vintl和第二积分信号Vint2的上升速度保持不变,其上升到第S差值信号Ve的时间将会增加。 Also, because the rise speed of the first integrator and the second integrator signal Vintl Vint2 signal remains unchanged, it rises to Ve first time difference signal S will increase. 与上一个周期相比,开关管Sl的控制信号化谢开关管S3的控制信号化3的占空比将会增大。 Compared with the previous period, the control signal of the switch control signals Sl Xie duty cycle of the switch S3 3 will increase. 相反地,当输出负载减小时,即输出电流减小时,开关管Sl的控制信号Usi和开关管S3的控制信号化3的占空比将会减小。 Conversely, when the output load is reduced, i.e., the output current decreases, the control signal control signal Usi and the switch S3 duty cycle of switch Sl 3 will be reduced.

[0073] W上所有对外界扰动的抑制调节将会在一个周期内完成。 [0073] All of the external disturbance suppression adjustment W will be completed within one cycle. 与现有的开关电容变换器控制电路及控制方法对外界扰动的多周期调节时间相比,很大程度上提高了动态响应速度。 Multi-cycle control with the conventional switched capacitor circuit and the inverter control method of settling time compared to external disturbance, greatly improves the dynamic response speed.

[0074] -种上述开关电容变换器控制电路的控制方法,其特点是包括W下过程: [0074] - a control method for switched-capacitor circuit of the above inverter control, which is characterized by the process comprising W:

[0075] (1)设定需要控制的开关管。 [0075] The switch (1) setting needs to be controlled.

[0076] 设定开关管S2和开关管S4的占空比恒为0.5,相位相差180°的两组方波信号,无需调制。 [0076] The setting switch S2 and S4 constant duty ratio is 0.5, two square wave signals of phase of 180 °, without modulation. 控制电路仅调节开关管Sl和开关管S3的控制信号,且存储电容Cl和存储电容C2的充放电状态互补。 The control circuit adjusts only the switch control signal Sl and the switch S3, and the state of charging and discharging the storage capacitance of the storage capacitor Cl and C2 are complementary.

[0077] (2)推导存储电容Cx充电电流和放电电流的数学方程。 [0077] (2) derived mathematical equations stored in the capacitor Cx charging current and discharging current.

[0078] 根据电容电压安秒平衡关系,得到一周期内存储电容Cx电压变化量方程: [0078] The balance between safety second capacitor voltage, the capacitor Cx to give one cycle stored voltage change amount of the equation:

[0079] AVcx = -AVdx (I) [0079] AVcx = -AVdx (I)

[0080] 其中,Cx代表存储电容Cl和C2, A Vcx表示电容Cx充电时电压变化量,A Vdx表示电容Cx放电时电压变化量。 [0080] wherein, on behalf of the storage capacitance Cx Cl and C2, A Vcx represents the capacitor Cx charging voltage variation, A Vdx represents voltage variation when discharging the capacitor Cx.

[0081] 处于充电状态时,由基尔霍夫定律和电容电流方程,得到存储电容Cx的充电电流icx 为式(2): [0081] When the state of charge, the capacitive current and Kirchhoff's law equation, the charging current of the storage capacitor Cx icx formula (2):

[0082] [0082]

Figure CN105743327AD00111

(2) (2)

[0083]其中,Vin是输入电压,Vcx(t)是充电时存储电容Cx的电压,Rcx是充电状态时回路的总电阻,X取1和2。 [0083] where, Vin is the input voltage, Vcx (t) is the voltage at the charge storage capacitor Cx, Rcx is the total resistance of the circuit when the state of charge, X 2 and takes 1.

[0084] 处于放电状态时,由基尔霍夫定律和电容电流方程,得到存储电容Cx的放电电流idx为式(3): [0084] When in a discharged state, the capacitive current and Kirchhoff's law equation, the discharge current is stored in the capacitor Cx idx of formula (3):

[0085] [0085]

Figure CN105743327AD00112

巧) Qiao)

[0086] 其中,Vo是输出电压,vdx(t應放电时存储电容Cx的电压,Rdx是放电状态时回路的总电阻,X取1和2。 [0086] wherein, the output voltage Vo of the voltage time (t discharge should be stored in the capacitor Cx vdx, Rdx is the total resistance of the circuit when the discharge state, X 1 and 2 taken.

[0087] (3)利用电容电压和电流约束关系,得到一周期内电容电压变化量的数学方程。 [0087] (3) use of the capacitor voltage and current constraints, the mathematical equation of the capacitor voltage variation in one cycle.

[0088] 处干布由献杰时,存储由容Cx电压变化量为式(4): [0088] At the time of offering outstanding dry cloth, storage capacity Cx by the voltage variation of the formula (4):

[0089] [0089]

Figure CN105743327AD00113

巧) Qiao)

[0090] 其中,Ts是一个周期时间,DxTs是存储电容Cx的充电时间,X取1和2,化是开关管Si的占空比,是开关管S3的占空比。 [0090] where, Ts of a cycle time is, DxTs is stored in the capacitor Cx charging time, X taken 1 and 2, is the duty cycle of the switch Si is the duty cycle of the switch S3.

[0091] 檐击(2)带入击(4).得到布电状态时存储电容Cx电压变化量为式巧): [0091] eaves attack (2) into the strike (4) to give state-storage capacitance Cx cloth voltage change amount of clever formula):

[0092] [0092]

Figure CN105743327AD00114

巧) Qiao)

[0093] 处于放电状态时,存储电容Cx电压变化量为式(6) [0093] When the discharge state, the voltage stored in the capacitor Cx of variation of formula (6)

[0094] [0094]

Figure CN105743327AD00115

(6) (6)

[0095] 其中,0.5Ts是存储电容Cx的放电时间。 [0095] wherein, 0.5Ts storage capacitance Cx is the discharge time.

[0096] 檐古(3)带人古(fi).得哥I放电状态时存储电容Cx电压变化量为式(7): . [0096] Old eaves (3) with old people (fi) when I have brother discharged state voltage change amount of the capacitance Cx of formula (7):

[0097] [0097]

Figure CN105743327AD00116

(7) (7)

[009引其中,V似的是0.5Ts时间内存储电容Cx电压的平均值。 [009 cited wherein, V is an average value within a similar time storage capacitor Cx 0.5Ts voltage. [0099] (4)推导核屯、控制方程。 [0099] (4) derived core Tun, the control equation. [0100] 檐击化)巧击(7),带入击(1 ),得到单闻朋安棘平衡方程为式(8): [0100] blow of eaves) Qiao hit (7), into the strike (1), to give a single ratchet smell Points An equilibrium equation of Formula (8):

Figure CN105743327AD00117

[0101] 烦 [0101] bother

[0102] (8)得到式(9): [0102] (8) formula (9):

[01。 [01. 引㈱ Cited ㈱

[0104]令输出电压参考值 [0104] so that the output voltage reference value

Figure CN105743327AD00118

,式(11)改写为式(12): , Of formula (11) is rewritten as formula (12):

[0105] [0105]

Figure CN105743327AD00121

(10) (10)

[0106] 式(10)是改进的单周期控制方法的核屯、控制方程。 [0106] Formula (10) is a modified core Tun one cycle control method, the control equation.

[0107] (5)根据核屯、控制方程建立对开关管Si和开关管S3的控制模型。 [0107] (5) The nuclear Tun, the governing equation for the model control switch Si and the switch S3.

[0108] 此发明方法逻辑控制电路模型控制流程如下: [0108] The method of this invention, a control logic circuit model control flow is as follows:

[0109] 可复位积分器104在开关管Si导通时间内,连续的对第一差值信号(Vin-VcKt))进行积分,得到第一积分信号Vintl。 [0109] resettable integrator 104 in the conduction time of the switch Si, continuous first difference signal (Vin-VcKt)) is integrated to obtain a first integrated signal Vintl. 当第一积分信号Vintl小于第S差值信号Ve时,比较器106输出的比较结果信号化。 When the first integrated signal S Vintl smaller than the difference signal Ve, of the comparison result signal output from the comparator 106. ml为低电平,RS触发器108的输出维持现有状态(Q=1,Q = 0)。 ml maintain the current low output state, RS flip-flop 108 (Q = 1, Q = 0). 因为当前控制信号化1为高电平,则控制信号化1保持高电平,开关管Si继续导通,存储电容Cl保持充电状态;因为当前复位信号Uwi为低电平,可复位积分器104的复位开关Wi继续保持关断,可复位积分器104不复位。 Because the current control signal of a high level, the holding control signal of a high level, the switch Si is still turned on, the storage capacitor remains charged state Cl; Uwi reset signal since the current is low, resettable integrator 104 Wi reset switch remains off continued, resettable integrator 104 is not reset.

[0110] 当第一积分信号Vintl等于或大于第=差值信号Ve时,比较器106输出的比较结果信号化。 [0110] When the first integral signal is equal to or greater than the Vintl = difference signal Ve, of the comparison result signal output from the comparator 106. ml为高电平,RS触发器108复位(Q = 0,g = 1)。 ml is high, RS flip-flop 108 is reset (Q = 0, g = 1). 控制信号化1变成低电平,开关管Si关断, 存储电容Cl停止充电;复位信号Uwi为高电平,可复位积分器104的复位开关Wi导通,可复位积分器104置零并准备接收下一个周期的第一差值信号(Vin-Vsiw)。 1 becomes the low level of the control signal, the switch Si is off, to stop charging the storage capacitor Cl; Wi reset signal Uwi switch is turned on, resettable integrator 104 is reset to zero to high, resettable integrator 104 and ready to receive the first difference signal (Vin-Vsiw) of the next cycle. 当下一个周期的时钟信号CLKl到来时,可复位积分器104重新开始积分。 When the next cycle of a clock signal CLKl arrival, resettable integrator 104 restarts the integration.

[0111] 可复位积分器105在开关管S3导通时间内,连续的对第二差值信号(Vin-Vc2(t))进行积分,得到第二积分信号Vint2。 [0111] resettable integrator 105 within the switch S3 is on-time, continuous second difference signal (Vin-Vc2 (t)) is integrated to obtain a second integrated signal Vint2. 当第二积分信号Vint2小于第S差值信号Ve时,比较器107输出的比较结果信号化》2为低电平,RS触发器109的输出维持现有状态(Q=l,巧=(D。因为当前控制信号化3为高电平,则控制信号化3保持高电平,开关管S3继续导通,存储电容C2保持充电状态;因为当前复位信号机2为低电平,可复位积分器105的复位开关化继续保持关断,可复位积分器105不复位。 When the second integrated signal S Vint2 is smaller than the first difference signal Ve, of the comparison result signal output from the comparator 107 '2 is low, the output of the RS flip-flop 109 to maintain the current state (Q = l, Qiao = (D because of the current control signal 3 is high, the control signal maintains a high level of 3, the switch S3 is turned on continues, maintaining the state of charge storage capacitor C2; 2 because the current reset signal is low, resettable integrator of the reset switch 105 remains off continued, resettable integrator 105 is not reset.

[0112] 当第二积分信号Vint2等于或大于第S差值信号Ve时,比较器107输出的比较结果信号化。 [0112] When the second integrated signal is equal to or larger than S Vint2 difference signal Ve, of the comparison result signal output from the comparator 107. m2为高电平,RS触发器109复位(Q = O,巧=1)。 m2 is high, RS flip-flop 109 is reset (Q = O, Qiao = 1). 控制信号帖变成低电平,开关管S3关断, 存储电容C2停止充电;复位信号机2为高电平,可复位积分器105的复位开关化导通,可复位积分器105置零并准备接收下一个周期的第二差值信号(Vin-VsSW)。 Posts control signal becomes low level, the switch S3 is turned off, to stop charging the storage capacitor C2; 2 high level reset signal, the reset resettable integrator 105 of the switch is turned on, the integrator 105 may be reset to zero and ready to receive a second difference signal (Vin-VsSW) of the next cycle. 当下一个周期的时钟信号CLK2到来时,可复位积分器105重新开始积分。 When the next cycle of a clock signal CLK2 arrives, the integrator 105 may be reset to restart integration.

Claims (2)

1. 一种开关电容变换器控制电路,其特征在于:包括减法器101、减法器102、减法器103、可复位积分器104、可复位积分器105、比较器106、比较器107、RS触发器108和RS触发器109; 所述减法器101的同向输入端接收反馈的输入信号vin,反向输入端接收反馈的存储电容Cl电压信号Vciw,其输出信号是第一差值信号(Vin-Vciw),并作为可复位积分器104的输入信号; 所述减法器102的同向输入端接收反馈的输入信号Vin,反向输入端接收反馈的存储电容C2电压信号Vc;2W,其输出信号是第二差值信号(Vin-Vc;2W),并作为可复位积分器105的输入信号; 所述减法器103的同向输入端接收输出电压参考信号Vrrf,反向输入端接收反馈的输出电压信号V。 A switched capacitor converter control circuit comprising: a subtractor 101, subtractor 102, subtractor 103, integrator 104 may be reset, resettable integrator 105, a comparator 106, a comparator 107, RS trigger RS flip-flop 108 and 109; the subtractor 101 receive the same feedback signal VIN to the input terminal, an inverting input signal voltage of the storage capacitor Cl Vciw terminal receiving feedback, an output signal of the first difference signal (Vin -Vciw), and as the input signal of the resettable integrator 104; the same subtractor 102 receiving feedback input signal to the input terminal Vin, the storage capacitor C2 inverting input terminal receives a voltage feedback signal Vc; 2W, outputs the second signal is a difference signal (Vin-Vc; 2W), and as a reset input signal of the integrator 105; subtractor receives the output voltage of the reference signal 103 with Vrrf input terminal, an inverting input receiving feedback output voltage signal V. ,其输出信号是第三差值信号VeilUVref-V。 , Whose output signal is a third difference signal VeilUVref-V. )』是常数,第三差值信号Ve作为比较器106的反向输入端的输入信号; 所述可复位积分器104由电阻Ri和电容C3组成;所述电阻心的一端作为输入端接收第一差值信号(Vin-VclW),电阻h的另一端与所述电容C3相连,共同作为所述可复位积分器104 输出端,电容C3另一端与地线相连; 复位开关Wl并联在所述电容C3两端; 所述可复位积分器104对第一差值信号(Vin-VelW)进行积分,生成并输出第一积分信号Vintl; 所述可复位积分器105由电阻R2和电容C4组成;所述电阻办的一端作为输入端接收第二差值信号(Vin-Vc;2(t)),电阻R2的另一端与所述电容C4相连,共同作为所述可复位积分器105 输出端,电容C4另一端与地线相连; 复位开关W2并联在所述电容C4两端; 所述可复位积分器105对第二差值信号(Vin-Vc;2W)进行积分,生成并输出第二积分信号Vint2 ; 所述比较器106的同向输入端接收第 ) "Is a constant, the third difference signal as an input signal Ve to the inverting input of comparator 106; the integrator 104 may be reset by a capacitor C3 and a resistor Ri; end of the resistor core receives as an input a first difference signal (Vin-VclW), the other end of the resistor and the capacitor C3 h connected together as said reset output of the integrator 104, connected to the other end of the capacitor C3 and the ground; Wl reset switch connected in parallel with the capacitor a C3 ends; the resettable integrator 104 may be a first difference signal (Vin-VelW) integrating the first integral signal to generate and output Vintl; the integrator 105 may be reset by the resistor R2 and the capacitor C4 form; the said second end of the resistor do difference signal received as an input (Vin-Vc; 2 (t)), the other end of the resistor R2 and the capacitor C4 is connected to the output terminal 105 together as resettable integrator, the capacitance C4 and the other end connected with the ground; W2 reset switch in parallel with the capacitor C4 at both ends; the resettable integrator 105 may be a second difference signal (Vin-Vc; 2W) is integrated, generates and outputs a second integrated signal Vint2; with the comparator 106 receives a first input terminal 一积分信号Vintl,反向输入端接收第三差值信号Ve;所述比较器106生成并输出数字电平形式的比较结果信号VCMl; 所述比较器107的同向输入端接收第二积分信号Vint2,反向输入端接收第三差值信号Ve;所述比较器107生成并输出数字电平形式的比较结果信号Ucm2; 所述RS触发器108的R输入端接收所述比较结果信号lUml,S输入端接收外部周期时钟信号CLK1;所述RS触发器108的Q输出端生成控制信号US1并送入外部驱动电路,控制开关电容变换器开关管3:的导通和关断,§输出端生成所述复位信号UW1,控制所述可复位积分器104 复位开关1的导通和关断; 所述RS触发器109的R输入端接收所述比较结果信号lUm2,S输入端接收外部周期时钟信号CLK2;所述RS触发器109的Q输出端生成控制信号US3并送入外部驱动电路,控制开关电容变换器开关管S3的导通和关断,泛输出端生成所述复位信号UW2,控 An integration signal Vintl, an inverting input terminal receiving a third difference signal Ve; of the comparator 106 generates and outputs a digital level comparison result signal VCML form; a second comparator receives the signal 107 is integrated with the input terminal Vint2, an inverting input terminal receiving a third difference signal Ve; the comparator 107 generates and outputs a digital level comparison result signal in the form of Ucm2; R input of the RS flip-flop 108 receives the comparison result signal lUml, S input for receiving an external clock signal cycle CLK1; Q output of the RS flip-flop 108 generates a control signal US1 and sent to an external driving circuit for controlling the switch converter switched-capacitor 3: oN and oFF, the output terminal § generating said reset signal UW1, resettable integrator controls the reset switch 104 is turned on and off 1; R & lt input of the RS flip-flop 109 receives the comparison result signal lUm2, S input for receiving an external clock cycles signal CLK2; Q output of the RS flip-flop 109 generates a control signal US3 and sent to an external driving circuit, switched capacitor converter controls the switch S3 is turned on and off, the output terminal of the pan UW2 generating said reset signal, control 所述可复位积分器105 复位开关%的导通和关断。 The resettable integrator 105% of the reset switch is turned on and off.
2. -种适用于权利要求1所述开关电容变换器控制电路的控制方法,其特征在于包括以下步骤: 步骤一、设定开关管s2和S4的控制信号为占空比恒为0.5,相位相差180°的两组方波信号;其中,开关管32的控制信号和开关管S3的控制信号同步;开关管S4的控制信号与开关管Si的控制信号同步; 步骤二、对存储电容&和存储电容C2的充放电过程分别建立改进的单周期控制模型,控制公式分别为式(1)和式(2): 2. - species suitable for the switching capacitor as claimed in claim inverter control circuit controlling method, comprising the steps of: step a, setting switch s2 and the control signal S4 is a constant duty ratio is 0.5, the phase two 180 ° apart square wave signal; wherein the control signals and the switch S3 synchronizing switch 32; the control signals to switch the switch S4 Si synchronization; step two, and the storage capacitor & charging and discharging the storage capacitor C2 is to establish an improved single-cycle control model, control formulas are formulas (1) and (2):
Figure CN105743327AC00031
(1) (2) 其中,L,K2和K都是常数,Vin是输入电压,Vo是输出电压,Vrrf是输出参考电压,vClW是充电状态下存储电容&的电压,vC2(t)是充电状态下存储电容(:2的电压,DA是存储电容&的充电时间,D2TS是存储电容C2的充电时间; 核心控制公式(1)和(2)所生成的控制信号分别实时调节控制开关管S4P开关管S3的导通和关断; 步骤三、可复位积分器104在RS触发器108置位(Q= 即在开关管51导通时间内,连续的对第一差值信号(Vin-Vcaw)进行积分,得到第一积分信号Vintl;并实时的与第三差值信号Ve进行比较;当第一积分信号^耐小于第三差值信号VJ寸,比较器106保持低电平, 开关管Si继续导通,RS触发器108维持置位;当第一积分信号^耐等于或者大于第三差值信号VJ寸,比较器106变为高电平,开关管51关断,RS触发器108复位(Q. = 1);可复位积分器104的复位开关I导通,可复位积分器104置 (1) (2) where, L, K2 and K are constants, Vin is the input voltage, Vo is the output voltage, Vrrf reference voltage is output, vClW storage capacitor is at a state of charge & voltage, vC2 (t) is the charge a state storage capacitor (: 2 voltage, DA is the charging time of the storage capacitor of &, D2TS charging time storage capacitor C2; core control formula (1) and (2) the generated control signals in real time regulating control switch S4P the switch S3 is turned on and off; step three, i.e. resettable integrator 104 during the on time of the switch tube 51, a continuous first difference signal (Vin-Vcaw the RS flip-flop 108 is set (Q = ) were integrated to obtain a first integrated signal Vintl; real time is compared with a third difference signal Ve; a first integrated signal when the third difference signal is less than the resistance ^ VJ inch, comparator 106 is held low, the switch Si continues to conduct, RS flip-flop 108 is set to maintain; ^ integral signal when the first resistance is greater than or equal to the third difference signal VJ inch, comparator 106 goes high, the switch 51 is turned off, RS flip-flop 108 reset (Q. = 1); resettable integrator 104 is reset switch I is turned on, resettable integrator 104 is set 零并准备接收下一个周期的第一差值信号(Vin_Vcl(t)); 可复位积分器105在RS触发器109置位即在开关管S3导通时间内,连续的对第二差值信号(Vm-Vc^w)进行积分,得到第二积分信号Vint2,并实时地与第三差值信号Ve进行比较;当第二积分信号1^小于第三差值信号VJ寸,比较器107保持低电平,开关管S3 继续导通,RS触发器109维持置位;当第二积分信号¥^2等于或者大于第三差值信号Ve时,比较器107变为高电平,开关管S3关断,RS触发器109复位(Q=I),夺=1);可复位积分器105的复位开关%导通,可复位积分器105置零并准备接收下一个周期的第二差值信号(Vin- Vc2(t) ) 〇 Zero and ready to receive a first difference signal period (Vin_Vcl (t)); resettable integrator 105 in the RS flip-flop 109 is set i.e. the time the switch S3 is turned on, the second difference signal for successive (Vm-Vc ^ w) is integrated to obtain a second integrated signal Vint2, and in real time with a third difference signal Ve; 1 ^ when the second integrated signal VJ inch less than the third difference signal, the comparator 107 remains low level, the switch S3 is turned on continues, RS flip-flop 109 is set to maintain; when the second integrated signal ¥ ^ 2 greater than or equal to the third difference signal Ve, the comparator 107 goes high, the switch S3 off, RS flip-flop 109 is reset (Q = I), wins = 1); resettable integrator reset switch 105 is turned%, resettable integrator 105 to zero and a second difference signal ready to receive the next cycle (Vin- Vc2 (t)) square
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