CN105632935B - A method of regulation and control semiconductor nanowires field-effect transistor threshold voltage - Google Patents
A method of regulation and control semiconductor nanowires field-effect transistor threshold voltage Download PDFInfo
- Publication number
- CN105632935B CN105632935B CN201511028926.2A CN201511028926A CN105632935B CN 105632935 B CN105632935 B CN 105632935B CN 201511028926 A CN201511028926 A CN 201511028926A CN 105632935 B CN105632935 B CN 105632935B
- Authority
- CN
- China
- Prior art keywords
- nano
- effect transistor
- field
- nwfet
- threshold voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000002070 nanowire Substances 0.000 title claims abstract description 144
- 239000004065 semiconductor Substances 0.000 title claims abstract description 59
- 230000005669 field effect Effects 0.000 title claims abstract description 54
- 238000000034 method Methods 0.000 title claims abstract description 42
- 230000033228 biological regulation Effects 0.000 title claims abstract description 11
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 39
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 39
- 239000000463 material Substances 0.000 claims abstract description 23
- 239000007769 metal material Substances 0.000 claims abstract description 11
- 230000008569 process Effects 0.000 claims abstract description 11
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 claims description 81
- 229910000673 Indium arsenide Inorganic materials 0.000 claims description 76
- 239000002105 nanoparticle Substances 0.000 claims description 71
- QPLDLSVMHZLSFG-UHFFFAOYSA-N CuO Inorganic materials [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 claims description 53
- 238000012986 modification Methods 0.000 claims description 26
- 230000004048 modification Effects 0.000 claims description 26
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 18
- 229910052710 silicon Inorganic materials 0.000 claims description 18
- 239000010703 silicon Substances 0.000 claims description 18
- XOLBLPGZBRYERU-UHFFFAOYSA-N SnO2 Inorganic materials O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 claims description 16
- 239000002184 metal Substances 0.000 claims description 13
- 229910052751 metal Inorganic materials 0.000 claims description 13
- 238000002207 thermal evaporation Methods 0.000 claims description 13
- 238000001259 photo etching Methods 0.000 claims description 9
- 238000000137 annealing Methods 0.000 claims description 8
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052681 coesite Inorganic materials 0.000 claims description 6
- 229910052906 cristobalite Inorganic materials 0.000 claims description 6
- 238000005566 electron beam evaporation Methods 0.000 claims description 6
- 239000002086 nanomaterial Substances 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 229910000108 silver(I,III) oxide Inorganic materials 0.000 claims description 6
- 229910052682 stishovite Inorganic materials 0.000 claims description 6
- 229910052905 tridymite Inorganic materials 0.000 claims description 6
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims description 5
- 229910052759 nickel Inorganic materials 0.000 claims description 5
- 230000001105 regulatory effect Effects 0.000 claims description 5
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 claims description 4
- 238000002508 contact lithography Methods 0.000 claims description 4
- 238000001035 drying Methods 0.000 claims description 4
- 229910005542 GaSb Inorganic materials 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 claims description 3
- 230000007246 mechanism Effects 0.000 claims description 3
- 239000013528 metallic particle Substances 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000007787 solid Substances 0.000 claims description 3
- 239000007790 solid phase Substances 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 229910052718 tin Inorganic materials 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- 238000001017 electron-beam sputter deposition Methods 0.000 claims description 2
- 238000007747 plating Methods 0.000 claims description 2
- 230000001276 controlling effect Effects 0.000 claims 3
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 239000000126 substance Substances 0.000 abstract description 2
- 238000009776 industrial production Methods 0.000 abstract 1
- 238000002474 experimental method Methods 0.000 description 19
- 238000012546 transfer Methods 0.000 description 18
- 239000010410 layer Substances 0.000 description 9
- 241000209094 Oryza Species 0.000 description 8
- 235000007164 Oryza sativa Nutrition 0.000 description 8
- 235000013339 cereals Nutrition 0.000 description 8
- 238000010586 diagram Methods 0.000 description 8
- 235000009566 rice Nutrition 0.000 description 8
- 239000003574 free electron Substances 0.000 description 6
- 238000000151 deposition Methods 0.000 description 5
- 230000008021 deposition Effects 0.000 description 5
- 238000002360 preparation method Methods 0.000 description 5
- -1 aromatic thiol salt Chemical class 0.000 description 4
- 230000005611 electricity Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000002082 metal nanoparticle Substances 0.000 description 2
- 238000001000 micrograph Methods 0.000 description 2
- 235000012149 noodles Nutrition 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 230000008439 repair process Effects 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 1
- 239000005864 Sulphur Substances 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 238000006555 catalytic reaction Methods 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000005034 decoration Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000008246 gaseous mixture Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 239000002052 molecular layer Substances 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 150000002927 oxygen compounds Chemical class 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000009738 saturating Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
- 238000003949 trap density measurement Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
Abstract
The invention belongs to transistor threshold voltage control technique fields, it is related to a kind of method of regulation and control semiconductor nanowires field-effect transistor threshold voltage, metal oxide semiconductor material or metal material are respectively deposited on the semiconductor nanowires field-effect transistor prepared or nano-wire array field-effect transistor, the surface of semiconductor nanowires field-effect transistor or nano-wire array field-effect transistor plate film modified, the thickness of plated film is 0.2 5nm, to regulate and control the threshold voltage of semiconductor nanowires field-effect transistor and nano-wire array field-effect transistor, its is simple for process, it is easy to operate, principle is reliable, production cost is low, in electronic switching device, display, the fields such as biology and chemical sensor have broad application prospects, it is easy to carry out large-scale industrial production.
Description
Technical field：
The invention belongs to transistor threshold voltage control technique fields, and it is brilliant to be related to a kind of regulation and control semiconductor nanowires field-effect
The method of body pipe (NWFET) threshold voltage, especially it is a kind of using metal-oxide semiconductor (MOS) nano particle regulation and control iii-v and
The technique of metal-oxide semiconductor (MOS) NWFET threshold voltages, can be widely used in high-performance sensors, detector, opto-electronic device
Equal fields.
Background technology：
With the development of nanotechnology, One, Dimensional Semiconductor Nano Materials have become the hot spot of people's research.Semiconductor nano
Line has many advantages compared with its bulk, such as：Nano wire since its size is small, not only can greatly save material at
This, improves the utilization ratio of material, and can effectively improve the packing density of device；Construct the radial direction and axis of nanoscale
To p-n, p-i-n hetero-junctions can improve nanowire photovoltaic devices transfer efficiency (J.Wallentin, N.Anttu,
D.Asoli, etal., InP nanowire array solar cells achieving 13.8%efficiency by
exceeding the ray optics limit,Science,339,1057(2013))；In addition, semi-conducting material is reduced
Its mechanics flexibility can increase substantially after to nanocrystalline size so that they can become the reason of the following flexible electronic industrial circle
Think one of material (N.Han, Z.X.Yang, F.Y.Wang, etal., High-Performance GaAs Nanowire Solar
Cells for Flexible and Transparent Photovoltaics,ACS Appl.Mater.Interfaces,7,
20454(2015)).Iii-v and metal-oxide semiconductor (MOS) nano wire are due to having suitable energy gap, higher electricity
The characteristics such as transport factor, larger carrier concentration, it is considered to be applied to next-generation electronic device, display, chemistry and life
One of the most promising channel material in the fields such as object detector.In various applications, semiconductor nanowires field-effect transistor
(NWFET) it is the base components for making next-generation Efficient devices, most of NWFET are shown as since its free electron density is higher
Depletion type.When grid voltage is zero, enhancement mode field effect transistor (FET) is closed, and depletion type field-effect is brilliant
But there is certain electric current in body pipe (FET), to close its channel, it is necessary to apply a grid voltage.Although enhanced and consumption
Type FET to the greatest extent is necessary component in electronic circuit, but enhanced FET is since power consumption is very low, the polarity of grid bias-voltage and leakage
The features such as pole tension is identical is compared and is favored.Therefore realize that the regulation and control of NWFET electric properties are semiconductor nanowires Successful utilizations
Deciding factor in fields such as high-performance electronic, photoelectron and detectors.
In order to control the operating mode of NWFET, several different techniques have now been developed to control the threshold value of NWFET
Voltage, for example, by the surface topography of control ZnO nano-wire to generate different surface electronic trap densities, certainly to regulation and control
By the density of carrier, may finally obtain enhanced and depletion type FET (W.K.Hong, J.I.Sohn, D.K.Hwang,
etal.,Tunable Electronic Transport Characteristics of Surface-Architecture-
Controlled ZnO Nanowire Field Effect Transistors,Nano Lett.,8,950,(2008))；
Liao etc. utilizes metal-doped In2O3Nano wire compensates the Lacking oxygen in nano wire, to reduce the close of carrier in nano wire
Degree so that the threshold voltage of NWFET towards positive voltage direction move, finally obtain enhanced NWFET (X.M.Zou, J.L.Wang,
X.Q.Liu,etal.,Controllable Electrical Prop erties of Metal-Doped
In2O3Nanowires for High-Performance Enhancement Mode Transistors,Nano Lett.,
13,3287(2013))；Tomioka etc. wraps up the grid of vertical structure InGaAs NWFET using the metal with higher work-functions
Pole has successfully regulated and controled threshold voltage (K.Tomioka, M.Yoshimura, T.Fukui, A the III-V of the device
Nanowire Channel on Silicon for High-Performance Vertical Transistors,Nature,
488,189 (2012)), however complicated gate structure can limit the element in electronic device, sensor and other fields
Using；Han etc. modifies the surface of InAs, InP, InGaAs nano wire using the metal nanoparticle with different work functions, at
The regulation and control of iii-v nano wire threshold voltage are realized to work(, obtain depletion type and enhanced NWFET, and they are assembled in
Efficient N-shaped reverser (N.Han, F.Y.Wang, J.J.Hou, etal., Tunable Electronic has been obtained together
Transport Properties of Metal-ClusterDecorated III–VNanowire Transistors,
Adv.Mater.,25,4445(2013))；But metal nanoparticle is unstable in air, it is heavy on the surface of nano wire to need
The Al of one layer of 20nm of product2O3Protective layer, however Al2O3Layer will limit application of such device in fields such as sensor, detectors；
Cheung etc. is utilized respectively the surface of aromatic thiol salt monolayer modification InAs nano wires in the recent period, which not only can be with
The surface state of InAs nano wires is passivated to improve its electron mobility, and the fragrant sulphur with supplied for electronic and electron-withdrawing group
Alkoxide can also regulate and control respectively InAs NWFET threshold voltages respectively to positive voltage and negative voltage direction movement (H.Y.Cheung,
S.P.Yip,N.Han,etal.,Modulating Electrical Properties of InAs Nanowires via
Molecular Monolayers,ACSNano,9,7545(2015))；However, aromatic thiol salt monolayer attracts InAs to receive
The ability of free electron is limited in rice noodles, only can the threshold voltage of InAs NWFET be moved 1.5V to forward direction, it is more difficult to be increased
Strong type FET；Further, since aromatic thiol salt cannot exist steadily in the long term in air, device its threshold after molecular layer modification
Threshold voltage cannot remain unchanged for a long time in air.Therefore, a kind of easy, easy, efficient technique of exploitation is to regulate and control NWFET
Threshold voltage and nano-wire array field-effect transistor (NW Array FET) threshold voltage, to construct enhanced and exhaust
The NWFET of type, and so that it is stabilized and have a very important significance.
Invention content：
It is an object of the invention to overcome disadvantage of the existing technology, a kind of regulation and control semiconductor nanowires field-effect is provided
The method of transistor threshold voltage, using the nano-particle modified One, Dimensional Semiconductor Nano Materials surface of metal-oxide semiconductor (MOS),
Reach and simply, efficiently regulate and control iii-v and the threshold voltage of metal oxide NWFET, NW Array FET, to be enhanced
NWFET the and NW Array FET of type and depletion type.
To achieve the goals above, the present invention regulates and controls the concrete technology of semiconductor nanowires field-effect transistor threshold voltage
Step is：
(1) first the iii-v prepared and metal oxide nano-wire are dispersed in absolute ethyl alcohol, ultrasonic disperse is equal
It is even；
(2) One, Dimensional Semiconductor Nano Materials are dispersed in by surface by low rubbing method and cover 50nm SiO2The p of dielectric layer
Type heavily doped silicon on piece, back grid of the silicon chip as semiconductor nanowires field-effect transistor (NWFET)；
(3) iii-v prepared and metal oxide nano-wire surface is transferred to by contact printing method to cover
50nmSiO2The p-type heavily doped silicon on piece of dielectric layer obtains nano-wire array, and the silicon chip is as nano-wire array field effect transistor
Manage the back grid of (NW Array FET)；
(4) use photoetching process in the back grid or nano-wire array of semiconductor nanowires field-effect transistor (NWFET)
On the back grid of field-effect transistor (NW Array FET) prepare source, drain electrode photoetching offset plate figure, then by thermal evaporation,
The method metal film of electron beam evaporation or vacuum sputtering coating is removed as source, drain electrode by metal lift-off material
Semiconductor nanowires field-effect transistor (NWFET) or nano-wire array is prepared in unwanted photoresist and metallic film
Field-effect transistor (NW Array FET)；
(5) selection with iii-v and metal oxide nano-wire there is the metal oxide of different work functions partly to lead respectively
Metal material corresponding to body material or metal oxide, by thermal evaporation, electron beam evaporation or sputtering vacuum process by metal
Oxide semiconductor material or metal material be respectively deposited at the semiconductor nanowires field-effect transistor (NWFET) prepared or
On nano-wire array field-effect transistor (NW Array FET), to semiconductor nanowires field-effect transistor (NWFET) or receive
The surface of nanowire arrays field-effect transistor (NW Array FET) plate film modified, and the thickness of plated film is 0.2-5nm, is used
When metal material carries out plating film modified, by the semiconductor nanowires field-effect transistor (NWFET) or nano-wire array after modification
Field-effect transistor (NW Array FET) handles 20-40min with 100-150 DEG C of annealing temperature in air, then dry
72h is placed in dry case makes metallic particles be completely oxidized to metal oxide nanoparticles, to regulate and control the semiconductor nano field of line
The threshold voltage of effect transistor (NWFET) and nano-wire array field-effect transistor (NNW Array FET) obtains enhanced
Semiconductor nanowires field-effect transistor (NWFET), nano-wire array field-effect transistor (NW Array with depletion type
FET)。
Iii-v of the present invention and metal oxide nano-wire are to utilize solid phase source chemical vapor deposition method, pass through gas
Phase-liquid-solid growth mechanism is prepared in double temperature-area tubular furnaces, including InAs, InP, InGaAs, InSb, GaSb,
In2O3、SnO2With one kind in ZnO.
The metal-oxide semiconductor (MOS) with iii-v and metal oxide nano-wire with different work functions of the present invention
Material includes CuO, Ag2O, SnO2Or NiO；Metal material corresponding to metal oxide includes Cu, Ag, Sn or Ni.
Ni, Al or Au film that source of the present invention, leakage metal electrode are thickness 80nm.
The operation principle of the present invention is：Select with nano wire there is the metal semiconductor nano particle of different work functions to repair
Adorn nano wire surface, when nanowire surface modification metal-oxide semiconductor (MOS) nano particle work function than nano wire work(
When function is big, the part free electron in nano wire can flow in nano particle, and the energy band of nanowire surface is bent upwards at this time,
The threshold voltage of NWFET is moved towards positive voltage direction；If the work function of nano wire is partly led than the metal oxide of its surface modification
When the work function of body nano particle is big, the part free electron in nano particle can flow in nano wire, at this time nanowire surface
Energy band be bent downwardly, the threshold voltage of NWFET is moved towards negative voltage direction.Therefore, have from nano wire by selection different
The metal-oxide semiconductor (MOS) nano particle of work function, so that it may simply, efficiently to regulate and control the threshold voltage of NWFET, to obtain
Enhanced and depletion type NWFET, and can be stabilized.
Compared with prior art, the present invention its is simple for process, easy to operate, principle is reliable, and production cost is low, in electronic cutting
It closes the fields such as device, display, biology and chemical sensor to have broad application prospects, is easy to carry out large-scale industry life
Production.
Description of the drawings：
Fig. 1 (a) is band structure schematic diagram of the InAs nano wires when grid voltage is zero, is (b) that CuO nano particles are repaiied
Its band structure schematic diagram (grid voltage zero) when adoring InAs nanowire surfaces, when the nano-particle modified InAs nano wires of CuO
When surface, due to the work function ratio InAs of CuO, the part free electron in nano wire can flow in CuO nano particles, cause
The energy band of InAs nanowire surfaces is bent upwards, and the threshold voltage of InAs NWFET is moved towards positive voltage direction；(c) it is SnO2It receives
Its band structure schematic diagram (grid voltage zero) when rice grain modifies InAs nanowire surfaces, utilizes SnO2It is nano-particle modified
InAs nano wires, since its work function ratio InAs is small, SnO2Part free electron in nano particle can flow to InAs nano wires
In, the energy band of nanowire surface is bent downwardly at this time, and the threshold voltage of InAs NWFET is moved towards negative voltage direction.
Fig. 2 (a), (b) are respectively the scanning electron microscopic picture of InAs, InP nano wire used in the present invention, show nano wire
It is long, relatively straight, diameter is relatively uniform, quality is preferable.
Fig. 3 (a) is the back grid NWFET structural schematic diagrams prepared in the present invention；(b) figure is the backgate prepared in the present invention
Pole NW Array FET structure schematic diagrames.
Fig. 4 (a), (b) are respectively NWFET, NW Array that metal-oxide semiconductor (MOS) is nano-particle modified in the present invention
FET structure schematic diagram.
Fig. 5 (a) is that 0.5nmCu films are formed by the saturating of the nano-particle modified InAs NW of CuO in the embodiment of the present invention 1
Electromicroscopic photograph is penetrated, shows that CuO nano particle sizes are uniform (4.6 ± 1.1nm), is dispersed in nanowire surface；(b) figure is this
0.5nm Cu films are formed by the scanning of a nano-particle modified typical InAs NWFET of CuO in inventive embodiments 1
Electromicroscopic photograph shows that the device channel prepared in the present invention is more straight, and source, drain electrode are more smooth, smooth, InAs nano wires
A diameter of~30nm；(c) figure is transfer curves of the InAs NWFET shown in (b) figure before and after 0.5nmCuO is nano-particle modified,
Show 0.5nm Cu films be formed by CuO nano particles by the threshold voltage of single a diameter of~30nm InAs NWFET to
Positive voltage direction movement~3.3V；NWFET threshold voltages after modification are~0.7V, are successfully transformed into enhanced InAs
NWFET；(d) it is nano-particle modified forward and backward to be that diameter~40nm InAs NWFET in 0.5nm Cu films are formed by CuO for figure
Transfer curve, illustrating that 0.5nm Cu films are formed by CuO nano particles also can be by the InAs of single thicker, a diameter of 40nm
The threshold voltage of NWFET is to positive voltage direction movement~2.2V；NWFET threshold voltages after modification are~0V, are turned by depletion type
Become enhanced.
Fig. 6 (a) is that diameter~30nm InAs NWFET are formed by CuO in 0.2nm Cu films in the embodiment of the present invention 2
Nano-particle modified forward and backward transfer curve, illustrating that 0.2nm Cu films are formed by CuO nano particles can successfully will be single
Nanowire diameter is~threshold voltage of the InAs NWFET of 30nm to positive voltage direction movement~2.1V, the NWFET after modification
The InAs NWFET of depletion type are almost transformed into enhanced by threshold voltage~0V；(b) be the embodiment of the present invention 3 in diameter~
30nm InAs NWFET are formed by the nano-particle modified forward and backward transfer curves of CuO in 2.0nmCu films, illustrate 2.0nm
Cu films be formed by CuO nano particles can successfully by single nano-wire it is a diameter of~the threshold value electricity of the InAs NWFET of 30nm
Positive voltage direction movement~6.2V is pressed to, NWFET threshold voltages~5.0V after modification, successfully by the InAs NWFET of depletion type
It is transformed into enhanced.
Fig. 7 is that diameter~30nm InAs NWFET are formed by Ag in 0.5nmAg films in the embodiment of the present invention 42O receives
Rice grain modifies forward and backward transfer curve, illustrates that 0.5nm Ag films are formed by Ag2O nano particles can be by single nano-wire
The threshold voltage of the InAs NWFET of diameter~30nm is to positive voltage direction movement~0.7V.
Fig. 8 is that diameter~30nm InAs NWFET are formed by SnO in 0.5nm Sn films in the embodiment of the present invention 52It receives
Forward and backward transfer curve is modified in rice grain modification, illustrates that 0.5nm Sn films are formed by SnO2Nano particle can be received single
The threshold voltage of the InAs NWFET of a diameter of 30nm of rice noodles is to negative voltage direction movement~1.53V.
Fig. 9 is to be formed by CuO with diameter~30nm InP NWFET in the embodiment of the present invention 7 in 0.5nmCu films and received
Rice grain modifies forward and backward transfer curve, illustrates that 0.5nmCu films are formed by CuO nano particles by single a diameter of 30nm
InP NWFET threshold voltage to positive voltage direction movement~4.1V, NWFET threshold voltages~3.7V after modification, success
The InP NWFET of depletion type are transformed into enhanced InP NWFET by ground.
Figure 10 is in the embodiment of the present invention 9 with diameter~30nmIn0.7Ga0.3As NWFET are formed in 0.5nm Cu films
The nano-particle modified forward and backward transfer curves of CuO, illustrating that 0.5nm Cu films are formed by CuO nano particles can will be single
Diameter~30nm In0.7Ga0.3The threshold voltage of As NWFET is to positive voltage direction movement~2.8V, the NWFET threshold values after modification
Voltage is~2.5V, successfully by the In of depletion type0.7Ga0.3As NWFET are transformed into enhanced.
Figure 11 is in the embodiment of the present invention 12, and 0.5nm Cu films are formed by the nano-particle modified InAs NW of CuO
Transfer curve forward and backward Array FET；Showing that 0.5nmCu films are formed by CuO nano particles can be by InAs NW Array
For the threshold voltage of FET to positive voltage direction movement~3.0V, the NWFET threshold voltages after modification are~1.43V, successfully will consumption
The InAs NW Array FET of type to the greatest extent are transformed into enhanced.
Specific implementation mode：
It is described further by way of example and in conjunction with the accompanying drawings.
The semiconductor nanowires studied in the present embodiment include InAs, InP, InGaAs, InSb, GaSb, In2O3、SnO2
And ZnO；Semiconductor nanowires are to utilize solid phase source chemical vapor deposition method, by vapor-liquid-solid growth mechanism in dual temperature
(J.J.Hou, N.Han, F.Y.Wang, etal., ACS Nano, 6,3624 (2012) are prepared in area's tube furnace；N.Han,
F.Y.Wang,Z.X.Yang,etal.,NanoscaleRes.Lett.,9,347(2014)；Z.X.Yang,S.P.Yip,
D.P.Li,etal.,ACSNano,9,9268(2015))；The growth source of nano wire is provided with the powder of various types of materials；Au or Ni
Nano particle (6-20nm) catalysis induction nanowire growth；(surface covers SiO to amorphous substrate2Silicon chip, quartz or the glass of layer)
Substrate as nanowire growth；High-purity H2, Ar and O2Gaseous mixture is III-V and metal oxide nano-wire respectively as carrier gas
Growth transport growth source.Fig. 2 (a), (b) show respectively be InAs and InP nano wires used in this experiment scanning electricity
Mirror photo shows that the Nanowire Quality used in the present invention is relatively good, the wire diameter distribution studied in the present embodiment in
Between 20-100nm.
The present embodiment prepares field-effect transistor and the specific process step of modification includes：
(1) first the iii-v prepared and metal oxide nano-wire are dispersed in absolute ethyl alcohol, ultrasonic disperse is equal
It is even；
(2) One, Dimensional Semiconductor Nano Materials are dispersed in by surface by low rubbing method and cover 50nm SiO2The p of dielectric layer
Type heavily doped silicon on piece, back grid of the silicon chip as FET；
(3) iii-v prepared and metal oxide nano-wire surface is transferred to by contact printing method to cover
50nm SiO2The p-type heavily doped silicon on piece of dielectric layer obtains nano-wire array, backgate of the silicon chip as NW Array FET
Pole；
(4) photoetching process is used to prepare source, drain electrode on the back grid of the back grid of FET or NW Array FET respectively
Photoetching offset plate figure, it is thin that 80nmNi or Al is then deposited by the method for thermal evaporation, electron beam evaporation or vacuum sputtering coating
Film removes unwanted photoresist and metallic film as source, drain electrode, and by metal lift-off material, completes back grid
The preparation of NWFET, NW Array FET；Fig. 3 (a) is the structural schematic diagram of single back grid NWFET, wherein Ni is as source, leakage
Electrode, the Si of p-type heavy doping is as back grid；Fig. 3 (b) is the structural representation of back grid nano-wire array NW Array FET
Figure, wherein Ni is as source, drain electrode, and the Si of p-type heavy doping is as back grid；
(5) selection with iii-v and metal oxide nano-wire there is the metal oxide of different work functions partly to lead respectively
Body material (CuO, Ag2O、SnO2, NiO) or the material corresponding to metal material (Cu, Ag, Sn, Ni) its surface is repaiied
Metal-oxide semiconductor (MOS) or metal material, the NWFET and NW that prepare are deposited on by thermal evaporation or electron beam evaporation by decorations
On Array FET, the thickness of plated film is 0.2-5nm, and for the metallic film of vapor deposition, process annealing handles 20- in air
40min, annealing temperature are 100-150 DEG C, and 72h is then placed in drying box to ensure that metallic particles is completely oxidized to metal oxygen
Compound nano particle；The threshold voltage that device can effectively be regulated and controled by metal-oxide semiconductor (MOS) nano particle, is increased
Single NWFET, the NW array FET of strong type and depletion type；Fig. 4 (a), 4 (b) are respectively for metal-oxide semiconductor (MOS) nanometer
The structural schematic diagram of single back grid NWFET and nano-wire array back grid NW Array FET after particle modification.
Embodiment 1：
The present embodiment regulation and control semiconductor N WFET threshold voltages specific process step be：
(1) the InAs nano wires prepared are dispersed in absolute ethyl alcohol first, ultrasonic disperse is uniform；
(2) One, Dimensional Semiconductor Nano Materials are dispersed in by surface by low rubbing method and cover 50nm SiO2The p of dielectric layer
Type heavily doped silicon on piece；
(3) use photoetching process in the p-type heavily doped silicon on piece preparation source that step (2) obtains, the photoresist figure of drain electrode
Shape is deposited 80nm Ni films by thermal evaporation and is used as source, drain electrode, then removes unwanted light by metal lift-off material
Photoresist and metallic film complete the preparation of back grid InAs NWFET；
(4) 0.5nm Cu films are deposited on the back grid InAs NWFET prepared by thermal evaporation, then in sky
Process annealing handles 20min in gas, and annealing temperature is 120 DEG C, and 72h is finally placed in drying box to ensure Cu nano particle quilts
It is completely oxidized to CuO nano particles；Experiment shows that 0.5nm Cu films are formed by CuO nano particles can be by single InAs
The threshold voltage of NWFET is moved towards positive voltage direction, and Fig. 5 a are that CuO nano particles load single InAs nano wires in the embodiment
Transmission electron microscope photo, illustrate that CuO nano particles are evenly distributed, scale ratio is more uniform (4.6 ± 1.1nm)；Fig. 5 b are
The electron scanning micrograph of a typical nano-particle modified InAs NWFET of CuO in this example illustrates making
Device channel is more straight, and Ni electrode films are more smooth, fine and close, diameter~30nm of nano wire；Fig. 5 c are that 5b figures are shown
InAs NWFET are formed by the nano-particle modified forward and backward transfer curves of CuO in 0.5nmCu films, illustrate 0.5nmCu films
Being formed by CuO nano particles can be by the threshold voltage of single InAs NWFET to positive voltage direction movement~3.3V, after modification
NWFET threshold voltages be~0.7V, successfully the InAs NWFET of depletion type are transformed into enhanced；Fig. 5 d are single diameters
The InAs NWFET of~40nm are formed by the nano-particle modified forward and backward transfer curves of CuO, explanation in 0.5nm thickness Cu films
0.5nm thickness Cu films be formed by CuO nano particles can successfully single nano-wire is thicker, a diameter of 40nm InAs
The threshold voltage of NWFET is to positive voltage direction movement~2.2V；InAs NWFET threshold voltages after modification are~0V, are transformed into
It is enhanced.
Embodiment 2：
The deposition thickness of Cu films is 0.2nm in the present embodiment, and other experiment conditions are same as Example 1, and experiment shows
0.2nm thickness Cu films are formed by CuO nano particles and can move the threshold voltage of single InAs NWFET towards positive voltage direction,
Fig. 6 a are that single InAs NWFET are formed by the nano-particle modified forward and backward transfer curves of CuO in 0.2nm thickness Cu films, are said
Bright 0.2nmCu films are formed by CuO nano particles can be successfully by the InAs NWFET's of single nano-wire diameter~30nm
Threshold voltage is to positive voltage direction movement~2.1V；NWFET threshold voltages~0V after modification, becomes enhanced InAs
NWFET。
Embodiment 3：
The deposition thickness of Cu films is 2.0nm modifying the surface of InAs nano wires, other experiment items in the present embodiment
Part is same as Example 1, and experiment shows that 2.0nm Cu films are formed by CuO nano particles can be by single InAs NWFET by consuming
Type is transformed into enhanced to the greatest extent, Fig. 6 b be single InAs NWFET 2.0nm Cu films be formed by CuO it is nano-particle modified before,
Transfer curve afterwards, illustrating that 2.0nm Cu films are formed by CuO nano particles can be by single nano-wire diameter~30nm's
The threshold voltage of InAs NWFET is to positive voltage direction movement~6.2V；InAs NWFET threshold voltages~5.0V after modification,
Successfully it is transformed into enhanced.
Embodiment 4：
In the present embodiment using thermal evaporation deposition thickness be 0.5nm Ag films to modify the surface of InAs nano wires,
Its experiment condition is same as Example 1, and experiment shows that Ag films are formed by Ag2O nano particles can be by single different-diameter
The threshold voltage of InAs NWFET is moved in various degree towards positive voltage direction, and Fig. 7 is single InAs NWFET in 0.5nmAg
Film is formed by Ag2The nano-particle modified forward and backward transfer curves of O illustrate that 0.5nm Ag films are formed by Ag2O nanometers
Grain can be by the threshold voltage of the InAs NWFET of single nano-wire diameter~30nm to positive voltage direction movement~0.7V.
Embodiment 5：
In the present embodiment using thermal evaporation deposition thickness be 0.5nm Sn films to modify the surface of InAs nano wires,
Its experiment condition is same as Example 1, and experiment shows that Sn films are formed by SnO2Nano particle can be by single different-diameter
The threshold voltage of InAs NWFET is moved in various degree towards negative voltage direction；Fig. 8 is single InAs NWFET in 0.5nmSn
Film is formed by SnO2Nano-particle modified forward and backward transfer curve illustrates that 0.5nmSn films are formed by SnO2Nanometer
Grain can be by the threshold voltage of the InAs NWFET of single nano-wire diameter~30nm to negative voltage direction movement~1.53V.
Embodiment 6：
In the present embodiment using thermal evaporation deposition thickness be 0.5nm Ni films to modify the surface of InAs nano wires,
Its experiment condition is same as Example 1, and experiment shows that Ni films are formed by NiO nano particles can be by single different-diameter
The threshold voltage of InAs NWFET is moved in various degree towards positive voltage direction；Such as 0.5nm Ni films are formed by NiO
The threshold voltage of the InAs NWFET of single nano-wire diameter~30nm can be moved 0.9V by nano particle to positive voltage direction.
Embodiment 7：
Using InP nano wires as the channel material of NWFET in the present embodiment, other experiment conditions are same as Example 1, real
Test show that Cu films are formed by CuO nano particles can be by the threshold voltage of InP NWFET and NW Array FET to positive electricity
Press direction movement；Fig. 9 is that single diameter~30nm InP NWFET are formed by CuO nano particles in 0.5nm thickness Cu films and repair
Forward and backward transfer curve is adornd, illustrates that 0.5nm thickness Cu films are formed by CuO nano particles by single, a diameter of~30nm InP
The threshold voltage of NWFET is to positive voltage direction movement~4.1V, InP NWFET threshold voltages~3.7V after modification, successfully
It is transformed into enhanced.
Embodiment 9：
With In in the present embodiment0.7Ga0.3Channel material of the As nano wires as NWFET, other experiment conditions and embodiment 1
Identical, experiment shows that Cu films are formed by CuO nano particles can be by In0.7Ga0.3As NWFET and NW Array FET's
Threshold voltage is moved to positive voltage direction；For example, 0.5nm thickness Cu films are formed by CuO nano particles by diameter~30nm
In0.7Ga0.3The threshold voltage of As NWFET to positive voltage direction movement~2.8V, NWFET threshold voltages after modification are~
The InP NWFET of depletion type are successfully transformed into enhanced InP NWFET by 2.5V.
Embodiment 10：
With In in the present embodiment2O3Channel material of the nano wire as NWFET, 2.0nm thickness Cu films are formed by CuO and receive
Rice grain modifies the surface of nano wire, and other experiment conditions are same as Example 1, and experiment shows that Cu films are formed by CuO and receive
Rice grain can be by different-diameter In2O3The threshold voltage of NWFET is moved in various degree towards positive voltage direction；For example,
2.0nm Cu films are formed by CuO nano particles by diameter~40nm In2O3The threshold voltage of NWFET is to positive voltage direction
Movement~3.0V, threshold voltage~-7.0V.
Embodiment 11：
With SnO in the present embodiment2Channel material of the nano wire as NWFET, 2.0nm Cu films are formed by CuO nanometers
The surface of particle modification nano wire, other experiment conditions are same as Example 1, and experiment shows that Cu films are formed by CuO nanometers
Particle can be by different-diameter In2O3The threshold voltage of NWFET is moved in various degree towards positive voltage direction；For example, 2.0nm
Cu films are formed by CuO nano particles by diameter~50nm SnO2The threshold voltage of NWFET to positive voltage direction move~
4.0V, NWFET threshold voltages~-1.0V after modification.
Embodiment 12：
The specific process step of the present embodiment is：
(1) the InAs nano wires prepared are transferred to surface by contact printing method first and cover 50nm SiO2Dielectric
The p-type heavily doped silicon on piece of layer obtains parallel array of nanowires, back grid of the silicon chip as FET；
(2) using photoetching process preparation source, the photoetching offset plate figure of drain electrode, it is thin that 80nm Ni are then deposited by thermal evaporation
Film removes unwanted photoresist and metallic film as source, drain electrode, by metal lift-off material, completes NW Array FET
The preparation of device；
(3) 0.5nm Cu films are deposited on preparing NW Array FET by thermal evaporation, it is then low in air
Temperature annealing 20min, annealing temperature are 120 DEG C, and 72h is finally placed in drying box to ensure Cu nano particles by complete oxygen
It is melted into CuO nano particles；Figure 11 a are the InAs of typical CuO nano particles (0.5nm Cu film oxidations an obtain) modification
NW Array FET electron scanning micrographs illustrate that the device channel that we make is more straight, and Ni electrode films are relatively more flat
Whole, fine and close, nanowire alignment is more neat；Figure 10 b are the devices in the nano-particle modified forward and backward transfer curves of CuO, by turning
Move curve graph it is found that the threshold voltage of InAs NW Array FET to positive voltage direction movement~3.0V, the NW after modification
Array FET threshold voltages are~1.43V.Therefore, 0.5nmCu films, which are formed by CuO nano particles, can not only adjust list
The threshold voltage of root nano wire makes depletion type NWFET be transformed into enhanced, can also regulate and control InAs nano-wire array field-effect tube
Threshold voltage, so that the InAs NW Array FET of depletion type is transformed into enhanced.
Claims (4)
1. a kind of method of regulation and control semiconductor nanowires field-effect transistor threshold voltage, it is characterised in that specific process step
For：
(1) first the iii-v prepared and metal oxide nano-wire are dispersed in absolute ethyl alcohol, ultrasonic disperse is uniform；
(2) One, Dimensional Semiconductor Nano Materials are dispersed in surface covering 50nm SiO by dripping rubbing method2The p-type weight of dielectric layer
In doped silicon wafer, back grid of the silicon chip as semiconductor nanowires field-effect transistor；
(3) iii-v prepared and metal oxide nano-wire are transferred to surface by contact printing method and cover 50nm
SiO2The p-type heavily doped silicon on piece of dielectric layer obtains nano-wire array, and the silicon chip is as nano-wire array field-effect transistor
Back grid；
(4) use photoetching process in the back grid or nano-wire array field-effect transistor of semiconductor nanowires field-effect transistor
Back grid on prepare source, drain electrode photoetching offset plate figure, then pass through thermal evaporation, electron beam evaporation or vacuum sputtering coating
Method metal film removes unwanted photoresist and metallic film as source, drain electrode, by metal lift-off material, system
It is standby to obtain semiconductor nanowires field-effect transistor or nano-wire array field-effect transistor；
(5) the metal-oxide semiconductor (MOS) material that there are different work functions with iii-v and metal oxide nano-wire is selected respectively
Metal material corresponding to material or metal oxide, is aoxidized metal by thermal evaporation, electron beam evaporation or sputtering vacuum process
Object semi-conducting material or metal material are respectively deposited at the semiconductor nanowires field-effect transistor or nano-wire array prepared
On field-effect transistor, the surface of semiconductor nanowires field-effect transistor or nano-wire array field-effect transistor is plated
Film modified, the thickness of plated film is 0.2-5nm, when carrying out plating film modified using metal material, by the semiconductor nanowires after modification
Field-effect transistor or nano-wire array field-effect transistor handle 20- with 100-150 DEG C of annealing temperature in air
40min, 72h is then placed in drying box makes metallic particles be completely oxidized to metal oxide nanoparticles, to regulate and control
The threshold voltage of semiconductor nanowires field-effect transistor or nano-wire array field-effect transistor obtains enhanced and depletion type
Semiconductor nanowires field-effect transistor, nano-wire array field-effect transistor.
2. regulating and controlling the method for semiconductor nanowires field-effect transistor threshold voltage according to claim 1, it is characterised in that
The iii-v and metal oxide nano-wire are to utilize solid phase source chemical vapor deposition method, are given birth to by vapor-liquid-solid
What long mechanism was prepared in double temperature-area tubular furnaces, including InAs, InP, InGaAs, InSb, GaSb, In2O3、SnO2And ZnO
In one kind.
3. regulating and controlling the method for semiconductor nanowires field-effect transistor threshold voltage according to claim 1, it is characterised in that
With iii-v and metal oxide nano-wire have the metal oxide semiconductor material of different work functions include CuO, Ag2O,
SnO2Or NiO；Metal material corresponding to metal oxide includes Cu, Ag, Sn or Ni.
4. regulating and controlling the method for semiconductor nanowires field-effect transistor threshold voltage according to claim 1, it is characterised in that
Ni, Al or Au film that the source, leakage metal electrode are thickness 80nm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201511028926.2A CN105632935B (en) | 2015-12-31 | 2015-12-31 | A method of regulation and control semiconductor nanowires field-effect transistor threshold voltage |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201511028926.2A CN105632935B (en) | 2015-12-31 | 2015-12-31 | A method of regulation and control semiconductor nanowires field-effect transistor threshold voltage |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105632935A CN105632935A (en) | 2016-06-01 |
| CN105632935B true CN105632935B (en) | 2018-09-25 |
Family
ID=56047736
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201511028926.2A Expired - Fee Related CN105632935B (en) | 2015-12-31 | 2015-12-31 | A method of regulation and control semiconductor nanowires field-effect transistor threshold voltage |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105632935B (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106290525B (en) * | 2016-08-04 | 2018-08-28 | 北京大学 | A kind of nanowire biosensor part and preparation method thereof with grid electrode front regulation and control |
| CN106252227B (en) * | 2016-08-12 | 2019-06-07 | 北京大学 | A kind of integrated approach of the vertical nano-wire biosensor with grid regulation |
| CN107706088A (en) * | 2017-09-08 | 2018-02-16 | 吉林建筑大学 | A kind of semiconductor material surface wet method passivating method |
| CN109585574B (en) * | 2018-11-26 | 2021-03-09 | 长春理工大学 | Method for adjusting response wavelength of GaSb nanowire detector |
| CN112071759B (en) * | 2020-09-14 | 2021-10-15 | 山东大学 | Method for improving hole mobility of p-type field effect transistor |
| CN114242816A (en) * | 2021-12-20 | 2022-03-25 | 北京工业大学 | Single-molecular-layer surface-modified InGaAs nanowire photoelectric detector and preparation method thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102428564A (en) * | 2009-05-21 | 2012-04-25 | 国际商业机器公司 | Nanowire mesh FET with multiple threshold voltages |
-
2015
- 2015-12-31 CN CN201511028926.2A patent/CN105632935B/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102428564A (en) * | 2009-05-21 | 2012-04-25 | 国际商业机器公司 | Nanowire mesh FET with multiple threshold voltages |
Non-Patent Citations (4)
| Title |
|---|
| Ⅲ-Ⅴ Nanowires:synthesis,property manipulations,and device applications;Ming Fang等;《Journal of nanomaterrials》;20140407;第1-14页 * |
| Hydrogen gas sensor based on metal oxide nanoparticles decorated gaphene transistor;zhangyuan zhang等;《nanoscale》;20150505;第10078-10084页 * |
| Selective n-type doping in graphene via the aluminium nanoparticle decoration approach;Xiaoling shi等;《Journal of Materials Chemistry C》;20140512;第5417-5421页 * |
| Tunable electonic Transport Properties of metal-cluster-decorated Ⅲ-Ⅴ Nanowire Transistors;Ning Han等;《ADVANCED MATERIALS》;20130620;第4445-4451页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105632935A (en) | 2016-06-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105632935B (en) | A method of regulation and control semiconductor nanowires field-effect transistor threshold voltage | |
| Zheng et al. | High-performance near-infrared photodetectors based on p-type SnX (X= S, Se) nanowires grown via chemical vapor deposition | |
| Shen et al. | Recent developments in III–V semiconducting nanowires for high-performance photodetectors | |
| Das et al. | Topological insulator Bi2Se3/Si-nanowire-based p–n junction diode for high-performance near-infrared photodetector | |
| Sun et al. | Ultrahigh hole mobility of Sn-catalyzed GaSb nanowires for high speed infrared photodetectors | |
| Fang et al. | III–V nanowires: synthesis, property manipulations, and device applications | |
| Liu et al. | Ultrathin high-quality SnTe nanoplates for fabricating flexible near-infrared photodetectors | |
| Milliron et al. | Solution-processed metal chalcogenide films for p-type transistors | |
| Huang et al. | Metal oxide nanowire transistors | |
| Li et al. | High-performance transparent ultraviolet photodetectors based on InGaZnO superlattice nanowire arrays | |
| Yang et al. | Complementary Metal Oxide Semiconductor-Compatible, High-Mobility,⟨ 111⟩-Oriented GaSb Nanowires Enabled by Vapor–Solid–Solid Chemical Vapor Deposition | |
| Liu et al. | A wafer-scale synthesis of monolayer MoS 2 and their field-effect transistors toward practical applications | |
| Li et al. | Zinc oxide nanostructures and high electron mobility nanocomposite thin film transistors | |
| EP3011596A1 (en) | Thermal doping by vacancy formation in nanocrystals | |
| Wirth-Lima et al. | Graphene/silicon and 2D-MoS2/silicon solar cells: a review | |
| Lah et al. | Engineered nanomaterial in electronics and electrical industries | |
| Gu et al. | Fabrication and investigation of the optoelectrical properties of MoS 2/CdS heterojunction solar cells | |
| Nishikubo et al. | Solution-processed Bi2S3 photoresistor film to mitigate a trade-off between morphology and electronic properties | |
| Al-Samarai et al. | Optoelectronic properties of n-Ag2S nanotubes/p-Si heterojunction photodetector prepared by chemical bath deposition technique: An effect of deposition time | |
| Jin et al. | Efficient silicon solar cells applying cuprous sulfide as hole-selective contact | |
| Ji et al. | Annealing effect and photovoltaic properties of nano-ZnS/textured p-Si heterojunction | |
| Singh et al. | Fabrication and properties of ZnO nanorods based MSM UV detectors on silicon substrates | |
| Gao et al. | Defect engineering in thickness-controlled Bi2O2Se-based transistors by argon plasma treatment | |
| Nallabala et al. | UV-to-NIR broadband photodetecting sensors using n-TiO2 nanorods/p-Si heterojunction in lateral and vertical configurations | |
| Han et al. | Modulating the morphology and electrical properties of GaAs nanowires via catalyst stabilization by oxygen |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20180925 Termination date: 20201231 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |