CN105575919A - 电子封装件及其制法 - Google Patents

电子封装件及其制法 Download PDF

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CN105575919A
CN105575919A CN201410695960.4A CN201410695960A CN105575919A CN 105575919 A CN105575919 A CN 105575919A CN 201410695960 A CN201410695960 A CN 201410695960A CN 105575919 A CN105575919 A CN 105575919A
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electronic
building brick
making
encapsulated layer
electronic building
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唐绍祖
蓝章益
蔡瀛洲
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
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Abstract

一种电子封装件及其制法，该电子封装件包括：电子组件、多个设于该电子组件上的导电组件以及封装层，该封装层覆盖该电子组件的作用面与侧面及该导电组件的部分表面上而未覆盖该电子组件的非作用面，藉以提升该电子组件的作用面的结构强度，使其不会产生裂损，因而能避免该些导电组件自该作用面上脱落。

Description

电子封装件及其制法
技术领域
本发明涉及一种电子封装件，尤指一种能提升产品可靠度的电子封装件及其制法。
背景技术
随着电子产业的发达，现今的电子产品已趋向轻薄短小与功能多样化的方向设计，半导体封装技术亦随之开发出不同的封装型态。为满足半导体装置的高积集度(Integration)、微型化(Miniaturization)以及高电路效能等需求，遂而发展出现行晶圆级芯片尺寸封装(waferlevelchipscalepackage，简称WLCSP)的封装技术。
图1A至图1E为现有WLCSP的封装件1的制法的剖面示意图。
如图1A及图1B所示，将一晶圆12’切割成多个半导体组件12，再置放该些半导体组件12于一承载板10的黏着层11上，之后检测各该半导体组件12。该些半导体组件12具有相对的作用面12a与非作用面12b、及邻接该作用面12a与非作用面12b的侧面12c，该作用面12a上具有多个电极垫120，且各该作用面12a黏着于该黏着层11上。
如图1C所示，形成一封装层13于该黏着层11上，以包覆该半导体组件12。
如图1D所示，移除该承载板10及黏着层11，以外露该半导体组件12的作用面12a。
如图1E所示，进行线路重布层(Redistributionlayer，简称RDL)制程，形成一线路重布结构14于该封装层13与该半导体组件12的作用面12a上，令该线路重布结构14电性连接该半导体组件12的电极垫120。
接着，形成一绝缘保护层15于该线路重布结构14上，且该绝缘保护层15外露该线路重布结构14的部分表面，以供结合如焊锡凸块的导电组件16。
之后，沿如图1E所示的切割路径S进行切单制程。
惟，现有封装件1于切单制程后，该半导体组件12的作用面12a的结构强度较低，因而容易于图1A至图1B的制程时产生裂损(Crack)，且于切单制程前已先检测各该半导体组件12，所以无法检出切单制程所造成的裂损，导致该些导电组件16容易发生脱落的问题，以于取放该封装件1至适合位置以进行表面贴焊技术(SurfaceMountTechnology，简称SMT)时，易使产品的良率不佳。
因此，如何克服上述现有技术的问题，实已成为目前业界亟待克服的难题。
发明内容
鉴于上述现有技术的种种缺失，本发明提供一种电子封装件及其制法，能避免该些导电组件自该作用面上脱落。
本发明的电子封装件，包括：电子组件，其具有相对的作用面与非作用面、及邻接该作用面与非作用面的侧面，且该作用面具有多个电极垫；多个导电组件，其设于该些电极垫上；以及封装层，其形成于该电子组件的作用面与侧面上及该导电组件的部分表面上，而未形成于该电子组件的非作用面上。
本发明还提供一种电子封装件的制法，包括：提供一整版面基板，该整版面基板包含多个电子组件与间隔部，该间隔部位于各该电子组件之间，且该电子组件具有相对的作用面与非作用面，该作用面具有多个电极垫；于对应该电子组件的作用面的一侧，形成沟道于该间隔部上，且该沟道未贯穿该整版面基板；形成封装层于该沟道中与该电子组件的作用面上，且该封装层未覆盖该些电极垫；以及于对应该电子组件的非作用面的一侧，沿该间隔部分离各该电子组件，使该封装层形成于该电子组件的作用面与侧面上，其中，该侧面邻接该作用面与非作用面。
前述的制法中，沿该间隔部分离各该电子组件的路径的宽度小于该间隔部的宽度。
前述的制法中，该封装层未形成于该电子组件的非作用面上。
前述的制法中，还包括形成该封装层之后，先检测该整版面基板，再分离各该电子组件。
前述的制法中，还包括分离各该电子组件之前，先进行薄化制程以移除该非作用面的部分材质。
前述的电子封装件及其制法制法中，该封装层的表面齐平该非作用面。
前述的电子封装件及其制法中，形成该封装层的材质为绝缘材。
前述的电子封装件及其制法中，该封装层还形成于该电子组件的非作用面上。
前述的电子封装件及其制法中，还包括形成多个导电组件于该些电极垫上，使该封装层还形成于该导电组件的部分表面上，且该封装层位于该导电组件上的高度为0.01至0.9㎜。例如，先形成该封装层，再形成该些导电组件于该些电极垫上；或者，先形成该些导电组件于该些电极垫上，再以软性绝缘层包覆该些导电组件，之后形成该封装层，最后，移除该软性绝缘层。
前述的电子封装件及其制法中，该电子组件为主动组件、被动组件或其组合者。
前述的电子封装件及其制法中，还包括于分离各该电子组件之后，该电子组件以其作用面结合至一电子装置上。
由上可知，本发明的电子封装件及其制法，主要藉由先形成未贯穿该间隔部的沟道，再形成封装层于该沟道中与该电子组件的作用面上，使该封装层形成于该电子组件的作用面与侧面上，以提升该电子组件的结构强度，所以相较于现有技术，于切单制程时，该电子组件的作用面的结构强度较强，因而不会产生裂损。
此外，藉由先检测该整版面基板，以确认形成该沟道时所造成的裂损状况，再进行切单，以淘汰不良电子封装件，所以于进行表面贴焊制程时，能提升产品的良率。
附图说明
图1A至图1E为现有WLCSP的封装件的制法的剖视示意图；以及
图2A至图2F为本发明的电子封装件的制法的剖视示意图；其中，图2A’、图2C’与图2F”为图2A、图2C与图2F的另一方法；其中，图2F’为图2F(含电路板)的下视图。
主要组件符号说明
1封装件
10承载板
11黏着层
12’晶圆
12半导体组件
12a、22a作用面
12b、22b非作用面
12c、22c侧面
120、220电极垫
13、25封装层
14线路重布结构
15、221绝缘保护层
16、23导电组件
2电子封装件
20整版面基板
21间隔部
22电子组件
24沟道
25a表面
26软性绝缘层
8电路板
A、B高度
d厚度
S切割路径
L、W宽度
Y箭头。
具体实施方式
以下藉由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其它优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用于配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用于限定本发明可实施的限定条件，所以不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”及“一”等用语，也仅为便于叙述的明了，而非用于限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
图2A至图2F为本发明的电子封装件2的制法的剖视示意图。
如图2A所示，提供一整版面基板20，该整版面基板20包含多个电子组件22与间隔部21，且该间隔部21结合于各该电子组件22之间。
于本实施例中，该电子组件22具有作用面22a与相对该作用面22a的非作用面22b，该作用面22a上具有多个电极垫220，并形成一绝缘保护层221于该作用面22a与该些电极垫220上，且该绝缘保护层221外露该些电极垫220。
此外，该电子组件22为主动组件、被动组件或其组合者，且该主动组件例如为半导体芯片，而该被动组件例如为电阻、电容及电感。于此，该整版面基板20为晶圆，且该电子组件22为主动组件。
又，该电子组件22已完成线路重布层(Redistributionlayer，简称RDL，图略)制程，该线路重布结构的最外侧设有该些电极垫220。
如图2B所示，于对应该电子组件22的作用面22a的一侧(即自该作用面22a上方)，以激光切割方式形成一沟道24于单一该间隔部21上，使各该电子组件22形成有侧面22c，且该侧面22c相邻该作用面22a，其中，该沟道24并未贯穿该间隔部21。
于本实施例中，移除部分该间隔部21，使该间隔部21的保留厚度d为20μm，以形成该沟道24，且该沟道24的宽度L(或该间隔部21的宽度)为10μm至3㎜。
如图2C所示，形成一封装层25于该沟道24中与该作用面22a的绝缘保护层221上，且该封装层25未覆盖该些电极垫220。接着，检测该整版面基板20以检出于形成该沟道24时所产生的裂损。
于本实施例中，该封装层25填满该沟道24，使该封装层25环设于该电子组件22的周围，且该封装层25为绝缘材，例如，模封材(moldingcompound)、干膜材(dryfilm)、光阻材(photoresist)或防焊层(soldermask)。
此外，该封装层25未形成于该电子组件22的非作用面22b上。
如图2D所示，进行薄化制程，即研磨移除该非作用面22b的部分材质，使该沟道24中的封装层25外露于该非作用面22b，且该沟道24中的封装层25的表面25a齐平该非作用面22b。
接着，形成多个导电组件23于该些电极垫220上，使该封装层25还形成于该导电组件23的部分表面上。
于本实施例中，该些导电组件23为焊球、金属凸块或其结合的态样。
如图2E所示，于对应该电子组件22的非作用面22b的一侧进行切单制程(如图中的箭头Y的方向)，沿图2D所示的切割路径S(即沿该间隔部21的路径)切割该整版面基板20，以分离各该电子组件22，使该封装层25形成于该电子组件22的作用面22a与侧面22c上，俾获取多个电子封装件2。
于本实施例中，以钻石刀切割该封装层25的方式进行切单制程，且该切割路径S的宽度W小于该沟道24的宽度L(如图2B所示)。
如图2F及图2F’所示，该电子组件22藉其结合至一如电路板8的电子装置上(即覆晶式结合)，且该些导电组件23结合至该电路板8的电性接触垫(图略)上。
于另一实施例中，也可于形成该沟道24之前，先形成多个导电组件23于该些电极垫220上，如图2A’所示；接着，如图2C’所示，以软性绝缘层26包覆该些导电组件23，再形成该封装层25，且该封装层25未覆盖该些电极垫220与该些导电组件23，其中，前述形成封装层25于电子组件22的主动面22a的方式可以模压或是旋转涂布方式形成；最后，如图2F”所示，移除该软性绝缘层26，使该封装层25还形成于该导电组件23的部分表面上，且该封装层25爬升于该导电组件23侧面的高度B约占该导电组件23的侧面高度A的0.05至0.9(即B＝0.05A～0.9A)，其中，该封装层25爬升于该导电组件23侧面的高度B为0.01至0.9㎜；实际上，该导电组件23一般侧面高度约为1mm(但会依导电组件的种类不同而有所改变)，欲形成B＝0.05A～0.9A的方式为以旋转涂布为佳。由于该软性绝缘层26的特性，使该封装层25位于该导电组件23处的表面会呈现非平整面(即不规则状)，如图2F”所示。
本发明的制法中，藉由先形成未贯穿该间隔部21的沟道24，再形成封装层25于该沟道24中与该电子组件22的作用面22a上，使该封装层25形成于该电子组件22的作用面22a与侧面22c上，以提升该电子封装件2的强度，所以于进行切单制程时，该电子组件22的作用面22a的结构强度较强，因而不会产生裂损。因此，该些导电组件23不会发生脱落的问题，以于后续进行表面贴焊技术或运送该电子封装件2时，能提升产品的良率。
此外，于形成该封装层25后，先检测该整版面基板20的结构良率，以辨识出不良电子组件22，再进行切单，以淘汰不良电子封装件2，所以于进行表面贴焊制程时，能提升产品的良率。
又，如图2C’所示，若先形成该些导电组件23，再形成该封装层25，所以可藉由该封装层25的保护，以增加该些导电组件23的结合稳定性，使该些导电组件23更不会发生脱落的问题，而达到增加封装信赖性的目的。
本发明还提供一种电子封装件2，其包括：一电子组件22、一封装层25以及多个导电组件23。
所述的电子组件22为主动组件、被动组件或其组合者，其具有相对的作用面22a与非作用面22b、及邻该作用面22a与非作用面22b的侧面22c，且该作用面22a设有多个电极垫220。
所述的封装层25形成于该电子组件22的作用面22a与侧面22c上而未形成于该非作用面22b上，且形成该封装层25的材质为绝缘材。
所述的导电组件23设于该些电极垫220上并电性连接该些电极垫220，且该封装层25还形成于该导电组件23的部分表面上，其中，该封装层25位于该导电组件23上的高度B为0.01至0.9㎜。
于一实施例中，该封装层25的表面齐平该非作用面22b。
于一实施例中，该电子组件22藉由该些导电组件23结合至一电路板8上。
综上所述，本发明的电子封装件，藉由该封装层的设计，以提升该电子封装件的结构强度，而能避免该电子组件产生裂损，因而提升该电子封装件的良率。
此外，先检测该整版面基板，再进行切单，以于进行表面贴焊制程时，能提升产品的良率。
上述实施例仅用于例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (20)

1.一种电子封装件，包括：
电子组件，其具有相对的作用面与非作用面、及邻接该作用面与非作用面的侧面，且该作用面具有多个电极垫；
多个导电组件，其设于该些电极垫上；以及
封装层，其形成于该电子组件的作用面与侧面上及该导电组件的部分表面上，而未形成于该电子组件的非作用面上。
2.如权利要求1所述的电子封装件，其特征为，该电子组件为主动组件、被动组件或其组合者。
3.如权利要求1所述的电子封装件，其特征为，该电子组件以其作用面结合至一电子装置上。
4.如权利要求1所述的电子封装件，其特征为，该封装层的表面齐平该非作用面。
5.如权利要求1所述的电子封装件，其特征为，形成该封装层的材质为绝缘材。
6.如权利要求1所述的电子封装件，其特征为，该封装层位于该导电组件上的高度为0.01至0.9mm。
7.一种电子封装件的制法，包括：
提供一整版面基板，该整版面基板包含多个电子组件与间隔部，该间隔部位于各该电子组件之间，且该电子组件具有相对的作用面与非作用面，该作用面并具有多个电极垫；
于对应该电子组件的作用面的一侧，形成沟道于该间隔部上，且该沟道未贯穿该整版面基板；
形成封装层于该沟道中与该电子组件的作用面上，且该封装层未覆盖该些电极垫；以及
于对应该电子组件的非作用面的一侧，沿该间隔部分离各该电子组件，使该封装层形成于该电子组件的作用面与侧面上，其中，该侧面邻接该作用面与非作用面。
8.如权利要求7所述的电子封装件的制法，其特征为，形成该封装层的材质为绝缘材。
9.如权利要求7所述的电子封装件的制法，其特征为，该封装层未形成于该电子组件的非作用面上。
10.如权利要求7所述的电子封装件的制法，其特征为，沿该间隔部分离各该电子组件的路径的宽度小于该间隔部的宽度。
11.如权利要求7所述的电子封装件的制法，其特征为，该封装层的表面齐平该非作用面。
12.如权利要求7所述的电子封装件的制法，其特征为，该制法还包括，于形成该封装层之后，先检测该整版面基板，再分离各该电子组件。
13.如权利要求7所述的电子封装件的制法，其特征为，该制法还包括，于分离各该电子组件之前，先移除该非作用面的部分材质。
14.如权利要求7所述的电子封装件的制法，其特征为，该制法还包括形成多个导电组件于该些电极垫上。
15.如权利要求14所述的电子封装件的制法，其特征为，该封装层还形成于该导电组件的部分表面上。
16.如权利要求15所述的电子封装件的制法，其特征为，该封装层位于该导电组件上的高度为0.01至0.9mm。
17.如权利要求14所述的电子封装件的制法，其特征为，该封装层为先予形成，再形成该些导电组件于该些电极垫上。
18.如权利要求14所述的电子封装件的制法，其特征为，该些导电组件先形成于该些电极垫上，再以软性绝缘层包覆该些导电组件，于形成该封装层后，移除该软性绝缘层。
19.如权利要求7所述的电子封装件的制法，其特征为，该制法还包括于分离各该电子组件之后，该电子组件以其作用面结合至一电子装置上。
20.如权利要求7所述的电子封装件的制法，其特征为，该电子组件为主动组件、被动组件或其组合者。
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US20180068896A1 (en) 2018-03-08
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