CN105575907B - A kind of manufacturing method and electronic device of semiconductor devices - Google Patents

A kind of manufacturing method and electronic device of semiconductor devices Download PDF

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CN105575907B
CN105575907B CN201410538677.0A CN201410538677A CN105575907B CN 105575907 B CN105575907 B CN 105575907B CN 201410538677 A CN201410538677 A CN 201410538677A CN 105575907 B CN105575907 B CN 105575907B
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layer
gate
grid
semiconductor devices
logical
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CN105575907A (en
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王新鹏
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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Abstract

The present invention provides a kind of manufacturing method and electronic device of semiconductor devices, is related to technical field of semiconductors.The manufacturing method of the semiconductor devices of the present invention is initially formed the gate structure of formation flash memory after the grid of logical device, thus can be to avoid the improper etching of the control gate to flash area;In addition, the step of this method will carry out LDD processing to flash cell area is inserted into the step of forming offset side-wall material floor and performs etching offset side-wall material floor to be formed between the step of deviating side wall layer, and between the step of being inserted into the step of forming side-wall material layer and performing etching side-wall material layer to form side wall layer the step of source electrode and drain electrode of the ion implanting to form flash memory will be carried out, thus the breakdown voltage of flush memory device can be improved.The electronic device of the present invention includes equally being had the advantages that above-mentioned according to semiconductor devices made from the above method.

Description

A kind of manufacturing method and electronic device of semiconductor devices
Technical field
The present invention relates to technical field of semiconductors, the manufacturing method in particular to a kind of semiconductor devices and electronics dress It sets.
Background technology
In technical field of semiconductors, embedded flash memory (eFlash) technology is to integrate logical device and flash memory Technology.Since the manufacturing process of logical device has different demands from the manufacturing process of flash memory, in embedded flash memory Manufacturing process in, there is shifting relationships between logical device manufacturing process and the manufacturing process of flash memory, it is difficult to together When the two is controlled in relatively good process conditions.
A kind of manufacturing method of current embedded flash memory, is initially formed the grid of flash memory, the rear grid for forming logical device. After the grid for forming flash memory, as shown in Figure 1A, the grid for being used to form logical device will be existed simultaneously in flash cell area Material (be usually polysilicon) and control grid material and floating gate material, i.e. the grid of flash memory includes above-mentioned three kinds of materials, such as In Figure 1A shown in 101.At this point, the difference in height h of flash cell area and logic device area is very big, such as it is likely to be up toThis is resulted in during the mask for forming the grid for etching logical device, the bottom anti-reflection layer of formation 110 and the thickness of photoresist 120 be difficult to meet etching needs, as shown in Figure 1B.Then, the grid of logical device is formed in etching During, often cause the control gate 130 of flash memory by improper etching, as shown in Figure 1 C.
Since the above method be easy to cause the control gate of flash memory by improper etching, the embedded sudden strain of a muscle of another kind in the prior art The technique that the manufacturing method deposited re-forms the grid of flash memory using the grid for being initially formed logical device.The technique specifically includes as follows Step:Polysilicon deposition (poly2 dep);High pressure polysilicon pre-doping (HV poly pre-doping);BNP ion implantings; Form the grid of logical device;Form control gate;Gate re-ox (GT Re-OX);To the N-type transistor in high tension apparatus into Row LDD;LDD is carried out to the P-type transistor in high tension apparatus;Form offset side wall etc..This method can improve the control of flash memory The problem of grid (CG) processed are by improper etching, it is still, embedding obtained by the manufacturing method relative to the first above-mentioned embedded flash memory Enter formula flash memory, the breakdown voltage (break down voltage) of embedded flash memory made from this method declines to a great extent, usually 10% or so can be declined.That is, the manufacturing method of second of embedded flash memory, can cause the performance of device to decline.
As it can be seen that the manufacturing method of two kinds of embedded flash memorys in the prior art, be difficult to ensure simultaneously the yield of device and Performance.Therefore, to solve this problem, it is necessary to propose a kind of manufacturing method of new semiconductor devices.
Invention content
In view of the deficiencies of the prior art, the present invention proposes a kind of manufacturing method of semiconductor devices, the method includes:
Step S101:Offer includes the semiconductor substrate of flash cell area and logic device area, in the semiconductor substrate Upper formation gate material layers perform etching to form the logical device positioned at the logic device area gate material layers Grid;
Step S102:The flash cell area formed flash memory gate structure, wherein the gate structure include floating boom, Dielectric layer between control gate on the floating boom and the grid between the floating boom and the control gate;
Step S103:Oxidation processes are carried out in the side of the grid of the logical device and the gate structure of the flash memory Oxide skin(coating) is formed with top surface;
Step S104:The offset side-wall material layer for forming the covering semiconductor substrate and the oxide skin(coating), to described Flash cell area carries out LDD processing, performs etching the offset side-wall material layer with the two of the grid of the logical device The both sides of the gate structure of side and the flash memory form offset side wall layer;
Step S105:LDD processing is carried out to the logic device area;
Step S106:It is formed and covers the semiconductor substrate, the gate structure of the flash memory and the logical device The side-wall material layer of grid carries out ion implanting to form the source electrode and drain electrode of flash memory in the flash cell area, to the side The wall material bed of material is performed etching to form side in the both sides of the grid of the logical device and the both sides of the gate structure of the flash memory Parietal layer.
Optionally, in the step S101, the gate material layers is performed etching and are located at the logic device to be formed The method of the grid of the logical device in part area includes:
The patterned of the region where the grid of the quasi- logical device formed of covering is formed in the gate material layers Mask layer;
The gate material layers are performed etching to form the grid of logical device.
Optionally, in the step S101, the mask layer includes photoresist, the crucial ruler of the line width of the mask layer Very little ranging from 55~65nm, ranging from 115~125nm of the critical size of the spacing of figure in the mask layer.
Optionally, in the step S101, the critical size of the line width of the mask layer is 60nm, the mask layer The critical size of spacing is 120nm.
Optionally, in the step S103, the thickness of the oxide skin(coating) is
Optionally, in the step S104, the material of the offset side-wall material layer includes silicon nitride, the offset side The thickness of the wall material bed of material is
Optionally, in the step S106, the side-wall material layer is for silicon oxide layer or by silicon oxide layer, silicon nitride layer The composite layer constituted with silicon oxide layer, the thickness of the side-wall material layer are
Optionally, further include step S107 after the step S106:Ion implanting is carried out in the logical device Area forms the source electrode and drain electrode of logical device.
Optionally, in the step S101, in the step of forming the gate material layers and the grid for forming logical device Further include following steps between the step of pole:
The gate material layers are carried out with the pre-doping processing of the high tension apparatus of flash area;
The gate material layers are carried out with the ion implanting of the local device of logic region.
The present invention also provides a kind of electronic device, including electronic building brick and the semiconductor device that is connected with the electronic building brick Part, wherein the semiconductor devices is prepared using the manufacturing method of semiconductor devices described in any one of the above embodiments.
The manufacturing method of the semiconductor devices of the present invention forms the grid of flash memory due to being initially formed after the grid of logical device Structure, thus can be to avoid the improper etching of the control gate to flash area;Since LDD processing will be carried out to flash cell area Step is inserted into the step of forming offset side-wall material layer and performs etching offset side-wall material layer to form offset side wall layer The step of between, the step of carrying out source electrode and drain electrode of the ion implanting to form flash memory is inserted into the step to form side-wall material layer Suddenly with the step of performing etching side-wall material layer to form side wall layer between, thus the breakdown potential of flush memory device can be improved Pressure.Therefore, method of the invention can improve the performance and yield of semiconductor devices obtained.The electronic device of the present invention, by In including above-mentioned semiconductor devices, thus equally have the advantages that above-mentioned.
Description of the drawings
The following drawings of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair Bright embodiment and its description, principle used to explain the present invention.
In attached drawing:
Figure 1A and Figure 1B is that a kind of correlation step of the manufacturing method of semiconductor devices is formed by structure in the prior art Schematic cross sectional views;
Fig. 1 C for a kind of manufacturing method of semiconductor devices in the prior art formation logical device grid the step of institute The SEM of the structure of formation schemes;
Fig. 2A to Fig. 2 L is the structure that the correlation step of the manufacturing method of the semiconductor devices of the embodiment of the present invention one is formed Schematic cross sectional views;
Fig. 3 is a kind of schematic flow chart of the manufacturing method of the semiconductor devices of the embodiment of the present invention one.
Specific implementation mode
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into Row description.
It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here Embodiment.Disclosure will be made thoroughly and complete on the contrary, providing these embodiments, and will fully convey the scope of the invention to Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in the areas Ceng He may be exaggerated.From beginning to end Same reference numerals indicate identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other When element or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or There may be elements or layer between two parties by person.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly It is connected to " or " being directly coupled to " other elements or when layer, then element or layer between two parties is not present.It should be understood that although can make Various component, assembly units, area, floor and/or part are described with term first, second, third, etc., these component, assembly units, area, floor and/ Or part should not be limited by these terms.These terms be used merely to distinguish a component, assembly unit, area, floor or part with it is another One component, assembly unit, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, portion Part, area, floor or part are represented by second element, component, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... it On ", " above " etc., herein can for convenience description and being used describe an elements or features shown in figure with The relationship of other elements or features.It should be understood that other than orientation shown in figure, spatial relationship term intention further includes making With the different orientation with the device in operation.For example, if the device in attached drawing is overturn, then, it is described as " under other elements Face " or " under it " or " under it " elements or features will be oriented in other elements or features "upper".Therefore, exemplary art Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole The presence of number, step, operations, elements, and/or components, but be not excluded for one or more other features, integer, step, operation, The presence or addition of component, assembly unit and/or group.Herein in use, term "and/or" includes any of related Listed Items and institute There is combination.
It describes to send out herein with reference to the cross-sectional view of the schematic diagram of the desirable embodiment (and intermediate structure) as the present invention Bright embodiment.As a result, it is contemplated that due to caused by such as manufacturing technology and/or tolerance from the variation of shown shape.Therefore, The embodiment of the present invention should not necessarily be limited to the specific shape in area shown here, but include due to for example manufacturing caused shape Shape deviation.For example, be shown as the injection region of rectangle its edge usually there is circle or bending features and/or implantation concentration ladder Degree, rather than the binary from injection region to non-injection regions changes.Equally, the disposal area can be led to by injecting the disposal area formed Some injections in area between the surface passed through when injection progress.Therefore, the area shown in figure is substantially schematic , their shape is not intended the true form in the area of display device and is not intended to limit the scope of the present invention.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, so as to Illustrate technical scheme of the present invention.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, this Invention can also have other embodiment.
Embodiment one
In the following, describing the manufacturer of the semiconductor devices of proposition of the embodiment of the present invention with reference to Fig. 2A to Fig. 2 L and Fig. 3 Method.Wherein, Fig. 2A to Fig. 2 L is the structure of the correlation step formation of the manufacturing method of the semiconductor devices of the embodiment of the present invention one Schematic cross sectional views;Fig. 3 is a kind of schematic flow chart of the manufacturing method of the semiconductor devices of the embodiment of the present invention one.
The manufacturing method of the semiconductor devices of the embodiment of the present invention can be used for preparing embedded flash memory (eFlash), main Include the following steps:
Step A1:Offer includes the semiconductor substrate 200 of flash cell area and logic device area, in semiconductor substrate 200 Upper formation gate material layers 2010, as shown in Figure 2 A.
Gate material layers 2010 are performed etching, to form the grid 201 of the logical device positioned at logic device area, are such as schemed Shown in 2B.
In the present embodiment, it after the step of forming gate material layers 2010, before forming the step of grid 201, goes back It may include steps of:
The pre-doping that gate material layers 2010 are carried out with the high tension apparatus of flash area handles (HV poly pre- doping);
The gate material layers are carried out with the ion implanting of the local device of logic region.
Wherein, various feasible schemes in the prior art may be used in high pressure pre-doping and BNP ion implantings, herein simultaneously Without limiting.
It will be understood to those skilled in the art that before forming gate material layers 2010, also wrapped in semiconductor substrate 200 Include other film layers or structure, such as gate dielectric, shallow trench isolation etc..Semiconductor substrate 200 can be monocrystalline substrate or Other suitable substrates.The material of gate material layers 2010 can be polysilicon or other suitable materials.Form grid material The method of layer 2010 can be sedimentation or other suitable methods.
Illustratively, the method that gate material layers 2010 are performed etching with the grid 201 to form logical device includes:
The patterned of the region where the grid of the quasi- logical device formed of covering is formed in gate material layers 2010 Mask layer;
Gate material layers 2010 are performed etching to form the grid 201 of logical device.
Wherein, mask layer can be photoresist or other suitable materials.The critical size of the line width (line) of mask layer (CD) ranging from 55~65nm, preferably 60nm;The critical size of the spacing (space) of figure is ranging from mask layer 115~125nm, preferably 120nm.
Step A2:The gate structure 300 of flash memory is formed in flash cell area, wherein the gate structure of the flash memory includes floating Grid (FG) 301, the control gate (CG) 303 on the floating boom 301 and between floating boom 301 and control gate 303 Dielectric layer 302 between grid, as shown in Figure 2 C.
Formed gate structure 300 method can be:It is sequentially depositing floating gate material layer, dielectric on semiconductor substrate 200 Material layer and control gate material layer;Control gate material layer, dielectric materials layer and floating gate material layer are performed etching, in flash memory Cellular zone forms shown control gate 303, gate dielectric 302 and floating boom 301.
Wherein, the material of dielectric layer 302 can be silica or other suitable dielectric materials between grid.Floating boom 301 and control The material of grid 303 processed can be polysilicon or other suitable materials.
By step A1 and step A2 it is found that the manufacturing method of the semiconductor devices of the present embodiment is to be initially formed logical device Grid re-forms the gate structure of flash memory.It, can be to avoid control gate by improper quarter compared with first method in the prior art The problem of erosion.
Step A3:Oxidation processes are carried out in the side and top of the gate structure 300 of the grid 201 and flash memory of logical device Face forms oxide skin(coating) 202, as shown in Figure 2 D.
Wherein, existing various feasible method for oxidation may be used in oxidation processes.The material of oxide skin(coating) 202 is usually Silica.Illustratively, the thickness of oxide skin(coating) 202 is
Step A4:The offset side-wall material layer 2030 for forming covering semiconductor substrate 200 and oxide skin(coating) 202, such as Fig. 2 E It is shown.
Wherein, the method for forming offset side-wall material layer 2030 can be sedimentation.Deviate the material of side-wall material layer 2030 Material can be silicon nitride or other suitable materials.The thickness range of offset side-wall material layer 2030 is
LDD (lightly doped drain) is carried out to flash cell area to handle, as shown in Figure 2 F.Wherein, in fig. 2f, downward arrow For illustrating LDD processing.LDD processing to flash cell area, generally includes N-type LDD processing and p-type LDD processing, the two are usual Separately carry out.
Illustratively, during LDD is handled, the region handled without LDD is covered using mask layer 600 Lid.As it can be seen that LDD (lightly doped drain) processing carried out to flash cell area is not blanket type ion implanting (blanket implantation)。
Offset side-wall material layer 2030 is performed etching, in 201 both sides of grid of logical device and the grid knot of flash memory The both sides of structure 300 form offset side wall layer 203, as shown in Figure 2 G.Wherein, the etching can be dry etching or other are suitable Lithographic method.
The method of the embodiment of the present invention and the one of the prior art the difference is that, form offset side-wall material layer 2030 The step of with to offset side-wall material layer 2030 perform etching to be formed offset side wall layer 203 the step of not be carried out continuously, but The step of LDD is carried out to flash cell area is inserted between them.Compared with second method in the prior art, this is helped In the breakdown voltage for improving device.
Step A5:LDD (lightly doped drain) is carried out to logic device area to handle, as illustrated in figure 2h.
Wherein, in Fig. 2 H, downward arrow is for illustrating LDD processing.During LDD is handled, do not carry out at LDD The region of reason is covered by mask layer 700.N-type LDD processing and p-type LDD processing are generally included to the LDD processing of logic device area, The two is usually spaced apart by progress.
Step A6:Form the grid 201 of covering semiconductor substrate 200, the gate structure 300 of flash memory and logical device Side-wall material layer 2040, as shown in figure 2i.
Wherein, the method for forming side-wall material layer 2040 can be sedimentation.Side-wall material layer 2030 can be silica Layer can be the lamination layer structure being made of silica, silicon nitride, silica, can be with other suitable film layers.Side-wall material Layer 2040 thickness range be
Then, ion implanting is carried out to form the source electrode and drain electrode of flash memory in flash cell area, as shown in fig. 2j.
Wherein, in Fig. 2 J, downward arrow is for illustrating ion implantation process.The source electrode and drain electrode of formation includes N-type The source electrode and drain electrode of transistor and the source electrode and drain electrode of P-type transistor.Brief for expression, the source of flash memory is not shown in Fig. 2 J Pole and drain electrode.Illustratively, during ion implanting, the region for not carrying out ion implanting is covered by mask layer 800.Also The step of being to say, the source electrode and drain electrode of flash memory is formed by ion implanting not blanket type ion implanting (blanket implantation)。
Then, side-wall material layer 2040 is performed etching, in 201 both sides of grid of logical device and the grid knot of flash memory The both sides of structure 300 form side wall layer 204, as shown in figure 2k.Wherein, the etching can be dry etching or other suitable quarters Etching method.
The method of the embodiment of the present invention and the one of the prior art the difference is that, form the step of side-wall material layer 2040 Suddenly with the step of forming side wall layer 204 performed etching to side-wall material layer 2040 be not carried out continuously, but insert between them The step of source electrode and drain electrode of flash memory is formed by ion implanting is entered.Compared with second method in the prior art, this has Help improve the breakdown voltage of device.
Step A7:Carry out ion implanting to form the source electrode and drain electrode of logical device in logic device area, as shown in figure 2l.
Wherein, in Fig. 2 L, downward arrow is for illustrating ion implantation process.During ion implanting, not into The region of row ion implanting is covered by mask layer 900.The source electrode and drain electrode of formation include N-type transistor source electrode and drain electrode and The source electrode and drain electrode of P-type transistor.Brief for expression, flash memory source electrode and drain electrode is not shown in Fig. 2 L.
So far, the introduction of the committed step of the manufacturing method of the semiconductor devices of the embodiment of the present invention is completed.This field Technical staff be appreciated that in addition to above-mentioned step A1 to A7, between adjacent step and after step A7, this implementation Example can also include other steps in the prior art, such as:After step A 7 can also include formed interlayer dielectric layer with And the step of forming contact hole etc., details are not described herein again.
The manufacturing method of the semiconductor devices of the embodiment of the present invention, by forming flash memory after being initially formed the grid of logical device Gate structure, can be to avoid the improper etching of the control gate to flash area;By the way that LDD processing will be carried out to flash cell area The step of be inserted into be formed offset side-wall material layer 2030 the step of with to offset side-wall material layer 2030 perform etching with formed It is inserted into shape between the step of deviating side wall layer 203 and the step of source electrode and drain electrode of the ion implanting to form flash memory will be carried out It, can between the step of side-wall material layer 2040 and the step of performing etching side-wall material layer 2040 to form side wall layer 204 To improve the breakdown voltage (break down voltage) of flush memory device.Thus, the semiconductor devices of the embodiment of the present invention Manufacturing method can improve the yield and performance of semiconductor devices obtained.
Fig. 3 shows a kind of schematic flow chart of the manufacturing method for the semiconductor devices that the embodiment of the present invention proposes, uses In the typical process for schematically illustrating the above method.It specifically includes:
Step S101:Offer includes the semiconductor substrate of flash cell area and logic device area, in the semiconductor substrate Upper formation gate material layers perform etching to form the logical device positioned at the logic device area gate material layers Grid;
Step S102:The flash cell area formed flash memory gate structure, wherein the gate structure include floating boom, Dielectric layer between control gate on the floating boom and the grid between the floating boom and the control gate;
Step S103:Oxidation processes are carried out in the side of the grid of the logical device and the gate structure of the flash memory Oxide skin(coating) is formed with top surface;
Step S104:The offset side-wall material layer for forming the covering semiconductor substrate and the oxide skin(coating), to described Flash cell area carries out LDD processing, performs etching the offset side-wall material layer with the two of the grid of the logical device The both sides of the gate structure of side and the flash memory form offset side wall layer;
Step S105:LDD processing is carried out to the logic device area;
Step S106:It is formed and covers the semiconductor substrate, the gate structure of the flash memory and the logical device The side-wall material layer of grid carries out ion implanting to form the source electrode and drain electrode of flash memory in the flash cell area, to the side The wall material bed of material is performed etching to form side in the both sides of the grid of the logical device and the both sides of the gate structure of the flash memory Parietal layer.
Embodiment two
The embodiment of the present invention provides a kind of electronic device comprising electronic building brick and what is be connected with the electronic building brick partly lead Body device.Wherein, which is the semiconductor of the manufacturing method manufacture of the semiconductor devices according to embodiment one Device.The electronic building brick can be any suitable component, such as storage control etc..
The electronic device of the present embodiment can be mobile phone, tablet computer, laptop, net book, game machine, TV Any electronic product such as machine, VCD, DVD, navigator, camera, video camera, recording pen, MP3, MP4, PSP or equipment, or Any intermediate products for including the semiconductor devices.
The electronic device of the embodiment of the present invention, due to the use of according to semiconductor devices made from the above method, thus it is same Sample has the advantages that above-mentioned.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to The purpose of citing and explanation, and be not intended to limit the invention within the scope of described embodiment.In addition people in the art It is understood that the invention is not limited in above-described embodiment, introduction according to the present invention can also be made more kinds of member Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by The appended claims and its equivalent scope are defined.

Claims (10)

1. a kind of manufacturing method of semiconductor devices, which is characterized in that the method includes:
Step S101:Offer includes the semiconductor substrate of flash cell area and logic device area, on the semiconductor substrate shape At gate material layers, the gate material layers are performed etching to form the grid of the logical device positioned at the logic device area Pole;
Step S102:The gate structure of flash memory is formed in the flash cell area, wherein the gate structure includes floating boom, is located at Dielectric layer between control gate on the floating boom and the grid between the floating boom and the control gate;
Step S103:Oxidation processes are carried out in the side and top of the grid of the logical device and the gate structure of the flash memory Face forms oxide skin(coating);
Step S104:It is initially formed the offset side-wall material layer of the covering semiconductor substrate and the oxide skin(coating), then to described Flash cell area carries out LDD processing, then performs etching the offset side-wall material layer in the grid of the logical device Both sides and the flash memory gate structure both sides formed offset side wall layer;
Step S105:LDD processing is carried out to the logic device area;
Step S106:It is initially formed the covering semiconductor substrate, the gate structure of the flash memory and the grid of the logical device The side-wall material layer of pole, then ion implanting is carried out to form the source electrode and drain electrode of flash memory in the flash cell area, then to institute Side-wall material layer is stated to perform etching in the both sides shape of the both sides of the grid of the logical device and the gate structure of the flash memory At side wall layer.
2. the manufacturing method of semiconductor devices as described in claim 1, which is characterized in that in the step S101, to institute It states gate material layers and performs etching and include with the grid for forming the logical device positioned at the logic device area:
The patterned mask in the region where the grid of the quasi- logical device formed of covering is formed in the gate material layers Layer;
The gate material layers are performed etching to form the grid of logical device.
3. the manufacturing method of semiconductor devices as claimed in claim 2, which is characterized in that described in the step S101 Mask layer includes photoresist, ranging from 55~65nm of the critical size of the line width of the mask layer, figure in the mask layer Spacing critical size ranging from 115~125nm.
4. the manufacturing method of semiconductor devices as claimed in claim 3, which is characterized in that described in the step S101 The critical size of the line width of mask layer is 60nm, and the critical size of the spacing of the mask layer is 120nm.
5. the manufacturing method of semiconductor devices as described in claim 1, which is characterized in that described in the step S103 The thickness of oxide skin(coating) is
6. the manufacturing method of semiconductor devices as described in claim 1, which is characterized in that described in the step S104 The material for deviating side-wall material layer includes silicon nitride, and the thickness of the offset side-wall material layer is
7. the manufacturing method of semiconductor devices as described in claim 1, which is characterized in that described in the step S106 Side-wall material layer is silicon oxide layer or the composite layer being made of silica, silicon nitride, silica, the thickness of the side-wall material layer For
8. the manufacturing method of semiconductor devices as described in any one of claim 1 to 7, which is characterized in that in the step Further include step S107 after S106:Ion implanting is carried out to form source electrode and the leakage of logical device in the logic device area Pole.
9. the manufacturing method of semiconductor devices as claimed in claim 8, which is characterized in that in the step S101, in shape At the step of the gate material layers and formed logical device grid the step of between further include following steps:
The gate material layers are carried out with the pre-doping processing of the high tension apparatus of flash area;
The gate material layers are carried out with the ion implanting of the local device of logic region.
10. a kind of electronic device, which is characterized in that the semiconductor devices being connected including electronic building brick and with the electronic building brick, The wherein described semiconductor devices is prepared using the manufacturing method of claim 1 to 9 any one of them semiconductor devices.
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102222645A (en) * 2010-04-15 2011-10-19 联华电子股份有限公司 Method for making flash memory element
CN102254867A (en) * 2010-05-21 2011-11-23 华邦电子股份有限公司 Flash memory manufacturing method

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102222645A (en) * 2010-04-15 2011-10-19 联华电子股份有限公司 Method for making flash memory element
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