CN105571749B - Pressure sensor forming method - Google Patents

Pressure sensor forming method Download PDF

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Publication number
CN105571749B
CN105571749B CN201410545227.4A CN201410545227A CN105571749B CN 105571749 B CN105571749 B CN 105571749B CN 201410545227 A CN201410545227 A CN 201410545227A CN 105571749 B CN105571749 B CN 105571749B
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China
Prior art keywords
layer
pressure sensor
groove
piezo
sensor forming
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CN201410545227.4A
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Chinese (zh)
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CN105571749A (en
Inventor
郭亮良
郑超
刘国安
刘煊杰
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中芯国际集成电路制造(上海)有限公司
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Publication of CN105571749A publication Critical patent/CN105571749A/en
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Publication of CN105571749B publication Critical patent/CN105571749B/en

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Abstract

The present invention provides a kind of pressure sensor forming method, including:First semiconductor substrate is provided;It forms the insulating layer for covering first semiconductor substrate surface and covers the substrate layer of the surface of insulating layer;The device layer for covering the substrate layer surface is formed, piezo-resistive arrangement is formed in the device layer;Form the dielectric layer for covering the device layer;The protective layer for covering the dielectric layer surface is formed, bonding pad is formed in the protective layer;The first groove through the protective layer and dielectric layer is formed, the first groove exposes piezo-resistive arrangement part surface;The second semiconductor substrate with connection surface is provided, the connection surface is formed with second groove;Bonding connects the bonding pad and connection surface, forms cavity;The first semiconductor substrate is removed, insulating layer is exposed.The method can reduce the production cost of pressure sensor.

Description

Pressure sensor forming method
Technical field
The present invention relates to field of semiconductor manufacture, more particularly to a kind of pressure sensor forming method.
Background technology
Pressure sensor is developed based on MEMS (Micro Electro Mechanical System, MEMS) The microdevice to get up is a kind of sensor the most commonly used in industrial practice, instrument and meter control, is also widely used for each The industrial automatic control environment of kind is related to water conservancy and hydropower, railway traffic, production automatic control, aerospace, military project, petrochemical industry, oil well, electric power, ship Numerous industries such as oceangoing ship, lathe, pipeline.It collect microsensor, actuator and signal processing and control circuit, interface circuit, Communication and power supply are in one, and based on semiconductor fabrication, manufacturing process is compatible with integrated circuit technique.Pressure sensor Type it is various, such as resistance strain gage pressure sensor, semiconductor gauge pressure sensor, piezoresistive pressure sensor, electricity Sense formula pressure sensor, capacitance pressure transducer, resonance type pressure sensor and capacitance acceleration transducer etc..
Piezoresistive pressure sensor has high-precision and preferable linear characteristic, in the use of pressure sensor again Favored.In general, piezoresistive pressure sensor has the film of deflection, the cavity of deflection space is provided for the film, works as institute Film deflection deformation can be led to by stating when film experiences external pressure variation, the resistivity of thin-film material be changed, so as to pass through The resistance variations for measuring film, linear relationship is established with external pressure.The pressure sensor has higher quality requirement to cavity, leads to Frequently with cavity-silicon-on-insulator as substrate, there is a problem that with high costs.
Invention content
Problems solved by the invention is, by providing a kind of forming method of pressure sensor, to reduce manufacturing cost, simultaneously Meet device quality requirement.
To solve the above problems, the present invention provides a kind of pressure sensor forming methods, including:First semiconductor is provided Substrate;It forms the insulating layer for covering first semiconductor substrate surface and covers the substrate layer of the surface of insulating layer;It is formed The device layer of the substrate layer surface is covered, piezo-resistive arrangement is formed in the device layer;Form Jie for covering the device layer Matter layer;Form the protective layer for covering the dielectric layer surface, be formed with bonding pad in the protective layer, the bonding pad top surface with Protective layer flushes, and projection of the bonding pad on device layer is located at piezo-resistive arrangement peripheral position;It is formed and runs through the protection The first groove of layer and dielectric layer, the first groove expose piezo-resistive arrangement part surface;The with connection surface is provided Two semiconductor substrates, the connection surface are formed with second groove, and the second groove position is corresponding with first groove position;Key It closes and connects the bonding pad and connection surface, form cavity;The first semiconductor substrate is removed, insulating layer is exposed.
Optionally, the insulating layer is silica, and thickness is 1 micron~5 microns.
Optionally, the substrate layer is silicon or germanium, and the technique for forming the substrate layer is epitaxial growth, and technological temperature is 500 DEG C~800 DEG C, air pressure is the support of 1 support~100, and reaction gas is silicon source gas SiH4Or SiH2Cl2Or ge source gas GeH4, the flow of the silicon source gas or ge source gas is that 1 mark condition milliliter every point~1000 marks every point of condition milliliter.
Optionally, the transistor positioned at piezo-resistive arrangement peripheral position is also formed in the device layer.
Optionally, be formed with interconnection structure in the dielectric layer, the interconnection structure through dielectric layer and with the pressure drag Structure is connected with transistor, and the interconnection structure being connect with piezo-resistive arrangement is located at piezo-resistive arrangement fringe region.
Optionally, the protective layer be thickness 100nm~5000nm insulating materials, the insulating materials be silica, The low k material of silicon nitride, silicon oxynitride, silicon oxide carbide or dielectric constant 2.0~4.0.
Optionally, the material of the bonding pad is metallic copper, aluminium, nickel etc., is suitable for the connection table with the second semiconductor substrate Face bonding connection.
Optionally, the technique for forming the first groove is dry etching, and the etching gas of the dry etching includes CF4、CH3F、CH2F2、CHF3、SF6、NF3、SO2、H2、O2、N2, it is one or more of in Ar and He, the flow of etching gas is 50 marks Every point of condition milliliter is marked in every point of condition milliliter~600, and bias is 100V~500V, and power is 200W~600W, and temperature is 40 DEG C~70 ℃。
Optionally, the sectional width of the first groove is less than the sectional width of piezo-resistive arrangement, a side of first groove The horizontal distance of edge one side edge corresponding with piezo-resistive arrangement is 200nm~2000nm, suitable for avoiding to being connected to piezo-resistive arrangement side The interconnection structure of edge causes to damage.
Optionally, the technique for forming the second groove is dry etching, and the etching gas of the dry etching includes HBr、Cl2、SF6、NF3、O2、Ar、He、CH2F2And CHF3The flow of middle one or more, etching gas is 50 every point of mark condition milliliters ~500 every point of mark condition milliliters, bias are 100V~650V, and power is 200W~600W, and temperature is 40 DEG C~70 DEG C.
Optionally, the depth of the second groove is 500nm~10000nm, and the sectional width of second groove is more than first The sectional width of groove.
Optionally, the bonding Joining Technology of the bonding pad and connection surface is that metal is diffusion interlinked, bonding temperature 300 DEG C~400 DEG C, while 5,000 Ns~100,000 Ns of pressure is applied to the second semiconductor substrate.
Optionally, the metal is diffusion interlinked completes under vacuum conditions, is vacuum in the cavity.
Optionally, the technique of the first semiconductor substrate of the removal is that chemically mechanical polishing, wet etching or dry method are carved Erosion.
Optionally, first semiconductor substrate is silicon substrate or germanium substrate, and the first semiconductor substrate is not adulterated, is suitable for Physical support is provided for insulating layer, substrate layer, device layer.
Optionally, the material of the dielectric layer is the low k material or dielectric constant of dielectric constant 2.0~4.0<2.0 Ultra low k material.
Optionally, the material of the interconnection structure be copper, aluminium, nickel either tungsten formation process be physical vapour deposition (PVD) or Electrochemical deposition.
Optionally, the top dimension of the interconnection structure section is more than bottom size.
Optionally, the top dimension of the first groove section greater than, equal to or be less than bottom size.
Compared with prior art, technical scheme of the present invention has the following advantages:
In pressure sensor forming method provided by the invention, sequentially formed in the first semiconductor substrate insulating layer and Substrate layer, then the device layer comprising piezo-resistive arrangement and several transistors is formed on substrate layer, and covering device layer sequentially forms Dielectric layer and protective layer.Form the epitaxial growth that the substrate layer uses, technical maturity, manufacturing cost are cheap, acquisition it is exhausted Edge layer and substrate layer also disclosure satisfy that the requirement of device layer, in the case where not sacrificing device function, greatly save Production cost.
Further, in technical solution of the present invention, is formed above piezo-resistive arrangement by etch-protecting layer and dielectric layer One groove, the first groove form cavity with subsequent second groove after being bonded connection, and the cavity can be pressure drag knot Structure is acted on by external pressure and bends and provide activity space, compared with cavity-silicon-on-insulator, can make device obtain identical function and Effect, and the process costs of the cavity are formed than directly being substantially reduced using the cost of cavity-silicon-on-insulator.
Further, in technical solution of the present invention, by removing the first semiconductor substrate to expose insulating layer, with cavity The corresponding partial insulative layer in position, portions of substrate layer and part thereof structure form flexible films, the formation deflection The process of film is simple, and manufacturing cost is low.
Description of the drawings
Fig. 1 is the cross-sectional view of the pressure sensor of one embodiment of the invention;
Fig. 2 to Fig. 9 is the cross-sectional view of the pressure sensor forming method process of another embodiment of the present invention.
Specific implementation mode
By background technology it is found that in the prior art, pressure sensor has higher quality requirement, generally use to cavity Cavity-silicon-on-insulator be there is a problem that with high costs as substrate.
In order to further illustrate the present invention provides the embodiments of a pressure sensor structure, referring to FIG. 1, including:
Basal layer 10,10 surface of the basal layer are formed with cavity 13, and 13 top surface of the cavity and 10 surface of basal layer are neat It is flat;
Insulating layer 11 positioned at 10 surface of the basal layer;
Device layer 12 positioned at 11 surface of the insulating layer is formed with piezo-resistive arrangement 14 in the device layer 12 and is located at institute The transistor 15 of 14 peripheral position of piezo-resistive arrangement is stated, the piezo-resistive arrangement 14 is located at 13 top of cavity;
Dielectric layer 18 positioned at 12 surface of the device layer, be formed through in the dielectric layer 18 dielectric layer 18 and with pressure Hinder the interconnection structure 16 of structure 14 and the connection of transistor 15;
Groove 17 in the dielectric layer 18, the groove 17 is located at 14 top of piezo-resistive arrangement, and exposes device 12 part surface of layer.
The basal layer 10 is silicon substrate or germanium substrate, is suitable for subsequent insulating layer 11 and device layer 12 provides physics Support.It is airtight vacuum in the cavity 13.
The insulating layer 11 is silica, suitable for making subsequent device layer 12 generate raceway groove depletion effect, while being subsequent Piezo-resistive arrangement 14 provides physical support, it is made to be unlikely to be broken when being acted on deflection deformation by external pressure.
The piezo-resistive arrangement 14 can be bent under external pressure, and resistivity and resistance value also will produce variation, be led to The case where relationship changed with external pressure can be set up, obtain external pressure variation indirectly by crossing the variation of measurement resistance value.
The transistor 15 is worked together with piezo-resistive arrangement 14 to form the pressure sensitive device of complex function, wherein crystal Pipe 15 can be the control circuit of piezo-resistive arrangement 14, or the input of piezo-resistive arrangement 14, output and storage circuit simultaneously are completed to transport It calculates, or power amplifying device is suitable for optimizing the output signal of piezo-resistive arrangement 14.
16 top surface of the interconnection structure is flushed with 18 surface of dielectric layer, and interconnection structure 16 is that transistor 15 provides electric signal simultaneously Feedback signal is received to complete device function, while being also that piezo-resistive arrangement 14 provides electric signal to measure resistance.With piezo-resistive arrangement The interconnection structure 16 of 14 connections is located at piezo-resistive arrangement fringe region.
Partial insulative layer 11 corresponding with 13 position of cavity and part thereof structure 14 form pressure sensor structure Flexible films.The flexible films can be bent under the action of external pressure so that the piezo-resistive arrangement in flexible films 14 also bend, and to change the resistance value of piezo-resistive arrangement 14, the variation by measuring its resistance value can obtain corresponding outer The variation of pressure.
Above-described embodiment is carried out the study found that when forming the pressure sensor, 10 surface of covering basal layer is formed absolutely The method of edge layer 11 is mostly physical vapour deposition (PVD) or chemical vapor deposition, in the insulating layer formed with 13 corresponding position of cavity 11 poor flatness, thickness uniformity is low, or even the collapse-deformation being easy to happen into cavity 13, causes the pressure drag knot being subsequently formed Structure poor flatness, the uniformity are low or even fail.The collapse-deformation also greatly reduces the volume of cavity 13 simultaneously, is unfavorable for pressing The flexure activity for hindering structure, reduces the accuracy of device induction pressure.It is exhausted in order to obtain that flatness is good, thickness uniformity is high Edge layer 11 and piezo-resistive arrangement 14 mostly use silicon-on-insulator to manufacture the pressure sensor at present.The silicon-on-insulator one As be divided into three layers, including substrate silicon layer, the substrate silicon positioned at the silicon oxide layer of substrate silicon surface and positioned at silicon oxide layer surface Layer, wherein substrate silicon layer can be as the insulating layers 11 in Fig. 1, in substrate as the basal layer 10 in Fig. 1, silicon oxide layer Silicon surface can form transistor and piezo-resistive arrangement and further obtain the device layer 12 in Fig. 1.In practical applications, a kind of Method is to use cavity-silicon-on-insulator, the cavity-silicon-on-insulator advance shape between substrate silicon layer and silicon oxide layer At cavity, it only need to manufacture device layer in substrate silicon layer surface corresponding region and complete subsequent technique.But the cavity-is exhausted The cost of silicon is too high on edge body, and the parameters such as preformed empty cavity position, size, depth are that manufacturer provides, and be cannot be satisfied Changeable chip design requirement, there is significant limitation in practical applications.Another method is to provide general wafer and at it Surface forms required groove;Silicon-on-insulator wafer is provided again, it is carried out back thinning to remove substrate silicon layer and exposure Silicon oxide layer;It connects the general wafer and forms fluted surface and the silicon oxide layer surface of silicon-on-insulator, obtain required Cavity.But the conventional silicon-on-insulator cost in the method is also relatively high, and the stability of Joining Technology is not high and is easy There is defect and flaw, device can be adversely affected.
To solve the above problems, the present invention provides a kind of embodiment of pressure sensor forming method, led the first half Insulating layer and substrate layer are sequentially formed in body substrate, then the device comprising piezo-resistive arrangement and several transistors is formed on substrate layer Part layer, and covering device layer sequentially forms dielectric layer and protective layer.Form the epitaxial growth that the substrate layer uses, technique at It is ripe, manufacturing cost is cheap, the insulating layer and substrate layer of acquisition also disclosure satisfy that the use demand of device layer, to not sacrificing device In the case of part function, production cost is greatly saved.Is formed above piezo-resistive arrangement by etch-protecting layer and dielectric layer One groove, the first groove form cavity with subsequent second groove after being bonded connection, and the cavity can be pressure drag knot Structure is acted on by external pressure and bends and provide activity space, compared with cavity-silicon-on-insulator, can make device obtain identical function and Effect, and the process costs for forming the cavity are substantially reduced than directly buying the cost of cavity-silicon-on-insulator.And by going Except the first semiconductor substrate is to expose insulating layer, partial insulative layer corresponding with empty cavity position, portions of substrate layer and part are pressed Resistance structure forms flexible films, and the process for forming flexible films is simple, and manufacturing cost is low.
It is understandable to enable the above objects, features, and advantages of this method to become apparent, below in conjunction with the accompanying drawings to this method Specific implementation mode be described in detail.When describing the embodiments of the present invention, for purposes of illustration only, schematic diagram can disobey general ratio Example makees partial enlargement, and the schematic diagram is example, should not be limited the scope of the invention herein.In addition, in reality Border make in should include length, width and depth three-dimensional space.
With reference to figure 2, the first semiconductor substrate 100 is provided.
First semiconductor substrate 100 is silicon substrate or germanium substrate, and the first semiconductor substrate 100 is not adulterated, is suitable for Physical support is provided for insulating layer 101, substrate layer 100a, device layer 102 and subsequent technique.
With continued reference to FIG. 2, being formed described in the insulating layer 101 for covering 100 surface of the first semiconductor substrate and covering The substrate layer 100a on 101 surface of insulating layer.
The insulating layer 101 is silica, and thickness is 1 micron~5 microns, and 101 technique of insulating layer for forming silica is Thermal oxide, physical vapour deposition (PVD) or atomic layer deposition.
The insulating layer 101 is suitable for isolating device layer 102 and generates raceway groove depletion effect, and fine and close silica material can be more Good raising device performance, in the present embodiment, in case of insulating layer 101 is dense oxide silicon, presenting a demonstration property explanation. As one embodiment, 101 formation process of insulating layer of the dense oxide silicon is atomic layer deposition.The atomic layer deposition packet Include following steps:A, SiCl is passed through into reaction chamber4Gas deposits one layer of SiCl on 100 surface of the first semiconductor substrate4Afterwards, it takes out Fall the remaining SiCl in reaction chamber4Gas;B, it is passed through vapor into reaction chamber, is formed with 100 surface of the first semiconductor substrate SiCl4After reaction generates one layer of silica, the residual water vapor in reaction chamber is taken out;N times cycle is carried out to step A and B, N is Integer more than 1, until obtaining 1 micron~5 microns of insulating layer of silicon oxide 101.The silica that the atomic layer deposition is formed Insulating layer 101, finer and close, lattice parameter and silicon crystal lattices compared with the silica of the methods of physical vapour deposition (PVD) deposition The lattice mismatch smaller of parameter, is conducive to subsequently epitaxial growing crystalline silicon, and insulating layer 101 is also the branch of piezo-resistive arrangement 104 simultaneously Layer is supportted, piezo-resistive arrangement 104 can be avoided to be broken in flexure.
The thickness of insulating layer uses 1 micron~5 microns, if thickness is too thin, does not have not only and is effectively isolated device layer 102 effect can not also provide piezo-resistive arrangement 104 enough support forces;If thickness is too thick, although device can be effectively isolated Part layer 102, but the deflection deformation of piezo-resistive arrangement 104 can be hindered, cause device sensitivity to decline.
The substrate layer 100a is crystalline silicon, and as one embodiment, the substrate layer 100a can be by insulating layer 101 surface epitaxial growth crystal silicon are formed, the epitaxial growth technology of the substrate layer 100a for forming crystalline silicon, technological temperature It it is 500 DEG C~800 DEG C, air pressure is the support of 1 support~100, and reaction gas is silicon source gas SiH4Or SiH2Cl2, the silicon source gas Flow is that 1 mark condition milliliter every point~1000 marks every point of condition milliliter.The method of the epitaxial growth, can be in the atomic layer deposition Obtained 101 surface of insulating layer of silicon oxide grows to obtain required crystalline silicon substrate layer 100a, the crystalline silicon substrate layer 100a It disclosure satisfy that the follow-up requirement for preparing transistor device.It should be noted that in the interface of insulating layer 101 and substrate layer 100a Can nearby there be the transition zone of certain thickness silica-crystalline silicon, but the transition zone exists only in insulating layer 101 and lining Near the interface of bottom 100a, do not influence that transistor device is prepared using substrate layer 100a.
The insulating layer 101 and substrate layer 100a formed using the present embodiment method, it is of low cost compared with silicon-on-insulator, Insulating layer 101 and substrate layer 100a also disclosure satisfy that the requirement of subsequent device layer 102 simultaneously, to not sacrifice device work( In the case of energy, production cost is greatly saved.
With continued reference to FIG. 2, the device layer 102 for covering the surfaces the substrate layer 100a is formed, shape in the device layer 102 At there is piezo-resistive arrangement.
The transistor positioned at 104 peripheral position of the piezo-resistive arrangement can also be formed in the device layer 102, in this reality It applies in example, in case of device layer 102 includes the piezo-resistive arrangement 104 and transistor 103, presenting a demonstration property explanation please join Examine Fig. 2.
The piezo-resistive arrangement 104 includes the pressure positioned at the separation layer on the surfaces substrate layer 100a and positioned at the insulation surface Resistance layer, the separation layer and piezoresistance layer are simultaneously not shown in FIG. 2.
The insolated layer materials can be silicon nitride, silica, silicon oxynitride or silicon oxide carbide, and separation layer is suitable for isolation Piezoresistance layer and substrate layer 100a avoid substrate layer 100a from influencing the resistance value of pressure drag layer material.The pressure drag layer material is polycrystalline Silicon, the technique for forming the piezoresistance layer are epitaxial growth.When piezo-resistive arrangement 104 is by external pressure deflection deformation, the piezoresistance layer Deflection deformation therewith, the resistivity and resistance value of piezoresistance layer can all change, and the variation by measuring resistance value can establish The case where playing the relationship changed with external pressure, obtaining external pressure variation indirectly.
The step of forming the device layer 102 include:Transistor 103 and piezo-resistive arrangement are formed on the surfaces substrate layer 100a 104;Formed covering substrate layer 100a surfaces, transistor 103 and piezo-resistive arrangement 104 device medium layer, the device medium layer It is not shown in FIG. 2;Chemically mechanical polishing is carried out to the device medium layer until exposing transistor 103 and piezo-resistive arrangement 104 surfaces.The device medium layer is silica material, and formation process is chemical vapor deposition, physical vapour deposition (PVD) or original Sublayer deposits.
The transistor 103 is worked together with piezo-resistive arrangement 104 to form the pressure sensitive device of complex function, wherein brilliant Body pipe 103 can be as the control circuit of piezo-resistive arrangement 104, or 104 input and output signal of piezo-resistive arrangement, storage letter It ceases and completes some simple operations, while being also used as power amplifying device etc. to optimize the output letter of piezo-resistive arrangement 104 Number.
With reference to figure 3, the dielectric layer 106 for covering the device layer 102 is formed.
Interconnection structure can also be formed in the dielectric layer 106, in the present embodiment, to be formed in dielectric layer 106 In case of interconnection structure 105, presenting a demonstration property explanation.The interconnection structure 105 runs through dielectric layer 106 and and piezo-resistive arrangement 104 and transistor 103 connect, the interconnection structure 105 being connect with piezo-resistive arrangement 104 is located at piezo-resistive arrangement fringe region.
The material of the dielectric layer 106 is the low k material or dielectric constant of dielectric constant 2.0~4.0<2.0 ultralow k It is worth material, as one embodiment, the low k material of the dielectric constant 2.0~4.0 is organic polymer, amorphous chlorination Carbon, the Silicon On Insulator comprising organic polymer, the Si oxide for being doped with carbon or the Si oxide for being doped with chlorine.
The material of the interconnection structure 105 is that either tungsten formation process is physical vapour deposition (PVD) or electrification for copper, aluminium, nickel Learn deposition.
The interconnection structure 105 being connect with piezo-resistive arrangement 104 is located at the fringe region of piezo-resistive arrangement 104, and connection position Set also at the edge of piezo-resistive arrangement 104, the Edge Distance of link position side corresponding with piezo-resistive arrangement 104 be 100nm~ 1000nm.The position distribution of the interconnection structure 105 is to reserve the upper dielectric layer of 104 central area of piezo-resistive arrangement 106, rear extended meeting forms groove in the top of 104 central area of piezo-resistive arrangement and exposes 104 part surface of piezo-resistive arrangement.With pressure The interconnection structure 105 that resistance structure 104 connects, link position one side edge distance 100nm corresponding with piezo-resistive arrangement 104~ 1000nm, it is therefore an objective to ensure that interconnection structure 105 of this part can be stably connected with piezo-resistive arrangement 104, not occur position inclined Difference, to reduce the unnecessary fluctuation for 104 resistance value of piezo-resistive arrangement measured.
In the present embodiment, the top dimension of 105 section of the interconnection structure is more than bottom size, the reason is that:Interconnection Structure 105 needs accurately to connect each transistor 103 and piezo-resistive arrangement 104, while to avoid generating big parasitic capacitance, Therefore the section bottom size of interconnection structure 105 is smaller;And after transistor 103 and piezo-resistive arrangement 104 are connected to upper layer, this The parasitic capacitance at place will not generate device big influence, while continue to connect for the ease of subsequent technique, therefore mutually connection The profile top size of structure 105 is larger.In the present embodiment, as lower section rectangle and it is located at using the section shape of interconnection structure 105 Presenting a demonstration property of the case where top rectangle stacked combination on the rectangle of lower section forms illustrates, wherein the sectional width of top rectangle is more than The sectional width of lower section rectangle.
As one embodiment, the step of forming the interconnection structure 105, includes:Shape is etched in the dielectric layer 106 At shallow interconnection structure groove;Continue to etch the shallow interconnection structure groove, forms deep interconnection structure groove, the depth interconnection structure Trench profile size is less than shallow interconnection structure trench profile size, and deep interconnection structure groove exposes 104 part of piezo-resistive arrangement 103 part surface of surface or transistor;Form the mutual connection of the filling full shallow interconnection structure groove and deep interconnection structure groove Structure 105.The shallow interconnection structure groove and deep interconnection structure groove are not shown in FIG. 3.It is described to form shallow interconnection structure groove And the lithographic method of deep interconnection structure groove is dry etching, etching gas includes CF4、CH3F、CH2F2、CHF3、SF6、NF3、 SO2、H2、O2、N2, it is one or more of in Ar and He, it is every that the flow of etching gas is that 10 mark condition milliliters every point~400 mark condition milliliter Point, bias is 50V~500V, and power is 100W~600W, and temperature is 30 DEG C~70 DEG C.
With reference to figure 4, the protective layer 107 for covering 106 surface of dielectric layer is formed, the company of being formed in the protective layer 107 Area 108 is met, 108 top surface of the bonding pad is flushed with 107 surface of protective layer, and projection position of the bonding pad 108 on device layer 102 In 104 peripheral position of piezo-resistive arrangement.
The protective layer 107 is the insulating materials of thickness 100nm~5000nm, and the insulating materials is silica, nitridation The low k material of silicon, silicon oxynitride, silicon oxide carbide or dielectric constant 2.0~4.0, in the present embodiment, with protective layer 107 In case of material is the low k material of dielectric constant 2.0~4.0, presenting a demonstration property explanation.It is described as one embodiment Low k material is organic polymer, amorphous chlorination carbon, the Silicon On Insulator comprising organic polymer, the silica for being doped with carbon Compound or the Si oxide for being doped with chlorine.
The material of the bonding pad 108 is metallic copper, aluminium, nickel etc., is suitable for and the bonding of subsequent second semiconductor substrate connects It connects, in the present embodiment, presenting a demonstration property explanation the case where using the material of bonding pad 108 as aluminium.
The step of forming the bonding pad 108 include:Dry etching forms bonding pad groove in protective layer 107;Deposition Metallic aluminium is until the full bonding pad groove of filling.The technique of the deposited metal aluminium is physical vapour deposition (PVD), electrochemical deposition Or atomic layer deposition.
Projection of the bonding pad 108 on device layer 102 is located at 104 peripheral position of piezo-resistive arrangement, its purpose is to It avoids being covered in 104 top of piezo-resistive arrangement, first groove is formed subsequently above piezo-resistive arrangement 104 to hinder.
With reference to figure 5, the first groove 109 through the protective layer 107 and dielectric layer 106, the first groove 109 are formed Expose 104 part surface of piezo-resistive arrangement.
The sectional width of the first groove 109 is less than the sectional width of piezo-resistive arrangement 104, the first groove 109 The horizontal distance of one side edge one side edge corresponding with piezo-resistive arrangement 104 is 200nm~2000nm, suitable for avoiding to being connected to pressure The interconnection structure 105 at 104 edge of resistance structure causes to damage.
The top dimension of 109 section of first groove can greater than, equal to or be less than bottom size, in the present embodiment, Use the case where top dimension is equal to bottom size presenting a demonstration property explanation.The first groove 109 is suitable for subsequently with second Cavity is collectively formed in groove, therefore is not particularly limited to section shape.
The technique for forming the first groove 109 is dry etching, as one embodiment, the etching of the dry etching Gas includes CF4、CH3F、CH2F2、CHF3、SF6、NF3、SO2、H2、O2、N2, one or more of, the stream of etching gas in Ar and He Amount marks every point of condition milliliter for 50 mark condition milliliters every point~600, and bias is 100V~500V, and power is 200W~600W, and temperature is 40 DEG C~70 DEG C.
With reference to figure 6, the second semiconductor substrate 110 with connection surface 111 is provided, the connection surface 111 is formed with Second groove 112,112 position of the second groove are corresponding with 109 position of first groove.
Second semiconductor substrate 110 is silicon substrate or germanium substrate.
The depth of the second groove 112 is 500nm~10000nm, and the sectional width of second groove 112 is more than the first ditch The sectional width of slot 109 (please referring to Fig. 5).Cavity is collectively formed with first groove 109 in extended meeting after the second groove 112.
The technique for forming the second groove 112 is dry etching, the etching gas of the dry etching include HBr, Cl2、SF6、NF3、O2、Ar、He、CH2F2And CHF3Middle one or more, the flow of etching gas be 50 every point of mark condition milliliters~ 500 every point of mark condition milliliters, bias are 100V~650V, and power is 200W~600W, and temperature is 40 DEG C~70 DEG C.
With reference to figure 7, bonding connects the bonding pad 108 and connection surface 111, forms cavity 113.
It is vacuum in the cavity 113, is suitable for piezo-resistive arrangement 104 and is provided space by external pressure deflection deformation.
The technique of the bonding connection is diffusion interlinked metal, thermocompression bonding or metal melting bonding, in the present embodiment In, illustrated with diffusion interlinked the presenting a demonstration property of metal, the diffusion interlinked bonding Joining Technology of the metal, bonding temperature is 300 DEG C ~400 DEG C, while applying 5,000 Ns~100,000 Ns of pressure to the second semiconductor substrate 110, the pressure is directed toward connection surface 111.Under the described conditions, the aluminium atom in articulamentum 108 diffuses into 110 connection surface of the second semiconductor substrate, forms silicon- Aluminium transition zone, the transition zone can securely connect bonding pad 108 and connection surface 111, and have good air-tightness.Key It closes connection procedure to complete under vacuum conditions, is vacuum in the cavity 113 of formation.
With reference to figure 8, the first semiconductor substrate 100 is removed, insulating layer 101 is exposed.
The technique for removing the first semiconductor substrate 100 can be chemically mechanical polishing, wet etching or dry etching, In the present embodiment, the first semiconductor substrate 100 is ground using chemically mechanical polishing, until exposing insulating layer 101.
Partial insulative layer 101 corresponding with 113 position of cavity, portions of substrate layer 100a and part thereof structure 104 are constituted Under external pressure P effects deflection deformation, the piezoresistance layer in piezo-resistive arrangement 104 can occur for flexible films, the flexible films Also deflection deformation occurs, causes the resistivity and resistance change of piezoresistance layer, by measuring the variation of the resistance value, energy Linear relationship is set up in the variation of enough and external pressure, to obtain the pressure value of external pressure.
The cavity 113 of the formation can make device obtain identical function and effect compared with cavity-silicon-on-insulator, And the process costs for forming the cavity 113 are substantially reduced than directly buying the cost of cavity-silicon-on-insulator.
It further comprises to be formed through insulating layer after exposing insulating layer 101 removing the first semiconductor substrate 100 101, substrate layer 100a, device layer 102 and certain media layer 106, and what is connect with interconnection structure 105 masters pore structure 114, asks With reference to figure 9.Fig. 9 only depicts one and masters pore structure 114, in practice each interconnection structure as cross-sectional view 105 all corresponding pore structures of mastering are connected with each other, but are not shown in fig.9.
The material for mastering pore structure 114 and 105 material identical of interconnection structure can be copper, aluminium, nickel or tungsten, shape It is physical vapour deposition (PVD) or electrochemical deposition at technique.The deep via 114 is convenient for subsequently to transistor 103 and piezo-resistive arrangement 104 electrical connection.
To sum up, in pressure sensor forming method embodiment provided by the invention, the shape successively in the first semiconductor substrate At insulating layer and substrate layer, then the device layer comprising piezo-resistive arrangement and several transistors is formed on substrate layer, and decover Part layer sequentially forms dielectric layer and protective layer.The epitaxial growth that the substrate layer uses is formed, technical maturity, manufacturing cost are low Honest and clean, the insulating layer and substrate layer of acquisition also disclosure satisfy that the requirement of device layer, to the case where not sacrificing device function Under, production cost is greatly saved.Further, in the embodiment of the present invention, by etch-protecting layer and dielectric layer in pressure drag knot First groove is formed above structure, the first groove forms cavity, the cavity with subsequent second groove after being bonded connection It can be bent by external pressure effect for piezo-resistive arrangement and activity space is provided, compared with cavity-silicon-on-insulator, device can be made to obtain Identical function and effect, and the process costs of the cavity are formed than directly buying the cost of cavity-silicon-on-insulator significantly It reduces.Further, in the embodiment of the present invention, by removing the first semiconductor substrate to expose insulating layer, with empty cavity position Corresponding partial insulative layer, portions of substrate layer and part thereof structure form flexible films, the formation flexible films Process it is simple, manufacturing cost is low.
Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute Subject to the range of restriction.

Claims (19)

1. a kind of pressure sensor forming method, which is characterized in that including:
First semiconductor substrate is provided;
It forms the insulating layer for covering first semiconductor substrate surface and covers the substrate layer of the surface of insulating layer;
The device layer for covering the substrate layer surface is formed, piezo-resistive arrangement is formed in the device layer;
Form the dielectric layer for covering the device layer;
Form the protective layer for covering the dielectric layer surface, be formed with bonding pad in the protective layer, the bonding pad top surface with Protective layer flushes, and projection of the bonding pad on device layer is located at piezo-resistive arrangement peripheral position;
The first groove through the protective layer and dielectric layer is formed, the first groove exposes piezo-resistive arrangement part surface;
The second semiconductor substrate with connection surface is provided, the connection surface is formed with second groove, the second groove Position is corresponding with first groove position;
Bonding connects the bonding pad and connection surface, forms cavity;
The first semiconductor substrate is removed, insulating layer is exposed.
2. pressure sensor forming method as described in claim 1, which is characterized in that the insulating layer is silica, thickness It is 1 micron~5 microns.
3. pressure sensor forming method as described in claim 1, which is characterized in that the substrate layer is silicon or germanium, shape Technique at the substrate layer is epitaxial growth, and technological temperature is 500 DEG C~800 DEG C, and air pressure is the support of 1 support~100, reaction gas For silicon source gas SiH4Or SiH2Cl2Or ge source gas GeH4, the flow of the silicon source gas or ge source gas is 1 mark condition Milliliter every point~1000 marks every point of condition milliliter.
4. pressure sensor forming method as described in claim 1, which is characterized in that be also formed with and be located in the device layer The transistor of piezo-resistive arrangement peripheral position.
5. pressure sensor forming method as described in claim 1, which is characterized in that be formed with mutual connection in the dielectric layer Structure, the interconnection structure is through dielectric layer and is connect with the piezo-resistive arrangement and transistor, the mutual connection being connect with piezo-resistive arrangement Structure is located at piezo-resistive arrangement fringe region.
6. pressure sensor forming method as described in claim 1, which is characterized in that the protective layer be thickness 100nm~ The insulating materials of 5000nm, the insulating materials are silica, silicon nitride, silicon oxynitride, silicon oxide carbide or dielectric constant 2.0 ~4.0 low k material.
7. pressure sensor forming method as claimed in claim 6, which is characterized in that the material of the bonding pad is metal Copper, aluminium, nickel, are suitable for and the bonding of the connection surface of the second semiconductor substrate connects.
8. pressure sensor forming method as described in claim 1, which is characterized in that the technique for forming the first groove is The etching gas of dry etching, the dry etching includes CF4、CH3F、CH2F2、CHF3、SF6、NF3、SO2、H2、O2、N2, Ar and One or more of in He, the flow of etching gas is that 50 mark condition milliliters every point~600 mark every point of condition milliliter, bias be 100V~ 500V, power are 200W~600W, and temperature is 40 DEG C~70 DEG C.
9. pressure sensor forming method as claimed in claim 8, which is characterized in that the sectional width of the first groove is small It is in the horizontal distance of the sectional width of piezo-resistive arrangement, the one side edge one side edge corresponding with piezo-resistive arrangement of first groove 200nm~2000nm causes to damage suitable for avoiding to the interconnection structure for being connected to piezo-resistive arrangement edge.
10. pressure sensor forming method as described in claim 1, which is characterized in that the technique for forming the second groove Etching gas for dry etching, the dry etching includes HBr, Cl2、SF6、NF3、O2、Ar、He、CH2F2And CHF3Middle one kind Or it is several, the flow of etching gas is that 50 mark condition milliliters every point~500 mark every point of condition milliliter, and bias is 100V~650V, power For 200W~600W, temperature is 40 DEG C~70 DEG C.
11. pressure sensor forming method as claimed in claim 10, which is characterized in that the depth of the second groove is 500nm~10000nm, the sectional width of second groove are more than the sectional width of first groove.
12. pressure sensor forming method as described in claim 1, which is characterized in that the bonding pad and connection surface It is that metal is diffusion interlinked to be bonded Joining Technology, and bonding temperature is 300 DEG C~400 DEG C, while applying 5,000 to the second semiconductor substrate The pressure of ox~100,000 N.
13. pressure sensor forming method as claimed in claim 12, which is characterized in that the metal is diffusion interlinked in vacuum It is completed under environment, is vacuum in the cavity.
14. pressure sensor forming method as described in claim 1, which is characterized in that the first semiconductor substrate of the removal Technique be chemically mechanical polishing, wet etching or dry etching.
15. pressure sensor forming method as described in claim 1, which is characterized in that first semiconductor substrate is silicon Substrate or germanium substrate, the first semiconductor substrate are not adulterated, and are suitable for insulating layer, substrate layer, device layer and are provided physical support.
16. pressure sensor forming method as described in claim 1, which is characterized in that the material of the dielectric layer is dielectric The low k material or dielectric constant of constant 2.0~4.0<2.0 ultra low k material.
17. pressure sensor forming method as claimed in claim 5, which is characterized in that the material of the interconnection structure be copper, Either tungsten formation process is physical vapour deposition (PVD) or electrochemical deposition for aluminium, nickel.
18. pressure sensor forming method as claimed in claim 17, which is characterized in that the top of the interconnection structure section Size is more than bottom size.
19. pressure sensor forming method as described in claim 1, which is characterized in that the top of the first groove section Size greater than, equal to or be less than bottom size.
CN201410545227.4A 2014-10-15 2014-10-15 Pressure sensor forming method CN105571749B (en)

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