CN105550075A - Method for realizing memory equipment redundancy - Google Patents

Method for realizing memory equipment redundancy Download PDF

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Publication number
CN105550075A
CN105550075A CN201510911785.2A CN201510911785A CN105550075A CN 105550075 A CN105550075 A CN 105550075A CN 201510911785 A CN201510911785 A CN 201510911785A CN 105550075 A CN105550075 A CN 105550075A
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CN
China
Prior art keywords
memory
cpu
method
system
cpus
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Application number
CN201510911785.2A
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Chinese (zh)
Inventor
刘元国
范致会
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浪潮电子信息产业股份有限公司
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Priority to CN201510911785.2A priority Critical patent/CN105550075A/en
Publication of CN105550075A publication Critical patent/CN105550075A/en

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Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16Error detection or correction of the data by redundancy in hardware
    • G06F11/1666Error detection or correction of the data by redundancy in hardware where the redundant component is memory or memory area

Abstract

The invention provides a method for realizing memory equipment redundancy. A memory is independently connected to two adjacent CPUs (Central Processing Unit) by a Memory controller to guarantee that paths between the two CPUs and the memory can be connected, and the memory automatically switches to the CPU with normal functions when one CPU is subjected to offline or other mistakes. Compared with the prior art, the method for realizing the memory equipment redundancy can improve the reliability and the fault tolerance of a multiprocessor server, and guarantees that the system automatically switches the corresponding memory under the failed CPU to other CPUs which normally work when certain one CPU is subjected to offline or other mistakes in the server system so as to guarantee that the memory can normally work. When the certain CPU fails, the system server switches the memory to other CPUs, and the memory under the failed CPU can normally work under the condition that the system is not shut down to improve the stability of the whole system. The method has the characteristics of being reasonable in design, simple in structure, convenient in use and the like.

Description

一种实现内存设备冗余的方法 A method for implementing redundancy in a memory device

技术领域 FIELD

[0001]本发明具体地说是一种实现内存设备冗余的方法。 [0001] The method of the present invention is a particular memory device to achieve redundancy.

背景技术 Background technique

[0002]现今服务器技术的发展对服务器的可维护性及服务器维护的简便性要求越来越高,目前的服务器,内存控制器集成在CPU内部,很多服务器并未使用对应CPU的所有内存资源,且系统已经可以支持CPU的online和off line功能,但当出现CPU off line状况时,offline CPU下的内存是不可用的,为了实现内存的冗余,通过本发明设计,可以实现内存工作的延续性。 [0002] Today the development of server technology increasingly high requirements for ease of maintainability server and server maintenance, the current server, integrated memory controller inside the CPU, many servers does not use all memory resources corresponding to the CPU, when CPU and the system has to support the online and off line functionality, but off line status occurs CPU, memory under Offline CPU is unavailable, in order to implement memory redundancy, by designing the present invention, may be implemented continuation of the work memory sex.

发明内容 SUMMARY

[0003]本发明的目的是克服现有技术中存在的不足,提供一种实现内存设备冗余的方法。 [0003] The object of the present invention is to overcome the disadvantages of the prior art, there is provided a method for implementing redundancy in a memory device.

[0004]本发明的技术方案是按以下方式实现的,Memory controller将内存分别连接到相邻的2个CPU上,保证内存到两个CPU的路径都是可连通的,当其中一个CPU出现off line或其他错误时,内存自带切换到功能正常的(PU上。 [0004] aspect of the present invention are achieved in the following manner, Memory controller memory is respectively connected to the two adjacent CPU, two memory to the CPU to ensure that the communication paths are available, wherein when a CPU appear off when the line or other error, the memory comes to the switch functioning (PU.

[0005] 上述内存固定在内存槽上,Memory controller将内存槽分别连接到相邻的2个CPU上,保证内存槽到两个CPU的路径都是可连通的。 [0005] The memory slot in the fixed memory, Memory controller memory slot are connected to two adjacent CPU, memory slots to ensure that the two paths are available CPU communication.

[0006] 系统中将内存设备通过Memory controlIer分别连接到CPUO和CPUl,系统通过FPGA/CPLD来监控每个CPU的状态,通过监控到CPU状态结果来控制Memory controlIerPort连接状态; [0006] System memory device will be respectively connected by the Memory controlIer CPUO and CPUl, each CPU to monitor the system by the FPGA / CPLD state to the connected state by controlling Memory controlIerPort state monitoring results to the CPU;

当CPUO工作正常时,FPGA/CPLD将Memory control Ier连接设置在PortO,内存通过Por t0连接到CPUO,此时Por 11为关闭状态; When the work CPUO, FPGA / CPLD the Memory control Ier connector disposed PortO, CPUO is connected to the memory through Por t0, Por 11 is closed at this time;

当CPUO出现off I ine或出现其他错误时,FPGA/CPLD监控CPUO出现故障,自动将Memorycontroller切换到Portl,内存通过Portl连接到CPUl,保证PCIE DEVICE正常工作。 Occurs when CPUO off I ine or other errors, FPGA / CPLD CPUO monitor fails to automatically switch Memorycontroller Portl, memory via Portl to CPUl, PCIE DEVICE ensure normal operation.

[0007]本发明的优点是: [0007] The advantage of the present invention are:

本发明的一种实现内存设备冗余的方法和现有技术相比,可提高多处理器服务器的可靠性、容错性,确保在服务器系统中某一个CPU出现of f I ine或者出现错误时,系统自动将出错CPU下对应的内存切换到其他工作正常的CPU下,保证内存可以正常工作。 One kind of a memory device of the present invention to achieve a method and redundancy compared to the prior art, improved reliability, fault-tolerant multiprocessor servers, to ensure that one of CPU occurs when f I ine or errors in the server system, the system will automatically lower the error corresponding to the other CPU memory is working properly switch a CPU, a memory can be guaranteed to work properly. 还可以实现服务器系统在某个CPU出现故障时,将内存切换到其他CPU上,可以在不用关闭系统的情况下,保证故障CHJ下的内存可以正常工作,以提高整个系统稳定性,而且本发明还具有设计合理、结构简单、使用方便等特点,因而,具有很好的使用价值。 The server system may also be implemented when a CPU fails, the other CPU is switched to the memory, can be closed without the use of the system, to ensure that the memory can work CHJ fault, in order to improve overall system stability, but the present invention also it has a reasonable design, simple structure, easy to use features, therefore, has a very good value.

附图说明 BRIEF DESCRIPTION

[0008]图1为一种实现内存设备冗余的方法的结构示意图。 [0008] FIG. 1 is a method for implementing redundancy memory device structure of FIG.

[0009] 实施方式下面结合附图对本发明的一种实现内存设备冗余的方法作以下详细说明。 Following detailed description of the accompanying drawings a method of the present invention achieves redundancy memory devices [0009] The following embodiments in conjunction.

[0010] 如图1所示,本发明的一种实现内存设备冗余的方法,用Memory controller将内存或内存槽分别连接到相邻的2个CPU上,保证内存或内存槽到两个CPU的路径都是可连通的,当其中一个CHJ出现off line或其他错误时,内存自带切换到功能正常的CPU上。 [0010] 1, the method of the present invention achieves redundancy memory devices, memory or Memory controller with memory slots are connected to adjacent two CPU, memory or memory slot to ensure that the two CPU the communication paths are available, wherein when a CHJ off line or other error occurs, the memory comes to the switch functioning CPU.

[0011] 系统中将内存设备通过Memory controlIer分别连接到CPUO和CPUl,系统通过FPGA/CPLD来监控每个CPU的状态,通过监控到CPU状态结果来控制Memory controlIerPort连接状态; [0011] System memory device will be respectively connected by the Memory controlIer CPUO and CPUl, each CPU to monitor the system by the FPGA / CPLD state to the connected state by controlling Memory controlIerPort state monitoring results to the CPU;

当CPUO工作正常时,FPGA/CPLD将Memory control Ier连接设置在PortO,内存通过Por tO连接到CPUO,此时Por 11为关闭状态; When the work CPUO, FPGA / CPLD the Memory control Ier connector disposed PortO, CPUO is connected to the memory through Por tO, Por 11 is closed at this time;

当CPUO出现off I ine或出现其他错误时,FPGA/CPLD监控CPUO出现故障,自动将Memorycontroller切换到Portl,内存通过Portl连接到CPUl,保证PCIE DEVICE正常工作。 Occurs when CPUO off I ine or other errors, FPGA / CPLD CPUO monitor fails to automatically switch Memorycontroller Portl, memory via Portl to CPUl, PCIE DEVICE ensure normal operation.

[0012]本发明的一种实现内存设备冗余的方法其加工制作非常简单方便,按照说明书附图所示即可加工。 [0012] A method of the present invention achieves redundancy memory apparatus which is easy to manufacture, according to the processing shown in the accompanying drawings.

[0013]除说明书所述的技术特征外,均为本专业技术人员的已知技术。 [0013] In addition to the technical features described in the specification, it is known to those skilled in the art.

Claims (2)

1.一种实现内存设备冗余的方法,其特征在于Memory controlIer将内存分别连接到相邻的2个CPU上,保证内存到两个CPU的路径都是可连通的,当其中一个CPU出现off line或其他错误时,内存自带切换到功能正常的(PU上。 A method for implementing redundancy in a memory device, wherein the memory Memory controlIer respectively connected to adjacent two CPU, to ensure that the CPU memory are two paths to be connected, wherein when one CPU off occurs when the line or other error, the memory comes to the switch functioning (PU.
2.根据权利要求1所述的一种实现内存设备冗余的方法,其特征在于内存固定在内存槽上,Memory controlIer将内存槽分别连接到相邻的2个CPU上,保证内存槽到两个CPU的路径都是可连通的。 The method for implementing the redundant memory device as claimed in claim 1, characterized in that the memory is fixed to the memory slot, Memory controlIer connected to each of the memory slots adjacent to the CPU 2, to ensure the two memory slots path-CPU communication is available.
CN201510911785.2A 2015-12-11 2015-12-11 Method for realizing memory equipment redundancy CN105550075A (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101071407A (en) * 2007-06-22 2007-11-14 中兴通讯股份有限公司 Active-standby system and method for realizing interconnecting device switching of external devices therebetween
US20100035681A1 (en) * 2004-12-07 2010-02-11 Michal Bortnik Ubiquitous unified player identity tracking system
CN104125049A (en) * 2014-08-08 2014-10-29 浪潮电子信息产业股份有限公司 Redundancy implementation method of PCIE (Peripheral Component Interface Express) device based on BRICKLAND platform
CN104484021A (en) * 2014-12-23 2015-04-01 浪潮电子信息产业股份有限公司 Server system with expandable memory

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100035681A1 (en) * 2004-12-07 2010-02-11 Michal Bortnik Ubiquitous unified player identity tracking system
CN101071407A (en) * 2007-06-22 2007-11-14 中兴通讯股份有限公司 Active-standby system and method for realizing interconnecting device switching of external devices therebetween
CN104125049A (en) * 2014-08-08 2014-10-29 浪潮电子信息产业股份有限公司 Redundancy implementation method of PCIE (Peripheral Component Interface Express) device based on BRICKLAND platform
CN104484021A (en) * 2014-12-23 2015-04-01 浪潮电子信息产业股份有限公司 Server system with expandable memory

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