CN105529340A - Transmission control transistor and preparation method thereof and CIS chip structure - Google Patents
Transmission control transistor and preparation method thereof and CIS chip structure Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 22
- 230000005540 biological transmission Effects 0.000 title abstract 8
- 239000004065 semiconductor Substances 0.000 claims abstract description 77
- 239000000758 substrate Substances 0.000 claims abstract description 75
- 238000005468 ion implantation Methods 0.000 claims abstract description 16
- 238000002161 passivation Methods 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 11
- 230000008569 process Effects 0.000 claims description 11
- 150000002500 ions Chemical class 0.000 claims description 8
- 238000002347 injection Methods 0.000 claims description 7
- 239000007924 injection Substances 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- 238000009413 insulation Methods 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 abstract 3
- 238000007254 oxidation reaction Methods 0.000 abstract 3
- 230000015572 biosynthetic process Effects 0.000 description 6
- 230000008859 change Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000003384 imaging method Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
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- 239000000126 substance Substances 0.000 description 2
- 230000000739 chaotic effect Effects 0.000 description 1
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- 238000005265 energy consumption Methods 0.000 description 1
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- 239000000203 mixture Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
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Abstract
The invention provides a transmission control transistor and a preparation method thereof and a CIS chip structure. The transmission control transistor comprises a semiconductor substrate, wherein an N-type deep well region and an FD active region are formed in the semiconductor substrate; a P-type shallow doped region is formed in the surface of the N-type deep well region; a shallow channel is formed in the semiconductor substrate and is located between the N-type deep well region and the FD active region; the depth of the shallow channel is greater than that of the P-type shallow doped region; and a transmission control grid oxidation layer and a transmission control grid are formed in the shallow channel. According to the transmission control transistor and the preparation method thereof and the CIS chip structure, the transmission control grid oxidation layer can isolate the P-type doped region and the FD active region, so that electric leakage generated by the P-type doped region is prevented from being transmitted to the FD active region. The semiconductor substrate damaged by ion implantation is etched away to form the transmission control grid oxidation layer, so that electric leakage generated by the damage can be reduced.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to a kind of conduction and control transistor and preparation method thereof and CIS chip structure.
Background technology
CIS (CMOSImageSensor) device plays more and more important role in our daily life, because its cost is low, low in energy consumption, integrated level advantages of higher, become the essential element in the multiple digital products such as mobile phone, notebook computer, digital camera, Digital Video.CIS utilizes photodiode that light signal is changed into the signal of telecommunication, then processes the signal of telecommunication and stores, as the data of figure reduction.And improving constantly along with CIS technology, in people's logarithmic code product, the quality requirement of display frame is also more and more higher.In order to obtain high-quality display frame, the pixel quantity in CIS device becomes more and more, and meanwhile, the size of each pixel becomes more and more less.
CIS comprises conduction and controls transistor, reset transistor, source output transistor, shown in CIS structural reference Fig. 1, comprising:
Semiconductor substrate 10, fleet plough groove isolation structure 20 is included in described Semiconductor substrate, described Semiconductor substrate 10 comprises a N-type deep-well region 30, described N-type deep-well region 30 includes a shallow doped region 31 of P type in described Semiconductor substrate 10 surface, described N-type deep-well region 30 and the shallow doped region 31 of described P type form PN junction structure, form photodiode, photodiode converts light signal to the signal of telecommunication.
Conduction controls transistor 50, and described conduction controls transistor 50 and comprises conduction control gate oxide layer 51 and conduction control gate 52.Described conduction controls transistor 50 and also comprises FD (FloatingDiffusion, floating diode) active area 53.Described FD active area 53 includes P moldeed depth well region 40 and a N-type doped region 531, and described P moldeed depth well region 40 and described N-type doped region 531 form PN junction structure.The PN junction of photodiode and FD active area is reverse.
Reset transistor 60, described reset transistor 60 comprises reset gate oxide layer 61 and reset gate 62.Described reset transistor 60 also reset active area 63.
Source output transistor 80, described source output transistor 80, is connected with FD active area 53.
FD active area 53 is a PN, in time will collecting photoelectronic, the reset transistor be connected with it can be closed, when having electronics to pass in FD active area 53, electronics is just stored by FD active area, cause the change of FD active area voltage, the voltage of this change can be applied on the grid of source output transistor 80, and the electric current flow through in source output transistor 80 is changed.During the work of CIS chip structure be exactly by judge the incident generation of light be electronically injected to FD active area after cause in source output transistor 80 current change quantity, thus voltage variety on anti-release FD active area, thus obtain incident number of electrons, finally obtain incident luminous intensity.
But, in the CIS chip structure of prior art, make the pixel cell of formation produce bright spot because FD active area 53 exists leaky, affect image quality.
The electric leakage of FD active area 53 is mainly from the metallic pollution etc. with described N-type deep-well region and the described shallow doped region of P type.In order to avoid electric leakage, in prior art usually when keeping original device architecture constant, adopt arsenic to inject and replace phosphorus to inject the described N-type deep-well region 30 of formation, the chemical property due to arsenic does not have the chemical property of phosphorus active, therefore can reduce the situation of part electric leakage.But the pixel cell of formation still has bright spot and produces, and is difficult to the basic problem solving electric leakage.
Summary of the invention
The object of the invention is to, provide a kind of conduction to control transistor and preparation method thereof and CIS chip structure, the leaky of the FD active area in CIS chip structure can be avoided, thus high-quality CIS chip structure is provided.
For solving the problems of the technologies described above, the invention provides a kind of conduction and controlling transistor, it is characterized in that, comprising:
Semiconductor substrate, is formed with a N-type deep-well region and a FD active area in described Semiconductor substrate, described N-type deep-well region surface is formed with a shallow doped region of P type;
Shallow slot, be formed in described Semiconductor substrate, described shallow slot is between described N-type deep-well region and described FD active area, and the degree of depth of described shallow slot is greater than the degree of depth of the described shallow doped region of P type, is formed with stacked conduction control gate oxide layer and conduction control gate in described shallow slot successively.
Optionally, described Semiconductor substrate is P type semiconductor substrate.
Optionally, described conduction control gate both sides are also formed with sidewall oxide.
Optionally, the side that described sidewall oxide deviates from described conduction control gate is formed with passivation layer.
Optionally, described passivation layer is silicon nitride.
Optionally, in the described Semiconductor substrate below described N-type deep-well region, also include a n type buried layer, described n type buried layer and described N-type deep-well region electric insulation.
The present invention also provides a kind of and conducts the preparation method controlling transistor, comprising:
Semiconductor substrate is provided, carries out ion implantation in described Semiconductor substrate and be formed with a N-type deep-well region, near the surface of described Semiconductor substrate, ion implantation is carried out to described N-type deep-well region and is formed with a shallow doped region of P type;
Etch the described Semiconductor substrate of part outside described N-type deep-well region, form a shallow slot, the degree of depth of described shallow slot is greater than the degree of depth of the described shallow doped region of P type;
In described shallow slot successively deposit conductive control gate oxide layer and conduction control gate;
Carry out ion implantation process to described Semiconductor substrate, form a FD active area, described shallow slot is between described N-type deep-well region and described FD active area.
Optionally, described Semiconductor substrate is P type semiconductor substrate.
Optionally, sidewall oxide is formed in described conduction control gate both sides.
Optionally, the side formation passivation layer of described conduction control gate is deviated from described sidewall oxide.
Optionally, described passivation layer is silicon nitride.
Optionally, respectively a shallow Doped ions injection process and dark Doped ions injection process are carried out to described Semiconductor substrate, form described FD active area.
Optionally, in the described Semiconductor substrate below described N-type deep-well region, be also formed with a n type buried layer, described n type buried layer and described N-type deep-well region electric insulation.
The present invention also provides a kind of CIS chip structure, comprises conduction and controls transistor, reset transistor, source output transistor, it is characterized in that, it is that above-described conduction controls transistor that described conduction controls transistor.
Compared with prior art, conduction control transistor provided by the invention and preparation method thereof and CIS chip structure have the following advantages:
Conduction provided by the invention controls in transistor and preparation method thereof and CIS chip structure, conduction controls transistor and comprises: Semiconductor substrate, a N-type deep-well region and a FD active area is formed in described Semiconductor substrate, described N-type deep-well region surface is formed with a shallow doped region of P type, and described N-type deep-well region and the shallow doped region of described P type form photodiode; A shallow slot is also formed in described Semiconductor substrate, described shallow slot is between described N-type deep-well region and FD active area, the degree of depth of described shallow slot is greater than the degree of depth of the described shallow doped region of P type, is formed with conduction control gate oxide layer and conduction control gate in described shallow slot.In the present invention, the conduction control gate oxide layer in described shallow slot can, by the described shallow doped region of P type and described FD active area isolation, avoid the electric leakage produced in the described shallow doped region of P type to pass to described FD active area.Meanwhile, the described Semiconductor substrate producing damage because of ion implantation is etched away and forms described conduction control gate oxide layer, the electric leakage that damage produces can be reduced.
Accompanying drawing explanation
Fig. 1 is CIS chip structure schematic diagram in prior art;
Fig. 2 is the flow chart that in the present invention, conduction controls transistor preparation method;
Fig. 3 a to Fig. 3 d is that in the present invention, preparation conduction controls device profile structural representation corresponding to each step of transistor;
Fig. 4 is CIS chip structure schematic diagram in the present invention.
Embodiment
Below in conjunction with schematic diagram, conduction control transistor of the present invention and preparation method thereof and CIS chip structure are described in more detail, which show the preferred embodiments of the present invention, should be appreciated that those skilled in the art can revise the present invention described here, and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensively knowing for those skilled in the art, and not as limitation of the present invention.
In order to clear, whole features of practical embodiments are not described.They in the following description, are not described in detail known function and structure, because can make the present invention chaotic due to unnecessary details.Will be understood that in the exploitation of any practical embodiments, a large amount of implementation detail must be made to realize the specific objective of developer, such as, according to regarding system or the restriction about business, change into another embodiment by an embodiment.In addition, will be understood that this development may be complicated and time-consuming, but be only routine work to those skilled in the art.
In the following passage, more specifically the present invention is described by way of example with reference to accompanying drawing.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts the form that simplifies very much and all uses non-ratio accurately, only in order to object that is convenient, the aid illustration embodiment of the present invention lucidly.
Core concept of the present invention is, the conduction provided controls in transistor and preparation method thereof and CIS chip structure, conduction controls transistor and comprises: Semiconductor substrate, a N-type deep-well region and a FD active area is formed in described Semiconductor substrate, described N-type deep-well region surface is formed with a shallow doped region of P type, and described N-type deep-well region and the shallow doped region of described P type form photodiode; A shallow slot is also formed in described Semiconductor substrate, described shallow slot is between described N-type deep-well region and FD active area, the degree of depth of described shallow slot is greater than the degree of depth of the described shallow doped region of P type, is formed with conduction control gate oxide layer and conduction control gate in described shallow slot.In the present invention, described conduction control gate oxide layer can, by the described shallow doped region of P type and described FD active area isolation, avoid the electric leakage produced in the described shallow doped region of P type to pass to described FD active area.Meanwhile, the described Semiconductor substrate producing damage because of ion implantation is etched away and forms described conduction control gate oxide layer, the electric leakage that damage produces can be reduced.
Fig. 2 conduction of the present invention controls the flow chart of preparation method of transistor, below according to Fig. 2 and composition graphs 3a to Fig. 3 d conduction control transistor of the present invention is specifically described:
Perform step S1: shown in figure 3a, Semiconductor substrate 100 is provided, in described Semiconductor substrate 100, a N-type deep-well region 210 is formed with by ion implantation, and carry out ion implantation in described N-type deep-well region 210 near described Semiconductor substrate 100 surface and form a shallow doped region 220 of P type, described N-type deep-well region and the described shallow doped region of P type form PN junction structure, form photodiode.
Perform step S2: shown in figure 3b, etch the described Semiconductor substrate 100 of part outside described N-type deep-well region 210, form a shallow slot 300, the degree of depth of described shallow slot 300 is greater than the degree of depth of the shallow doped region 220 of described P type, the follow-up conduction control gate oxide layer formed in described shallow slot is made to be greater than the distance of the described shallow doped region of P type 220 apart from the surface of described Semiconductor substrate 100 apart from the distance on the surface of described Semiconductor substrate 100, therefore the photodiode of described N-type deep-well region 210 and the formation of described P type shallow doped region 220 and the distance of described FD active area can be increased.
Perform step S3: with reference to figure 3c shown in, in described shallow slot 300 successively deposit conductive control gate oxide layer 410 with conduct control gate 420.In the present embodiment, when carrying out ion implantation to described Semiconductor substrate 100, described Semiconductor substrate 100 surface can be made to form damage, the surface etch of described for the part with damage Semiconductor substrate 100 is fallen to be formed described shallow slot 300, defect can be introduced in described Semiconductor substrate 100 in etching process, but after in described shallow slot 300, deposition forms described conduction control gate oxide layer 410, not only can reduce because of defect, the electric leakage that the defect in described Semiconductor substrate is brought can also be avoided.In the present embodiment, formed in described conduction control gate process in etching, make described layer conduct control gate 420 to offset to the right, ensure the impact that described N-type deep-well region 210 can not be etched, and ion implantation is formed in the process of described FD active area, ion can not described N-type deep-well region 210 spread.Further, form sidewall oxide 430 in described conduction control gate 420 both sides, the side deviating from described conduction control gate 420 at described sidewall oxide 430 forms passivation layer 440.Preferably, described passivation layer 440 is silicon nitride.
Perform step S4: shown in figure 3d, ion implantation process is carried out to described Semiconductor substrate 100, forms a FD active area 500.Preferably, first shallow Doped ions injection (LightlyDopedDrianIonImplantation) is carried out to the described Semiconductor substrate of part 100, form N doped region 510.Carry out dark Doped ions injection to described afterwards, form P moldeed depth well region 520, described N-type doped region 510 and described P moldeed depth well region 520 form FD active area 500.In the present embodiment, because described conduction control gate oxide layer 410 is in the inside of described Semiconductor substrate 100, when carrying out ion implantation to described semiconductor, the ion injected can be avoided to spread to described N-type deep-well region 210.
In the present invention, the described shallow doped region of P type 220 can isolate with described FD active area 500 by described conduction control gate oxide layer 410, the electric leakage produced in the described shallow doped region of P type 220 is avoided to pass to described FD active area 500, thus the bad phenomenon such as bright spot that the dot structure avoided the formation of produces because of electric leakage.
In the present embodiment, leakage current in described N-type deep-well region 210, when entering into the described P moldeed depth well region 520 under described FD active area 500, the more difficult described N doped region 510 being transported to described FD active area 500, therefore, described FD active area 500 can stop the leakage current produced in described N-type deep-well region 210.
Preferably, in the present embodiment, a n type buried layer 700 in described Semiconductor substrate 100, is also formed with, described n type buried layer 700 and described N-type deep-well region 210 electric insulation.Described n type buried layer 700 is dark doped N-type layer (DeepdopedNtypelayer), its effect is dark injection one deck N-type layer bottom described N-type deep-well region 210, play the effect of collecting described Semiconductor substrate 100 and leaking electricity, because described n type buried layer 700 exists, interference electric charge in described Semiconductor substrate 100 will be collected in described n type buried layer 700, and can not pass in described FD active area, thus reduce the interference that described Semiconductor substrate 100 is brought described pixel cell.
Conduction provided by the invention controls the structure of transistor as shown in Figure 3 d, comprising:
Semiconductor substrate 100, preferably, described Semiconductor substrate 100 is P type semiconductor substrate.N-type deep-well region 210 and a FD active area 500 is formed in described Semiconductor substrate 100, described N-type deep-well region 210 surface is formed with a shallow doped region 220 of P type, in the present embodiment, described N-type deep-well region 210 and the shallow doped region 220 of described P type form photodiode, can convert light signal to the signal of telecommunication.
A shallow slot 300 is formed in described Semiconductor substrate 100, described shallow slot 300 is between described N-type deep-well region 210 and described FD active area 500, the degree of depth of described shallow slot 300 is greater than the degree of depth of the shallow doped region 220 of described P type, is formed with conduction control gate oxide layer 410 and conduction control gate 420 in described shallow slot 300.Further, described conduction control gate 420 both sides are also formed with sidewall oxide 430, and the side that described sidewall oxide 430 deviates from described conduction control gate is formed with passivation layer 440.Described passivation layer 440 is silicon nitride.
Described Semiconductor substrate 100 is formed with a FD active area 500 in going back.Described FD active area 500 includes N-type doped region 510 and a P moldeed depth well region 520.
Preferably, in the described Semiconductor substrate 100 below described N-type deep-well region 210, also include a n type buried layer 700, described n type buried layer 700 and described N-type deep-well region 210 electric insulation.
As another side of the present invention, the present invention also provides a kind of CIS chip structure, comprises conduction and controls transistor, reset transistor, source output transistor.CIS chip structure of the present invention adopts above-described conduction to control transistor.Shown in figure 4, it is inner that described conduction control gate oxide layer 410 is positioned at described Semiconductor substrate 100, the described shallow doped region of P type 220 and described FD active area 500 can be isolated, the electric leakage produced in the described shallow doped region of P type 220 is avoided to transmit to described FD active area 500, solve the imaging because of described FD active area effect of leakage CIS chip, thus improve the quality of CIS chip structure imaging.
In sum, conduction provided by the invention controls in transistor and preparation method thereof and CIS chip structure, conduction controls transistor and comprises: Semiconductor substrate, a N-type deep-well region and a FD active area is formed in described Semiconductor substrate, described N-type deep-well region surface is formed with a shallow doped region of P type, and described N-type deep-well region and the shallow doped region of described P type form photodiode; A shallow slot is also formed in described Semiconductor substrate, described shallow slot is between described N-type deep-well region and FD active area, the degree of depth of described shallow slot is greater than the degree of depth of the described shallow doped region of P type, is formed with conduction control gate oxide layer and conduction control gate in described shallow slot.In the present invention, described conduction control gate oxide layer can, by the described shallow doped region of P type and described FD active area isolation, avoid the electric leakage produced in the described shallow doped region of P type to pass to described FD active area.Meanwhile, the described Semiconductor substrate producing damage because of ion implantation is etched away and forms described conduction control gate oxide layer, the electric leakage that damage produces can be reduced.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (14)
1. conduction controls a transistor, it is characterized in that, comprising:
Semiconductor substrate, is formed with a N-type deep-well region and a FD active area in described Semiconductor substrate, described N-type deep-well region surface is formed with a shallow doped region of P type;
Shallow slot, be formed in described Semiconductor substrate, described shallow slot is between described N-type deep-well region and described FD active area, and the degree of depth of described shallow slot is greater than the degree of depth of the described shallow doped region of P type, is formed with stacked conduction control gate oxide layer and conduction control gate in described shallow slot successively.
2. conduction as claimed in claim 1 controls transistor, and it is characterized in that, described Semiconductor substrate is P type semiconductor substrate.
3. conduction as claimed in claim 1 controls transistor, and it is characterized in that, described conduction control gate both sides are also formed with sidewall oxide.
4. conduction as claimed in claim 3 controls transistor, and it is characterized in that, the side that described sidewall oxide deviates from described conduction control gate is also formed with passivation layer.
5. conduction as claimed in claim 4 controls transistor, and it is characterized in that, described passivation layer is silicon nitride.
6. conduction as claimed in claim 1 controls transistor, it is characterized in that, also includes a n type buried layer in the described Semiconductor substrate below described N-type deep-well region, described n type buried layer and described N-type deep-well region electric insulation.
7. conduct the preparation method controlling transistor, comprising:
Semiconductor substrate is provided, in described Semiconductor substrate, carries out ion implantation be formed with a N-type deep-well region, ion implantation is carried out to the surface of described N-type deep-well region and is formed with a shallow doped region of P type;
Etch the described Semiconductor substrate of part outside described N-type deep-well region, to form a shallow slot, the degree of depth of described shallow slot is greater than the degree of depth of the described shallow doped region of P type;
In described shallow slot successively deposit conductive control gate oxide layer and conduction control gate;
Carry out ion implantation process to described Semiconductor substrate, form a FD active area, described shallow slot is between described N-type deep-well region and described FD active area.
8. conduction as claimed in claim 7 controls the preparation method of transistor, and it is characterized in that, described Semiconductor substrate is P type semiconductor substrate.
9. conduction as claimed in claim 7 controls the preparation method of transistor, it is characterized in that, forms sidewall oxide in described conduction control gate both sides.
10. conduction as claimed in claim 9 controls the preparation method of transistor, it is characterized in that, the side deviating from described conduction control gate at described sidewall oxide forms passivation layer.
11. conduct the preparation method controlling transistor as claimed in claim 10, and it is characterized in that, described passivation layer is silicon nitride.
12. conduct the preparation method controlling transistor as claimed in claim 7, it is characterized in that, carry out a shallow Doped ions injection process and dark Doped ions injection process respectively, form described FD active area to described Semiconductor substrate.
13. conduct the preparation method controlling transistor as claimed in claim 7, it is characterized in that, are also formed with a n type buried layer in the described Semiconductor substrate below described N-type deep-well region, described n type buried layer and described N-type deep-well region electric insulation.
14. 1 kinds of CIS chip structures, comprise conduction control transistor, reset transistor, source output transistor, it is characterized in that, described conduction control transistor for such as in claim 1-6 as described in any one conduction control transistor.
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| CN1819232A (en) * | 2004-12-29 | 2006-08-16 | 东部亚南半导体株式会社 | CMOS image sensor and method for fabricating the same |
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| CN1839484A (en) * | 2004-03-17 | 2006-09-27 | 松下电工株式会社 | Light detecting element and control method of light detecting element |
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Application publication date: 20160427 |