CN105527884B - Support the WIA-PA communication sequence controllers that more communication sequences are built automatically - Google Patents
Support the WIA-PA communication sequence controllers that more communication sequences are built automatically Download PDFInfo
- Publication number
- CN105527884B CN105527884B CN201410566359.5A CN201410566359A CN105527884B CN 105527884 B CN105527884 B CN 105527884B CN 201410566359 A CN201410566359 A CN 201410566359A CN 105527884 B CN105527884 B CN 105527884B
- Authority
- CN
- China
- Prior art keywords
- signal
- timing
- state machine
- timer
- communication
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000006854 communication Effects 0.000 title claims abstract description 174
- 238000004891 communication Methods 0.000 title claims abstract description 172
- 230000004044 response Effects 0.000 claims description 115
- 230000005540 biological transmission Effects 0.000 claims description 95
- 238000001514 detection method Methods 0.000 claims description 88
- 238000010276 construction Methods 0.000 claims description 9
- 238000006467 substitution reaction Methods 0.000 abstract 1
- 230000000977 initiatory effect Effects 0.000 description 15
- 238000000034 method Methods 0.000 description 8
- 230000008569 process Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 4
- 238000012544 monitoring process Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000008447 perception Effects 0.000 description 1
- 238000003786 synthesis reaction Methods 0.000 description 1
Landscapes
- Mobile Radio Communication Systems (AREA)
Abstract
The present invention relates to the WIA PA communication sequence controllers for supporting that more communication sequences are built automatically, including decoding circuit, state machine and the timer group being linked in sequence；Decoding circuit, the operation code for receiving the definition communication sequence type that processor is sent, and operation code is parsed into communication request signal and is sent to state machine；State machine for the opening and closing according to timer and receiver, transmitter and physical radio circuit in communication request signal control timer group, and according to the transmitting-receiving of the requirement of present communications sequence completion data, controls the execution of communication process；It is connect with transmitter, receiver, physical radio circuit；Timer group is timed for each time parameter in communication sequence, the timing enable signal of user equipment, is generated timing and is overflowed indication signal to state machine.The present invention controls entire communication process using communication sequence controller substitution processor, can improve the real-time of communication, reduce the workload of processor.
Description
Technical Field
The invention relates to an industrial wireless communication technology, in particular to a controller capable of automatically constructing a plurality of WIA-PA wireless communication sequences.
Background
The industrial wireless network standard WIA-PA is one of IEC international standards in the field of industrial process automation, and with the continuous improvement of wireless technology, the WIA network is gradually applied to an industrial automation control system, so that a user can realize the ubiquitous perception of the whole industrial process with lower investment and use cost, and the aims of improving the product quality and saving energy and reducing consumption are achieved.
In the WIA network, the wireless nodes communicate based on the slot of the time slice most of the time, that is, the data is received and transmitted in the allocated slot, and the other time is in a silent state. The conventional wireless node controls the execution of its communication flow by its internal processor. When the wireless node is in the slot allocated to the wireless node, enabling a timer by a processor, and enabling a transmitter by the processor after the timer reaches a timing value, wherein the transmitter starts to transmit request data; and after the data is sent, enabling the timer by the processor, enabling the receiver by the processor after the timer reaches a timing value, starting to receive response data by the receiver, and finishing one-time communication flow after the data is received. The wireless node may also perform reception of the request data first and then perform transmission of the response data in the same manner.
As can be seen from the above process, the circuit structure of the communication part adopted by the conventional wireless node has a disadvantage that the processor must perform multiple interventions in one communication flow, which complicates the control process and increases the workload of the processor. Therefore, the invention provides a communication sequence controller, which can automatically construct a communication sequence in a primary communication flow as required, control the work of a receiver and a transmitter, and reduce the work load of a processor without the intervention of the processor.
Disclosure of Invention
The invention aims to add a communication sequence controller in a wireless node to solve the defects of complex control process and heavy processor workload caused by that a processor directly controls a receiver, a transmitter and a timer in the traditional structure.
In order to achieve the purpose, the invention adopts the following technical scheme:
the WIA-PA communication sequence controller supporting automatic construction of multiple communication sequences comprises a decoding circuit, a state machine and a timer group which are sequentially connected;
the decoding circuit is used for receiving an operation code which defines the type of a communication sequence and is sent by the processor, resolving the operation code into a communication request signal and sending the communication request signal to the state machine;
the state machine is used for controlling the opening and closing of a timer, a receiver, a transmitter and a physical radio frequency circuit in the timer group according to the communication request signal, completing the transceiving of data according to the requirement of the current communication sequence and controlling the execution of the communication flow; the transmitter, the receiver and the physical radio frequency circuit are connected;
and the timer group is used for timing each time parameter in the communication sequence, receiving a timing enabling signal of the state machine and generating a timing overflow indicating signal to the state machine.
A communication starting signal end, a communication termination signal end, an idle channel detection request signal end, a sending request signal end, a receiving request signal end, a data response request signal end, a timing starting request signal end and a continuous receiving indication signal end of the state machine are connected with the output end of the decoding circuit;
a timing enable signal interface and a timing overflow indication signal interface of the state machine are connected with a timer group;
the receiver enabling signal end and the receiving end indicating signal end of the state machine are connected with the control end of the receiver; the transmitter enabling signal end and the transmission ending indication signal end are connected with the control end of the transmitter; the physical radio frequency receiving enabling signal end, the physical radio frequency transmitting enabling signal end, the idle channel detection enabling signal end and the idle channel state indicating signal end are connected with the physical radio frequency circuit.
The timing enabling signal interface comprises a starting timing enabling signal end, an idle channel detection timing enabling signal end, a sending delay timing enabling signal end, a sending response delay timing enabling signal end and a receiving response delay timing enabling signal end, and the starting timing enabling signal end, the idle channel detection timing enabling signal end, the sending delay timing enabling signal end, the sending response delay timing enabling signal end and the receiving response delay timing enabling signal end are respectively connected with each timer in the timer group.
The timing overflow indication signal interface comprises a starting timing overflow indication signal end, an idle channel detection timing overflow indication signal end, a sending delay timing overflow indication signal end, a sending response delay timing overflow indication signal end and a receiving response delay timing overflow indication signal end, and is respectively connected with each timer in the timer group.
The timer group includes:
the starting timer is used for starting timing of a communication sequence, receiving a starting timing enabling signal of the state machine and generating a starting timing overflow indicating signal to the state machine;
an idle channel detection timer, which is used for timing the time length for executing the idle channel detection; receiving an idle channel detection timing enabling signal of the state machine, and generating an idle channel detection timing overflow indicating signal to the state machine;
a sending delay timer for timing the delay from the end of the idle channel detection execution to the start of the request data sending; receiving a sending delay timing enabling signal of the state machine, and generating a sending delay timing overflow indicating signal to the state machine;
a response transmission delay timer for timing the delay from the completion of the reception of the request data to the start of the transmission of the response data; receiving a sending response delay timing enabling signal of the state machine, and generating a sending response delay timing overflow indicating signal to the state machine;
a response receiving delay timer for timing the delay from the completion of the transmission of the request data to the start of the reception of the response data; and receiving a receiving response delay timing enable signal of the state machine, and generating a receiving response delay timing overflow indication signal to the state machine.
The communication sequence controller provided by the invention is provided on the premise of fully considering the communication characteristics of the wireless nodes in the WIA network, has the advantages of strong communication real-time performance, good use flexibility and the like, and is specifically represented as follows:
1. the invention adopts a hardware mode to realize the automatic construction of the communication sequence, avoids excessive intervention of the processor, reduces the workload of the processor and improves the software execution efficiency.
2. The invention adopts the mode that the hardware processes the physical radio frequency circuit, the receiver and the transmitter interface signals, so that the triggering and the response of each event are more timely and accurate in the execution process of the communication sequence, and the certainty of the execution time sequence of the communication sequence is ensured.
3. The invention adopts the mode of configuring the operation codes by the processor, can configure the communication sequence controller to generate various required communication sequences according to application requirements, and meets all communication functions required by the wireless node.
4. The invention adopts the special timer to time the time parameter in the communication sequence, ensures that the communication operations in the communication sequence can be accurately linked in real time, and ensures the real-time performance of communication.
5. The invention adopts the mode that the processor configures the timing value of each timer, can set different timing values according to different real-time requirements, and ensures the support of different real-time applications.
6. The invention adopts the communication sequence controller to replace the processor to control the whole communication flow, can improve the real-time performance of communication and reduce the working load of the processor.
Drawings
FIG. 1 is a block diagram of a communication portion of a wireless node with a communication sequence controller according to the present invention;
FIG. 2 is a diagram of a communication sequence controller architecture;
fig. 3 is a state transition diagram of a state machine within a communication sequence controller.
Detailed Description
The invention is described in further detail below with reference to the figures and specific examples of the specification.
A WIA-PA communication sequence controller supporting automatic construction of a plurality of communication sequences comprises a decoding circuit, a timer group and a state machine. The decoding circuit receives an operation code sent by the processor, the operation code defines the type of the communication sequence, and the decoding circuit analyzes the operation code into a group of communication request signals and sends the communication request signals to the state machine.
The timer group comprises 5 timers, namely a starting timer: a start timing for the communication sequence, the timing value configured by the processor; idle channel detection timer: the device is used for timing the time length for executing the channel idle detection, and the timing value is configured through the processor; sending a delay timer: the device is used for timing the time delay from the end of the idle channel detection execution to the start of the request data transmission, and the timing value is configured through the processor; transmit response delay timer: the timing device is used for timing the time delay between the completion of the reception of the request data and the start of the transmission of the response data, and the timing value is configured through the processor; receive response delay timer: the timing device is used for timing the time delay from the completion of the sending of the request data to the beginning of the receiving of the response data, and the timing value is configured through the processor.
The state machine receives the communication request signal generated by the decoding circuit, controls the opening and closing of the relevant timer, the receiver, the transmitter and the physical radio frequency circuit in the timer group according to the value of the request signal, further completes the data receiving and transmitting according to the requirement of the current communication sequence, and controls the execution of the communication flow.
Before a communication sequence is started, a processor configures timing values of related timers in a timer group according to time parameters of the communication sequence to be started; then, configuring an operation code and starting a corresponding communication sequence; then, the communication sequence controller starts to work, the decoding circuit translates the operation code into a communication request signal, and the state machine controls the on and off of the timer, the receiver, the transmitter and the physical radio frequency circuit according to the communication request signal, monitors the state signals of the timer, the receiver, the transmitter and the physical radio frequency circuit and controls the execution of the communication flow.
The types of the communication sequence include: immediately initiating idle channel detection, timing initiating idle channel detection, immediately initiating data transmission, timing initiating data transmission, immediately initiating data reception, timing initiating data reception, immediately initiating data transmission with idle channel detection, timing initiating data transmission with idle channel detection, immediately initiating data transmission and receiving response data, timing initiating data transmission and receiving response data, immediately initiating data transmission with idle channel detection and receiving response data, timing initiating data transmission and receiving response data with idle channel detection, immediately initiating data reception and transmitting response data, timing initiating data reception and transmitting data response, continuous reception, communication termination.
The communication request signal generated by the decoding circuit includes:
a communication initiation signal indicating that a communication sequence is to be initiated if the signal is valid;
a communication termination signal indicating that execution of the current communication sequence is terminated if the signal is valid;
an idle channel detection request signal, if the signal is valid, indicating that the current communication sequence includes an idle channel detection operation, otherwise, excluding the operation;
sending a request signal, if the signal is valid, indicating that the current communication sequence comprises a request data sending operation, otherwise, not comprising the operation;
receiving a request signal, if the signal is valid, indicating that the current communication sequence comprises a request data receiving operation, otherwise, not comprising the operation;
responding to the data request signal, if the signal is valid, indicating that the current communication sequence comprises the sending or receiving operation of the response data, otherwise, not comprising the sending or receiving operation of the response data;
a timed start request signal which is effective to indicate that the current communication sequence is timed to start, and otherwise, indicates that the current communication sequence is immediately started;
and continuously receiving an indication signal, wherein when the signal is effective, if the receiving request signal is also effective, the current communication sequence is continuously received, otherwise, the current communication sequence is not continuously received.
The decoding circuit adopts the following decoding strategies:
if the operation code is to immediately start idle channel detection, setting a communication starting signal and an idle channel detection request signal as valid, and setting other signals as invalid;
if the operation code is to start idle channel detection at regular time, setting a communication starting signal, an idle channel detection request signal and a timing starting request signal as valid, and setting other signals as invalid;
if the operation code is to immediately start data transmission, setting the communication starting signal and the transmission request signal as valid, and setting other signals as invalid;
if the operation code is to start data transmission at regular time, setting the communication starting signal, the transmission request signal and the timing starting request signal as valid, and setting other signals as invalid;
if the operation code is to immediately start data reception, setting the communication start signal and the reception request signal as valid, and setting other signals as invalid;
if the operation code is to start data reception at regular time, setting the communication start signal, the reception request signal and the timing start request signal as valid, and setting other signals as invalid;
if the operation code is to immediately start the data transmission with the idle channel detection, setting the communication starting signal, the idle channel detection request signal and the transmission request signal as valid, and setting other signals as invalid;
if the operation code is used for starting the data transmission with idle channel detection in a timing mode, setting a communication starting signal, an idle channel detection request signal, a transmission request signal and a timing starting request signal to be valid, and setting other signals to be invalid;
if the operation code is to immediately start data transmission and receive response data, setting the communication starting signal, the transmission request signal and the response data request signal as valid, and setting other signals as invalid;
if the operation code is the timing starting data sending and receiving response data, setting the communication starting signal, the sending request signal, the response data request signal and the timing starting request signal as valid, and setting other signals as invalid;
if the operation code immediately starts the data transmission with the idle channel detection and receives the response data, setting the communication starting signal, the idle channel detection request signal, the transmission request signal and the response data request signal as valid, and setting other signals as invalid;
if the operation code is used for regularly starting the data transmission with the idle channel detection and receiving the response data, setting a communication starting signal, an idle channel detection request signal, a transmission request signal, a response data request signal and a timing starting request signal as valid, and setting other signals as invalid;
if the operation code is to immediately start data reception and send response data, setting the communication start signal, the reception request signal and the response data request signal as valid, and setting other signals as invalid;
if the operation code is to start the data reception and send the response data regularly, set the communication start signal, the reception request signal, the response data request signal and the timing start request signal as valid, and set other signals as invalid;
if the operation code is continuously received, setting the communication starting signal, the receiving request signal and the continuous receiving indication signal as valid, and setting other signals as invalid;
if the operation code is communication termination, the communication termination signal is set to be effective, and other signals are set to be ineffective.
The state machine controls the work flow of the communication sequence controller, and has 11 working states: an idle state, a wait for start state, an idle channel detect state, a wait for transmit state, a request data transmit state, a wait for response receive state, a request data receive state, a wait for response transmit state, a response transmit state, and a continuous receive state. Wherein,
an idle state, indicating that no communication sequence is currently executing;
a waiting starting state which indicates that the waiting starting timer reaches a timing value;
an idle channel detection state indicating that idle channel detection is being performed;
a waiting-to-send state which indicates that the waiting-to-send delay timer reaches a timing value;
a request data transmission state indicating that the transmitter is enabled to perform request data transmission;
a wait response reception state indicating that the wait response delay timer reaches a timing value;
a response reception state indicating that the receiver is enabled to perform response data reception;
a request data reception state indicating that the receiver is enabled to perform request data reception;
a wait response transmission state indicating that the wait response delay timer reaches a timing value;
a response transmission state indicating that the transmitter is enabled to perform response data transmission;
a continuous reception state, which means that the receiver is enabled for continuous data listening.
The execution flow of the immediately started idle channel detection is as follows: firstly, enabling a receiving part of a physical radio frequency circuit and an idle channel detection timer by a state machine; then, when the idle channel detection timer overflows, checking a channel state signal generated by the physical radio frequency circuit, and judging whether the signal is idle; finally, the receiving part of the physical radio frequency circuit and the idle channel detection timer are disabled.
The execution process of the timing starting idle channel detection comprises the following steps: firstly, enabling a state machine to start a timer; then, after the start timer overflows, the execution flow of immediately starting idle channel detection is executed.
The execution flow of immediately starting data transmission is as follows: firstly, enabling a sending part and a sender of a physical radio frequency circuit by a state machine, and starting data sending; then, the state machine monitors the feedback signal of the transmitter, and if the sending end signal or the sending error signal is detected to be effective, the data sending is finished; finally, the state machine disables the transmit portion of the physical radio frequency circuit and the transmitter.
The execution flow of the timing starting data transmission is as follows: firstly, enabling a state machine to start a timer; then, when the start timer overflows, the execution flow of immediately starting data transmission is executed.
The execution flow of the immediate start data receiving is as follows: firstly, enabling a receiving part and a receiver of a physical radio frequency circuit by a state machine, and starting data receiving; then, the state machine monitors the feedback signal of the receiver, and if the reception ending signal or the reception error signal is detected to be effective, the data reception is finished; finally, the state machine disables the receive portion of the physical radio frequency circuit and the receiver.
The execution process of the timing starting data receiving comprises the following steps: firstly, enabling a state machine to start a timer; then, when the start timer overflows, the execution flow for immediately starting data reception is executed.
The execution flow of immediately starting the data transmission with the idle channel detection is as follows: firstly, enabling a receiving part of a physical radio frequency circuit and an idle channel detection timer by a state machine; secondly, checking a channel state signal generated by the physical radio frequency circuit after the idle channel detection timer overflows, if the channel is busy, terminating the current communication sequence by the state machine, and forbidding a receiving part of the physical radio frequency circuit and the idle channel detection timer, otherwise, forbidding the receiving part of the physical radio frequency circuit and the idle channel detection timer by the state machine, and enabling the sending delay timer; thirdly, after the sending delay timer overflows, the state machine forbids the sending delay timer, enables a sending part and a sender of the physical radio frequency circuit, and starts to send data; fourthly, monitoring a feedback signal of the transmitter by the state machine, and finishing data transmission if detecting that a transmission finishing signal or a transmission error signal is effective; finally, the state machine disables the transmit portion of the physical radio frequency circuit and the transmitter.
The execution flow of the data transmission with the timing starting idle channel detection is as follows: firstly, enabling a state machine to start a timer; then, after the start timer overflows, the execution flow of immediately starting the data transmission with idle channel detection is executed.
The execution flow of immediately starting data sending and receiving response data is as follows: firstly, enabling a sending part and a sender of a physical radio frequency circuit by a state machine, and starting data sending; secondly, the state machine monitors a feedback signal of the transmitter, if the state machine detects that a transmission error signal is effective, the state machine terminates the current communication sequence and forbids a transmitting part and the transmitter of the physical radio frequency circuit, and if the state machine detects that a transmission finishing signal is effective, the transmitter enables a receiving response delay timer and forbids the transmitting part and the transmitter of the physical radio frequency circuit; thirdly, after the sending response delay timer overflows, enabling a receiving part and a receiver of the physical radio frequency circuit by the state machine, and starting receiving response data; fourthly, monitoring a feedback signal of the receiver by the state machine, and if detecting that a receiving end signal or a receiving error signal is effective, finishing receiving response data; finally, the state machine disables the receive portion of the physical radio frequency circuit and the receiver.
The execution flow of sending the timing starting data and receiving the response data comprises the following steps: firstly, enabling a state machine to start a timer; then, after the start timer overflows, the execution flow of immediately starting data transmission and receiving response data is executed.
The execution flow for immediately starting the data transmission with the idle channel detection and receiving the response data comprises the following steps: firstly, enabling a receiving part of a physical radio frequency circuit and an idle channel detection timer by a state machine; secondly, checking a channel state signal generated by the physical radio frequency circuit after the idle channel detection timer overflows, if the channel is busy, terminating the current communication sequence by the state machine, and forbidding a receiving part of the physical radio frequency circuit and the idle channel detection timer, otherwise, forbidding the receiving part of the physical radio frequency circuit and the idle channel detection timer by the state machine, and enabling the sending delay timer; thirdly, after the sending delay timer overflows, the state machine forbids the sending delay timer, enables a sending part and a sender of the physical radio frequency circuit, and starts to send data; fourthly, the state machine monitors a feedback signal of the transmitter, if the state machine detects that a transmission error signal is effective, the state machine terminates the current communication sequence and forbids a transmitting part and the transmitter of the physical radio frequency circuit, and if the state machine detects that a transmission finishing signal is effective, the transmitter enables a receiving response delay timer and forbids the transmitting part and the transmitter of the physical radio frequency circuit; fifthly, enabling a receiving part and a receiver of the physical radio frequency circuit by the state machine after the sending response delay timer overflows, and responding to the start of data receiving; sixthly, monitoring a feedback signal of the receiver by the state machine, and if the reception ending signal or the reception error signal is detected to be effective, finishing receiving the response data; finally, the state machine disables the receive portion of the physical radio frequency circuit and the receiver.
The execution process of starting the data transmission with idle channel detection and receiving response data at regular time comprises the following steps: firstly, enabling a state machine to start a timer; then, after the start timer overflows, the execution flow of immediately starting the data transmission with idle channel detection and receiving response data is executed.
The execution flow of immediately starting data receiving and sending response data is as follows: firstly, enabling a receiving part and a receiver of a physical radio frequency circuit by a state machine, and starting data receiving; secondly, the state machine monitors a feedback signal of the receiver, if the state machine detects that a receiving error signal is effective, the state machine terminates the current communication sequence and forbids a receiving part and the receiver of the physical radio frequency circuit, and if the state machine detects that a receiving end signal is effective, the state machine enables a sending response delay timer and forbids the receiving part and the receiver of the physical radio frequency circuit; thirdly, after the sending response delay timer overflows, enabling a sending part and a sender of the physical radio frequency circuit by the state machine, and starting sending of response data; fourthly, monitoring a feedback signal of the transmitter by the state machine, and if the sending end signal or the sending error signal is detected to be effective, finishing sending the response data; finally, the state machine disables the transmit portion of the physical radio frequency circuit and the transmitter.
The execution flow of receiving the timing starting data and sending the response data comprises the following steps: firstly, enabling a state machine to start a timer; then, after the start timer overflows, the execution flow of immediately starting data reception and sending response data is executed.
The execution flow of the continuous receiving is as follows: the state machine enables the receive portion of the physical radio frequency circuit and the receiver until the processor terminates the current communication sequence.
The execution flow of the communication termination comprises the following steps: the state machine terminates the last outstanding communication sequence and disables the physical radio circuit, receiver, transmitter, and timer set.
In this embodiment, RTL code is written in a hardware description language Verilog, and a logic synthesis tool design compiler is used to generate a Verilog netlist, so as to form a decoding circuit, a state machine, and a logic circuit of a timer set.
As shown in fig. 1, the structure of the wireless node communication part with the communication sequence controller is schematic. The processor configures the working parameters of the communication sequence controller through a system bus 101, wherein the working parameters comprise the timing values and the communication operation codes of all timers in the timer group; the communication sequence controller controls the on and off of the transmitter, the receiver and the physical radio frequency circuit through signal lines 102, 104 and 106, respectively, and acquires the feedback states of the transmitter, the receiver and the physical radio frequency circuit through signal lines 103, 105 and 107.
As shown in fig. 2, the internal structure of the communication sequence controller and the signal connection between the modules are schematically illustrated. The communication sequence controller consists of 3 modules, namely a decoding circuit, a timer group and a state machine.
The decoding circuit receives the operation code op _ code sent by the processor, analyzes the operation code op _ code into a group of communication request signals and sends the communication request signals to the state machine. The communication request signal includes: a communication start signal tran _ start, a communication termination signal tran _ abort, a clear channel detection request signal cca _ req, a transmission request signal tx _ req, a reception request signal rx _ req, a response data request signal ack _ req, a timing start request signal time _ en, and a continuous reception instruction signal continuousness.
The timer group comprises 5 timers, each timer takes microsecond as a time unit, and the timers are respectively as follows: starting a timer, wherein the width of the timer is 12 bits, and a timing value start _ time is configured by a processor; an idle channel detection timer with the width of 8 bits and a timing value cca _ time configured by the processor; sending a delay timer with the width of 8 bits, wherein a timing value tx _ time is configured by a processor; sending a response delay timer, the width of which is 12 bits, and the timing value ack _ tx _ time is configured by the processor; the receive response delay timer, 12 bits wide, the timer value ack _ rx _ time is configured by the processor. The timing enable signal of each timer is generated by the state machine, when the timing enable signal is valid, the timer starts to count at regular time, when the count value reaches the timing value, the timer overflow indication signal is valid and is sent to the state machine. The timing enabling signal for starting the timer is start _ timer _ en, and the overflow indicating signal is start _ timeout; the timing enabling signal of the idle channel detection timer is cca _ timer _ en, and the overflow indicating signal is cca _ timeout; sending a timing enabling signal of the delay timer as tx _ timer _ en, and an overflow indicating signal as tx _ timeout; sending a timing enable signal of the response delay timer as ack _ tx _ timer _ en, and an overflow indication signal as ack _ tx _ timeout; the timing enable signal of the reception response delay timer is ack _ rx _ timer _ en, and the overflow indication signal is ack _ rx _ timeout.
The state machine receives the communication request signal generated by the decoding circuit, generates a relevant timer timing enable signal, a receiver enable signal rx _ en, a transmitter enable signal tx _ en, an idle channel detection enable signal cca _ en, a physical radio frequency reception enable signal phy _ rx _ en and a physical radio frequency transmission enable signal phy _ tx _ en according to the value of the request signal, monitors an overflow indication signal of the timer, a reception end indication signal rx _ finish of the receiver, a transmission end indication signal tx _ finish of the transmitter and an idle channel state indication signal cca _ confirm, completes the transmission and reception of data according to the requirement of the current communication sequence, and controls the execution of the communication flow.
The bit width of the operation code op _ code is 5 bits, the encoding format is shown in table 1, and each encoded value corresponds to a communication sequence type.
TABLE 1 operation code op _ code encoding Table
The function of the decoding circuit is to decode the operation code op _ code and generate a communication request signal, and the correspondence between the communication request signal and the operation code op _ code is shown in table 2.
TABLE 2 communication request signal generation
The state machine controls the work flow of the communication sequence controller, fig. 3 depicts a state transition diagram of the state machine, and 11 work states are total: idle state idle, wait start state wait _ for _ start, idle channel detection state CCA, wait transmission state wait _ for _ TX, request data transmission state TX, wait response reception state wait _ for _ ack _ RX, response reception state ack _ RX, request data reception state RX, wait response transmission state wait _ for _ ack _ TX, response transmission state ack _ TX, and continuous reception state RX _ continuous.
In the idle state, the communication sequence controller does not execute any communication sequence, and each of the timer timing enable signal, the receiver enable signal rx _ en, the transmitter enable signal tx _ en, the idle channel detection enable signal cca _ en, the physical radio frequency reception enable signal phy _ rx _ en, and the physical radio frequency transmission enable signal phy _ tx _ en is inactive. When detecting that the tran _ start signal is valid and the time _ en signal is also valid, switching the state machine to a wait _ for _ start state, setting the start timer enable signal start _ timer _ en to be valid, and waiting for timing start; otherwise, when detecting that the tran _ start signal is effective and the CCA _ req signal is also effective, the state machine switches to the CCA state, and sets the clear channel detection timer enable signal CCA _ timer _ en to be effective to prepare for clear channel detection; otherwise, when detecting that the tran _ start signal is valid and the TX _ req signal is also valid, the state machine switches to the TX state, and sets the physical radio frequency transmission enable signal phy _ TX _ en and the transmitter enable signal TX _ en to be valid at the same time to prepare for data transmission; otherwise, when detecting that the tran _ start signal is valid and the RX _ req signal is also valid, the state machine switches to the RX state, and simultaneously sets the physical radio frequency reception enable signal phy _ RX _ en and the receiver enable signal RX _ en to be valid to prepare for data reception; otherwise, when it is detected that the tran _ start signal is valid and the rx _ req signal and the continuous signal are also valid, the state machine switches to the rx _ continuous state while the physical rf reception enable signal phy _ rx _ en and the receiver enable signal rx _ en are set to be valid, and it is ready to perform continuous data reception.
In the wait _ for _ start state, the communication sequence controller waits for the start timer to overflow, at which time the start timer enable signal start _ timer _ en remains valid, and the other timer enable signal, the receiver enable signal rx _ en, the transmitter enable signal tx _ en, the idle channel detection enable signal cca _ en, the physical radio frequency reception enable signal phy _ rx _ en, and the physical radio frequency transmission enable signal phy _ tx _ en are all invalid. When detecting that the start _ timeout signal is valid and the CCA _ req signal is also valid, the state machine switches to the CCA state, and simultaneously sets the start timer enable signal start _ timer _ en to be invalid, sets the idle channel detection timer enable signal CCA _ timer _ en and the idle channel detection enable signal CCA _ en to be valid, and prepares to perform idle channel detection; otherwise, if the start _ timeout signal is detected to be valid and the TX _ req signal is also valid, the state machine switches to the TX state, sets the start _ timer _ en to be invalid, sets the physical radio frequency transmission enable signal phy _ TX _ en and the transmitter enable signal TX _ en to be valid, and prepares to transmit data; otherwise, if it is detected that the start _ timeout signal is valid and the RX _ req signal is also valid, the state machine switches to the RX state, and simultaneously sets the start _ timer _ en to be invalid, sets the physical rf receive enable signal phy _ RX _ en and the receiver enable signal RX _ en to be valid, and prepares to perform data reception.
In the CCA state, the communication sequence controller performs clear channel detection, keeps the clear channel detection timer enable signal CCA _ timer _ en and the clear channel detection enable signal CCA _ en active, and all of the other timer enable signal, the receiver enable signal rx _ en, the transmitter enable signal tx _ en, the physical radio frequency reception enable signal phy _ rx _ en, and the physical radio frequency transmission enable signal phy _ tx _ en are inactive. When detecting that an idle channel detection timer overflow signal cca _ timeout and an idle channel state indication signal cca _ confirm are valid and a tx _ req signal is valid, the state machine switches to wait _ for _ tx state, and simultaneously sets a cca _ timer _ en signal and a cca _ en signal to be invalid, sets a transmission delay timer enable signal tx _ time _ en to be valid, and waits for transmission delay overflow; otherwise, if the cca _ confirm signal is detected to be invalid or the tx _ req signal is detected to be invalid, the state machine is switched to the idle state, meanwhile, the cca _ timer _ en signal and the cca _ en signal are set to be invalid, and the execution of the communication sequence is finished.
In the wait _ for _ tx state, the communication sequence controller waits for the transmission delay to overflow, keeps the transmission delay timer enable signal tx _ time _ en valid, and disables all of the other timer enable signal, the receiver enable signal rx _ en, the transmitter enable signal tx _ en, the idle channel detection enable signal cca _ en, the physical radio frequency reception enable signal phy _ rx _ en, and the physical radio frequency transmission enable signal phy _ tx _ en. When the sending delay timer overflow signal TX _ timeout is detected to be effective, the state machine is switched to a TX state, meanwhile, the sending delay timer enable signal TX _ time _ en is set to be ineffective, the physical radio frequency sending enable signal phy _ TX _ en and the sender enable signal TX _ en are set to be effective, and data sending is ready to be executed.
In the TX state, the communication sequence controller performs data transmission, keeps the physical radio frequency transmission enable signal phy _ TX _ en and the transmitter enable signal TX _ en active, and disables each of the timer enable signal, the idle channel detection enable signal cca _ en, the receiver enable signal rx _ en, and the physical radio frequency reception enable signal phy _ rx _ en. When detecting that the transmission end indication signal tx _ finish and the response data request signal ack _ req are valid, the state machine switches to the wait _ for _ ack _ rx state, and simultaneously sets the physical radio frequency transmission enable signal phy _ tx _ en and the transmitter enable signal tx _ en to be invalid, sets the reception response delay timer enable signal ack _ rx _ timer _ en to be valid, and prepares to wait for the reception response delay timer to overflow; otherwise, if the transmission end indication signal tx _ finish is detected to be valid and the response data request signal ack _ req is invalid, the state machine switches to the idle state, and simultaneously sets the physical radio frequency transmission enable signal phy _ tx _ en and the transmitter enable signal tx _ en to be invalid, and the execution of the communication sequence is ended.
In the wait _ for _ ack _ rx state, the communication sequence controller waits for the reception response delay time to overflow, keeps the reception response delay timer enable signal ack _ rx _ timer _ en active, and disables all of the other timer enable signals, the receiver enable signal rx _ en, the transmitter enable signal tx _ en, the clear channel detection enable signal cca _ en, the physical radio frequency reception enable signal phy _ rx _ en, and the physical radio frequency transmission enable signal phy _ tx _ en. When detecting that the reception response delay timer overflow signal ack _ rx _ timeout is valid, the state machine switches to the ack _ rx state, and simultaneously sets the reception response delay timer enable signal ack _ rx _ timer _ en to be invalid, sets the physical radio frequency reception enable signal phy _ rx _ en and the receiver enable signal rx _ en to be valid, and prepares to perform reception of response data.
In the ack _ rx state, the communication sequence controller performs response data reception, keeps the physical radio frequency reception enable signal phy _ rx _ en and the receiver enable signal rx _ en active, and disables each of the timer enable signal, the transmitter enable signal tx _ en, the idle channel detection enable signal cca _ en, and the physical radio frequency transmission enable signal phy _ tx _ en. When the reception end indication signal rx _ finish is detected to be valid, the state machine is switched to an idle state, and meanwhile, the physical radio frequency reception enable signal phy _ rx _ en and the receiver enable signal rx _ en are set to be invalid, and the execution of the communication sequence is ended.
In the RX state, the communication sequence controller performs data reception, keeps the physical radio frequency reception enable signal phy _ RX _ en and the receiver enable signal RX _ en active, and disables each of the timer enable signal, the transmitter enable signal tx _ en, the idle channel detection enable signal cca _ en, and the physical radio frequency transmission enable signal phy _ tx _ en. When detecting that the reception end indication signal rx _ finish and the response data request signal ack _ req are valid, the state machine switches to the wait _ for _ ack _ tx state, and simultaneously sets the physical radio frequency reception enable signal phy _ rx _ en and the receiver enable signal rx _ en to be invalid, sets the transmission response delay timer enable signal ack _ tx _ timer _ en to be valid, and prepares to wait for the transmission response delay timer to overflow; otherwise, if the reception end indication signal rx _ finish is detected to be valid and the response data request signal ack _ req is not valid, the state machine switches to the idle state, and simultaneously sets the physical radio frequency reception enable signal phy _ rx _ en and the receiver enable signal rx _ en to be invalid, and the execution of the communication sequence is ended.
In the wait _ for _ ack _ tx state, the communication sequence controller waits for the transmission response delay time to overflow, keeps the transmission response delay timer enable signal ack _ tx _ timer _ en active, and disables all of the other timer enable signals, the receiver enable signal rx _ en, the transmitter enable signal tx _ en, the clear channel detection enable signal cca _ en, the physical radio frequency reception enable signal phy _ rx _ en, and the physical radio frequency transmission enable signal phy _ tx _ en. When detecting that the transmission response delay timer overflow signal ack _ tx _ timeout is valid, the state machine switches to the ack _ tx state, and simultaneously sets the transmission response delay timer enable signal ack _ tx _ timer _ en to be invalid, sets the physical radio frequency transmission enable signal phy _ tx _ en and the transmitter enable signal tx _ en to be valid, and prepares to execute the transmission of the response data.
In the ack _ tx state, the communication sequence controller performs response data transmission, keeping the physical radio frequency transmission enable signal phy _ tx _ en and the transmitter enable signal tx _ en active, and keeping the timer enable signal, the receiver enable signal rx _ en, the idle channel detection enable signal cca _ en, and the physical radio frequency reception enable signal phy _ rx _ en inactive. When the sending end indication signal tx _ finish is detected to be effective, the state machine is switched to an idle state, meanwhile, the physical radio frequency sending enabling signal phy _ tx _ en and the sending machine enabling signal tx _ en are set to be ineffective, and the execution of the communication sequence is ended.
In the rx _ continuous state, the communication sequence controller performs continuous data reception, keeping the physical radio frequency reception enable signal phy _ rx _ en and the receiver enable signal rx _ en active.
In any idle state, if it is detected that the communication termination signal tran _ abort is valid, the state machine switches to the idle state, and simultaneously disables all of the timer timing enable signal, the receiver enable signal rx _ en, the transmitter enable signal tx _ en, the idle channel detection enable signal cca _ en, the physical radio frequency reception enable signal phy _ rx _ en, and the physical radio frequency transmission enable signal phy _ tx _ en, thereby ending the execution of the communication sequence.
Claims (5)
1. The WIA-PA communication sequence controller supporting automatic construction of multiple communication sequences is characterized by comprising a decoding circuit, a state machine and a timer group which are sequentially connected;
the decoding circuit is used for receiving an operation code which defines the type of a communication sequence and is sent by the processor, resolving the operation code into a communication request signal and sending the communication request signal to the state machine;
the state machine is used for controlling the opening and closing of a timer, a receiver, a transmitter and a physical radio frequency circuit in the timer group according to the communication request signal, completing the transceiving of data according to the requirement of the current communication sequence and controlling the execution of the communication flow; the transmitter, the receiver and the physical radio frequency circuit are connected;
and the timer group is used for timing each time parameter in the communication sequence, receiving a timing enabling signal of the state machine and generating a timing overflow indicating signal to the state machine.
2. The WIA-PA communication sequence controller supporting automatic construction of multiple communication sequences of claim 1, wherein the timer set comprises:
the starting timer is used for starting timing of a communication sequence, receiving a starting timing enabling signal of the state machine and generating a starting timing overflow indicating signal to the state machine;
an idle channel detection timer, which is used for timing the time length for executing the idle channel detection; receiving an idle channel detection timing enabling signal of the state machine, and generating an idle channel detection timing overflow indicating signal to the state machine;
a sending delay timer for timing the delay from the end of the idle channel detection execution to the start of the request data sending; receiving a sending delay timing enabling signal of the state machine, and generating a sending delay timing overflow indicating signal to the state machine;
a response transmission delay timer for timing the delay from the completion of the reception of the request data to the start of the transmission of the response data; receiving a sending response delay timing enabling signal of the state machine, and generating a sending response delay timing overflow indicating signal to the state machine;
a response receiving delay timer for timing the delay from the completion of the transmission of the request data to the start of the reception of the response data; and receiving a receiving response delay timing enable signal of the state machine, and generating a receiving response delay timing overflow indication signal to the state machine.
3. The WIA-PA communication sequence controller supporting automatic construction of multiple communication sequences of claim 2, wherein:
a communication starting signal end, a communication termination signal end, an idle channel detection request signal end, a sending request signal end, a receiving request signal end, a data response request signal end, a timing starting request signal end and a continuous receiving indication signal end of the state machine are connected with the output end of the decoding circuit;
a timing enable signal interface and a timing overflow indication signal interface of the state machine are connected with a timer group;
the receiver enabling signal end and the receiving end indicating signal end of the state machine are connected with the control end of the receiver; the transmitter enabling signal end and the transmission ending indication signal end are connected with the control end of the transmitter; the physical radio frequency receiving enabling signal end, the physical radio frequency transmitting enabling signal end, the idle channel detection enabling signal end and the idle channel state indicating signal end are connected with the physical radio frequency circuit.
4. The WIA-PA communication sequence controller supporting automatic construction of multiple communication sequences according to claim 3, wherein the timing enable signal interface comprises a start timing enable signal terminal, an idle channel detection timing enable signal terminal, a transmit delay timing enable signal terminal, a transmit response delay timing enable signal terminal, and a receive response delay timing enable signal terminal, which are respectively connected to each timer in the timer group.
5. The WIA-PA communication sequence controller supporting automatic construction of multiple communication sequences according to claim 3, wherein the timing overflow indication signal interface comprises a start timing overflow indication signal terminal, an idle channel detection timing overflow indication signal terminal, a transmit delay timing overflow indication signal terminal, a transmit response delay timing overflow indication signal terminal, and a receive response delay timing overflow indication signal terminal, which are respectively connected with each timer in the timer group.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410566359.5A CN105527884B (en) | 2014-10-22 | 2014-10-22 | Support the WIA-PA communication sequence controllers that more communication sequences are built automatically |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410566359.5A CN105527884B (en) | 2014-10-22 | 2014-10-22 | Support the WIA-PA communication sequence controllers that more communication sequences are built automatically |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105527884A CN105527884A (en) | 2016-04-27 |
| CN105527884B true CN105527884B (en) | 2018-07-31 |
Family
ID=55770176
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410566359.5A Active CN105527884B (en) | 2014-10-22 | 2014-10-22 | Support the WIA-PA communication sequence controllers that more communication sequences are built automatically |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105527884B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1728714A (en) * | 2004-07-27 | 2006-02-01 | 邓里文 | Method for mutual communication between IPv4 network and IPv6 network |
| CN103733185A (en) * | 2011-05-16 | 2014-04-16 | 谈呀有限公司 | Multi-data type communications system |
| CN103945444A (en) * | 2013-01-18 | 2014-07-23 | 安立股份有限公司 | Scenario generation device and scenario generation method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100325040A1 (en) * | 2009-06-23 | 2010-12-23 | Craig Stephen Etchegoyen | Device Authority for Authenticating a User of an Online Service |
-
2014
- 2014-10-22 CN CN201410566359.5A patent/CN105527884B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1728714A (en) * | 2004-07-27 | 2006-02-01 | 邓里文 | Method for mutual communication between IPv4 network and IPv6 network |
| CN103733185A (en) * | 2011-05-16 | 2014-04-16 | 谈呀有限公司 | Multi-data type communications system |
| CN103945444A (en) * | 2013-01-18 | 2014-07-23 | 安立股份有限公司 | Scenario generation device and scenario generation method |
Non-Patent Citations (1)
| Title |
|---|
| 第四十三讲符合WIA-PA标准的工业无线芯片关键技术研究;王剑等;《仪器仪表标准化与计量》;20140226(第1期);第18-23页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105527884A (en) | 2016-04-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110417930B (en) | Automatic allocation method for serial device communication address | |
| CN110958668B (en) | Terminal state conversion method, network equipment and terminal | |
| CN111277478B (en) | RS485 bus multiplexing control method based on slave devices with different baud rates | |
| US20130176876A1 (en) | Radio communication terminal device and radio communication terminal device control method | |
| CN204652678U (en) | A kind of wired home controls gateway | |
| JP2013531822A (en) | Power management method and apparatus for network access module | |
| CN102598805A (en) | Communication device, communication system, communication device control method, and communication device control program | |
| EP2852214A1 (en) | Method, system, ue, and network device for reporting user equipment mobility parameter | |
| CN104469905A (en) | Method and system for reducing idle power consumption of NFC chip | |
| CN104411003A (en) | Dormancy wakeup control method and system of wireless communication equipment | |
| CN105261199A (en) | Infrared data coding and decoding method and apparatus thereof | |
| CN101645752B (en) | Automatic detection system and automatic detection method of communication protocol | |
| CN105553805B (en) | Main website power down protection system and method in CAN network | |
| EP3024160A1 (en) | Control method, device and optical transceiver | |
| CN110138761B (en) | MIPI (Mobile industry processor interface) protocol-based inter-device communication method and equipment topological structure | |
| CN109640304B (en) | Method for improving low-power-consumption Bluetooth connection stability | |
| CN104251536A (en) | One-to-many current loop communication method and communication device | |
| CN201860324U (en) | Multifunctional wireless apparatus | |
| CN105527884B (en) | Support the WIA-PA communication sequence controllers that more communication sequences are built automatically | |
| KR101082333B1 (en) | Apparatus and method for controlling operation state of physical layer | |
| CN109800201B (en) | Driving method for RS485 real-time receiving and transmitting control based on linux | |
| CN102736951B (en) | A method and an apparatus for calling a module | |
| CN208477514U (en) | A kind of SPI of intelligent temperature controller turns the analog circuit of UART | |
| CN109673044A (en) | Communication control method, chip, the gateway apparatus of chip | |
| CN111132279A (en) | Communication method and device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |