CN105452985A

CN105452985A - Power supply diagnostic strategy

Info

Publication number: CN105452985A
Application number: CN201480042821.XA
Authority: CN
Inventors: K·K·卡特拉克
Original assignee: TRW Automotive US LLC
Current assignee: ZF Active Safety and Electronics US LLC
Priority date: 2013-07-30
Filing date: 2014-07-30
Publication date: 2016-03-30
Anticipated expiration: 2034-07-30
Also published as: DE112014003506T5; WO2015017590A1; CN105452985B

Abstract

A power supply diagnostic strategy for discrete power supply diagnostic states is independent of the underlying memory structure. The values used in the associated algorithm are selected to ensure that random linked failures will be detected. This applies to planar memory structures with 1, 2, 4, 6, 8, 12, and 16 common lattices, or physical memory structures with individual bit dispersed memories with 1, 2, 4, 6, 8, 12, and 16 consecutive bit splices. Further, the strategy provides that the various monitored voltage tables remains distinct even with compiler optimization activated.

Description

Electric power supply Diagnostic Strategy

The cross reference of related application

This application claims the U.S. Provisional Application No.61/860 submitted on July 30th, 2013, the rights and interests of 032.The whole of this application are openly incorporated herein by reference.

Background technology

The present invention relates generally to and analyze and monitor discrete electric power supply diagnostic state and particularly relate to the method for anacom microprocessor system voltage.

The storer random hardware fault linked can be there is along the edge in flat memory or grid.In planar memory structures, 1,2,4,6,8,12 and 16 common grid can be had.Such as, when wantonly 22 other parallel strips together with flat memory of flat memory are back-to-back set up time there is 4 grids or edge.Planar memory structures grid is typically used by CISC (sophisticated vocabulary controller).

The storer random hardware fault of link may be there is when time in the multiplexed physical storage for disperseing of row using one or more.In existing dispersion memory construction, the row can with 1,2 and 4 are multiplexed.When one rank multiplexed for " n " individual address time, there is the possibility of physical dispersion storage failure of 1 and 2 link.Rank multiplexed for 2 and 4, the physical dispersion storage failure of similar link is possible.In addition, the storage failure of 6,8,12 or 16 links may be there is in the storer of physical dispersion.

Summary of the invention

For monitoring the method for discrete electric power supply diagnostic state independent of underlying memory structure in the present invention.Method described by utilization, the value of choice for use is to guarantee random hardware break links to be detected.This is applicable to the planar memory structures with 1,2,4,6,8,12 and 16 common grid, or has the physical memory structure of the single position dispersion storer having 1,2,4,6,8,12 and 16 continuous position splicing.

According to an aspect of the present invention, provide the method for the state for diagnostic work voltage, the method comprises the following steps: that (a) makes purpose processor read work voltage and determine in following state: (1) "No" superpotential (OV), "No" under-voltage (UV); (2) "No" OV, "Yes" UV; (3) "Yes" OV, "No" UV or (4) "Yes" OV, "Yes" UV; (b) in the step (a) mark state in each distribute different byte value, the different value wherein selected has the Hamming distance of at least 4 between function and fault mode value; And the operational state value corresponding with the mode of operation determined is stored in the designated memory position of processor by (c).The each different byte value of step (b) can comprise high-order effective half-word joint (USNb) and low level effective half-word joint (LSNb), and wherein all USNb are different and are chosen as the Hamming distance with at least 2, and all LSNb are different and are chosen as the Hamming distance with at least 2.Preferably, select each USNb and LSNb from the imbalance collection of nibble value, and select each in USNb and LSNb not to be complement code each other to make them for each different value.Before step (c), can for the byte value different from the matching check of in one group of definition value, and if there is coupling, if then different byte value is stored as operational state value and does not mate, then store independent " not mating " value.In addition, preferably, the different byte values of step (b) are the low bytes of word and comprise for word distributes the step of upper byte value, upper byte value comprises USNb and LSNb, and wherein in USNb and LSNb one be another in the voltage identification symbol of monitoring and USNb and LSNb is control/diagnosis path identifier.For upper byte, select each USNb and LSNb from the balance collection of nibble value.Even if use upper byte to guarantee that Compiler Optimization activates, each monitoring voltage table also keeps different.

According to another aspect of the present invention, provide the method for the state for diagnostic work voltage, the method comprises:

A () makes purpose processor read work voltage and determines in following state of a control: (1) "No" OV, "No" UV; (2) "No" OV, "Yes" UV; (3) "Yes" OV, "No" UV or (4) "Yes" OV, "Yes" UV;

Each in b state of a control that () is identification in step (a) distributes different control byte value;

C the operation state of a control value corresponding with the mode of operation determined is stored in the specified control memory location of processor by ().

D () uses the processor read work voltage of step (a) and determines in following diagnostic state: (1) "No" OV, "No" UV; (2) "No" OV, "Yes" UV; (3) "Yes" OV, "No" UV or (4) "Yes" OV, "Yes" UV;

Each in e state that () is identification in step (d) distributes different diagnosis byte value;

F the operation diagnostic state value corresponding with the mode of operation determined is stored in the appointment diagnostic memory position of processor by (); And

G operation state of a control value is compared whether be suitable for the middle diagnosis voltage status read of step (d) with the control voltage state read in determining step (a) with operation diagnostic state value by ().

In the method, different control byte and diagnosis byte is provided based on complementary nibble " mirror image " value.The each different control byte values of step (b) comprise USNb and LSNb, and all USNb and LSNb are different.Similarly, each difference diagnosis byte value of step (f) comprises USNb and LSNb, and all USNb and LSNb are also different.Preferably, USNb and the LSNb specular of USNb and LSNb about corresponding control byte value of byte value is diagnosed.In a version, USNb and LSNb of diagnosis byte value is compared with mirror image USNb and LSNb of corresponding control byte value.In another version, such as when processor have single bit error correct and double bit error detect (SECDED) time, by diagnose byte value USNb and LSNb in only one compare with in mirror image USNb and LSNb of corresponding control byte value.

Preferably, before step (c), for from one group of different control byte value of matching check defining of controlling in controlling value, and if there is coupling, if then different control byte value is stored as operation state of a control value and does not mate, then store independent " not mating " controlling value.Similarly, before step (f), for the different diagnosis byte value of the matching check of defined from a group in diagnostic value, and if there is coupling, if then different diagnosis byte value is stored as operation diagnostic state value and does not mate, then store independent " not mating " diagnostic value.

According to additional aspects of the present invention, provide analysis electric power supply system and comprise method, wherein to first processor source of supply input voltage and generate output voltage by first processor, the method comprises the following steps: that (a) uses first processor to determine the source mode of operation of described source input voltage; B () uses the second processor to determine the output function state of the output voltage from first processor; C () is to the second processor transmission source mode of operation; And (d) makes purpose processor analysis source and output state to diagnose according to source and output state certainty annuity.Preferably, do not use School Affairs or cyclic redundancy check (CRC) (CRC) to the second processor transmission source mode of operation.

When reading with reference to the accompanying drawings, by the following detailed description of preferred embodiment, various aspect of the present invention will become apparent those skilled in the art.

Accompanying drawing explanation

Fig. 1 shows the block diagram of an example of the operating environment of the electric power supply architecture for implementing the principle of the invention, and wherein the present invention is used as the electric power supply with multiple vehicle control system;

Fig. 2 is the block diagram of a part for the electric power supply supervisory system of Fig. 1;

Fig. 3 shows the balance collection 1 and the uneven representative table collecting the method for 2 that one group of binary nibble value to be divided into for the value forming low byte;

Fig. 4 shows the form of the various nibble values that can be used for formation control word or diagnostic sampling word;

Fig. 5 shows the form of the various embodiments of the low byte word value can selecting the voltage status identifying four monitoring;

Fig. 6 is the embodiment of the method being similar to Fig. 5, and it comprises and illustrates and select high-order effective half-word joint and low level effective half-word to save with the row forming low byte value;

Fig. 7 is another embodiment again of the method being similar to Fig. 6, and this embodiment comprises the row showing and store control store value, and method comprises the judgement depending on that state of a control value is mated with definition value or departed from;

Fig. 8 is the embodiment of the method being similar to Fig. 7, also add diagnosis path form;

Fig. 9 is the embodiment of the method being similar to Fig. 7, also for the first monitoring voltage (Va) form of Fig. 7 adds the second monitoring voltage (Vb) form;

Figure 10 a and Figure 10 b illustrates the control form of monitoring voltage Va and Vb and the combination of diagnosis form;

Figure 11 is the process flow diagram of the algorithm being configured to the method preventing systematicness mistake when electric power supply state being stored in memory location;

Figure 12 comprises determining that electric power supply mistake occurs wherein and whether this mistake is the process flow diagram of the embodiment of the method for systematic diagnosis methods;

Figure 13 a and Figure 13 b illustrates the combination of control form and the diagnosis form being similar to Figure 10 a and Figure 10 b, shows the control and diagnosis storing value that use when the microprocessor associated comprises single bit error correction and double bit error detects (SECDEC).

Embodiment

The present invention relates to the various embodiments of carrying out efficient allocation and failure safe monitoring for the electric power in micro controller system.Although various embodiment is specially adapted to vehicle application (comprising automobile and truck), should easy understand the present invention and various embodiment thereof can control to apply for other having similar operations to require individually or jointly.In one application, in electric power supply architecture (MultipleASILOptimizedPowerSupply) middle use the present invention that the many ASIL for the supervision input processing (radar, video camera etc.) of driver assistance system and the electronic control module of output order (engine torque, driving torque, steering angle or moment of torsion, brake command or moment of torsion, suspend command etc.) optimize.Various invention is provided for integrated approach or the device of electronic package Security Architecture, and this electronic package Security Architecture comprises diversity, the Time and place independence of the electric power supply for different ASIL microprocessor and Vehicle communications bus.

With reference now to accompanying drawing, illustrate the block diagram of an example of the operating environment that the electric power supply architecture implementing the principle of the invention is shown in FIG, wherein the present invention is used as the electric power supply in vehicle control system.Usually, with reference to Fig. 1, the function aspects of the electric power supply architecture of many ASIL optimizations of electronic package can characterize as follows:

A. the supervision input processing for driver assistance system and two the high integrality ASILD compatible microprocessors (1A and 1B) exporting order are comprised.

B. from two to or more multipair vehicle communication bus (CAN, Flexray etc.) receive input processing and export command information.These communication buss transmit high integrality information.Each external bus type has complementary role (if in them is cut off).As depicted in figs. 1 and 2, each communication bus receives electric power from separately and independently electric power supply.

C. other high-throughput process microprocessor (microprocessor 2A) with external memory storage is comprised.Microprocessor 2A can have quality management (non-ASIL) hardware requirement.Alternatively, microprocessor 2A can have the appointment of higher level, such as ASILB.

D. microprocessor 1A and 2A can be mainly used in controlling and microprocessor 1B can be mainly used in checking microprocessor 1A and 2A.

E., in an alternative, microprocessor 1B is for controlling minimum function collection and microprocessor 1A for checking these functions.

F. independence between microprocessor (microprocessor 2A) is managed for external microprocessor hardware provides 2 high integrality automotive safety level of integrity (ASILD) microprocessor (1A and 1B) and have high-throughput Disposal quality that ASILB monitors.

Fig. 2 shows the exemplary power supply supervisory system represented according to a part for the electric power supply architecture of Fig. 1 of one or more in the principle of the invention disclosed herein.Fig. 2 comprises some voltage to generate schematically showing of source and two voltage monitoring microprocessors (by microprocessor " A " and microprocessor " B " expressions).Battery and switching regulaor provide initial voltage source for system.According to the state of institute's monitoring voltage, this source is monitored by the external circuit producing discrete superpotential/under-voltage output.The output of this watch-dog is read by microprocessor A.The electrical management IC (PMIC) powered by switching regulaor generates other independent voltage source, and each in this independent voltage source is monitored by OV/UV watch-dog and read by microprocessor A.Microprocessor A has the ability using the electric power provided by switching regulaor and PMIC to generate other independent voltage source.The voltage generated by microprocessor A is read by OV/UV supervisory circuit by microprocessor B.When PMIC cannot provide electric power to microprocessor A, one or more voltage generated from microprocessor A also will failure.When switching regulaor cannot provide electric power to PMIC and microprocessor, the voltage results from all generations of PMIC and microprocessor will failure.

As used herein, term " position ", " byte ", " nibble " and " word " to be applied in the context of computer programming and operating system and to apply like that as those terms understood in calculating field.With reference to Fig. 3, show diagram and how to select one whole group of binary nibble value (altogether 16) and the representative table being divided into collection 1 and collection 2 subsequently.As will be described, collection 1 is for the formation of the upper byte of word, and collection 2 is for the formation of the low byte of word.Especially, collection 1 is balance, means that each nibble comprises even number 1 and/or 0.Collection 2 is unbalanced, means that each nibble comprises odd number 1 and/or 0.Select each concentrated value with the Hamming distance making them have to be at least 2, mean and in collection, another value will be moved to from a value, at least 2 necessary changes values in positions.Figure 3 illustrates corresponding decimal value and the hexadecimal value of each nibble equally

With reference to Fig. 4, show in a tabular form and how the upper byte selected in the value from collection 1 and the low byte selected from the value of collection 2 are combined with formation control word or diagnostic sampling word.Especially, the high-order effective half-word of upper byte saves the specific voltage in mark current monitor.As will be discussed, the low level effective half-word of upper byte is saved in identifying specific word is " control " word or " diagnosis " word.As will be discussed, low byte is for identifying the state of the specific voltage of current monitor.

With reference to Fig. 5, illustrate the abridgment of table of the example of the low byte value of Fig. 4 that the voltage status selected to identify four monitoring is shown: (1) "No" superpotential, "No" under-voltage; (2) "No" superpotential, "Yes" under-voltage; (3) "Yes" superpotential, "No" under-voltage; And (4) "Yes" superpotential, "Yes" under-voltage.For representing that the low byte of state of a control value distributes different hexadecimal value (such as respectively corresponding with state (1) to (4) 74, B2, D1 and E8).

Fig. 6 is similar to Fig. 5, but is the increase in illustrate how to select high-order effective half-word joint and low level effective half-word joint with the row forming low byte value.Especially, select both the high-order effective half-word joint of low byte and low level effective half-word save from the imbalance collection 2 of Fig. 3.The high-order effective half-word joint of low byte comprises and is such as worth 7, B, D and E, and they have the Hamming distance of 2.The low level effective half-word joint of low byte comprises and is such as worth 4,2,1 and 8, and they also have the Hamming distance of 2.When combining to form low byte, should be appreciated that four different low bytes have the Hamming distance of 4.It is also understood that low byte preferably includes high-order effective half-word joint and low level effective half-word joint, they are not complement codes each other.

Fig. 7 is similar to Fig. 6, but is the increase in illustrate how whether to mate definition value to store the row of controlling value according to state of a control value.After reading voltage Va, algorithm inspection is determining whether monitored value drops in definition value group (be in the figure 7 74, B2, D1 and E8).If so, then the analog value corresponding with measured voltage status is stored.If not, then algorithm stores another value selected, and such as, F0, instruction state of a control value drops on the outside of four expectation value groups.

Fig. 8 is similar to Fig. 7, but adds diagnosis path form for the controllability path form of Fig. 7.In fig. 8, for controllability path adds the row of the upper byte that controllability path word is shown.In addition, another form representing diagnosis path is added.In controllability path, the USNb (such as, 3) of upper byte value is corresponding with the specific voltage Va of current monitor.Voltage of other monitoring will be identified by different value, another in the USNb value of the upper byte listed in such as Fig. 4.The LSNb of high-order control byte value is depicted as F---and word is designated and is associated with controllability path by this.

In fig. 8, although diagnosis path form follows the form of controllability path form, some important difference are had.Low byte has specific importance, its have for the control byte of identical corresponding voltage state " mirror " as value.See, such as, for "No" superpotential, "No" under-voltage state, state of a control value is 74, and diagnostic state value is 47.Diagnosis " not mating " value is set to 0F, the mirror image of it still controls " not mating " value F0.In addition, (forms from 4) select USNb to control upper byte USNb (such as, A) to be different from.And the LSNb of diagnosis upper byte is set to 0, it is another value that can obtain from the respective column Fig. 4.

Fig. 9 is similar to Fig. 7, but adds the second monitoring voltage (Vb) form for the first monitoring voltage (Va) form of Fig. 7.The unique difference that should be appreciated that between Va form and Vb form is the difference in the USNb of upper byte.For Va voltage table, USNb has the value of 3, and for Vb voltage table, USNb has the value of A.From Fig. 4, this two values have been have selected.It should be noted that and control upper byte and diagnose upper byte to be unique for each supply voltage that will monitor.This prevents modern Compiler Optimization algorithm and combination identical table (it may increase the impact of system design error).

Figure 10 a and 10b is the combination of Fig. 8 and Fig. 9 substantially.Therefore, show control form and the diagnosis form of monitoring voltage Va and Vb, value is wherein similar to those values in Fig. 8 and Fig. 9.

Figure 11 describes the process analyzed and store monitoring input.Independent controllability path and diagnosis path use the form described in Fig. 8 to read and store monitoring input individually.The event memory in these paths compares real hardware fault and systematic failure are distinguished the most at last.In step 100, place starts, and reads monitoring input by controllability path.Based on Fig. 8, in step 110 for word value distributes this input.In the step 120, algorithm confirms that word mates with definition value collection.If do not mated, then store " not mating " value in step 122 place for controlling low byte.Otherwise, step 124 place mask word upper byte and step 126 place contrast definition low byte value collection check low byte.If do not mate the byte value of definition, then again store " not mating " value in step 122 place for controlling low byte.Otherwise, in step 128 place, store matched bytes value for controlling low byte.

As represented by step 200-228, diagnosis path performs similar operations to controllability path.To be read by controllability path in the monitoring input of step 200 place and be that monitoring input distributes word in step 210 based on Fig. 8.The upper byte of diagnostic sampling word is unique for control upper byte, and wherein Hamming distance is 6.Diagnosis low byte is the complementary nibble " mirror image " controlling low byte, and wherein Hamming distance is 4.Check that in step 220 place diagnostic sampling word is to mate the efficient diagnosis word collection of definition.If do not mated, then in step 222 place, for diagnosis low byte stores " not mating " value.Therefore, also " not mating " value is stored for controlling low byte in step 250.This additional step allows diagnosis path functionally different from controllability path, and therefore by prevent modern compiler in order to optimize combinatorial path thus reduce the wrong risk of systematicness.If diagnostic sampling word is mated with definition value, then shield its upper byte (step 224), and compare low byte (step 226) relative to definition value.The low byte of not mating definition value is stored as diagnosis and " not mating " value controlling low byte.Otherwise matching value is stored as diagnosis low byte (step 228).

If control and diagnose path to store the low byte value of definition, then estimate that these bytes are the complementary nibble " mirror image " introduced in Fig. 8.If their couplings are " mirror image " in step 300, then control low byte and be stored as effective voltage state (step 310).If nibble is not mated for " mirror image ", then there is software or systemic mistake in the algorithm, and final for controlling low byte storage " not mating " value (step 320).

Figure 12 describes processor and uses the algorithm in Figure 10 and by the more multiple voltage monitor in independent diagnostics path with the process of the position of the reason and tracing trouble of determining tracing trouble.The flow chart describe a concrete condition of the fault in diagnostic graph 1, wherein analyze the input voltage of microprocessor A together with the output voltage from processor A.

In step 400 place, the source voltage to microprocessor A is read by microprocessor A itself.In step 500, the voltage that microprocessor B reads from the generation of processor A exports simultaneously.During step 410 and 510, two microprocessors perform the control/diagnosis algorithm described in Figure 10.In this embodiment of the invention, microprocessor B analyzes the diagnostic state of multiple voltage.Therefore, at step 420 which, the source voltage status stored in microprocessor A will be sent to microprocessor B.In this transmission, do not perform School Affairs or cyclic redundancy check (CRC) (CRC).This is the fact because the algorithm in Figure 10 prevents data/storer from damaging when not needing by using School Affairs or CRC to make transmission slow down.

By knowing which voltage failure and making the device of their faults, microprocessor B can the root of tracing trouble up hill and dale.Step 520 comprises the voltage status byte of microprocessor B analysis from two independent pathways in circuit.If two state bytes are good, then do not diagnose be out of order (step 530).If the output voltage of microprocessor A is bad, and the source voltage of microprocessor A is good, then diagnose out of order output voltage (step 540).If source voltage is bad and therefore output voltage fault, then diagnose out source voltage failure (step 550).Finally, if active and output algorithm fault, then diagnose out non-hardware fault (step 560), this non-hardware fault can be the reason of System design mistake.

Figure 13 a and Figure 13 b is similar to Figure 10 a and Figure 10 b, if but the microprocessor showing association has single bit error corrects and double bit error detects (SECDEC), the control form of Va and Vb and diagnose form.In this case, more whole low byte is not needed.And path and low byte USNb or LSNb can be diagnosed to compare by control.In order to by SECDEC microprocessor mitigation system mistake, preferably the USNB of the voltage supply for the treatment of device and the LSNb of the voltage supply being used for complementary processor are compared.As recorded in Figure 13 a and 13b, the USNb (such as, 7) that Va control store value (for no-no voltage status) is low byte, and Vb control store value is the LSNb (such as, 4) of low byte.Storing value is diagnosed for Va, uses the LSNb (such as, 7) of " mirror image " low byte.For Vb voltage diagnostic storing value, use the USNb (such as, 4) of the low byte of " mirror image ".

Explain in a preferred embodiment of the invention and illustrate principle of the present invention and operator scheme.But, must be clear, when not deviating from the present invention's spirit or scope, can be different from specific explanations and illustrated mode implements the present invention.

Claims

1., for a method for the state of diagnostic work voltage, described method comprises:

A () makes purpose processor read work voltage and determines in following state: (1) "No" OV, "No" UV; (2) "No" OV, "Yes" UV; (3) "Yes" OV, "No" UV or (4) "Yes" OV, "Yes" UV;

Each in b described state that () is identification in step (a) distributes different byte values, and wherein said different value is selected as the Hamming distance with at least 4; And

C the operational state value corresponding with determined mode of operation is stored in the designated memory position of described processor by ().

2. method according to claim 1, wherein each different byte value of step (b) comprises USNb and LSNb, and wherein all described USNb are different and are chosen as the Hamming distance with at least 2, and all described LSNb are different and are chosen as the Hamming distance with at least 2.

3. method according to claim 2, wherein concentrates each described USNb and LSNb of selection from the imbalance of nibble value.

4. method according to claim 3, wherein for each different value selects each in described USNb and LSNb not to be complement code each other to make them.

5. method according to claim 3, wherein the imbalance collection of nibble comprise hexadecimal value 1,2,4,7,8, B, D and E.

6. method according to claim 5, wherein from 7, USNb described in the group selection of B, D and E, and from 1,2,4 and 8 group selection described in LSNb.

7. method according to claim 6, wherein the described different value of step (b) comprise 74, B2, D1 and E8.

8. method according to claim 2, wherein before step (c), about the byte value different from described in the matching check of in one group of definition value, and if there is coupling, then described different byte value is stored as described operational state value, if and less than coupling, then store independent " not mating " value.

9. method according to claim 1, wherein the described different byte value of step (b) is the low byte of word and comprises for described word distributes the step of upper byte value, described upper byte value comprises USNb and LSNb, and in wherein said USNb and LSNb one be another in the voltage identification symbol of monitoring and described USNb and LSNb is control/diagnosis path identifier.

10. method according to claim 9, wherein concentrates each described USNb and LSNb selecting described upper byte from the balance of nibble value.

11. 1 kinds of methods for the state of diagnostic work voltage, described method comprises:

H () makes purpose processor read work voltage and determines in following state of a control:

(1) "No" OV, "No" UV; (2) "No" OV, "Yes" UV; (3) "Yes" OV, "No" UV or (4) "Yes" OV, "Yes" UV;

Each in i described state of a control that () is identification in step (a) distributes different control byte values;

J the operation state of a control value corresponding with determined mode of operation is stored in the specified control memory location of described processor by ();

K () uses the processor of step (a) read described operating voltage and determine in following diagnostic state: (1) "No" OV, "No" UV; (2) "No" OV, "Yes" UV; (3) "Yes" OV, "No" UV or (4) "Yes" OV, "Yes" UV;

Each in l described state that () is identification in step (d) distributes different diagnosis byte values;

M the operation diagnostic state value corresponding with determined mode of operation is stored in the appointment diagnostic memory position of described processor by (); And

N whether described operation state of a control value and described operation diagnostic state value compare with the described control voltage state read in determining step (a) consistent with the middle described diagnosis voltage status read of step (d) by ().

12. methods according to claim 11, wherein each different control byte value of step (b) comprises USNb and LSNb, and wherein all described USNb and LSNb are different.

13. methods according to claim 12, wherein each different diagnosis byte value of step (f) comprises USNb and LSNb, and wherein all described USNb and LSNb are different.

14. methods according to claim 13, described USNb and LSNb of wherein said diagnosis byte value gets mirror image about USNb and LSNb of the control byte value of correspondence.

15. methods according to claim 14, wherein compare USNb and LSNb of described diagnosis byte value with USNb and LSNb of the mirror image of corresponding control byte value.

16. methods according to claim 14, wherein by USNb and LSNb of described diagnosis byte value only one compare with in USNb and LSNb of the mirror image of corresponding control byte value.

17. methods according to claim 11, wherein before step (c), about the control byte value different from described in the matching check of in the controlling value that a group defines, and if there is coupling, then described different control byte value is stored as described operation state of a control value, if and less than coupling, then store independent " not mating " controlling value.

18. methods according to claim 11, wherein before step (f), about the diagnosis byte value different from described in the matching check of in the diagnostic value that a group defines, and if there is coupling, then described different diagnosis byte value is stored as described operation diagnostic state value, if and less than coupling, then store independent " not mating " diagnostic value.

19. 1 kinds of methods analyzing electric power supply system, wherein generate output voltage to first processor source of supply input voltage and by described first processor, described method comprises:

A () uses described first processor to determine the source mode of operation of described source input voltage;

B () uses the second processor to determine the output function state of the described output voltage from described first processor;

C () sends described source mode of operation to described second processor; And

D () uses described processor to analyze described source and output state with according to described source and the diagnosis of output state certainty annuity.

20. methods according to claim 19, wherein do not use School Affairs or cyclic redundancy check (CRC) to send described source mode of operation to described second processor.