CN105405825A - 一种覆晶薄膜封装结构 - Google Patents

一种覆晶薄膜封装结构 Download PDF

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CN105405825A
CN105405825A CN201510907024.XA CN201510907024A CN105405825A CN 105405825 A CN105405825 A CN 105405825A CN 201510907024 A CN201510907024 A CN 201510907024A CN 105405825 A CN105405825 A CN 105405825A
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石磊
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Nantong Fujitsu Microelectronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本发明公开了一种覆晶薄膜(COF)封装结构，包括柔性电路板、芯片，还包括导电胶层，柔性电路板的金属层通过所述导电胶层连接所述芯片的功能区。本发明提出一种新型结构，既能解决在现有结构中凸点(bump)高度难以控制且其制备工艺较难的问题，又能降低成本，提高封装效率。

Description

一种覆晶薄膜封装结构
技术领域
本发明涉及半导体技术领域，尤其涉及一种覆晶薄膜封装结构。
背景技术
随着集成电路技术的不断发展，电子产品越来越向小型化、智能化以及高可靠性方向发展，而集成电路封装直接影响着集成电路、电子模块乃至整机性能，在集成电路晶片尺寸逐步缩小、集成度不断提高的情况下，电子工业对集成电路封装结束提出了越来越高的要求。
目前的芯片通过底填方式倒装在作为载体的柔性电路板(薄膜)上，芯片与膜上覆盖的金属层通过金属柱相连，与外界电性连接。典型的覆晶薄膜(COF)封装结构中，IC通过金制的凸点(bump)与金属层相连，凸点(bump)采用的是柱状形式。
但在实际生产中，在芯片上制备较高的凸点(bump)时，存在一些影响芯片制造良率的问题：
(1)凸点(bump)的高度控制，IC芯片下方的凸点(bump)难以控制其高度完全一致，高低不平易使芯片失效；
(2)在膜上生产凸点(bump)其制备工艺较难。
发明内容
鉴于现有技术中的上述缺陷或不足，本发明提供一种覆晶薄膜(COF)封装结构，包括柔性电路板、芯片，还包括导电胶层，所述柔性电路板的金属层通过所述导电胶层连接所述芯片的功能区。
与现有技术相比，本发明的有益效果是：
本专利提出一种新型结构，既能解决在现有结构中bump高度难以控制且其制备工艺较难的问题，又能降低成本，提高封装效率。
附图说明
通过阅读参照以下附图所作的对非限制性实施例所作的详细描述，本申请的其它特征、目的和优点将会变得更明显：
图1为在芯片的功能区和柔性电路板的金属层都形成有金属凸点后采用导电胶柱连接的覆晶薄膜(COF)封装结构图；
图2为在芯片的功能区形成有金属凸点和柔性电路板的金属层形成有焊盘后采用导电胶柱连接的(COF)封装结构图；
图3为柔性电路板的金属层形成有凸点后采用导电胶柱连接芯片的功能区的覆晶薄膜(COF)封装结构图；
附图标记：
1-芯片；2-柔性电路板；3-导电胶柱；4-金属层；
5-第一金属凸点；6-第二金属凸点；7-焊盘
8-第三金属凸点；9-塑封体。
具体实施方式
下面结合附图和实施例对本申请作进一步的详细说明。可以理解的是，此处所描述的具体实施例仅仅用于解释相关发明，而非对该发明的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与发明相关的部分。
需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。下面将参考附图并结合实施例来详细说明本申请。
如图1，本发明提供一种覆晶薄膜(COF)封装结构，包括柔性电路板2、芯片1，还包括导电胶层，柔性电路板的金属层4通过导电胶层连接芯片的功能区。
本发明提出一种新型结构，既能解决在现有结构中bump高度难以控制且其制备工艺较难的问题，又能降低成本，提高封装效率。
如图1，进一步，本发明所提供的导电胶层为连接柔性电路板2的金属层4和芯片1的功能区的多个导电胶柱3。
如图2，进一步，本发明提供的覆晶薄膜(COF)封装结构，在芯片的功能区上形成的多个第一金属凸点5，第一金属凸点5与导电胶柱3一一对应，导电胶柱3一端连接第一金属凸点5，另一端连接所述柔性电路板金属层4。
通过芯片的功能区形成第一金属凸点压合导电胶柱，使得芯片的功能区与导电胶柱的接触面积增大，也有利于加压导电胶柱，从而增加了芯片与柔性电路板的通电性能。
如图1，进一步，本发明提供的覆晶薄膜(COF)封装结构，还包括在柔性电路板1的金属层4上形成的多个第二金属凸点6，第二金属凸点6位于金属层4的表面且与第一金属凸点5一一对应，第二金属凸点6与第一金属凸点5通过所述导电胶柱3电连接。
通过在柔性电路板形成第二金属凸点，增加了柔性电路板对外电性连接的面积，同时通过上下两金属凸点的连接、压合，更加提高了芯片与柔性电路板之间的导电性能。
如图1，进一步，本发明提供的导电胶柱3、第一金属凸点5和第二金属凸点6均为圆柱形，导电胶柱3的截面直径大于第一金属凸点5和第二金属凸点6的截面直径。这样保证了第一金属凸点和第二金属凸点的充分连接，提高了芯片与柔性电路板之间的导电性能。
如图2，进一步，本发明提供的覆晶薄膜(COF)封装结构，在柔性电路板2的金属层上形成的多个焊盘7，焊盘7与第一金属凸点5一一对应，导电胶柱3一端连接第一金属凸点5，另一端连接焊盘7。
通过在柔性电路板的金属层形成焊盘，增加了柔性电路板对外电性连接的面积，同时通过金属凸点和焊盘的连接、压合，更加提高了芯片与柔性电路板之间的导电性能。
如图3，进一步，本发明提供的覆晶薄膜(COF)封装结构，在柔性电路板的金属层4上还包括形成的多个第三金属凸点8，第三金属凸点8与导电胶柱3一一对应，导电胶柱3一端连接第三金属凸点8，另一端连接芯片1的功能区上。
上述结构简单，通过柔性电路板形成的第三金属凸点压合导电胶柱，使得柔性电路板与导电胶柱的接触面积增大，从而增加了芯片与柔性电路板的通电性能。
如图3，进一步，本发明提供的导电胶柱3和第三金属凸点8均为圆柱形，导电胶柱3的截面直径大于第三金属凸点8的截面直径。这样保证了通过第三金属凸点的对导电胶柱的良好压合，提高了芯片与柔性电路板之间的导电性能。。
如图1、图2、图3进一步，本发明提供的导电胶柱为异方向性导电胶(ACF)。这样保证了芯片和柔性电路板之间的电性连接，又可以防止芯片或柔性电路板内部之间的短路。
如图1、图2、图3进一步，本发明提供覆晶薄膜(COF)封装结构包括在芯片1与柔性电路板2之间填充塑封底材料形成的塑封体9。通过设置塑封体，更好的固定芯片，更好的保护芯片不受外力损坏，更好的起到了防潮、防湿的作用。
以上描述仅为本申请的较佳实施例以及对所运用技术原理的说明。本领域技术人员应当理解，本申请中所涉及的发明范围，并不限于上述技术特征的特定组合而成的技术方案，同时也应涵盖在不脱离所述发明构思的情况下，由上述技术特征或其等同特征进行任意组合而形成的其它技术方案。例如上述特征与本申请中公开的(但不限于)具有类似功能的技术特征进行互相替换而形成的技术方案。

Claims (10)

1.一种覆晶薄膜封装结构，包括柔性电路板、芯片，其特征在于，还包括导电胶层，所述柔性电路板的金属层通过所述导电胶层连接所述芯片的功能区。
2.根据权利要求1所述的覆晶薄膜封装结构，其特征在于，所述导电胶层为连接所述柔性电路板的金属层和所述芯片的功能区的多个导电胶柱。
3.根据权利要求2所述的覆晶薄膜封装结构，其特征在于，
还包括在所述芯片的功能区上形成的多个第一金属凸点，所述第一金属凸点与所述导电胶柱一一对应，所述导电胶柱一端连接所述第一金属凸点，另一端连接所述柔性电路板的金属层。
4.根据权利要求3所述的覆晶薄膜封装结构，其特征在于，还包括在所述柔性电路板的金属层上形成的多个第二金属凸点，所述第二金属凸点与所述第一金属凸点一一对应；
所述第二金属凸点与所述第一金属凸点通过所述导电胶柱电连接。
5.根据权利要求4所述的覆晶薄膜封装结构，其特征在于，所述导电胶柱、第一金属凸点和第二金属凸点均为圆柱形，所述导电胶柱的截面直径大于所述第一金属凸点和所述第二金属凸点的截面直径。
6.根据权利要求3所述的覆晶薄膜封装结构，其特征在于，还包括在所述柔性电路板的金属层上形成的多个焊盘，所述焊盘与第一金属凸点一一对应，所述导电胶柱一端连接所述第一金属凸点，另一端连接所述焊盘。
7.根据权利要求2所述的覆晶薄膜封装结构，其特征在于，还包括在所述柔性电路板的金属层上形成的多个第三金属凸点，所述第三金属凸点与所述导电胶柱一一对应，所述导电胶柱一端连接所述第三金属凸点，另一端连接所述芯片的功能区。
8.根据权利要求7所述的覆晶薄膜封装结构，其特征在于，所述导电胶柱和第三金属凸点均为圆柱形，所述导电胶柱的截面直径大于所述第三金属凸点的截面直径。
9.根据权利要求1-8任一所述的覆晶薄膜封装结构，其特征在于，所述导电胶柱为异方向性导电胶。
10.根据权利要求1-9任一所述的覆晶薄膜封装结构，其特征在于，还包括在芯片与柔性电路板之间填充塑封底材料形成的塑封体。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109904078A (zh) * 2019-01-22 2019-06-18 浙江铖昌科技有限公司 一种砷化镓芯片和cmos芯片三维封装结构和制作工艺
WO2022042472A1 (zh) * 2020-08-25 2022-03-03 维沃移动通信有限公司 芯片封装模组及电子设备

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