CN105405782B - A kind of monitoring method of source and drain epitaxy technique - Google Patents
A kind of monitoring method of source and drain epitaxy technique Download PDFInfo
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- CN105405782B CN105405782B CN201410409038.4A CN201410409038A CN105405782B CN 105405782 B CN105405782 B CN 105405782B CN 201410409038 A CN201410409038 A CN 201410409038A CN 105405782 B CN105405782 B CN 105405782B
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Abstract
The present invention provides a kind of monitoring method of source and drain epitaxy technique, comprising: provides the quality target value and its range of tolerable variance for being epitaxially formed the substrate after source-drain area；Substrate is provided, source and drain groove is formed on the substrate, and be epitaxially formed source-drain area in source and drain groove；Obtain the quality for being epitaxially formed the substrate after source-drain area；Judge the quality whether in the range of tolerable variance of quality target value.This method is intuitive, damages quickly and not to chip, without specific test structure, to effective monitoring of source and drain epitaxial manufacture process when suitable for volume production, effectively to control the quality for being epitaxially formed source and drain.
Description
Technical field
The present invention relates to field of semiconductor manufacture, in particular to a kind of monitoring method of source and drain epitaxy technique.
Background technique
With the continuous development of integrated circuit technique, to the performance of device, higher requirements are also raised.Currently, in addition to height
The application of k/ metal gate engineering is outer, also introduces source and drain stress engineering, in 45 nm technology nodes to further increase current-carrying
The mobility of son.
Source and drain stress engineering, i.e. source and drain trench process, main technological steps include: after forming gate structure 110,
The position for carrying out source and drain strain adjusted will be needed to be exposed by photoetching, can by dry etching or wet etch techniques,
Form groove 120, formed in the substrate of usual crystalline silicon be SigMa shape silicon trench 120, as shown in Figure 1, the silicon trench
Shape is since wet chemical etching technique is caused by silicon (100) and (111) selective corrosion；Then, pass through selective epitaxial skill
Art carries out the epitaxial growth of the source-drain area 130 of selectivity SiGe, since Ge atomic radius is greater than for PMOS in silicon trench
Silicon, therefore the SiGe of extension will be to PMOS ditch to action of compressive stress is generated, to promote the hole mobility of PMOS；For
NMOS carries out the epitaxial growth of the source-drain area 130 of selectivity SiC, in silicon trench to improve NMOS electron mobility, such as Fig. 2
It is shown.
After wet chemical etching technique goes out silicon slot, by being epitaxially formed the source-drain area of stress, such as SiGe or SiC, due to
Grid has been formed at this time, cannot be planarized using CMP process, for different designs, the source-drain area being epitaxially formed has
Maintain an equal level with substrate, some is higher than substrate, i.e. promotion source and drain, and can not pass through flat chemical industry for the uniformity of source-drain area thickness
Skill realizes that this just needs to carry out effective monitoring to the epitaxy technique of source and drain.
For this reason, it may be necessary to quick monitoring method that is intuitive and being suitable for volume production be proposed, whether to judge source and drain epitaxy technique
Reach technique requirement.
Summary of the invention
The purpose of the present invention aims to solve at least one of above-mentioned technological deficiency, provides a kind of monitoring side of source and drain epitaxy technique
Method is suitable for volume production and monitors, quickly and effectively.
For this purpose, the present invention provides the following technical scheme that
A kind of monitoring method of source and drain epitaxy technique, comprising:
The quality target value and its range of tolerable variance for being epitaxially formed the substrate after source-drain area are provided；
Substrate is provided, source and drain groove is formed on the substrate, and be epitaxially formed source-drain area in source and drain groove；
Obtain the quality for being epitaxially formed the substrate after source-drain area；
Judge the quality whether in the range of tolerable variance of quality target value.
Optionally, the step of quality target value is provided specifically: the substrate for measuring specific products is being epitaxially formed source-drain area
Quality afterwards determines that the quality of the substrate is matter by the thickness and/or crystal structure of the scanning electron microscope analysis substrate
Measure target value.
Optionally, the step of quality tolerance is provided specifically: measure other multiple batches of substrates of the specific products outside
Prolong the quality after forming source-drain area, obtains being epitaxially formed the mass change data after source-drain area, to determine range of tolerable variance.
In addition, the present invention also provides a kind of monitoring methods of source and drain epitaxy technique, comprising:
Offer is epitaxially formed source-drain area forward and backward target value of poor quality and its range of tolerable variance；
Substrate is provided, source and drain groove is formed on the substrate, obtains the first mass of the substrate；
It is epitaxially formed source-drain area in the source and drain groove, obtains the second mass of the substrate；
Judge the of poor quality whether in the range of tolerable variance of target value of poor quality of the second mass and the first mass.
Optionally, the step of target value of poor quality is provided specifically: the substrate for measuring specific products is being epitaxially formed source and drain
The forward and backward quality in area determines the substrate outside by the thickness and/or crystal structure of the scanning electron microscope analysis substrate
Prolong that form source-drain area forward and backward of poor quality for target value of poor quality.
Optionally, the step of tolerance of poor quality is provided specifically: other the multiple batches of substrates for measuring the specific products exist
It is being epitaxially formed the forward and backward quality of source-drain area, is obtaining being epitaxially formed the forward and backward delta data of poor quality of source-drain area, is being held with determining
Poor range.
The monitoring method of source and drain epitaxy technique provided in an embodiment of the present invention is epitaxially formed source-drain area back substrate by measurement
Quality, carry out indirect monitoring source and drain epitaxy technique and whether reach requirement, this method is intuitive, damages quickly and not to chip,
Without specifically testing structure, to effective monitoring of source and drain epitaxial manufacture process when suitable for volume production, it is epitaxially formed effectively to control
The quality of source and drain.
Detailed description of the invention
Above-mentioned and/or additional aspect and advantage of the invention will become from the following description of the accompanying drawings of embodiments
Obviously and it is readily appreciated that, in which:
Fig. 1-2 is the device schematic cross-section in source and drain stress engineering technical process；
Fig. 3 is the flow diagram according to the monitoring method of the source and drain epitaxy technique of the embodiment of the present invention one；
Fig. 4-5 is that the section of device during monitoring source and drain epitaxy technique according to the method for the embodiment of the present invention one is illustrated
Figure；
Fig. 6 is the flow diagram according to the monitoring method of the source and drain epitaxy technique of the embodiment of the present invention two.
Specific embodiment
The embodiment of the present invention is described below in detail, examples of the embodiments are shown in the accompanying drawings, wherein from beginning to end
Same or similar label indicates same or similar element or element with the same or similar functions.Below with reference to attached
The embodiment of figure description is exemplary, and for explaining only the invention, and is not construed as limiting the claims.
In the present invention, the monitoring method of the source and drain epitaxy technique provided, the matter after being epitaxially formed by measurement source and drain
Amount, comes whether indirect monitoring source and drain epitaxy technique reaches requirement, this is intuitive, quick and does not damage to chip, without specific
Test structure, suitable for effective monitoring to source and drain epitaxy technique, effectively to control the quality for being epitaxially formed source and drain.
In order to better understand the present invention, it is described below with reference to specific embodiment.
Embodiment one
It is monitored using the quality of the chip after being epitaxially formed source-drain area as target below with reference to Fig. 3-5 detailed description
Embodiment.
Firstly, providing the quality target value and its range of tolerable variance for being epitaxially formed the substrate after source-drain area.
In the device fabrication of common source and drain stress engineering, refering to what is shown in Fig. 4, firstly, being formed on substrate 200
Gate structure 210；Then, the etching of source and drain groove 220 is carried out；Then, it is epitaxially formed source-drain area 230 in source and drain groove, joins
It examines shown in Fig. 5.
In embodiments of the present invention, the substrate, i.e. chip can be Si substrate, SOI (silicon-on-insulator, Silicon
On Insulator) or GOI (germanium on insulator, Germanium On Insulator) etc..In other embodiments, described half
Conductor substrate can also be include substrate of other elements semiconductor or compound semiconductor, such as GaAs or InP etc., may be used also
Think laminated construction.
Wherein, gate structure 210 generally includes gate dielectric layer and gate electrode, can further include side wall, grid knot
Structure can be the structure of high k/ metal gate, i.e. gate dielectric layer is high K medium material, and gate electrode is metal gate electrode, high K medium material
Material, such as compared with silica, material or other suitable dielectric materials with high dielectric constant, high K medium material is for example
Hafnium base oxide, HFO2, HfSiO, HfSiON, HfTaO, HfTiO etc., metal gate electrode can be one or more layers structure, can
To include metal material or polysilicon or their combination, metal material such as Ti, TiAlx、TiN、TaNx、HfN、TiCx、TaCx
Etc..
In the present embodiment, the substrate 200 is silicon substrate, after wet etching, forms opening for similar hexagon
The source and drain groove 220 of mouth.By selective epitaxial technology, for PMOS, it is raw that selective SiGe extension can be carried out in the trench
It is long, for NMOS, selectivity SiC epitaxial growth is carried out in the trench, to form source-drain area 230, as shown in Figure 5.
In the present embodiment, it selects the chip of specific model product for sampling substrate, and measures it and be epitaxially formed source and drain
Quality behind area has been formed with gate structure and source-drain area on the substrate, as shown in Figure 5；Then, pass through scanning electron microscope
(SEM) or transmission electron microscope (TEM) analyzes the parameter of the source-drain area of the substrate, such as source-drain area in the secure execution mode (sem
Whether the crystalline state of thickness and crystal structure meets the requirements, and for satisfactory substrate, determines that its quality is quality objective
Value.
Then, other quality of multiple batches of chip after being epitaxially formed source-drain area for measuring the type product, in this way, obtaining
The mass change data of substrate after being epitaxially formed source-drain area determine quality range of tolerable variance (spec) according to these qualitative datas.
After the quality that multiple chips can also be obtained, the quality target value and quality of chip are obtained according to other algorithms
Range of tolerable variance.
Then, substrate is provided, source and drain groove is formed on the substrate, and be epitaxially formed source-drain area in source and drain groove.
In this step, i.e., the chip of the volume production of above-mentioned specific model product is monitored.Lining is ibid sampled in step
The determination of the quality at bottom forms source and drain groove on the chip of volume production, and is epitaxially-formed source-drain area in source and drain groove, joins
It examines shown in Fig. 5.
Then, the quality of the substrate after source and drain groove is formed is obtained.
The acquisition of the above substrate quality can be obtained by high-precision quality measurement equipment.
Finally, judging the quality whether in the range of tolerable variance of quality target value.
If volume production wafer quality is in the range of tolerable variance of quality target value, it is believed that source and drain epitaxy technique reaches technique
It is required that on the contrary, it is believed that source and drain epitaxy technique does not reach technique requirement, when continuous appearance does not reach the crystalline substance of technique requirement
When piece, it can be analyzed with further progress, and process conditions are adjusted.
Embodiment two
It is described in detail below with reference to Fig. 4-6 to be epitaxially formed the forward and backward reality of poor quality being monitored for target of source-drain area
Apply example.
Source-drain area forward and backward target value of poor quality and its range of tolerable variance are epitaxially formed firstly, providing.
In the device fabrication of common source and drain stress engineering, refering to what is shown in Fig. 4, firstly, being formed on substrate 200
Gate structure 210；Then, the etching of source and drain groove 220 is carried out；Then, it is epitaxially formed source-drain area 230 in source and drain groove, joins
It examines shown in Fig. 5.
As in the first embodiment, gate structure can be high k/ metal-gate structures.In the present embodiment, in selection specific model
Chip is after sampling chip, to obtain before carrying out being epitaxially formed source-drain area first, as shown in figure 4, forming source and drain groove 220
First mass of chip later；Then, epitaxial growth is carried out, as shown in figure 5, obtaining the of chip after forming source-drain area 230
Two mass；Then, by scanning electron microscope (SEM) or transmission electron microscope (TEM) to the ginseng of the source-drain area of the substrate
Number is analyzed, and whether the thickness of source-drain area and the crystalline state of crystal structure such as in the secure execution mode (sem meets the requirements, for conforming to
The substrate asked determines that its quality is quality target value.
Then, other the multiple batches of chips for measuring the type product are being epitaxially formed the forward and backward quality of source-drain area, in this way,
It obtains being epitaxially formed the forward and backward delta data of poor quality of source-drain area, according to these ropy data, determines tolerance model of poor quality
Enclose (spec).
After the quality for obtaining multiple chips, can also be obtained according to other algorithms chip target value of poor quality and
Range of tolerable variance of poor quality.
Then, the monitoring of the source and drain epitaxy technique of the volume production chip of the model is carried out.
Substrate is provided, source and drain groove is formed on the substrate, obtains the first mass of the substrate.
For the volume production chip of the type, the first mass of the substrate being epitaxially formed before source-drain area is first obtained, i.e., in shape
After source and drain groove 220, before being epitaxially formed source-drain area in source and drain groove, the quality of the substrate, with reference to shown in Fig. 4.
Then, it is epitaxially formed source-drain area in the source and drain groove, obtains the second mass of the substrate.
Second mass, i.e., be epitaxially formed after source-drain area 230 in source and drain groove, before next manufacturing process starts,
Refering to what is shown in Fig. 5, the quality of substrate.
Finally, judging the of poor quality whether in the range of tolerable variance of target value of poor quality of the second mass and the first mass.
If volume production wafer quality is in the range of tolerable variance of quality target value, it is believed that source and drain epitaxy technique reaches technique
It is required that on the contrary, it is believed that source and drain epitaxy technique does not reach technique requirement, when continuous appearance does not reach the crystalline substance of technique requirement
When piece, it can be analyzed with further progress, and process conditions are adjusted.
Although the present invention has been disclosed in the preferred embodiments as above, however, it is not intended to limit the invention.It is any to be familiar with ability
The technical staff in domain, without departing from the scope of the technical proposal of the invention, all using in the methods and techniques of the disclosure above
Appearance makes many possible changes and modifications or equivalent example modified to equivalent change to technical solution of the present invention.Therefore,
Anything that does not depart from the technical scheme of the invention are made to the above embodiment any simple according to the technical essence of the invention
Modification, equivalent variations and modification, all of which are still within the scope of protection of the technical scheme of the invention.
Claims (4)
1. a kind of monitoring method of source and drain epitaxy technique characterized by comprising
The quality target value and its range of tolerable variance for being epitaxially formed the substrate after source-drain area are provided；
The step of quality target value is provided specifically: measure quality of the substrate of specific products after being epitaxially formed source-drain area, lead to
The thickness of the source-drain area of the electron-microscopic analysis substrate and the crystalline state of crystal structure are over-scanned, determines that the quality of the substrate is
Quality target value；
Substrate is provided, source and drain groove is formed on the substrate, and be epitaxially formed source-drain area in source and drain groove；
Obtain the quality for being epitaxially formed the substrate after source-drain area；
Judge the quality whether in the range of tolerable variance of quality target value.
2. monitoring method according to claim 1, which is characterized in that the step of providing quality tolerance specifically: measurement
Other quality of multiple batches of substrate after being epitaxially formed source-drain area of the specific products, obtain being epitaxially formed the quality after source-drain area
Delta data, to determine range of tolerable variance.
3. a kind of monitoring method of source and drain epitaxy technique characterized by comprising
Offer is epitaxially formed source-drain area forward and backward target value of poor quality and its range of tolerable variance；
The step of target value of poor quality is provided specifically: the substrate for measuring specific products is being epitaxially formed the forward and backward matter of source-drain area
Amount determines that the substrate exists by the thickness of the source-drain area of the scanning electron microscope analysis substrate and the crystalline state of crystal structure
It is forward and backward of poor quality for target value of poor quality to be epitaxially formed source-drain area；
Substrate is provided, source and drain groove is formed on the substrate, obtains the first mass of the substrate；
It is epitaxially formed source-drain area in the source and drain groove, obtains the second mass of the substrate；
Judge the of poor quality whether in the range of tolerable variance of target value of poor quality of the second mass and the first mass.
4. monitoring method according to claim 3, which is characterized in that the step of providing tolerance of poor quality specifically: survey
Other the multiple batches of substrates for measuring the specific products are being epitaxially formed the forward and backward quality of source-drain area, before obtaining being epitaxially formed source-drain area,
Delta data of poor quality afterwards, to determine range of tolerable variance.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7402207B1 (en) * | 2004-05-05 | 2008-07-22 | Advanced Micro Devices, Inc. | Method and apparatus for controlling the thickness of a selective epitaxial growth layer |
| US20090280579A1 (en) * | 2008-05-12 | 2009-11-12 | Advanced Micro Devices, Inc. | Method of controlling embedded material/gate proximity |
| CN102810492A (en) * | 2011-06-03 | 2012-12-05 | 中国科学院微电子研究所 | Processing procedure monitoring method after CMP for metal gate |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7402207B1 (en) * | 2004-05-05 | 2008-07-22 | Advanced Micro Devices, Inc. | Method and apparatus for controlling the thickness of a selective epitaxial growth layer |
| US20090280579A1 (en) * | 2008-05-12 | 2009-11-12 | Advanced Micro Devices, Inc. | Method of controlling embedded material/gate proximity |
| CN102810492A (en) * | 2011-06-03 | 2012-12-05 | 中国科学院微电子研究所 | Processing procedure monitoring method after CMP for metal gate |
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