CN105376581B - A kind of two-stage DCT coefficient storage method based on pointer suitable for HEVC standard - Google Patents
A kind of two-stage DCT coefficient storage method based on pointer suitable for HEVC standard Download PDFInfo
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- CN105376581B CN105376581B CN201510787965.4A CN201510787965A CN105376581B CN 105376581 B CN105376581 B CN 105376581B CN 201510787965 A CN201510787965 A CN 201510787965A CN 105376581 B CN105376581 B CN 105376581B
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Abstract
The invention belongs to high-definition digital video compression coding and decoding technical fields, specially a kind of two-stage DCT coefficient storage method based on pointer suitable for HEVC standard.DCT coefficient is divided into three parts by the present invention：Sign bit, high position data and low data, and the upper section of data bit is incorporated into as high position data, remaining bits incorporate into as low data；Simultaneously using SRAM as the first order in storage hierarchy, for stored symbols position, low data and the high bit pointer that can point at high position data；Using register as the second level in storage hierarchy, for storing the high position data that some need to store；And calculate that high bit pointer is gone forward side by side line index using counter.The present invention reduces hardware costs by the storage strategy of stratification.
Description
Technical field
The invention belongs to high-definition digital video compression coding and decoding technical field, it is specially a kind of suitable for HEVC standard two
Grade DCT coefficient storage method.
Background technology
HEVC（High Efficiency Video Coding）It is by International Telecommunication Union（ITU）And motion pictures expert
Group（MPEG）The next-generation video encoding and decoding standard that the tissue JCTVC that joint is set up is proposed.Target is in identical visual effect
Under the premise of, compared to previous generation standards, i.e., H.264/AVC standard, compression ratio double.
Video encoder based on HEVC, mainly by being formed with lower module：Intra prediction, inter-prediction, transformation, quantization,
Inverse quantization, inverse transformation, reconstruction, deblocking filter, the compensation of adaptive sampling point etc..Wherein, discrete cosine transform（DCT）It is coding
The essential part of device is responsible for concentrating the energy of residual error data, for subsequent quantization and entropy coding.Due to HEVC standard
The size of hypograph process block has had arrived at 64 × 64, discrete cosine transform（DCT）The size of process block also reaches 32 ×
32.This so that required Corner turn memory device becomes abnormal huge in common row-column transform framework, as shown in Figure 1.For such as
This huge storage demand, traditional based on register and based on Static RAM storage mode have become no longer
It is applicable in.
Invention content
It is an object of the invention to propose it is a kind of can be to overcome the deficiencies of the prior art, HEVC standard can be effectively applicable to
Two-stage discrete cosine transform（DCT）Coefficient storage method.
Two-stage DCT coefficient storage method proposed by the present invention suitable for HEVC standard is based on pointer, specific steps
For：
First, by discrete cosine transform（DCT）Coefficient（Hereinafter referred to as coefficient）, it is divided into three parts：Sign bit, seniority top digit
According to and low data.Under the mode of complement representation, the coefficient in HEVC standard can be indicated with 16 bits.Wherein, highest order
It is sign bit, remaining bits are data bit.And the further present invention incorporates the upper section of data bit for high position data into,
Remaining bits incorporate into as low data.Specific division methods can select different proportion, and as shown in Figure 2 draws high 11
For high position data, low 4 divide low data into.
Then, using static random-access memory（SRAM）As the first order in storage hierarchy, this level-one is used for depositing
Store up sign bit, low data and the high bit pointer that can point at high position data；Using register as second in storage hierarchy
Grade, this level-one are used for storing some high position datas for needing to store.
Herein, need whether all bits depended in the high position whether storage are equal to sign bit.In complement representation
Under, if a number close to 0, the higher several bits of the number all by be sign bit extension.And residual error is by discrete remaining
String converts（DCT）Later, a large amount of data all will be close to 0.For these numbers, as long as being aware of its sign bit, so that it may with
To high position data, therefore, they are It is not necessary to stored.The present invention arranges in this case, and high bit pointer is set
Specifically it is worth for one, such as 0.So, when the value of high bit pointer is the value, i.e., when 0, high position data is exactly the extension of sign bit.
And for needing to store high position data, then they will be by second level storage hierarchy, i.e. register stores, and uses counter
Calculate that high bit pointer is gone forward side by side line index.Storage hierarchy described above is as shown in Figure 3.
In order to simply establish index relative, the present invention may be used（But it is not limited only to）Use counter.It is still assumed that high
When bit pointer is equal to 0, the high position data corresponding to the pointer is the duplication of sign bit.So, when establishing index relative, hardware
A counter can be used to count the number for the high position data for needing to store.The counter is from 1 start recording, and if only if one
The high position data that a new needs store occurs, which is just stored in the deposit corresponding to nonce counter by hardware processor
In device, then counter increases 1 certainly.
The present invention reduces hardware costs by the storage strategy of stratification.
Description of the drawings
Fig. 1 is discrete cosine transform（DCT）With Corner turn memory device.
Fig. 2 is the division for coefficient.
Fig. 3 illustrates for two-level memory strategy.
Specific implementation mode
Below by example, the method for the present invention is further specifically described.
Assuming that currently needing 16 × 16 coefficient matrixes stored as shown in the table, and stored according to raster order.
So, the present invention will have following ablation process：
Under initial situation, all Static RAM（SRAM）Memory space with register is all 0, and counter is 1.
For the coefficient 24 of the 0th row the 0th row, the complement of two's two's complement corresponding to it is 0000_0000_0001_1000,
In, sign bit 0, high position data 000_0000_0001, low data 1000.Since high position data is not sign bit
Extension, therefore, high position data is stored in No. 1 register；Sign bit 0, pointer 1 and low data 1000 are stored in static state
Random access memory（SRAM）0 address in；Counter then from increasing 1, becomes 2.
For the coefficient 2 of the 0th row the 1st row, the complement of two's two's complement corresponding to it is 0000_0000_0000_0010, wherein
Sign bit is 0, high position data 000_0000_0000, low data 0010.Since high position data is the extension of sign bit,
It therefore, there is no need to store high position data；Sign bit 0, pointer 0 and low data 0010 are stored in Static RAM
（SRAM）1 address in；Counter is constant.
For the coefficient -7 of the 0th row the 2nd row, the complement of two's two's complement corresponding to it is 1111_1111_1111_1001,
In, sign bit 1, high position data 111_1111_1111, low data 1001.Since high position data is the expansion of sign bit
Exhibition therefore, there is no need to store high position data；Sign bit 1, pointer 0 and low data 1001 are stored in Static RAM
（SRAM）2 addresses in；Counter is constant.
For the coefficient -1 of the 0th row the 3rd row, the complement of two's two's complement corresponding to it is 1111_1111_1111_1111,
In, sign bit 1, high position data 111_1111_1111, low data 1111.Since high position data is the expansion of sign bit
Exhibition therefore, there is no need to store high position data；Sign bit 1, pointer 0 and low data 1111 are stored in Static RAM
（SRAM）3 addresses in；Counter is constant.
……。
For the coefficient 7 of the 1st row the 0th row, the complement of two's two's complement corresponding to it is 0000_0000_0000_0111, wherein
Sign bit is 0, high position data 000_0000_0000, low data 0111.Since high position data is the extension of sign bit,
It therefore, there is no need to store high position data；Sign bit 0, pointer 0 and low data 0111 are stored in Static RAM
（SRAM）16 addresses in；Counter is constant.
For the coefficient -17 of the 1st row the 1st row, the complement of two's two's complement corresponding to it is 1111_1111_1110_1111,
In, sign bit 1, high position data 111_1111_1110, low data 1111.Since high position data is not sign bit
Extension, therefore, high position data is stored in No. 2 registers；Sign bit 1, pointer 2 and low data 1111 are stored in static state
Random access memory（SRAM）17 addresses in；Counter then from increasing 1, becomes 3.
For the coefficient 21 of the 1st row the 2nd row, the complement of two's two's complement corresponding to it is 0000_0000_0001_0101,
In, sign bit 0, high position data 000_0000_0001, low data 0101.Since high position data is not sign bit
Extension, therefore, high position data is stored in No. 3 registers；Sign bit 0, pointer 3 and low data 0101 are stored in static state
Random access memory（SRAM）18 addresses in；Counter then from increasing 1, becomes 4.
……。
The present invention will have following readout：
For the coefficient 24 of the 0th row the 0th row, it is stored in Static RAM（SRAM）0 address, sign bit is
0, pointer is 1, and low data is 1000；Since pointer is 1, high position data is stored in No. 1 register, and content is
000_0000_0001.So last value is 0_000_0000_0001_1000, that is, 24.
For the coefficient 2 of the 0th row the 1st row, it is stored in Static RAM（SRAM）1 address, sign bit is
0, pointer is 0, and low data is 0010；Since pointer is 0, high position data is exactly the extension of sign bit, that is, 000_
0000_0000.So last value is 0_000_0000_0000_0010, that is, 2.
For the coefficient -7 of the 0th row the 2nd row, it is stored in Static RAM（SRAM）2 addresses, sign bit is
1, pointer is 0, and low data is 1001；Since pointer is 0, high position data is exactly the extension of sign bit, that is, 111_
1111_1111.So last value is 1_111_1111_1111_1001, that is, -7.
For the coefficient -1 of the 0th row the 3rd row, it is stored in Static RAM（SRAM）3 addresses, sign bit is
1, pointer is 0, and low data is 1111；Since pointer is 0, high position data is exactly the extension of sign bit, that is, 111_
1111_1111.So last value is 1_111_1111_1111_1111, that is, -1.
……。
For the coefficient 7 of the 1st row the 0th row, it is stored in Static RAM（SRAM）16 addresses, sign bit 0,
Pointer is 0, and low data is 0111；Since pointer is 0, high position data is exactly the extension of sign bit, that is, 000_
0000_0000.So last value is 0_000_0000_0000_0000, that is, 7.
For the coefficient -17 of the 1st row the 1st row, it is stored in Static RAM（SRAM）17 addresses, sign bit
1, pointer is 2, and low data is 1111；Since pointer is 2, high position data is stored in No. 2 registers, and content is
111_1111_1110.So last value is 1_111_1111_1110_1111, that is, -17.
For the coefficient 21 of the 1st row the 2nd row, it is stored in Static RAM（SRAM）18 addresses, sign bit
0, pointer is 3, and low data is 0101；Since pointer is 3, high position data is stored in No. 3 registers, and content is
000_0000_0001.So last value is 0_000_0000_0001_0101, that is, 21.
……。
Claims (2)
1. a kind of two-stage DCT coefficient storage method based on pointer suitable for HEVC standard, it is characterised in that the specific steps are：
First, DCT coefficient is divided into three parts：Sign bit, high position data and low data；Under the mode of complement representation,
Coefficient in HEVC standard is indicated with 16 bits, wherein highest order is sign bit, and remaining bits are data bit；Now by data bit
Upper section incorporate into as high position data, remaining bits incorporate into as low data；
Then, SRAM for stored symbols position, low data and can point at high position data as the first order in storage hierarchy
High bit pointer；Using register as the second level in storage hierarchy, for storing the high position data that some need to store；
When high bit pointer is a specific value 0, high position data is exactly the extension of sign bit；And for needing to store seniority top digit
According to then they will be stored by second level storage hierarchy, that is, register, and be calculated high bit pointer using counter and carried out rope
Draw.
2. the two-stage DCT coefficient storage method based on pointer according to claim 1 suitable for HEVC standard, feature
It is, it is still assumed that when high bit pointer is equal to 0, the high position data corresponding to the pointer is the extension of sign bit；So, rope is being established
When drawing relationship, hardware counts the number for the high position data for needing to store using counter, the counter from 1 start recording,
Occur and if only if the high position data that new needs store, hardware processor by the data be stored in nonce counter it is right
In the register answered, then counter increases 1 certainly.
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| CN102110058A (en) * | 2009-12-25 | 2011-06-29 | 上海芯豪微电子有限公司 | Low-deficiency rate and low-deficiency punishment caching method and device |
| CN103327331A (en) * | 2013-06-18 | 2013-09-25 | 复旦大学 | 8*8DCT transformation achieving method in HEVC standard |
| CN104253998A (en) * | 2014-09-25 | 2014-12-31 | 复旦大学 | Hardware on-chip storage method of deblocking effect filter applying to HEVC (High Efficiency Video Coding) standard |
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| CN102110058A (en) * | 2009-12-25 | 2011-06-29 | 上海芯豪微电子有限公司 | Low-deficiency rate and low-deficiency punishment caching method and device |
| CN103327331A (en) * | 2013-06-18 | 2013-09-25 | 复旦大学 | 8*8DCT transformation achieving method in HEVC standard |
| CN104253998A (en) * | 2014-09-25 | 2014-12-31 | 复旦大学 | Hardware on-chip storage method of deblocking effect filter applying to HEVC (High Efficiency Video Coding) standard |
Non-Patent Citations (1)
| Title |
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| "基于H.264的复杂度可分级的DCT算法研究";"张淑芳，李华，刘义明，刘亚欣";《电子测量技术》;20090130;第32卷(第1期);全文 * |
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