CN105374740B - A kind of semiconductor devices and its manufacturing method, electronic device - Google Patents
A kind of semiconductor devices and its manufacturing method, electronic device Download PDFInfo
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- CN105374740B CN105374740B CN201410438535.7A CN201410438535A CN105374740B CN 105374740 B CN105374740 B CN 105374740B CN 201410438535 A CN201410438535 A CN 201410438535A CN 105374740 B CN105374740 B CN 105374740B
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Abstract
A kind of semiconductor devices of present invention offer and its manufacturing method, electronic device, the method includes：(a) semiconductor substrate is provided；(b) the first etching stopping layer and the first interlayer dielectric layer are sequentially formed on a semiconductor substrate, and the first copper metal interconnection structure is formed in the first interlayer dielectric layer；(c) the second etching stopping layer and the second interlayer dielectric layer are sequentially formed, and forms the second copper metal interconnection structure being electrically connected with the first copper metal interconnection structure and the pseudo- copper metal layer for blocking the ultraviolet light from subsequent handling to avoid the irradiation to the first interlayer dielectric layer in the second interlayer dielectric layer.According to the present invention it is possible to the mechanical strength for the multiple layer of copper metal interconnection structure that effectively enhancing is formed using the method, avoiding each bed boundary position, delamination occurs.
Description
Technical field
The present invention relates to semiconductor fabrication process, in particular to a kind of semiconductor devices and its manufacturing method, electronics
Device.
Background technology
For the logic circuit in semiconductor devices, the number of plies of copper metal interconnection layer reaches several layers or even ten several layers.
As shown in Fig. 1 (a), it is formed with the first etching being laminated from bottom to top in the semiconductor substrate 100 for being formed with front-end devices and stops
Only layer 101 and the first interlayer dielectric layer 102 are formed be connected to the front-end devices in the first interlayer dielectric layer 102
One copper metal interconnection structure M1；The second etching stopping layer 201 being laminated from bottom to top is formed on the first interlayer dielectric layer 102
With the second interlayer dielectric layer 202, be connected to the first copper metal interconnection structure M1 is formed in the second interlayer dielectric layer 202
Two copper metal interconnection structure M2；The third etching stopping layer 301 being laminated from bottom to top is formed on the second interlayer dielectric layer 202
With third interlayer dielectric layer 302, be connected to the second copper metal interconnection structure M2 is formed in third interlayer dielectric layer 302
Three copper metal interconnection structure M3；The 4th etching stopping layer 401 being laminated from bottom to top is formed on third interlayer dielectric layer 302
With the 4th interlayer dielectric layer 402, be connected to third copper metal interconnection structure M3 is formed in the 4th interlayer dielectric layer 402
Four copper metal interconnection structure M4；The 5th etching stopping layer 501 being laminated from bottom to top is formed on the 4th interlayer dielectric layer 402
Dielectric layer 502 between layer 5 are formed be connected to the 4th copper metal interconnection structure M4 between layer 5 in dielectric layer 502
Five copper metal interconnection structure M5.
Between often being formed from level to level after dielectric layer, it is required to implement ultraviolet irradiation, it is normal with the dielectric for reducing interlayer dielectric layer
Number.During implementing ultraviolet irradiation to upper layer interlayer dielectric layer, lower layer's interlayer dielectric layer shrinks phenomenon, is formed in addition
The intrinsic stress effect of lower layer's copper metal interconnection structure in lower layer's interlayer dielectric layer, in upper layer and lower layer interlayer dielectric layer
Interface 103 can delamination occurs, in turn results in the failure of device.
It is, therefore, desirable to provide a kind of method, to solve the above problems.
Invention content
In view of the deficiencies of the prior art, the present invention provides a kind of manufacturing method of semiconductor devices, including：(a) half is provided
Conductor substrate；(b) the first etching stopping layer and the first interlayer dielectric layer are sequentially formed on the semiconductor substrate, described
The first copper metal interconnection structure is formed in one interlayer dielectric layer；(c) the second etching stopping layer and the second interlayer dielectric are sequentially formed
Layer, and the second copper metal interconnection being electrically connected with the first copper metal interconnection structure is formed in second interlayer dielectric layer
Structure and for block the ultraviolet light from subsequent handling to avoid the irradiation to first interlayer dielectric layer pseudo- copper gold
Belong to layer.
In one example, step (b)-(c) is repeated, until being formed by multiple described for being laminated and being connected to from bottom to top
The multilayer copper metal interconnection knot for the stepped construction composition that one copper metal interconnection structure and the second copper metal interconnection structure are constituted
Structure.
In one example, it is respectively formed after first interlayer dielectric layer, second interlayer dielectric layer, is all made of
The interlayer dielectric layer formed described in ultraviolet irradiation, to further decrease dielectric constant.
In one example, the second copper metal interconnection structure is isolated from each other with the pseudo- copper metal layer.
In one example, the second copper metal interconnection structure is electrically connected with the pseudo- copper metal layer.
In one example, the pseudo- copper metal is formed simultaneously in the process for forming the second copper metal interconnection structure
Layer.
In one embodiment, the present invention also provides a kind of semiconductor devices manufactured using the above method.
In one embodiment, the present invention also provides a kind of electronic device, the electronic device includes the semiconductor device
Part.
According to the present invention it is possible to effectively enhance the mechanical strength of the multiple layer of copper metal interconnection structure, each bed boundary is avoided
Delamination occurs for position.
Description of the drawings
The following drawings of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing：
Fig. 1 is the schematic diagram that delamination occurs in multiple layer of copper metal interconnection structure；
Fig. 2 is schematically cuing open for the multiple layer of copper metal interconnection structure formed according to the method for exemplary embodiment of the present one
Face figure.
Specific implementation mode
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into
Row description.
In order to thoroughly understand the present invention, detailed step will be proposed in following description, to illustrate proposition of the present invention
Semiconductor devices and its manufacturing method, electronic device.Obviously, execution of the invention is not limited to the technology of semiconductor applications
The specific details that personnel are familiar with.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, this
Invention can also have other embodiment.
It should be understood that when the term " comprising " and/or " including " is used in this specification, indicating described in presence
Feature, entirety, step, operation, element and/or component, but do not preclude the presence or addition of other one or more features, entirety,
Step, operation, element, component and/or combination thereof.
[Exemplary embodiment Yi ]
With reference to Fig. 2, the multilayer copper metal that the method for being shown according to an exemplary embodiment of the present one is formed interconnects
The schematic cross sectional view of structure.
The first etching stopping layer being laminated from bottom to top is formed in the semiconductor substrate 1000 for being formed with front-end devices
1001 and first interlayer dielectric layer 1002, the front-end devices refer to implement semiconductor devices post phase manufacturing technique (BEOL) it
The device of preceding formation is formed with the first copper metal being connected to the front-end devices in the first interlayer dielectric layer 1002 and mutually links
Structure N1；It is formed with the second etching stopping layer 2001 being laminated from bottom to top on the first interlayer dielectric layer 1002 and the second interlayer is situated between
It is mutual to be formed with the second copper metal being connected to the first copper metal interconnection structure N1 in the second interlayer dielectric layer 2002 for electric layer 2002
Link structure (being not shown in figure), be also formed in the second interlayer dielectric layer 2002 with the second copper metal interconnection structure that
This is isolated or what is be electrically connected is used to block the ultraviolet light from subsequent handling to avoid the irradiation to the first interlayer dielectric layer 1002
The first pseudo- copper metal layer L1；The third etching stopping layer being laminated from bottom to top is formed on the second interlayer dielectric layer 2002
3001 and third interlayer dielectric layer 3002, it is formed in third interlayer dielectric layer 3002 and the second copper metal interconnection structure
The third copper metal interconnection structure N3 of connection；The 4th etching being laminated from bottom to top is formed on third interlayer dielectric layer 3002
Stop-layer 4001 and the 4th interlayer dielectric layer 4002, are formed in the 4th interlayer dielectric layer 4002 and mutually link with third copper metal
4th copper metal interconnection structure (being not shown in figure) of structure N3 connection, is also formed with and institute in the 4th interlayer dielectric layer 4002
State that the 4th copper metal interconnection structure is isolated from each other or is electrically connected for blocking the ultraviolet light from subsequent handling to avoid to the
The pseudo- copper metal layer L2 of the second of the irradiation of three interlayer dielectric layers 3002；It is formed with from bottom to top on the 4th interlayer dielectric layer 4002
Dielectric layer 5002 between the 5th etching stopping layer 5001 and layer 5 of stacking, is formed between layer 5 in dielectric layer 5002 and institute
State the 5th copper metal interconnection structure N5 of the 4th copper metal interconnection structure connection.And so on, front-end devices can be formed with
Semiconductor substrate 1000 on formed with above structure feature multiple layer of copper metal interconnection structure.
Copper metal interconnection structure in above-mentioned multiple layer of copper metal interconnection structure is similar with the pseudo- forming method of copper metal layer, position
Copper metal interconnection structure and pseudo- copper metal layer in same interlayer dielectric layer can be formed in the same process.Below only with shape
It is illustrated at for the first copper metal interconnection structure N1 in semiconductor substrate 1000.
First, semiconductor substrate 1000 is provided, using chemical vapor deposition method in semiconductor substrate 1000 shape successively
At the first etching stopping layer 1001 and the first interlayer dielectric layer 1002.
Front-end devices are formed in semiconductor substrate 1000, to put it more simply, being not shown in legend.The front-end devices
Refer to implement semiconductor devices post phase manufacturing technique before formed device, herein not to the concrete structure of front-end devices into
Row limits.The front-end devices include gate structure, and as an example, gate structure includes the grid stacked gradually from bottom to top
Pole dielectric layer and gate material layers.It is formed with side wall construction in the both sides of gate structure, the semiconductor in side wall construction both sides serves as a contrast
It is formed with source/drain region in bottom 1000, is channel region between source/drain region；It is formed on the top and source/drain region of gate structure
There is self-aligned silicide.
Material preferred SiCN, SiC or SiN of first etching stopping layer 1001 are used as the first interlayer dielectric of subsequent etch
While 1002 etching stopping layer to form the first copper metal interconnection structure N1 wherein of layer, the first copper metal can be prevented mutual
Link in the interlayer dielectric layer where the copper in structure N1 is diffused into the front-end devices.
The constituent material of first interlayer dielectric layer 1002 can be selected from common various low-ks (k values) material in this field
Material, including but not limited to k values be 2.5-2.9 silicate compound (Hydrogen Silsesquioxane, referred to as HSQ),
Methane-siliconic acid salt compound (Methyl Silsesquioxane, abbreviation MSQ) that k values are 2.2, the HOSP that k values are 2.8TM
(advanced low-k materials of the mixture based on organic matter and Si oxide of Honeywell companies manufacture) and k values are
2.65 SiLKTM(a kind of advanced low-k materials of Dow Chemical companies manufacture) etc..In general, using ultraviolet irradiation or
The methods of person's heating makes 1002 porous of the first interlayer dielectric layer to be formed, to further decrease the first interlayer dielectric layer 1002
Dielectric constant.
Next, forming the first copper metal interconnection structure for being connected to the front-end devices in the first interlayer dielectric layer 1002
N1.The step of forming the first copper metal interconnection structure N1 include：Sequentially formed on the first interlayer dielectric layer 1002 buffer layer and
Hard mask layer, the effect of buffer layer are kept away in the copper metal interconnection layer that follow-up grinding is formed in the first copper metal interconnection structure N1
The porous structure for exempting from the first interlayer dielectric layer of mechanical stress pair 1002 causes to damage；The first opening is formed in hard mask layer,
To expose the buffer layer of lower section, first opening is used as the pattern of the groove in the first copper metal interconnection structure N1；It is buffering
The second opening is formed in layer and interlayer dielectric layer, second opening is used as the figure of the through-hole in the first copper metal interconnection structure N1
Case；Using hard mask layer as mask, it is mutual to synchronize the first copper metal of formation for synchronous etch buffer layers and the first interlayer dielectric layer 1002
Link the groove and through-hole in structure N1, it is described to be etched in the when of exposing the first etching stopping layer 1001 and terminate；Removal passes through the first bronze medal
The first etching stopping layer 1001 that metal interconnection structure N1 exposes, so that the first copper metal interconnection structure N1 and the front-end devices
Connection, in the present embodiment, using the removal for the first etching stopping layer 1001 that dry method etch technology is implemented to expose；Execute etching
Last handling process, to remove residuals and impurity caused by aforementioned etching process.
The technical process of above-mentioned formation the first copper metal interconnection structure N1 is only one kind in dual damascene process, ability
Field technique personnel should know, the first bronze medal gold can be equally formed using the other embodiment in dual damascene process
Belong to interconnection structure N1, such as is initially formed the throughhole portions of the first copper metal interconnection structure N1 and re-forms the first copper metal interconnection structure
The trench portions of N1, its detailed implementation steps that details are not described herein.
Next, forming copper metal interconnection layer in the first copper metal interconnection structure N1.Forming copper metal interconnection layer can be with
The various suitable technologies being familiar with using those skilled in the art, such as physical gas-phase deposition or galvanizer
Skill.
It is formed before copper metal interconnection layer, copper need to be sequentially formed in the bottom and side wall of the first copper metal interconnection structure N1
Metal diffusion barrier layer and copper metal seed layer, to put it more simply, being not shown in figure.Copper metal diffusion impervious layer can prevent copper
Diffusion of the copper into the first interlayer dielectric layer 1002 in metal interconnecting layer, copper metal seed layer can enhance copper metal interconnection layer
With the adhesion between copper metal diffusion impervious layer.It forms copper metal diffusion impervious layer and ability may be used in copper metal seed layer
The various suitable technologies that field technique personnel are familiar with, for example, forming copper metal diffusion using physical gas-phase deposition
Barrier layer forms copper metal seed layer using sputtering technology or chemical vapor deposition method.The material of copper metal diffusion impervious layer
Material is metal, metal nitride, the combination of preferably Ta and TaN or the combination of Ti and TiN.
Then, chemical mechanical milling tech is executed, until exposing the first interlayer dielectric layer 1002.In the process, it covers firmly
Film layer and buffer layer are removed.
According to the present invention it is possible to effectively enhance the mechanical strength of above-mentioned multiple layer of copper metal interconnection structure, each bed boundary is avoided
Delamination occurs for position.
[Exemplary embodiment Er ]
The present invention also provides a kind of semiconductor devices, the semiconductor devices includes accoding to exemplary embodiment described in one
Multiple layer of copper metal interconnection structure prepared by method.The semiconductor devices, due to the use of the multiple layer of copper metal interconnection structure,
Thus there is better performance.
[Exemplary embodiment San ]
The present invention also provides a kind of electronic devices comprising the semiconductor devices described in exemplary embodiment two.The electricity
Sub-device can be mobile phone, tablet computer, laptop, net book, game machine, television set, VCD, DVD, navigator, photograph
It includes the semiconductor device that any electronic product such as machine, video camera, recording pen, MP3, MP4, PSP or equipment, which can also be any,
The intermediate products of part.The electronic device due to the use of the semiconductor devices, thus has better performance.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, and be not intended to limit the invention within the scope of described embodiment.In addition people in the art
It is understood that the invention is not limited in above-described embodiment, introduction according to the present invention can also be made more kinds of member
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (6)
1. a kind of manufacturing method of semiconductor devices, including：
(a) semiconductor substrate is provided；
(b) the first etching stopping layer and the first interlayer dielectric layer are sequentially formed on the semiconductor substrate, in the first layer
Between form the first copper metal interconnection structure in dielectric layer；
(c) sequentially form the second etching stopping layer and the second interlayer dielectric layer, and formed in second interlayer dielectric layer with
Second copper metal interconnection structure of the first copper metal interconnection structure electrical connection and for blocking the purple from subsequent handling
Outer light to avoid the irradiation to first interlayer dielectric layer pseudo- copper metal layer, wherein being formed, second copper metal is mutual
Link and is formed simultaneously the pseudo- copper metal layer in the process of structure；
Step (b)-(c) is repeated, until being formed by multiple the first copper metal interconnection structures for being laminated and being connected to from bottom to top
The multiple layer of copper metal interconnection structure of the stepped construction composition constituted with the second copper metal interconnection structure.
2. according to the method described in claim 1, it is characterized in that, being respectively formed first interlayer dielectric layer, described second
After interlayer dielectric layer, it is all made of the interlayer dielectric layer formed described in ultraviolet irradiation, to further decrease dielectric constant.
3. according to the method described in claim 1, it is characterized in that, the second copper metal interconnection structure and the pseudo- copper metal
Layer is isolated from each other.
4. according to the method described in claim 1, it is characterized in that, the second copper metal interconnection structure and the pseudo- copper metal
Layer electrical connection.
5. a kind of semiconductor devices using the method manufacture described in one of claim 1-4.
6. a kind of electronic device, the electronic device includes the semiconductor devices described in claim 5.
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| CN1877834A (en) * | 2005-06-08 | 2006-12-13 | 三星电子株式会社 | Semiconductor integrated circuit device and method for fabricating the same |
| CN101021680A (en) * | 2006-02-14 | 2007-08-22 | 富士通株式会社 | Material for forming exposure light-blocking film, multilayer interconnection structure and manufacturing method thereof, and semiconductor device |
| CN101295722A (en) * | 2007-04-23 | 2008-10-29 | 冲电气工业株式会社 | Semiconductor device, optical measuring and detecting device, and method of manufacturing the same |
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| US7749892B2 (en) * | 2006-11-29 | 2010-07-06 | International Business Machines Corporation | Embedded nano UV blocking and diffusion barrier for improved reliability of copper/ultra low K interlevel dielectric electronic devices |
| JP2009021319A (en) * | 2007-07-11 | 2009-01-29 | Panasonic Corp | Nonvolatile semiconductor storage device and manufacturing method thereof |
| JP5385564B2 (en) * | 2008-08-18 | 2014-01-08 | ラピスセミコンダクタ株式会社 | Semiconductor device and manufacturing method thereof |
| JP2011082308A (en) * | 2009-10-06 | 2011-04-21 | Panasonic Corp | Method of manufacturing semiconductor apparatus |
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| CN1877834A (en) * | 2005-06-08 | 2006-12-13 | 三星电子株式会社 | Semiconductor integrated circuit device and method for fabricating the same |
| CN101021680A (en) * | 2006-02-14 | 2007-08-22 | 富士通株式会社 | Material for forming exposure light-blocking film, multilayer interconnection structure and manufacturing method thereof, and semiconductor device |
| CN101295722A (en) * | 2007-04-23 | 2008-10-29 | 冲电气工业株式会社 | Semiconductor device, optical measuring and detecting device, and method of manufacturing the same |
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