CN105337594A - Two-wire system delay control switch - Google Patents

Abstract

A two-wire system delay control switch is composed of a power supply control module M0, a power management module M1, a delay control module M2 and a starting and resetting module M3, wherein the power supply control module M0 achieves dynamic power supply distribution of a load and a delay control circuit; the power management module M1 utilizes a capacitive energy storage principle for carrying out filtering, energy storage and DC-DC conversion on a rectified direct current, supplies power to a control circuit under the monitoring of a filtered voltage, improves electric energy conversion efficiency, and significantly reduces an operating current of the control circuit (can be as low as less than 1mA minimally); the delay control module M2 ensures accuracy and effectiveness of delay time through combined control of zero clearing, timing and resetting; and the starting and resetting module M3 utilizes a self-locking mechanism so that the delay control switch is completely disconnected from a controlled power supply in a non operating state, and achieves zero quiescent power consumption thus the two-wire system delay control switch is suitable for various kinds of loads such as resistive, capacitive and inductive loads. The two-wire system delay control switch substantially improves safety, reliability and applicability of the delay control switch on the premise of ensuring a two-wire system connecting method.

Description

A kind of two-wire system delay control switch

Technical field

The present invention relates to a kind of delay control switch, particularly a kind of two-wire system delay control switch.

Background technology

The main body control device of delay control switch circuit has: controllable silicon, triode or MOS transistor, relay.The mode of connection is divided into: two-wire system and three-wire system.All there is quiescent current in conventional two-wire system delay control switch, load is turned off not thorough, there is potential safety hazard.In addition, conventional delay control switch goes back Problems existing in control mode or the mode of connection to be had:

1. control mode

(1) SCR control: leakage current is large, is not suitable for small area analysis load (as LED).

(2) triode or MOS transistor control: in a control cycle, can not keep slave mode after disconnecting control signal source, need to maintain to control electric current or electromotive force, make control procedure complicated, general use Single-chip Controlling, height of controlling cost, needs during deadlock to reset.

(3) Control: control electric current large, direct access control circuit is not suitable for small area analysis load.

2. the mode of connection

(1) two-wire system: electric current needed for control circuit is by the impact of load current, and namely load current must be greater than electric current needed for control circuit, limits least-loaded electric current.

(2) three-wire system: do not meet normal switch control circuit, need to increase zero line, field of employment is restricted, especially all the more so to already present circuit.

Summary of the invention

In order to overcome above-mentioned defect, the object of the present invention is to provide a kind of two-wire system delay control switch, power control module realizes load and delay control circuit and powers and distribute; Power management module utilizes capacitance energy storage principle, direct current after rectification is carried out filtering, energy storage and DC-DC conversion, power to control circuit under to the monitoring of filtered voltage, improve energy conversion efficiency, considerably reduce the minimum working current of control circuit, reach the object that small area analysis (most I is low to moderate below 1mA) controls; Delays time to control module comprises clearing, timing and reset and controls, and ensure that accuracy and the validity of delay time; Starting reseting module utilizes self-lock mechanism to be communicated with delay control circuit by controlled source, after delay time arrives, relay switch resets, the connection of thorough disconnection controlled source and delay control circuit, achieve zero quiescent dissipation, make delay control switch be applicable to all kinds of load: resistive, capacitive and inductive load; The present invention, on the basis keeping the two-wire system mode of connection, has increased substantially the fail safe of delay control switch circuit, reliability and applicability.

In order to achieve the above object, technical scheme of the present invention is achieved in that

A kind of two-wire system delay control switch, comprises power control module M0, power management module M1, delays time to control module M2 and starts reseting module M3; Power control module M0 and power management module M1, delays time to control module M2 and start reseting module M3 power end and be connected power supply VCC is provided, power management module M1 and delays time to control module M2 and start reseting module M3 power end and be connected power vd D is provided, power control module M0, power management module M1, delays time to control module M2 and start reseting module M3 common source negative pole VSS, power management module M1 is respectively with delays time to control module M2 with starts reseting module M3 respective signal port and be connected and provide timing reset signal Vdisc and start reference signal Vctr; Controlled source is input to by controlled source input and starts reseting module M3, the controlled source line output 3-1 starting reseting module M3 is connected with the controlled source line input 0-1 of power control module M0, and controlled source is outputted to controlled source output by power control module M0; The delay control signal output 2-1 of delays time to control module M2 is connected with the delay control signal input 3-2 and enabling signal output 3-3 that start reseting module M3 respectively with enabling signal input 2-2.

Described power control module M0 comprises controlled source lead-out terminal P0-1, unidirectional controllable silicon S CR0-1, unidirectional controllable silicon S CR0-2, diode D0-1, diode D0-2, voltage stabilizing didoe DZ0-1, rectifier bridge B0-1; An input of the positive pole of unidirectional controllable silicon S CR0-1, the negative pole of unidirectional controllable silicon S CR0-2 and rectifier bridge B0-1 is connected with controlled source lead-out terminal P0-1; Another input of the negative pole of unidirectional controllable silicon S CR0-1, the positive pole of unidirectional controllable silicon S CR0-2 and rectifier bridge B0-1 is connected with the controlled source line input 0-1 of power control module M0; The control pole of unidirectional controllable silicon S CR0-1 is connected with the negative pole of diode D0-2; The control pole of unidirectional controllable silicon S CR0-2 is connected with the negative pole of diode D0-1; The positive pole of diode D0-1 and the positive pole of diode D0-2 are connected with the positive pole of voltage stabilizing didoe DZ0-1; The cathode output end of rectifier bridge B0-1 meets VSS, and the cathode output end of rectifier bridge B0-1 and the negative pole of voltage stabilizing didoe DZ0-1 meet VCC.

Described power management module M1 comprises two independent amplifier U1-1A and U1-1B, electrochemical capacitor C1-1 and C1-4 of four-operational amplifier U1-1, electric capacity C1-2 ~ C1-3 and C1-5 ~ C1-6, resistance R1-1 ~ R1-10, diode D1-1 ~ D1-4, Micro Energy Lose voltage-reference diodes DZ1-1, LED 1-1 and PMOS transistor Q1-1 and nmos pass transistor Q1-2; The positive pole of the positive pole of electrochemical capacitor C1-1, one end of resistance R1-1, one end of resistance R1-3, the source electrode of PMOS transistor Q1-1 and LED 1-1 meets VCC; The negative power end 11 of one end of one end of the negative pole of electrochemical capacitor C1-1 and C1-4, one end of electric capacity C1-2, electric capacity C1-3, one end of electric capacity C1-5, electric capacity C1-6, the positive pole of Micro Energy Lose voltage-reference diodes DZ1-1, the negative pole of diode D1-1, one end of resistance R1-4 and one end of resistance R1-9, the source electrode of nmos pass transistor Q1-2 and four-operational amplifier U1-1 meets VSS; The negative pole of LED 1-1 and the positive pole of electrochemical capacitor C1-4 are connected with the positive power source terminal 4 of four-operational amplifier U1-1; The other end and the negative pole of Micro Energy Lose voltage-reference diodes DZ1-1 of the other end of resistance R1-1, one end of resistance R1-2, electric capacity C1-2 are connected with the inverting input 2 of independent amplifier U1-1A; One end of resistance R1-5 and the grid of PMOS transistor Q1-1 are connected with the output 1 of independent amplifier U1-1A; The other end of resistance R1-2 and one end of resistance R1-6 are connected with the in-phase input end 5 of independent amplifier U1-1B; The other end of resistance R1-3 is connected with the inverting input 6 of independent amplifier U1-1B with the other end of resistance R1-4 and the other end of electric capacity C1-3; The other end of resistance R1-6, one end of resistance R1-10 and the positive pole of diode D1-2 with D1-3 are connected with the output 7 of independent amplifier U1-1B; The other end of the other end of resistance R1-10, the negative pole of diode D1-3 and electric capacity C1-6 is connected with the grid of nmos pass transistor Q1-2; The drain electrode of nmos pass transistor Q1-2 meets Vdisc; The in-phase input end 3 of one end of resistance R1-7, one end of resistance R1-8 and the other end of resistance R1-9, the negative pole of diode D1-2 and independent amplifier U1-1A meets Vctr; The other end of resistance R1-8 is connected with the negative pole of diode D1-4; The positive pole of diode D1-4, the other end of electric capacity C1-5 and the drain electrode of PMOS transistor Q1-1 meet VDD; The other end of resistance R1-5 and the other end of resistance R1-7 are connected with the positive pole of diode D1-1.

Described delays time to control module M2 comprises independent amplifier U1-1C, the resistance R2-1 ~ R2-7 of four-operational amplifier U1-1, electrochemical capacitor C2-1, electric capacity C2-2 and diode D2-1; One end of resistance R2-1 and a termination VDD of resistance R2-3; The other end of resistance R2-1 and one end of resistance R2-2 are connected with one end of resistance R2-5; The other end of resistance R2-2 and the positive pole of electrochemical capacitor C2-1 meet Vdisc; The other end of resistance R2-5 and one end of resistance R2-7 are connected with the in-phase input end 10 of independent amplifier U1-1C; One end of resistance R2-6, one end of electric capacity C2-2 and the negative pole of diode D2-1 are connected with the inverting input 9 of independent amplifier U1-1C; The other end of resistance R2-7 and the output 8 of independent amplifier U1-1C are connected with the delay control signal output 2-1 of delays time to control module M2; The positive pole of diode D2-1 is connected with the enabling signal input 2-2 of delays time to control module M2; The other end of resistance R2-3 and the other end of resistance R2-6 are connected with one end of resistance R2-4; Another termination VSS of the negative pole of electrochemical capacitor C2-1, the other end of electric capacity C2-2 and resistance R2-4.

Described startup reseting module M3 comprises the independent amplifier U1-1D of four-operational amplifier U1-1, controlled source input terminal P3-1, fuse F3-1, starting switch S3-1, twin coil magnetic latching relay K3-1, diode D3-1 and D3-2, resistance R3-1 and R3-2 and nmos pass transistor Q3-1 and Q3-2; Controlled source input terminal P3-1 is connected with one end of fuse F3-1; The other end of fuse F3-1 and the contact 3 of twin coil magnetic latching relay K3-1 are connected with one end of starting switch S3-1; The other end of starting switch S3-1 and the contact 1 of twin coil magnetic latching relay K3-1 are connected with the controlled source line output 3-1 starting reseting module M3; The negative pole of diode D3-1 and D3-2 and the contact 5 of twin coil magnetic latching relay K3-1 meet VDD; The grid of nmos pass transistor Q3-1 is connected with the delay control signal input 3-2 starting reseting module M3; The positive pole of diode D3-1 and the contact 6 of twin coil magnetic latching relay K3-1 are connected with the drain electrode of nmos pass transistor Q3-1; The positive pole of diode D3-2 and the contact 4 of twin coil magnetic latching relay K3-1 are connected with the drain electrode of nmos pass transistor Q3-2; The contact 2 of twin coil magnetic latching relay K3-1 is connected with one end of resistance R3-1; The other end of resistance R3-1 and one end of resistance R3-2 are connected with the in-phase input end 12 of independent amplifier U1-1D; The inverting input 13 of independent amplifier U1-1D meets Vctr; The grid of nmos pass transistor Q3-2 and the output 14 of independent amplifier U1-1D are connected with the enabling signal output 3-3 starting reseting module M3; The other end of resistance R3-2 and the source electrode of nmos pass transistor Q3-1 and Q3-2 meet VSS.

The present invention, on the basis keeping two-wire system supply line, achieves a kind of two-wire system delay control switch.Start-up circuit, relay set, delay control circuit is communicated with controlled source, and time control circuit starts timing, and load is started working, and delay time arrives, and relay resets, and the connection of off delay control circuit and controlled source, load quits work.If the improper power-off of controlled source, when recovering incoming call, reset control circuit control relay resets, the connection of off delay control circuit and controlled source.

The present invention is compared with existing delay control switch, and tool has the following advantages:

1. utilize capacitance energy storage principle and DC-DC conversion, improve energy conversion efficiency, considerably reduce the maximum operating currenbt of control circuit, achieve small area analysis (most I be low to moderate below 1mA) and control, widened the applicability of delay control switch.

2. utilize self-lock mechanism, the connection of delay control switch and controlled source is thoroughly disconnected in non operating state, achieve zero quiescent dissipation, make the present invention be applicable to all kinds of load: resistive, capacitive and inductive load, improve the fail safe of delay control circuit, reliability and applicability.

3. the present invention adopts two-wire system connected mode, without the need to changing former control switch circuit (two-wire system), maintains the advantage of existing delay control switch.

Accompanying drawing explanation

Fig. 1 is circuit structure schematic diagram of the present invention.

Fig. 2 is power control module M0 circuit theory diagrams of the present invention.

Fig. 3 is power management module M1 circuit theory diagrams of the present invention.

Fig. 4 is delays time to control module M2 circuit theory diagrams of the present invention.

Fig. 5 is startup reseting module M3 circuit theory diagrams of the present invention.

Fig. 6 is winding diagram of the present invention.

Embodiment

Below in conjunction with accompanying drawing, structural principle of the present invention and operation principle are described in detail.

With reference to Fig. 1, a kind of two-wire system delay control switch, comprises power control module M0, power management module M1, delays time to control module M2 and starts reseting module M3; Power control module M0 and power management module M1, delays time to control module M2 and start reseting module M3 power end and be connected power supply VCC is provided, power management module M1 and delays time to control module M2 and start reseting module M3 power end and be connected power vd D is provided, power control module M0, power management module M1, delays time to control module M2 and start reseting module M3 common source negative pole VSS, power management module M1 is respectively with delays time to control module M2 with starts reseting module M3 respective signal port and be connected and provide timing reset signal Vdisc and start reference signal Vctr; Controlled source is input to by controlled source input and starts reseting module M3, the controlled source line output 3-1 starting reseting module M3 is connected with the controlled source line input 0-1 of power control module M0, and controlled source is outputted to controlled source output by power control module M0; The delay control signal output 2-1 of delays time to control module M2 is connected with the delay control signal input 3-2 and enabling signal output 3-3 that start reseting module M3 respectively with enabling signal input 2-2.

Controlled source lead-out terminal P0-1, unidirectional controllable silicon S CR0-1 and SCR0-2, diode D0-1 and D0-2, voltage stabilizing didoe DZ0-1, rectifier bridge B0-1 is comprised with reference to Fig. 2, power control module M0; An input of the positive pole of unidirectional controllable silicon S CR0-1, the negative pole of unidirectional controllable silicon S CR0-2 and rectifier bridge B0-1 is connected with controlled source lead-out terminal P0-1; Another input of the negative pole of unidirectional controllable silicon S CR0-1, the positive pole of unidirectional controllable silicon S CR0-2 and rectifier bridge B0-1 is connected with the controlled source line input 0-1 of power control module M0; The control pole of unidirectional controllable silicon S CR0-1 is connected with the negative pole of diode D0-2; The control pole of unidirectional controllable silicon S CR0-2 is connected with the negative pole of diode D0-1; The positive pole of diode D0-1 and the positive pole of diode D0-2 are connected with the positive pole of voltage stabilizing didoe DZ0-1; The cathode output end of rectifier bridge B0-1 meets VSS, and the cathode output end of rectifier bridge B0-1 and the negative pole of voltage stabilizing didoe DZ0-1 meet VCC.

Two independent amplifier U1-1A and U1-1B, electrochemical capacitor C1-1 and C1-4 of four-operational amplifier U1-1, electric capacity C1-2 ~ C1-3 and C1-5 ~ C1-6, resistance R1-1 ~ R1-10, diode D1-1 ~ D1-4, Micro Energy Lose voltage-reference diodes DZ1-1, LED 1-1 and PMOS transistor Q1-1 and nmos pass transistor Q1-2 is comprised with reference to Fig. 3, power management module M1; The positive pole of the positive pole of electrochemical capacitor C1-1, one end of resistance R1-1, one end of resistance R1-3, the source electrode of PMOS transistor Q1-1 and LED 1-1 meets VCC; The negative power end 11 of one end of one end of the negative pole of electrochemical capacitor C1-1 and C1-4, one end of electric capacity C1-2, electric capacity C1-3, one end of electric capacity C1-5, electric capacity C1-6, the positive pole of Micro Energy Lose voltage-reference diodes DZ1-1, the negative pole of diode D1-1, one end of resistance R1-4 and one end of resistance R1-9, the source electrode of nmos pass transistor Q1-2 and four-operational amplifier U1-1 meets VSS; The negative pole of LED 1-1 and the positive pole of electrochemical capacitor C1-4 are connected with the positive power source terminal 4 of four-operational amplifier U1-1; The other end and the negative pole of Micro Energy Lose voltage-reference diodes DZ1-1 of the other end of resistance R1-1, one end of resistance R1-2, electric capacity C1-2 are connected with the inverting input 2 of independent amplifier U1-1A; One end of resistance R1-5 and the grid of PMOS transistor Q1-1 are connected with the output 1 of independent amplifier U1-1A; The other end of resistance R1-2 and one end of resistance R1-6 are connected with the in-phase input end 5 of independent amplifier U1-1B; The other end of resistance R1-3 is connected with the inverting input 6 of independent amplifier U1-1B with the other end of resistance R1-4 and the other end of electric capacity C1-3; The other end of resistance R1-6, one end of resistance R1-10 and the positive pole of diode D1-2 with D1-3 are connected with the output 7 of independent amplifier U1-1B; The other end of the other end of resistance R1-10, the negative pole of diode D1-3 and electric capacity C1-6 is connected with the grid of nmos pass transistor Q1-2; The drain electrode of nmos pass transistor Q1-2 meets Vdisc; The in-phase input end 3 of one end of resistance R1-7, one end of resistance R1-8 and the other end of resistance R1-9, the negative pole of diode D1-2 and independent amplifier U1-1A meets Vctr; The other end of resistance R1-8 is connected with the negative pole of diode D1-4; The positive pole of diode D1-4, the other end of electric capacity C1-5 and the drain electrode of PMOS transistor Q1-1 meet VDD; The other end of resistance R1-5 and the other end of resistance R1-7 are connected with the positive pole of diode D1-1.

Independent amplifier U1-1C, resistance R2-1 ~ R2-7, electrochemical capacitor C2-1, electric capacity C2-2, the diode D2-1 of four-operational amplifier U1-1 is comprised with reference to Fig. 4, delays time to control module M2; One end of resistance R2-1 and a termination VDD of resistance R2-3; The other end of resistance R2-1 and one end of resistance R2-2 are connected with one end of resistance R2-5; The other end of resistance R2-2 and the positive pole of electrochemical capacitor C2-1 meet Vdisc; The other end of resistance R2-5 and one end of resistance R2-7 are connected with the in-phase input end 10 of independent amplifier U1-1C; One end of resistance R2-6, one end of electric capacity C2-2 and the negative pole of diode D2-1 are connected with the inverting input 9 of independent amplifier U1-1C; The other end of resistance R2-7 and the output 8 of independent amplifier U1-1C are connected with the delay control signal output 2-1 of delays time to control module M2; The positive pole of diode D2-1 is connected with the enabling signal input 2-2 of delays time to control module M2; The other end of resistance R2-3 and the other end of resistance R2-6 are connected with one end of resistance R2-4; Another termination VSS of the negative pole of electrochemical capacitor C2-1, the other end of electric capacity C2-2 and resistance R2-4.

With reference to Fig. 5, start reseting module M3 and comprise the independent amplifier U1-1D of four-operational amplifier U1-1, controlled source input terminal P3-1, fuse F3-1, starting switch S3-1, twin coil magnetic latching relay K3-1, diode D3-1 and D3-2, resistance R3-1 and R3-2 and nmos pass transistor Q3-1 and Q3-2; Controlled source input terminal P3-1 is connected with one end of fuse F3-1; The other end of fuse F3-1 and the contact 3 of twin coil magnetic latching relay K3-1 are connected with one end of starting switch S3-1; The other end of starting switch S3-1 and the contact 1 of twin coil magnetic latching relay K3-1 are connected with the controlled source line output 3-1 starting reseting module M3; The contact 5 of the negative pole of diode D3-1 and the negative pole of diode D3-2 and twin coil magnetic latching relay K3-1 meets VDD; The grid of nmos pass transistor Q3-1 is connected with the delay control signal input 3-2 starting reseting module M3; The positive pole of diode D3-1 and the contact 6 of twin coil magnetic latching relay K3-1 are connected with the drain electrode of nmos pass transistor Q3-1; The positive pole of diode D3-2 and the contact 4 of twin coil magnetic latching relay K3-1 are connected with the drain electrode of nmos pass transistor Q3-2; The contact 2 of twin coil magnetic latching relay K3-1 is connected with one end of resistance R3-1; The other end of resistance R3-1 and one end of resistance R3-2 are connected with the in-phase input end 12 of independent amplifier U1-1D; The inverting input 13 of independent amplifier U1-1D meets Vctr; The grid of nmos pass transistor Q3-2 and the output 14 of independent amplifier U1-1D are connected with the enabling signal output 3-3 starting reseting module M3; The other end of resistance R3-2 and the source electrode of nmos pass transistor Q3-1 and Q3-2 meet VSS.

With reference to Fig. 6, comprise controlled source (live wire) input terminal P1, controlled source (zero line) input terminal P2, delay switch and load; Controlled source (live wire) input terminal P1 is connected with the controlled source input P3-1 of delay switch, the controlled source output P0-1 of delay switch is connected with one end of load, and the other end of load is connected with controlled source (zero line) input terminal P2.

Operation principle of the present invention is:

In power control module M0, access unidirectional controllable silicon S CR0-1 and SCR0-2 before rectifier bridge B0-1, the break-make controlling unidirectional controllable silicon S CR0-1 and SCR0-1 by voltage stabilizing didoe DZ0-1, reaches the object of dynamic assignment load and delay control circuit voltage; Diode D0-1 and D0-2 controls the isolating diode of pole respectively as unidirectional controllable silicon S CR0-1 and SCR0-1, avoids controlling extremely mutually to disturb.Concrete control procedure is as follows:

1., as unidirectional controllable silicon S CR0-1 or SCR0-1 conducting, controlled source only powers to the load.

2., when unidirectional controllable silicon S CR0-1 and SCR0-1 cut-off, controlled source is powered to load and control circuit simultaneously.

In power management module M1, electrochemical capacitor C1-1 plays filtering and energy storage; Micro Energy Lose voltage-reference diodes DZ1-1 provide burning voltage Vref; Resistance R1-1 and electric capacity C1-2 is respectively as the current-limiting resistance of Micro Energy Lose voltage-reference diodes DZ1-1 and shunt capacitance; Electric capacity C1-3 is as buffer capacitor, and when ensureing that four-operational amplifier U1-1 just starts working, inverting input 6 voltage of independent amplifier U1-1B is lower than in-phase input end 5, and output 7 exports high level; Electrochemical capacitor C1-4 is as fixed ampllitude electric capacity, the input of the power supply and positive power source terminal 4 that reduce four-operational amplifier U1-1 is subject to the impact of VCC change, when the output 1 of independent amplifier U1-1A exports high level, grid, the source voltage difference of PMOS transistor Q1-1 are less, PMOS transistor Q1-1 cut-off is more thorough, and then improves DC-DC conversion efficiency; Electric capacity C1-5 is as the filter capacitor of VDD; Diode D1-1, as limiter diode, reduces the amplitude of oscillation pressure reduction of output voltage VDD; Diode D1-2 and D1-4 is as isolating diode, and wherein the negative pole output signal Vctr of D1-2 is as the DC-DC control signal changed and the startup benchmark starting reset control module M3; The drain electrode of nmos pass transistor Q1-2 outputs signal the clearing control signal of Vdisc as time-delay reset module M2, if its conducting hourglass, source voltage are V _ds; As power supply indicator and buffering isolating diode while of LED 1-1, if voltage is V during LED 1-1 conducting _led, work as VCC>V _ledtime provide operating voltage V to four-operational amplifier U1-1 _src=VCC-V _led; VCC converts VDD to by PMOS transistor Q1-1; The electric energy that the twin coil magnetic latching relay K3-1 of startup reseting module M3 consumes when normally working is wherein t _rstbe respectively the switch maximum actuation time of coil power dissipation and set or reset, in order to ensure that VDD can provide enough electric energy for the set or reset starting the twin coil magnetic latching relay K3-1 in reseting module M3 under less control electric current, utilize capacitance energy storage principle, VCC>VDD is set, makes electrochemical capacitor C1-1 store enough electric energy; If V _{+ Out}the high level voltage exported when representing each independent amplifier saturation condition of four-operational amplifier U1-1, V _-Outthe low level voltage exported when representing each independent amplifier saturation condition of four-operational amplifier U1-1, R _1-1~ R _1-10represent resistance R1-1 ~ R1-10 respectively, circuit is composed as follows:

1. independent amplifier U1-1A and resistance R1-5 and R1-7 ~ R1-9, electric capacity C1-5, diode D1-1 and PMOS transistor Q1-1 form DC-DC change-over circuit jointly.

2. independent amplifier U1-1B and resistance R1-2 ~ R1-4 and R1-6 forms hysteresis comparator, VCC voltage is monitored, resistance R1-3 and R1-4 is as divider resistance, for the inverting input 6 of independent amplifier U1-1B provides sampled voltage, if corresponding VCC voltage is respectively U when the upset of independent amplifier high level and low level upset _highand U _low:

$\left\{\begin{array}{c}{U}_{High}=\left(1+R_{1-3}/R_{1-4}\right)\[\left(V_{+Out}-Vref\right)R_{1-2}/\left(R_{1-2}+R_{1-6}\right)+Vref\]\\ U_{Low}=\left(1+R_{1-3}/R_{1-4}\right)\[\left(Vref-V_{-Out}\right)R_{1-6}/\left(R_{1-2}+R_{1-6}\right)+V_{-Out}\]\end{array}\right.$

Suitable U is set _highand U _low, make capacitor charging to U _highprocess complete in near-linear district, the time of reaching exchanges the object of electric energy for, ensure less operating current be the twin coil magnetic latching relay K3-1 starting reseting module M3 normally work the prerequisite of enough electric energy is provided under make the charging interval the shortest; The electric energy that electrochemical capacitor C1-1 provides for the twin coil magnetic latching relay K3-1 starting reseting module M3 is not less than W _pro=C _1-1(U ² _high-U ² _low)/2, wherein C _1-1represent electrochemical capacitor C1-1, then VCC provides energy to meet W for the twin coil magnetic latching relay K3-1 starting reseting module M3 normally works _pro>=W _con+ W _oth, W _othfor self energy consumption of delay control circuit.

Concrete control procedure is as follows:

1. when VCC voltage is lower than U _lowtime, the output 7 of independent amplifier U1-1B exports high level, Vctr=V _{+ Out}-V _d1-2, wherein V _d1-2represent the forward voltage of diode D1-2:

(1) PMOS transistor Q1-1 cut-off, VDD=0.

(2) nmos pass transistor Q1-2 conducting, exports clearing control signal Vdisc effective.

2. when VCC voltage is higher than U _hightime, output 7 output low level of independent amplifier U1-1B, the value of Vctr is similar to Vref, nmos pass transistor Q1-2 cut-off when electric capacity C1-6 is discharged to the threshold voltage of nmos pass transistor Q1-2 by resistance R1-10, and it is invalid to reset control signal Vdisc:

(1) when inverting input 2 voltage of independent amplifier U1-1A is higher than in-phase input end 3, output 1 output voltage V _-Out, PMOS transistor Q1-1 conducting, electric capacity C1-5 charges.

(2) when in-phase input end 3 voltage of independent amplifier U1-1A is higher than inverting input 2, output 1 output voltage V _{+ Out}, PMOS transistor Q1-1 ends, and electric capacity C1-5 discharges.

(3) be so concatenated to form vibration, reach the DC-DC conversion of VCC to VDD, when resistance R1-5 and R1-7 ~ R1-9 is given, its frequency of oscillation and duty ratio are determined by the load of electric capacity C1-5 and VDD.

3. when VCC voltage is at U _lowand U _highbetween time, output 7 output voltage of independent amplifier U1-1B maintains the original state.

In delays time to control module M2, resistance R2-1 is the charging current limiter resistance of electrochemical capacitor C2-1; Resistance R2-2 and electric capacity C2-2 is respectively as reset resistor and reset capacitance; Resistance R2-3 and R2-4 as divider resistance, for the inverting input 9 of independent amplifier U1-1C provides timing reference voltage; Diode D2-1 is as isolating diode; When in-phase input end 10 voltage of independent amplifier U1-1C is higher than inverting input 9, output 8 is high level, inputted the reset signal of twin coil magnetic latching relay K3-1 to the delay control signal input 3-2 starting reseting module M3 by the delay control signal output 2-1 of delays time to control module M2, start the nmos pass transistor Q3-1 conducting of reseting module M3, disconnect the connection of controlled source and delay control circuit.Concrete control procedure is as follows:

1. press the starting switch S3-1 starting reseting module M3, the contact 1 starting the twin coil magnetic latching relay of reseting module M3 is temporarily communicated with by starting switch S3-1 with 3, contact 1 and 2 closes, when the clearing control signal Vdisc of power management module M1 is effective, the voltage of release electrochemical capacitor C2-1, reaches the object resetting and control:

(1) if the voltage of electrochemical capacitor C2-1 exceedes charging starting voltage V _st=V _ds, reset control signal Vdisc and drag down the voltage of electrochemical capacitor C2-1 to charging starting voltage V _st.

(2) if the voltage of electrochemical capacitor C2-1 is lower than charging starting voltage V _st, make electrochemical capacitor C2-1 charge to V because the effective time resetting control signal Vdisc is greater than VDD _sttime, make the charging starting voltage of electrochemical capacitor C2-1 be all V _st.

2. resistance R2-5 and R2-7 and independent amplifier U1-1C forms hysteresis comparator, realizes timing and reset controlling:

(1) timing controls: press the starting switch S3-1 starting reseting module M3, the contact 1 starting the twin coil magnetic latching relay K3-1 of reseting module M3 is temporarily communicated with by starting switch S3-1 with 3, contact 1 and 2 closes, the enabling signal input 2-2 of delays time to control module M2 has high level signal to input, charge to electric capacity C2-2, inverting input 9 voltage of independent amplifier U1-1C is higher than in-phase input end 10, and the nmos pass transistor Q3-1 starting reseting module M3 ends; When power management module M1 exports VDD, and when the contact 1 and 3 starting the twin coil magnetic latching relay K3-1 of reseting module M3 is closed, contact 1 and 2 disconnects, VDD charges to electrochemical capacitor C2-1 and starts timing; When in-phase input end 10 voltage of independent amplifier U1-1C is higher than inverting input 9, start the nmos pass transistor Q3-1 conducting of reseting module M3, delay time arrives.

(2) reset control: if the improper power-off of controlled source, when recovering incoming call, the contact 1 and 3 starting the twin coil magnetic latching relay K3-1 of reseting module M3 closes, contact 1 and 2 disconnects, the enabling signal input 2-2 of delays time to control module M2 can not suddenly change without high level signal input and electric capacity C2-2 both end voltage, the inverting input 9 of independent amplifier U1-1C is low level, resistance R2-2 provides comparative voltage by dividing the in-phase input end 10 pressing to independent amplifier U1-1C, in-phase input end 10 voltage of independent amplifier U1-1C is higher than inverting input 9, start the nmos pass transistor Q3-1 conducting of reseting module M3, the twin coil magnetic latching relay K3-1 starting reseting module M3 resets.

Start in reseting module M3, fuse F3-1 plays overcurrent protection; The contact 5 and 6 of diode D3-1 and D3-2 respectively as twin coil magnetic latching relay K3-1, the fly-wheel diode of contact 5 and 4, play the effect suppressing surge voltage; Resistance R3-1 and R3-2 plays dividing potential drop metering function, and V _{+ Out}-V _d1-2>VCC [R _3-2/ (R _3-1+ R _3-2)] >Vref, wherein R _3-1and R _3-2represent resistance R3-1 and R3-2 respectively; Pressing starting switch S3-1 makes the contact 1 of twin coil magnetic latching relay K3-1 temporarily be communicated with 3, by the controlled source line input 0-1 of the controlled source line output 3-1 and power control module M0 that start reseting module M3, the controlled source that controlled source input terminal P3-1 introduces is supplied to power control module M0, in order to reduce to start power consumption, the contact 1 of startup twin coil magnetic latching relay K3-1 is communicated with 3 export carry out simultaneously with VDD, concrete control procedure is as follows:

(1) when the output 7 of the independent amplifier U1-1B of power management module M1 export high level namely export without VDD time, Vctr=V _{+ Out}-V _d1-2, Vctr>VCC [R _3-2/ (R _3-1+ R _3-2)], output 14 output low level of independent amplifier U1-1D, nmos pass transistor Q3-2 ends.

(2) when namely output 7 output low level of the independent amplifier U1-1B of power management module M1 has VDD to export, the value of Vctr is similar to Vref, Vctr<VCC [R _3-2/ (R _3-1+ R _3-2)], the output 14 of independent amplifier U1-1D exports high level, nmos pass transistor Q3-2 conducting, and twin coil magnetic latching relay K3-1 contact 1 and 3 is closed, contact 1 and 2 disconnects, and controlled source is communicated with delay control circuit.

A kind of situation that realizes of two-wire system delay control switch is: press starting switch S3-1, electrochemical capacitor C2-1 resets, when the normal phase input end 12 of independent amplifier U1-1D is higher than inverting input 13, the contact 1 and 3 of twin coil magnetic latching relay K3-1 is closed, contact 1 and 2 disconnects, open time delay control circuit, VDD charges to electrochemical capacitor C2-1 and starts timing, and load is started working; When in-phase input end 10 voltage of independent amplifier U1-1C is higher than inverting input 9, nmos pass transistor Q3-1 conducting, delay time arrives, and load quits work; If the improper power-off of controlled source, when recovering incoming call, in-phase input end 10 voltage of independent amplifier U1-1C is higher than inverting input 9, nmos pass transistor Q3-1 conducting, twin coil magnetic latching relay K3-1 resets, and the connection of off delay control circuit and controlled source, load quits work.

Claims (5)

1. a two-wire system delay control switch, is characterized in that, comprises power control module M0, power management module M1, delays time to control module M2 and starts reseting module M3; Power control module M0 and power management module M1, delays time to control module M2 and start reseting module M3 power end and be connected power supply VCC is provided, power management module M1 and delays time to control module M2 and start reseting module M3 power end and be connected power vd D is provided, power control module M0, power management module M1, delays time to control module M2 and start reseting module M3 common source negative pole VSS, power management module M1 is respectively with delays time to control module M2 with starts reseting module M3 respective signal port and be connected and provide timing reset signal Vdisc and start reference signal Vctr; Controlled source is input to by controlled source input and starts reseting module M3, the controlled source line output 3-1 starting reseting module M3 is connected with the controlled source line input (0-1) of power control module M0, and controlled source is outputted to controlled source output by power control module M0; Delay control signal output (2-1) and the enabling signal input of delays time to control module M2 | (2-2) is connected with the delay control signal input (3-2) and enabling signal output (3-3) that start reseting module M3 respectively.

2. a kind of two-wire system delay control switch according to claim 1, it is characterized in that, described power control module M0 comprises controlled source lead-out terminal P0-1, unidirectional controllable silicon S CR0-1 and SCR0-2, diode D0-1 and D0-2, voltage stabilizing didoe DZ0-1, rectifier bridge B0-1; An input of the positive pole of unidirectional controllable silicon S CR0-1, the negative pole of unidirectional controllable silicon S CR0-2 and rectifier bridge B0-1 is connected with controlled source lead-out terminal P0-1; Another input of the negative pole of unidirectional controllable silicon S CR0-1, the positive pole of unidirectional controllable silicon S CR0-2 and rectifier bridge B0-1 is connected with the controlled source line input (0-1) of power control module M0; The control pole of unidirectional controllable silicon S CR0-1 is connected with the negative pole of diode D0-2; The control pole of unidirectional controllable silicon S CR0-2 is connected with the negative pole of diode D0-1; The positive pole of diode D0-1 and the positive pole of diode D0-2 are connected with the positive pole of voltage stabilizing didoe DZ0-1; The cathode output end of rectifier bridge B0-1 meets VSS, and the cathode output end of rectifier bridge B0-1 and the negative pole of voltage stabilizing didoe DZ0-1 meet VCC.

3. a kind of two-wire system delay control switch according to claim 1, it is characterized in that, described power management module M1 comprises two independent amplifier U1-1A and U1-1B, electrochemical capacitor C1-1 and C1-4 of four-operational amplifier U1-1, electric capacity C1-2 ~ C1-3 and C1-5 ~ C1-6, resistance R1-1 ~ R1-10, diode D1-1 ~ D1-4, Micro Energy Lose voltage-reference diodes DZ1-1, LED 1-1 and PMOS transistor Q1-1 and nmos pass transistor Q1-2; The positive pole of the positive pole of electrochemical capacitor C1-1, one end of resistance R1-1, one end of resistance R1-3, the source electrode of PMOS transistor Q1-1 and LED 1-1 meets VCC; The negative power end 11 of one end of one end of the negative pole of electrochemical capacitor C1-1 and C1-4, one end of electric capacity C1-2, electric capacity C1-3, one end of electric capacity C1-5, electric capacity C1-6, the positive pole of Micro Energy Lose voltage-reference diodes DZ1-1, the negative pole of diode D1-1, one end of resistance R1-4 and one end of resistance R1-9, the source electrode of nmos pass transistor Q1-2 and four-operational amplifier U1-1 meets VSS; The negative pole of LED 1-1 and the positive pole of electrochemical capacitor C1-4 are connected with the positive power source terminal (4) of four-operational amplifier U1-1; The other end of the other end of resistance R1-1, one end of resistance R1-2, electric capacity C1-2 and the negative pole of Micro Energy Lose voltage-reference diodes DZ1-1 are connected with the inverting input (2) of independent amplifier U1-1A; One end of resistance R1-5 and the grid of PMOS transistor Q1-1 are connected with the output (1) of independent amplifier U1-1A; The other end of resistance R1-2 and one end of resistance R1-6 are connected with the in-phase input end (5) of independent amplifier U1-1B; The other end of resistance R1-3 is connected with the inverting input (6) of independent amplifier U1-1B with the other end of resistance R1-4 and the other end of electric capacity C1-3; The other end of resistance R1-6, one end of resistance R1-10 and the positive pole of diode D1-2 with D1-3 are connected with the output (7) of independent amplifier U1-1B; The other end of the other end of resistance R1-10, the negative pole of diode D1-3 and electric capacity C1-6 is connected with the grid of nmos pass transistor Q1-2; The drain electrode of nmos pass transistor Q1-2 meets Vdisc; The in-phase input end 3 of one end of resistance R1-7, one end of resistance R1-8 and the other end of resistance R1-9, the negative pole of diode D1-2 and independent amplifier U1-1A meets Vctr; The other end of resistance R1-8 is connected with the negative pole of diode D1-4; The positive pole of diode D1-4, the other end of electric capacity C1-5 and the drain electrode of PMOS transistor Q1-1 meet VDD; The other end of resistance R1-5 and the other end of resistance R1-7 are connected with the positive pole of diode D1-1.

4. a kind of two-wire system delay control switch according to claim 1, it is characterized in that, described delays time to control module M2 comprises the independent amplifier U1-1C of four-operational amplifier U1-1, resistance R2-1 ~ R2-7, electrochemical capacitor C2-1, electric capacity C2-2, diode D2-1; One end of resistance R2-1 and a termination VDD of resistance R2-3; The other end of resistance R2-1 and one end of resistance R2-2 are connected with one end of resistance R2-5; The other end of resistance R2-2 and the positive pole of electrochemical capacitor C2-1 meet Vdisc; The other end of resistance R2-5 and one end of resistance R2-7 are connected with the in-phase input end 10 of independent amplifier U1-1C; One end of resistance R2-6, one end of electric capacity C2-2 and the negative pole of diode D2-1 are connected with the inverting input 9 of independent amplifier U1-1C; The other end of resistance R2-7 and the output 8 of independent amplifier U1-1C are connected with the delay control signal output (2-1) of delays time to control module M2; The positive pole of diode D2-1 is connected with the enabling signal input (2-2) of delays time to control module M2; The other end of resistance R2-3 and the other end of resistance R2-6 are connected with one end of resistance R2-4; Another termination VSS of the negative pole of electrochemical capacitor C2-1, the other end of electric capacity C2-2 and resistance R2-4.

5. a kind of two-wire system delay control switch according to claim 1, it is characterized in that, described startup reseting module M3 comprises the independent amplifier U1-1D of four-operational amplifier U1-1, controlled source input terminal P3-1, fuse F3-1, starting switch S3-1, twin coil magnetic latching relay K3-1, diode D3-1 and D3-2, resistance R3-1 and R3-2 and nmos pass transistor Q3-1 and Q3-2; Controlled source input terminal P3-1 is connected with one end of fuse F3-1; The other end of fuse F3-1 and the contact 3 of twin coil magnetic latching relay K3-1 are connected with one end of starting switch S3-1; The other end of starting switch S3-1 and the contact 1 of twin coil magnetic latching relay K3-1 are connected with the controlled source line output (3-1) starting reseting module M3; The contact 5 of the negative pole of diode D3-1 and the negative pole of diode D3-2 and twin coil magnetic latching relay K3-1 meets VDD; The grid of nmos pass transistor Q3-1 is connected with the delay control signal input 3-2 starting reseting module M3; The positive pole of diode D3-1 and the contact (6) of twin coil magnetic latching relay K3-1 are connected with the drain electrode of nmos pass transistor Q3-1; The positive pole of diode D3-2 and the contact (4) of twin coil magnetic latching relay K3-1 are connected with the drain electrode of nmos pass transistor Q3-2; The contact (2) of twin coil magnetic latching relay K3-1 is connected with one end of resistance R3-1; The other end of resistance R3-1 and one end of resistance R3-2 are connected with the in-phase input end (12) of independent amplifier U1-1D; The inverting input (13) of independent amplifier U1-1D meets Vctr; The grid of nmos pass transistor Q3-2 and the output (14) of independent amplifier U1-1D are connected with the enabling signal output (3-3) starting reseting module M3; The other end of resistance R3-2 and the source electrode of nmos pass transistor Q3-1 and Q3-2 meet VSS.