CN105335299A - Data storage method, memory control circuit unit and memory storage apparatus - Google Patents

Data storage method, memory control circuit unit and memory storage apparatus Download PDF

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CN105335299A
CN105335299A CN 201410394322 CN201410394322A CN105335299A CN 105335299 A CN105335299 A CN 105335299A CN 201410394322 CN201410394322 CN 201410394322 CN 201410394322 A CN201410394322 A CN 201410394322A CN 105335299 A CN105335299 A CN 105335299A
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data
programmed
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CN105335299B (en )
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叶志刚
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群联电子股份有限公司
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Abstract

The invention provides a data storage method, a memory control circuit unit and a memory storage apparatus. The method comprises: generating odd-even information according to first data. The method further comprises: when the first data are programmed to a first entity programming unit, programming at least one mark to a redundancy bit region in the first entity programming unit. The method further comprises: programming the odd-even information into at least one second entity programming unit arranged after the first entity programming unit, wherein the at least one mark indicates that the odd-even information is programmed into the at least one second entity programming unit.

Description

数据存储方法、存储器控制电路单元及存储器存储装置 The data storage method, the memory control circuit unit and a memory storage device

技术领域 FIELD

[0001] 本发明是有关于一种数据存储方法,且特别是有关于一种用于可复写式非易失性存储器的数据存储方法、存储器控制电路单元及存储器存储装置。 [0001] The present invention relates to a data storage method, and more particularly relates to a rewritable data storage method for a nonvolatile memory, the memory control circuit unit and a memory storage device.

背景技术 Background technique

[0002] 数码相机、手机与MP3在这几年来的成长十分迅速,使得消费者对存储媒体的需求也急速增加。 [0002] Digital cameras, mobile phones and MP3 growing very rapidly in the past few years, making the consumer demand for storage media is also rapidly increasing. 由于可复写式非易失性存储器(rewritable non-volatile memory)具有数据非易失性、省电、体积小、无机械结构、读写速度快等特性,因此,近年可复写式非易失性存储器产业成为电子产业中相当热门的一环。 Since the rewritable nonvolatile memory (rewritable non-volatile memory) having a non-volatile, low power, small size, no mechanical structure, characteristics such as data read and write speed, and therefore, in recent years, non-volatile rewritable the memory industry has become very popular in the electronics industry a ring. 例如,以快闪存储器作为存储媒体的固态硬盘(Solid-state drive)已广泛应用作为电脑主机的硬盘,以提升电脑的存取效能。 For example, in a flash memory as a storage medium SSD (Solid-state drive) has been widely used as a host computer hard drive, a computer to improve access performance.

[0003] 由于存储在可复写式非易失性存储器的数据可能会因各种因素(例如,存储器单元的漏电、程序化失败、损毁等)而产生错误比特,因此,在存储器存储系统中一般会配置错误检查与校正电路并为所存储的数据产生错误检查与校正码以确保数据的正确性。 [0003] Data stored in the rewritable nonvolatile memory may be a bit error due to various factors (e.g., the drain of memory cells, programming failure, damage, etc.) due, therefore, is generally stored in a memory system You configure the error checking and correcting circuit and an error checking and correction code stored data to ensure data accuracy. 然而,当数据中的错误比特数目超过错误检查与校正电路所能检测与校正的错误比特数时,含有错误比特的数据就无法被校正,而造成数据遗失。 However, when the number of error bits in the data exceeds the error checking and correcting circuit of error bits can be detected and corrected, the data containing error bits can not be corrected, and cause data loss. 一般来说,当此情况发生时,可根据存储在可复写式非易失性存储器中对应于所欲校正的数据的奇偶性(Parity)来校正此数据。 In general, when this happens, this may be corrected in accordance with stored data corresponds to the desired correction parity data (Parity) in the rewritable nonvolatile memory. 传统上,由于此些奇偶信息所在的实体程序化单元的数据比特区与冗余比特区中的数据也是通过其他受保护的数据所计算出来的,即,无法通过冗余比特区中的信息得知此些实体程序化单元即是奇偶信息所在的实体程序化单元。 Conventionally, since the data of such physical information of the program unit where the ratio of parity redundancy SAR ratio of the SAR data is also calculated by the other protected data, i.e., can not be prepared by the redundancy of the SAR ratio information Such known solid programming unit, that unit is programmed parity information entity is located. 因此,传统的方法会将奇偶信息放置在固定的位置上。 Thus, the conventional method will parity information is placed in a fixed position.

[0004] 例如,假设存储器存储系统具有八个存储器晶粒,则使用其中最后一个存储器晶粒来存储奇偶信息。 [0004] For example, assuming memory storage system having eight memory die, wherein a last memory die is used to store parity information. 倘若来自主机系统的数据仅需写入一个实体程序化单元时,则必须要将其中间的六个存储器晶粒中相对应的实体程序化单元填上虚构数据(dummy data),以产生欲存放在第八个存储器晶粒中相对应的实体程序化单元中的奇偶信息。 When data from the host system if the only program to write a solid unit, the memory must want six grain wherein an entity corresponding to the program data unit fictitious fill (dummy data), to be stored to generate parity information entity in the programming unit in the eighth memory dies corresponding. 也就是说,此种作法将造成存储器存储装置中存储空间的浪费。 In other words, this approach would result in a waste of memory stored in the storage space. 基此,如何在避免存储器存储装置中存储空间的浪费下增加并提升错误校正的更正能力与效率是此领域技术人员所致力的目标。 By virtue of this, how to avoid wasting the memory storage device and the storage space is increased to enhance the capacity and efficiency of correction in the error correction is skilled in this field of endeavor target.

发明内容 SUMMARY

[0005] 本发明提供一种数据存储方法、存储器控制电路单元及存储器存储装置,其可以有效地避免存储器存储装置中存储空间的浪费并且当无法由错误检查与校正码校正数据的错误比特时,可通过所存储的奇偶信息来更正此数据的错误比特,由此提升错误校正的能力。 [0005] The present invention provides a method of storing data, the memory control circuit unit and a memory storage device, which can effectively avoid wasting memory storage device and the storage space when the uncorrectable error bit data by the error checking and correction code, the error bits can be corrected by parity data of this stored information, thereby to enhance the error correction capability.

[0006] 本发明的一范例实施例提供一种用于可复写式非易失性存储器模块的数据存储方法,所述可复写式非易失性存储器模块包括多个实体抹除单元,且每一实体抹除单元包括多个实体程序化单元,以及其中每一实体程序化单元包括数据比特区与冗余比特区,本数据存储方法包括:依据第一数据产生一奇偶信息;将所述数据程序化至所述实体程序化单元之中的第一实体程序化单元中;以及将所述奇偶信息程序化至所述实体程序化单元之中的至少一第二实体程序化单元中,其中所述至少一第二实体程序化单元是排列在所述第一实体程序化单元之后。 [0006] an exemplary embodiment of the present invention provides a method of storing data rewritable non-volatile memory module, the rewritable non-volatile memory module comprises a plurality of physical erase unit, and each a physical erase unit includes a plurality of entities a program unit, and wherein each entity comprises a data programming unit than the SAR, the present data storage method comprises the redundant DC ratio: generating parity information based on a first data; said data programmed to the first entity among entities programming unit programming unit; and the parity information to the at least one programming unit programmed second entity among the entities programming unit, wherein said at least one second entity is a programming unit arranged after the first program entity unit. 在上述将所述数据程序化至所述实体程序化单元之中的所述第一实体程序化单元的步骤包括:将至少一标记程序化至所述第一实体程序化单元之中的冗余比特区,其中所述至少一标记指示所述奇偶信息被程序化至所述至少一第二实体程序化单元中。 In the data programmed into the programming unit, the steps among the first entity entity program unit comprising: at least one tag programmed to the redundant entity among the first program unit SAR ratio, wherein said at least one flag indicating the parity information is programmed to the second entity at least one programming unit.

[0007] 在本发明的一实施例中,上述第一数据包括一使用者数据与对应所述使用者数据的一管理信息,其中所述使用者数据被程序化至所述第一实体程序化单元之中的数据比特区,其中对应所述使用者数据的所述管理信息被程序化至所述第一实体程序化单元之中的冗余比特区。 [0007] In an embodiment of the present invention, the first data comprising a data management information corresponding to a user of the user data, wherein the user data is programmed to the first programmed entity among the data units than the SAR, wherein the management information corresponding to the user data is programmed into the redundancy among the first entity than the SAR program unit.

[0008] 在本发明的一实施例中,上述第一数据包括一使用者数据、对应所述使用者数据的一管理信息以及对应所述使用者数据的一错误检查与校正码。 [0008] In an embodiment of the present invention, the first data comprises a user data, a corresponding one of said error checking and correcting codes, and a management information corresponding to the user data is user data. 其中所述错误检查与校正码是根据所述使用者数据所产生的。 Wherein said error checking and correction code according to said user data is generated. 其中所述使用者数据被程序化至所述第一实体程序化单元之中的数据比特区,其中对应所述使用者数据的所述管理信息被程序化至所述第一实体程序化单元之中的冗余比特区,其中对应所述使用者数据的所述错误检查与校正码被程序化至所述第一实体程序化单元之中的冗余比特区。 Wherein said user data is programmed to the first data among the entities than the SAR program unit, wherein the management information corresponding to the user data is programmed into the programming unit of the first entity redundancy than the SAR, wherein said user data corresponding to the error checking and correction code to be programmed into the first redundancy unit than the SAR program entity.

[0009] 在本发明的一实施例中,上述将所述至少一标记程序化至所述第一实体程序化单元之中的冗余比特区的步骤包括:将第一标记程序化至所述第一实体程序化单元之中的最后一个实体程序化单元的冗余比特区,其中所述至少一第二实体程序化单元是排列在所述第一实体程序化单元之中的所述最后一个实体程序化单元之后,其中所述第一标记指示所述至少一第二实体程序化单元存储所述奇偶信息;以及将第二标记程序化至所述实体程序化单元之中的至少一第三实体程序化单元的冗余比特区,其中所述至少一第三实体程序化单元是排列在所述至少一第二实体程序化单元之后,其中所述第二标记指示所述至少一第二实体程序化单元存储所述奇偶信息。 [0009] In an embodiment of the present invention, the above-described at least one marker to the programmed redundancy among the first entity procedural steps than the SAR unit comprises: a first mark to the programmed Finally, a redundancy entity in programmed cell first entity than the SAR program unit, wherein said at least one second entity is a programming unit arranged in said first entity said programming unit last after solid programming unit, wherein the first flag indicates that the at least one second entity of a program unit stores the parity information; and a second mark programmed to said at least one third entity in programmed cell redundancy programming entities than the SAR unit, wherein the at least one third entity is a programming unit arranged after said at least one second entity programming unit, wherein said second indicia indicating said at least one second entity the programming unit stores parity information.

[0010] 在本发明的一实施例中,上述将所述至少一标记程序化至所述第一实体程序化单元之中的冗余比特区的步骤还包括:建立一奇偶信息地址对应表;以及将一第三标记记录在所述奇偶信息地址对应表,其中所述第三标记指示所述至少一第二实体程序化单元存储所述奇偶信息。 [0010] In an embodiment of the present invention, the above-described at least one marker to the programmed redundancy among the first entity procedural steps than the SAR unit further comprises: establishing a parity address correspondence table; a third mark recording and the parity information in the address correspondence table, wherein the third flag indicates that the at least one second entity of a program unit stores the parity information.

[0011 ] 在本发明的一实施例中,上述将所述至少一标记程序化至所述第一实体程序化单元之中的冗余比特区的步骤包括:计数所述第一实体程序化单元的个数;以及根据所述第一实体程序化单元的个数,在每一所述第一实体程序化单元的冗余比特区中记录一标记值,其中记录在所述第一实体程序化单元中的所述标记值依据所述第一实体程序化单元的排列依序地递减。 [0011] In an embodiment of the present invention, the above-described at least one marker to the programmed redundancy among the first entity procedural steps than the SAR unit comprises: a counting unit of the first program entity number; and a program unit according to the number of the first entity, a recording mark than the DC values ​​in each of the redundancy programming unit in the first entity, wherein the first entity in the recording of the program the first permutation process unit based on the value of the marker entity unit sequentially decremented.

[0012] 在本发明的一实施例中,上述标记值之中的第一标记值为1,且所述第一标记值被记录在所述第一实体程序化单元之中的最后一个实体程序化单元的冗余比特区中,且所述至少一第二实体程序化单元是排列在所述第一实体程序化单元之中的所述最后一个实体程序化单元之后,其中所述标记值之中的第二标记值为2,且所述第二标记值被记录在所述第一实体程序化单元之中相邻且排列在所述最后一个实体程序化单元之前的实体程序化单元的冗余比特区中,其中所述标记值之中的第三标记值为3,且所述第三标记值被记录在所述第一实体程序化单元之中相邻且排列在记录所述第二标记值的实体程序化单元之前的实体程序化单元的冗余比特区中。 [0012] In an embodiment of the present invention, the first marker in the flag value is 1, and the first mark value is recorded in the last entity of the first program unit is programmed entity after redundancy unit than in the SAR, and the at least one second entity of the program unit is arranged in said first entity a final programming unit programming means entity, wherein the flag values the second marker is 2, and the second flag value is recorded before a final redundant physical entities programming unit and a program unit are arranged adjacent to the first entity in the program unit I ratio of the SAR, wherein the third label value tag among the value 3, and the third flag value is recorded adjacent to the first entity in programmed recording unit and aligned in said second redundancy programming unit programming entity before the entity tag value means the ratio of the SAR.

[0013] 在本发明的一实施例中,上述第一数据包括一第二数据以及一错误检查与校正码,并且上述数据存储方法,还包括:当无法通过使用所述错误检查与校正码来校正所述第二数据时,根据所述至少一标记获得记录所述奇偶信息的所述至少一第二实体程序化单元的地址,从所述至少一第二实体程序化单元中读取所述奇偶信息以及依据所读取的所述奇偶信息来校正所述第二数据。 [0013] In an embodiment of the present invention, the first data comprises a second data and an error checking and correction code, and the data storage method further comprising: when not the error checking and correction codes by using the second correction data, obtained from the at least one recording mark the parity of the address information of at least a second program unit of the entity, the at least one reading from the second entity in the programming unit the parity information and the parity information read based on the second corrected data.

[0014] 本发明的一范例实施例提供一种用于可复写式非易失性存储器模块的数据存储方法,所述可复写式非易失性存储器模块包括多个实体抹除单元,且每一实体抹除单元包括多个实体程序化单元,以及其中每一实体程序化单元包括数据比特区与冗余比特区,本数据存储方法包括:建立一奇偶信息地址对应表;依据第一数据产生一奇偶信息;将所述数据程序化至所述实体程序化单元之中的第一实体程序化单元中;将所述奇偶信息程序化至所述实体程序化单元之中的至少一第二实体程序化单元中,以及将至少一标记记录在所述奇偶信息地址对应表,其中所述标记指示所述奇偶信息被程序化至所述至少一第二实体程序化单元中。 [0014] an exemplary embodiment of the present invention provides a method of storing data rewritable non-volatile memory module, the rewritable non-volatile memory module comprises a plurality of physical erase unit, and each a physical erase unit includes a plurality of entities a program unit, and wherein each unit comprises a data entity programmed redundancy ratio than DC, DC, the present data storage method comprising: establishing a parity address correspondence table; data generated according to a first a parity information; the data programmed into the programming unit programming entity of the first entity among the units; programmed the parity information to the at least one second entity in the entity program unit programming unit, and at least a mark parity information is recorded in the address correspondence table, wherein the marker indicates the parity information is programmed to the second entity at least one programming unit.

[0015] 本发明的一范例实施例提出一种用于控制可复写式非易失性存储器模块的存储器控制电路单元,其中所述可复写式非易失性存储器模块包括多个实体抹除单元,且每一实体抹除单元包括多个实体程序化单元,以及其中每一实体程序化单元包括数据比特区与冗余比特区。 Example proposes a method of controlling the memory rewritable non-volatile memory module of the control circuit unit for an exemplary [0015] embodiment of the present invention, wherein the rewritable non-volatile memory module comprises a plurality of physical erase unit , and each unit comprises a plurality of physical entities erase programming unit, and wherein each entity comprises a programming unit and the redundant data than the ratio of DC DC. 此存储器控制电路单元包括主机接口、存储器接口与存储器管理电路。 This memory control circuit includes a host interface unit, a memory interface and memory management circuitry. 主机接口用以耦接至主机系统,存储器接口用以耦接至可复写式非易失性存储器模块,以及存储器管理电路耦接至主机接口与存储器接口。 A host interface for coupling to the host system, a memory interface for coupling to a rewritable nonvolatile memory module, and a memory management circuit coupled to a host interface and the memory interface. 存储器管理电路用以依据第一数据产生一奇偶信息并且将所述第一数据程序化至所述实体程序化单元之中的第一实体程序化单元中,其中所述存储器管理电路还用以将所述奇偶信息程序化至所述实体程序化单元之中的至少一第二实体程序化单元中,其中所述至少一第二实体程序化单元是排列在所述第一实体程序化单元之后。 Memory management circuitry for generating a parity data according to the first information and the first data is programmed to the first entity in the entity programming unit programming unit, wherein the memory management circuitry is further configured to the parity information to the at least one programming unit programmed second entity among the entities programming unit, wherein the at least one second entity is a programming unit arranged after the first program entity unit. 在上述将所述数据程序化至所述实体程序化单元之中的所述第一实体程序化单元的操作中,存储器管理电路将至少一标记程序化至所述第一实体程序化单元之中的冗余比特区,其中所述至少一标记指示所述奇偶信息被程序化至所述至少一第二实体程序化单元中。 The above data is programmed in the operating program to the unit entity among the first entity programming unit, the memory management circuitry to the at least one marker in said first programming unit program entity redundant DC ratio, wherein said at least one flag indicating the parity information is programmed to the at least one second entity programming unit.

[0016] 在本发明的一实施例中,上述第一数据包括一使用者数据与对应所述使用者数据的一管理信息,其中所述使用者数据被程序化至所述第一实体程序化单元之中的数据比特区,其中对应所述使用者数据的所述管理信息被程序化至所述第一实体程序化单元之中的冗余比特区。 [0016] In an embodiment of the present invention, the first data comprising a data management information corresponding to a user of the user data, wherein the user data is programmed to the first programmed entity among the data units than the SAR, wherein the management information corresponding to the user data is programmed into the redundancy among the first entity than the SAR program unit.

[0017] 在本发明的一实施例中,上述第一数据包括一使用者数据、对应所述使用者数据的一管理信息以及对应所述使用者数据的一错误检查与校正码。 [0017] In an embodiment of the present invention, the first data comprises a user data, a corresponding one of said error checking and correcting codes, and a management information corresponding to the user data is user data. 其中所述错误检查与校正码是根据所述使用者数据所产生的。 Wherein said error checking and correction code according to said user data is generated. 其中所述使用者数据被程序化至所述第一实体程序化单元之中的数据比特区,其中对应所述使用者数据的所述管理信息被程序化至所述第一实体程序化单元之中的冗余比特区,其中对应所述使用者数据的所述错误检查与校正码被程序化至所述第一实体程序化单元之中的冗余比特区。 Wherein said user data is programmed to the first data among the entities than the SAR program unit, wherein the management information corresponding to the user data is programmed into the programming unit of the first entity redundancy than the SAR, wherein said user data corresponding to the error checking and correction code to be programmed into the first redundancy unit than the SAR program entity.

[0018] 在本发明的一实施例中,上述将所述至少一标记程序化至所述第一实体程序化单元之中的冗余比特区的操作中,存储器管理电路将第一标记程序化至所述第一实体程序化单元之中的最后一个实体程序化单元的冗余比特区,其中所述至少一第二实体程序化单元是排列在所述第一实体程序化单元之中的所述最后一个实体程序化单元之后,其中所述第一标记指示所述至少一第二实体程序化单元存储所述奇偶信息,其中存储器管理电路还用以将第二标记程序化至所述实体程序化单元之中的至少一第三实体程序化单元的冗余比特区,其中所述第三实体程序化单元是排列在所述至少一第二实体程序化单元之后,并且所述第二标记指示所述至少一第二实体程序化单元存储所述奇偶信息。 [0018] In an embodiment of the present invention, the aforementioned at least one marker to the programming to the redundant entity among the first programming operation unit than in the SAR, the first marker memory management circuitry programmed a redundancy entity to the last programmable unit among the first entity than the SAR program unit, wherein said at least one second entity is a programming unit arranged in said first entity being programmed unit after the last entity of said programming means, wherein said first indicia indicating said at least one second entity of a program unit stores the parity information, wherein the memory management circuitry is further programmed for converting the second mark to the program entity at least a third program redundancy unit among the entities than the SAR unit, wherein the third entity is a programming unit arranged after said at least one second entity programming unit, and the second flag indicating at least one second entity of a program unit stores the parity information.

[0019] 本发明的一范例实施例提出一种存储器存储装置,其包括连接接口单元、可复写式非易失性存储器模块与存储器控制电路单元。 [0019] an exemplary embodiment of the present invention provides a memory storage device, which includes a unit connection interface, a nonvolatile rewritable memory module and the memory control circuit unit. 连接接口单元用以耦接至主机系统。 Connection interface unit for coupling to the host system. 可复写式非易失性存储器模块包括多个实体抹除单元,且每一实体抹除单元包括多个实体程序化单元,其中每一实体程序化单元包括数据比特区与冗余比特区。 Rewritable nonvolatile memory module comprises a plurality of physical erase unit, and each unit comprises a plurality of physical entities erase programming unit, wherein each entity comprises a programming unit and the redundant data than the ratio of DC DC. 存储器控制电路单元耦接至连接接口单元与可复写式非易失性存储器模块,并且用以依据第一数据产生一奇偶信息,并且将所述第一数据程序化至所述实体程序化单元之中的一第一实体程序化单元中。 The memory unit is coupled to a control circuit connected to the interface unit with a rewritable non-volatile memory module, and for generating a parity data according to the first information, and the data programmed to the first physical unit of programming a first entity in the programming unit. 此外,存储器控制电路单元还用以将所述奇偶信息程序化至所述实体程序化单元之中的至少一第二实体程序化单元中,其中所述至少一第二实体程序化单元是排列在所述第一实体程序化单元之后。 Further, the memory control circuit unit for the parity information further programmed to at least a second entity among the programming unit programming entity unit, wherein the at least one second physical unit is arranged in the program after programming the first physical unit. 在上述将所述第一数据程序化至所述实体程序化单元之中的所述第一实体程序化单元的操作中,存储器控制电路单元将至少一标记程序化至所述第一实体程序化单元之中的冗余比特区,其中所述至少一标记指示所述奇偶信息被程序化至所述至少一第二实体程序化单元中。 The above-mentioned first data to the programming unit of the operation program among the program entity first entity unit, the memory control circuit unit to the at least one marker to the first entity programmed programmable redundancy among the DC unit ratio, wherein said at least one flag indicating the parity information is programmed to the at least one second entity programming unit.

[0020] 在本发明的一实施例中,上述第一数据包括一使用者数据与对应所述使用者数据的一管理信息,其中所述使用者数据被程序化至所述第一实体程序化单元之中的数据比特区,其中对应所述使用者数据的所述管理信息被程序化至所述第一实体程序化单元之中的冗余比特区。 [0020] In an embodiment of the present invention, the first data comprising a data management information corresponding to a user of the user data, wherein the user data is programmed to the first programmed entity among the data units than the SAR, wherein the management information corresponding to the user data is programmed into the redundancy among the first entity than the SAR program unit.

[0021] 在本发明的一实施例中,上述第一数据包括一使用者数据、对应所述使用者数据的一管理信息以及对应所述使用者数据的一错误检查与校正码。 [0021] In an embodiment of the present invention, the first data comprises a user data, a corresponding one of said error checking and correcting codes, and a management information corresponding to the user data is user data. 其中所述错误检查与校正码是根据所述使用者数据所产生的。 Wherein said error checking and correction code according to said user data is generated. 其中所述使用者数据被程序化至所述第一实体程序化单元之中的数据比特区,其中对应所述使用者数据的所述管理信息被程序化至所述第一实体程序化单元之中的冗余比特区,其中对应所述使用者数据的所述错误检查与校正码被程序化至所述第一实体程序化单元之中的冗余比特区。 Wherein said user data is programmed to the first data among the entities than the SAR program unit, wherein the management information corresponding to the user data is programmed into the programming unit of the first entity redundancy than the SAR, wherein said user data corresponding to the error checking and correction code to be programmed into the first redundancy unit than the SAR program entity.

[0022] 在本发明的一实施例中,上述将所述至少一标记程序化至所述第一实体程序化单元之中的冗余比特区的操作中,存储器控制电路单元将一第一标记程序化至所述第一实体程序化单元之中的最后一个实体程序化单元的冗余比特区,其中所述至少一第二实体程序化单元是排列在所述第一实体程序化单元之中的所述最后一个实体程序化单元之后,其中所述第一标记指示所述至少一第二实体程序化单元存储所述奇偶信息,其中存储器控制电路单元还用以将第二标记程序化至所述实体程序化单元之中的至少一第三实体程序化单元的冗余比特区,其中所述至少一第三实体程序化单元是排列在所述至少一第二实体程序化单元之后,并且所述第二标记指示所述至少一第二实体程序化单元存储所述奇偶信息。 [0022] In an embodiment of the present invention, the above-described at least one marker to the programmed redundancy among the first physical unit than the operating program of the SAR, the memory control circuit unit a first marker programming said redundant to the last entity in programmed cell first entity than the SAR program unit, wherein said at least one second entity is a programming unit arranged in said first entity program unit after the last program entity unit, wherein the first flag indicates that the at least one second entity of a program unit stores the parity information, wherein the memory control circuit for converting the second unit is further programmed to mark the at least a third entity redundancy programming unit among said entity than the SAR program unit, wherein said at least one third entity is a programming unit arranged after said at least one second entity programming unit, and the said at least one second entity of a program unit stores the flag indicating the second parity information.

[0023] 在本发明的一实施例中,上述将所述至少一标记程序化至所述第一实体程序化单元之中的冗余比特区的操作中,存储器控制电路单元建立一奇偶信息地址对应表并且将第三标记记录在所述奇偶信息地址对应表,其中所述第三标记指示所述至少一第二实体程序化单元存储所述奇偶信息。 [0023] In an embodiment of the present invention, the aforementioned at least one marker to the programming to the redundant entity among the first SAR program than the operating unit, the memory control circuit unit to establish an address parity information third correspondence table and the mark parity information is recorded in the address correspondence table, wherein the third flag indicates that the at least one second entity of a program unit stores the parity information.

[0024] 在本发明的一实施例中,上述将所述至少一标记程序化至所述第一实体程序化单元之中的冗余比特区的操作中,存储器控制电路单元计数所述第一实体程序化单元的个数,并且根据所述第一实体程序化单元的个数,在每一第一实体程序化单元的冗余比特区中记录一标记值,其中记录在所述第一实体程序化单元中的所述标记值依据所述第一实体程序化单元的排列依序地递减。 [0024] In an embodiment of the present invention, the above-described at least one marker to the programmed redundancy among the first physical unit than the operating program of the SAR, the memory control circuit unit counts the first the number of entities programming unit, and the program according to the number of cells in the first entity, a recording mark than the DC values ​​in the program unit in the redundancy each first entity, wherein in recording said first entity the first permutation process unit based on the value of the marker entity programming unit sequentially decremented.

[0025] 在本发明的一实施例中,上述标记值之中的第一标记值为1,且所述第一标记值被记录在所述第一实体程序化单元之中的最后一个实体程序化单元的冗余比特区中,且所述至少一第二实体程序化单元是排列在所述第一实体程序化单元之中的所述最后一个实体程序化单元之后。 [0025] In an embodiment of the present invention, the first marker in the flag value is 1, and the first mark value is recorded in the last entity of the first program unit is programmed entity redundancy unit than in the SAR, and the at least one second entity is a programming unit arranged after the first entity in the program unit last entity program unit. 其中标记值之中的第二标记值为2,且所述第二标记值被记录在所述第一实体程序化单元之中相邻且排列在所述最后一个实体程序化单元之前的实体程序化单元的冗余比特区中。 Wherein the second mark from among the label value is 2, and the adjacent second mark value is recorded in the first physical unit and arranged in the last program a physical entity program before the program unit redundancy unit than in the SAR. 其中所述标记值之中的第三标记值为3,且所述第三标记值被记录在所述第一实体程序化单元之中相邻且排列在记录所述第二标记值的实体程序化单元之前的实体程序化单元的冗余比特区中。 Wherein the third label value tag among the value 3, and the third flag value is recorded adjacent to the first entity in programmed recording unit and aligned in said second program entity tag value redundant before the unit solid than the programming unit in the SAR.

[0026] 在本发明的一实施例中,上述第一数据包括一第二数据以及一错误检查与校正码,当无法通过使用所述错误检查与校正码来校正所述第二数据时,存储器控制电路单元还用以根据所述至少一标记获得记录所述奇偶信息的所述至少一第二实体程序化单元的地址,从所述至少一第二实体程序化单元中读取所述奇偶信息以及依据所读取的所述奇偶信息来校正所述第二数据。 [0026] In an embodiment of the present invention, the first data comprises a second data and an error checking and correcting code when said error checking and correction can not code by using the second correction data memory the control circuit unit is further configured to address the at least one recording mark to obtain the parity information for at least one second entity programming unit, reads the parity information from the at least one second entity programming unit the parity information and the read data based on the second corrected.

[0027] 基于上述,当从可复写式非易失性存储器模块中读取的数据比特存在错误时,本发明的一范例实施例可以根据记录在实体程序化单元中的至少一标记,快速地获得奇偶信息所在的实体程序化单元地址。 [0027] Based on the above, when the data read from the rewritable non-volatile memory module of bit errors, an exemplary embodiment of the present invention may be at least one recording mark entity programming unit, rapidly those entities with programmed cell address parity information is located. 据此,本发明范例实施例提出的数据存储方法、存储器控制电路单元与存储器存储装置可有效地增加错误校正的更正能力与效率。 Accordingly, the data storage method of the exemplary embodiment of the present invention proposed embodiment, the memory control circuit unit and the memory storage device may be effective to increase the correcting capability of the error correction efficiency.

[0028] 为让本发明的上述特征和优点能更明显易懂,下文特举实施例,并配合附图作详细说明如下。 [0028] In order to make the above features and advantages of the invention more comprehensible, several embodiments accompanied with figures are described in detail below.

附图说明 BRIEF DESCRIPTION

[0029] 图1A是根据本发明第一范例实施例所示出的主机系统与存储器存储装置的示意图; [0029] FIG 1A is a first exemplary embodiment of the present invention is shown in Scheme host system and out of the memory storage devices;

[0030] 图1B是根据本发明的第一范例实施例所示出的电脑、输入/输出装置与存储器存储装置的示意图; [0030] FIG. 1B is in accordance with a first exemplary embodiment of the present invention is shown in the schematic computer, input / output devices and memory storage devices out;

[0031] 图1C是根据本发明第一范例实施例所示出的主机系统与存储器存储装置的示意图; [0031] FIG 1C is a first exemplary embodiment of the present invention is shown in Scheme host system and out of the memory storage devices;

[0032] 图2是示出图1A所示的存储器存储装置的概要方块图; [0032] FIG. 2 shows a schematic block diagram of a memory storage device 1A shown;

[0033] 图3是根据本发明第一范例实施例所示出的存储器控制电路单元的概要方块图; [0033] FIG. 3 is a first exemplary embodiment of the present invention is shown a schematic block diagram of a circuit of a memory control unit;

[0034] 图4A与图4B是根据第一范例实施例所示出的管理实体抹除单元的范例示意图; [0034] FIG. 4A and 4B according to the first exemplary embodiment is shown a schematic view of a management entity exemplary erase unit;

[0035] 图5A至图5B是根据本发明第一范例实施例所示出的将写入数据、对应于写入数据的错误检查与校正码以及用以记录奇偶信息的至少一标记写入至实体程序化单元的范例示意图; [0035] Figures 5A-5B are exemplary embodiments of the present invention according to the first embodiment shown the write data, write to the write data corresponding to the error checking and correction code for recording mark and at least one parity information to sample application unit schematic entity;

[0036] 图6是根据本发明第一范例实施例所示出的将写入数据、对应于写入数据的错误检查与校正码以及用以记录奇偶信息的至少一标记写入至实体程序化单元的另一个范例不意图; [0036] FIG. 6 is a first exemplary embodiment of the present invention is shown to write data corresponding to write procedural entities write data error checking and correcting code and at least one mark for recording information to parity another example of the unit is not intended;

[0037] 图7是根据本发明的第一范例实施例所示出的数据存储方法的流程图; [0037] FIG. 7 is a first exemplary embodiment of the present invention shown in a flowchart of a method of storing data;

[0038] 图8A至图SB是根据本发明第二范例实施例所示出的将写入数据、对应于写入数据的错误检查与校正码以及用以记录奇偶信息的至少一标记写入至实体程序化单元的范例示意图; [0038] FIGS. 8A to FIG. SB is according to a second exemplary embodiment of the present invention embodiment shown the write data, write to the write data corresponding to the error checking and correction code for recording mark and at least one parity information to sample application unit schematic entity;

[0039] 图9是根据本发明第三范例实施例所示出的根据写入数据欲写入的每一实体程序化单元的个数将其排列与记录标记值的范例示意图; [0039] FIG. 9 is a schematic diagram showing the recording mark arrangement which is exemplary values ​​programmed according to the number of each physical unit write data to be written in accordance with a third exemplary embodiment illustrated embodiment of the present invention;

[0040] 图10是根据本发明第三范例实施例所示出的将写入数据、对应于写入数据的错误检查与校正码与用以记录奇偶信息的至少一标记写入至实体程序化单元的另一范例示意图; [0040] FIG. 10 is an exemplary embodiment of the present invention according to a third embodiment shown the write data corresponding to write data to the write physical programming error checking and correction code for recording mark and at least one of parity information a schematic view of another example of means;

[0041] 图11是根据本发明第四范例实施例所示出的将写入数据、对应于写入数据的错误检查与校正码程序化至实体程序化单元以及将用以记录奇偶信息的至少一标记记录在奇偶信息地址对应表的范例示意图; [0041] FIG. 11 is an exemplary embodiment of the present invention according to the fourth embodiment shown the write data corresponding to the error checking and correction code programmed to write data to the entity and the programming unit for recording at least parity information recording a mark in the schematic example of parity information corresponding to the address table;

[0042] 图12是根据本发明的第四范例实施例所示出的数据存储方法的流程图。 [0042] FIG. 12 is a flowchart illustrating a fourth example of the present invention, the data storage method shown in Example.

[0043] 附图标记说明: [0043] REFERENCE NUMERALS:

[0044] 1000:主机系统; [0044] 1000: a host system;

[0045] 1100:电脑; [0045] 1100: Computer;

[0046] 1102:微处理器; [0046] 1102: a microprocessor;

[0047] 1104:随机存取存储器(RAM); [0047] 1104: a random access memory (the RAM);

[0048] 1106:输入/输出装置; [0048] 1106: input / output means;

[0049] 1108:系统总线; [0049] 1108: a system bus;

[0050] 1110:数据传输接口; [0050] 1110: data transmission interface;

[0051] 1202:鼠标; [0051] 1202: Mouse;

[0052] 1204:键盘; [0052] 1204: keyboard;

[0053] 1206:显示器; [0053] 1206: a display;

[0054] 1208:打印机; [0054] 1208: the printer;

[0055] 1212:优盘; [0055] 1212: USB;

[0056] 1214:存储卡; [0056] 1214: memory card;

[0057] 1216:固态硬盘; [0057] 1216: SSDs;

[0058] 1310:数码相机; [0058] 1310: a digital camera;

[0059] 1312:SD 卡; [0059] 1312: SD card;

[0060] 1314:MMC 卡; [0060] 1314: MMC card;

[0061] 1316:存储棒; [0061] 1316: memory stick;

[0062] 1318:CF 卡; [0062] 1318: CF card;

[0063] 1320:嵌入式存储装置; [0063] 1320: embedded memory means;

[0064] 100:存储器存储装置; [0064] 100: memory storage means;

[0065] 102:连接接口单元; [0065] 102: connection interface unit;

[0066] 104:存储器控制电路单元; [0066] 104: memory control circuit means;

[0067] 106:可复写式非易失性存储器模块; [0067] 106: rewritable non-volatile memory module;

[0068] 410(0)〜410 (N):实体抹除单元; [0068] 410 (0) ~410 (N): physical erase unit;

[0069] 202:存储器管理电路; [0069] 202: memory management circuitry;

[0070] 204:主机接口; [0070] 204: host interface;

[0071] 206:存储器接口; [0071] 206: a memory interface;

[0072] 208:缓冲存储器; [0072] 208: a buffer memory;

[0073] 210:电源管理电路; [0073] 210: power management circuitry;

[0074] 212:错误检查与校正电路; [0074] 212: error checking and correction circuit;

[0075] 502:数据区; [0075] 502: data area;

[0076] 504:闲置区; [0076] 504: inactive region;

[0077] 506:系统区; [0077] 506: system area;

[0078] 508:取代区; [0078] 508: substitution region;

[0079] 510(0)〜510(D):逻辑地址; [0079] 510 (0) ~510 (D): a logical address;

[0080] 520:数据比特区; [0080] 520: DC ratio data;

[0081] 540:冗余比特区; [0081] 540: redundancy ratio, DC;

[0082] 542:第一记录区; [0082] 542: a first recording area;

[0083] 544:第二记录区; [0083] 544: second recording area;

[0084] 800、110:奇偶信息地址对应表; [0084] 800,110: parity address correspondence table;

[0085] 602,702,802:第一实体程序化单元; [0085] 602,702,802: a first entity programming unit;

[0086] 604,704,804:第二实体程序化单元; [0086] 604,704,804: second entity programming unit;

[0087] 606,706,806:第三实体程序化单元; [0087] 606,706,806: a third entity programming unit;

[0088] 808:第四实体程序化单元; [0088] 808: fourth entity programming unit;

[0089] 810:第五实体程序化单元; [0089] 810: a fifth entity programming unit;

[0090] 812:第六实体程序化单元; [0090] 812: a sixth entity programming unit;

[0091] 900:排序; [0091] 900: sorting;

[0092] D1、D1-1〜D1-4:第一使用者数据; [0092] D1, D1-1~D1-4: a first user data;

[0093] D2、D2-1、D2_2:第二使用者数据; [0093] D2, D2-1, D2_2: second user data;

[0094] D3、D3-1、D3_2:第三使用者数据; [0094] D3, D3-1, D3_2: third user data;

[0095] S1、Sl-1〜S1-4:第一使用者数据的管理信息; [0095] S1, Sl-1~S1-4: a first user data management information;

[0096] S2、S2-1、S2-2:第二使用者数据的管理信息; [0096] S2, S2-1, S2-2: second user data management information;

[0097] S3-1、S3-2:第三使用者数据的管理信息; [0097] S3-1, S3-2: the third user data management information;

[0098] Ml:第一标记; [0098] Ml: a first marker;

[0099] M2:第二标记; [0099] M2: a second marker;

[0100] M3:第二标记; [0100] M3: a second marker;

[0101] ECCl-1 〜ECCl-4、ECC2、ECC2-l、ECC2-2、ECC3-l、ECC3-2:错误检查与校正码; [0101] ECCl-1 ~ECCl-4, ECC2, ECC2-l, ECC2-2, ECC3-l, ECC3-2: error checking and correcting code;

[0102] P:奇偶信息; [0102] P: parity information;

[0103] Pl:第一奇偶信息; [0103] Pl: a first parity information;

[0104] P2:第二奇偶信息; [0104] P2: second parity information;

[0105] P3:第三奇偶信息; [0105] P3: third parity information;

[0106] S701、S703、S705、S707、S1201、S1203、S1205、S1207、S1209:数据存储方法的步骤。 [0106] S701, S703, S705, S707, S1201, S1203, S1205, S1207, S1209: step data storing method.

具体实施方式 Detailed ways

[0107][第一范例实施例] [0107] [First exemplary embodiment]

[0108] —般而言,存储器存储装置(也称,存储器存储系统)包括可复写式非易失性存储器模块与控制器(也称,控制电路)。 [0108] - In general, the memory storage device (also called, memory storage system) includes a rewritable non-volatile memory module and a controller (also referred to as control circuit). 通常存储器存储装置是与主机系统一起使用,以使主机系统可将数据写入至存储器存储装置或从存储器存储装置中读取数据。 Memory storage device is typically used in conjunction with a host system, so that the host system may write data to the memory storage device or reading data from the memory storage device.

[0109] 图1A是根据本发明第一范例实施例所示出的主机系统与存储器存储装置的示意图。 [0109] FIG 1A is a first exemplary embodiment of the present invention is shown in a schematic view illustrating a host system and a memory storage device.

[0110] 请参照图1A,主机系统1000—般包括电脑1100与输入/输出(input/output,简称I/O)装置1106。 [0110] Referring to FIGS. 1A, a host computer system typically includes 1000- 1100 and input / output (input / output, referred to as I / O) device 1106. 电脑1100包括微处理器1102、随机存取存储器(random access memory,简称RAM) 1104、系统总线1108与数据传输接口1110。 Computer 1100 includes a microprocessor 1102, a random access memory (random access memory, referred to as RAM) 1104, a system bus 1108 and data transmission interface 1110. 输入/输出装置1106包括如图1B的鼠标1202、键盘1204、显示器1206与打印机1208。 Input / output device 1106 includes a mouse 1202 in FIG. 1B, a keyboard 1204, display 1206 and printer 1208. 必须了解的是,图1B所示的装置非限制输入/输出装置1106,输入/输出装置1106可还包括其他装置。 It must be understood that the apparatus shown in FIG. 1B non-limiting input / output device 1106, an input / output device 1106 may further include other devices.

[0111] 在本发明实施例中,存储器存储装置100是通过数据传输接口1110与主机系统1000的其他元件电性连接。 [0111] In an embodiment of the present invention, the memory storage device 100 is electrically 1000 other elements of the data transmission interface through the connector 1110 and the host system. 通过微处理器1102、随机存取存储器1104与输入/输出装置1106的运作可将数据写入至存储器存储装置100或从存储器存储装置100中读取数据。 1102 microprocessor, a random access memory 1104 and the input / output device 1106 operating data can be written to the read data from a memory storage device 100 or memory storage device 100. 例如,存储器存储装置100可以是如图1B所示的优盘1212、存储卡1214或固态硬盘(SolidState Drive,简称SSD) 1216等的可复写式非易失性存储器存储装置。 For example, the memory 100 may be a USB storage device shown in FIG. 1B 1212, rewritable non-volatile memory device or a memory card 1214 SSD (SolidState Drive, referred to as SSD) 1216 or the like.

[0112] —般而言,主机系统1000为可实质地与存储器存储装置100配合以存储数据的任意系统。 [0112] - In general, the host system 1000 to be substantially any system to store data with the memory storage device 100. 虽然在本范例实施例中,主机系统1000是以电脑系统来做说明,然而,在本发明另一范例实施例中主机系统1000可以是数码相机、摄影机、通信装置、音频播放器或视频播放器等系统。 Digital cameras, video cameras, a communication device, an audio player or video player embodiment, although the host system is a computer system 1000 do embodiment described, however, the host system according to the embodiment of the present invention In another example 1000 may be present in the sample and other systems. 例如,在主机系统为图1C中的数码相机(摄影机)1310时,可复写式非易失性存储器存储装置则为其所使用的SD卡1312、MMC卡1314、存储棒(memory stick) 1316、CF卡1318或嵌入式存储装置1320 (如图1C所示)。 For example, FIG. 1C is a digital camera (video camera) 1310, rewritable non-volatile memory storage device in which it is used, compared with the SD card host system 1312, MMC card 1314, a memory stick (memory stick) 1316, 1318 CF card or embedded memory device 1320 (shown in FIG. 1C). 嵌入式存储装置1320包括嵌入式多媒体卡(Embedded MMC,简称eMMC)。 Embedded memory device 1320 includes an embedded multimedia card (Embedded MMC, referred eMMC). 值得一提的是,嵌入式多媒体卡是直接电性连接在主机系统的基板上。 It is worth mentioning that the embedded multimedia card is directly electrically connected to the substrate on the host system.

[0113] 图2是示出图1A所示的存储器存储装置的概要方块图。 [0113] FIG. 2 shows a schematic block diagram of a memory storage device 1A shown in FIG.

[0114] 请参照图2,存储器存储装置100包括连接接口单元102、存储器控制电路单元104与可复写式非易失性存储器模块106。 [0114] Referring to FIG 2, a memory storage device 100 includes a connection interface unit 102, the memory control circuit unit 104 and the rewritable nonvolatile memory module 106.

[0115] 在本范例实施例中,连接接口单元102是符合串行高级技术附件(SerialAdvanced Technology Attachment,简称SATA)标准。 [0115] In the present exemplary embodiment, the interface unit 102 is connected in line with a serial Advanced Technology Attachment (SerialAdvanced Technology Attachment, referred SATA) standard. 然而,必须了解的是,本发明不限于此,连接接口单元102也可以是符合平行高级技术附件(Parallel Advanced TechnologyAttachment,简称PATA)标准、电气和电子工程师协会(Institute of Electrical andElectronic Engineers,简称IEEE) 1394 标准、高速外围组件互连接口(PeripheralComponent Interconnect Express,简称PCI Express)标准、通用串行总线(UniversalSerial Bus,简称USB)标准、超高速一代(Ultra High Speed-1,简称UHS-1)接口标准、超高速二代(Ultra High Speed-1I,简称UHS-1I)接口标准、安全数位(Secure Digital,简称SD)接口标准、存储棒(Memory Stick,简称MS)接口标准、多媒体存储卡(Multi MediaCard,简称MMC)接口标准、小型快闪(Compact Flash,简称CF)接口标准、电子集成驱动器接口(Integrated Device Electronics,简称IDE)标准或其他适合的标准。 However, it must be understood that the invention is not limited thereto, and may be connected to the interface unit 102 is in line parallel advanced technology attachment (Parallel Advanced TechnologyAttachment, referred PATA) standard, the Institute of Electrical and Electronics Engineers (Institute of Electrical andElectronic Engineers, referred to as IEEE) 1394 standard, an interface peripheral component interconnect (PeripheralComponent interconnect Express, referred to as PCI Express) standard, a universal serial bus (UniversalSerial bus, referred to as USB) standard, ultra high-speed generation (ultra High Speed-1, referred UHS-1) interface standard , ultra-high speed II (ultra High Speed-1I, referred UHS-1I) interface standard, secure digital (secure Digital, referred to as SD) interface standard, memory Stick (memory Stick, referred to as MS) interface standard, multimedia memory card (Multi MediaCard , referred to as MMC) interface standard, a compact flash (compact flash, referred to as CF) interface standard, an integrated drive electronics interface (integrated device Electronics, referred to as IDE) standard or other suitable standards. 在本范例实施例中,连接器可与存储器控制电路单元封装在一个芯片中,或布设在一包含存储器控制电路单元的芯片外。 In the present exemplary embodiment, the connector may be the memory control circuit unit packaged in a chip, or laid in a chip comprising the memory control circuit unit outside.

[0116] 存储器控制电路单元104用以执行以硬件型式或固件型式实现的多个逻辑门或控制指令,并且根据主机系统1000的指令在可复写式非易失性存储器模块106中进行数据的写入、读取、抹除与合并等运作。 [0116] The memory control circuit unit 104 to perform a plurality of logic gates or control instructions to implement the hardware type or firmware type, and the write data in a rewritable nonvolatile memory module 106 according to the instruction of the host system 1000 into, read, erase and merger operations.

[0117] 可复写式非易失性存储器模块106是耦接至存储器控制电路单元104,并且用以存储主机系统1000所写入的数据。 [0117] non-volatile rewritable memory module 106 is coupled to the memory control circuit unit 104, and the host system 1000 for storing data written. 可复写式非易失性存储器模块106具有实体抹除单元410(0)〜410 (R)。 Rewritable nonvolatile memory module 106 having a physical erase unit 410 (0) ~410 (R). 例如,实体抹除单元410 (O)〜410 (R)可属于同一个存储器晶粒(die)或者属于不同的存储器晶粒。 For example, physical erase unit 410 (O) ~410 (R) may belong to the same memory die (Die), or belong to different memory dies. 每一实体抹除单元分别具有复数个实体程序化单元,其中属于同一个实体抹除单元的实体程序化单元可被独立地写入且被同时地抹除。 Each entity having a plurality of erase units each unit program entities which belong to the same physical entity erase programming unit cells may be independently written and is simultaneously erased. 此外,每一实体抹除单元可由64个实体程序化单元、256个实体程序化单元或其他任意个实体程序化单元所组成。 In addition, each physical erase unit may be programmed unit 64 entities, 256 entities consisting of a program unit or any other entities of a program unit.

[0118] 更详细来说,实体抹除单元为抹除的最小单位。 [0118] In more detail, the physical erase unit is a minimum unit of erase. 即,每一实体抹除单元含有最小数目的一并被抹除的存储单元。 That is, each physical erase unit contains a minimum number of memory cells and erasing. 实体程序化单元为程序化的最小单元。 Solid programming unit the minimum unit of programming. 即,实体程序化单元为写入数据的最小单元。 I.e., solid unit programmed minimum unit for writing data. 每一实体程序化单元通常包括数据比特区与冗余比特区。 Each entity programming unit typically includes data redundancy than the ratio of the SAR and SAR. 数据比特区包含多个实体存取地址用以存储使用者的数据,而冗余比特区用以存储系统的数据(例如,控制信息与错误更正码)。 Comprising a plurality of data entities access address for storing data of the user than the SAR, but for the redundancy of the data storage system (e.g., control information and error correction code) than DC. 在本范例实施例中,每一个实体程序化单元的数据比特区中会包含4个实体存取地址,且一个实体存取地址的大小为512字节(byte)。 In the present exemplary embodiment, each data entity programmed cell contains four physical access addresses than the SAR, the access address and a physical size of 512 bytes (byte). 然而,在其他范例实施例中,数据比特区中也可包含数目更多或更少的实体存取地址,本发明并不限制实体存取地址的大小以及个数。 However, in other exemplary embodiments, the data may contain more or fewer number of entities than the access address in the SAR, according to the present invention is not limited physical size and number of the access address. 例如,在一范例实施例中,实体抹除单元为实体抹除单元,并且实体程序化单元为实体程序化单元或实体扇区,但本发明不以此为限。 For example, in one exemplary embodiment, the physical erase unit erasing unit entity and entity programming unit programming unit as an entity or entity sectors, but the present invention is not limited thereto.

[0119] 在本范例实施例中,可复写式非易失性存储器模块106为多层单元(Multi LevelCell,简称ML0NAND型快闪存储器模块(即,一个存储单元中可存储2个比特数据的快闪存储器模块)。然而,本发明不限于此,可复写式非易失性存储器模块106也可是单层单元(Single Level Cell,简称SLC)NAND型快闪存储器模块(即,一个存储单元中可存储I个比特数据的快闪存储器模块)、三层单元(Trinary Level Cell,简称TLC)NAND型快闪存储器模块(即,一个存储单元中可存储3个比特数据的快闪存储器模块)、其他快闪存储器模块或其他具有相同特性的存储器模块。 [0119] In the present exemplary embodiment, the non-volatile rewritable memory module 106 is a multi-level cell (Multi LevelCell, referred ML0NAND type flash memory module (i.e., one memory cell can store 2-bit data fast flash memory module). However, the present invention is not limited to, rewritable non-volatile memory module 106 may also be a single-level cell (Single Level cell, referred to as SLC) NAND type flash memory module (i.e., one memory cell can be I bits of the data stored in the flash memory module), three units (trinary Level cell, referred to as TLC) NAND type flash memory module (i.e., one memory cell can store 3-bit data of a flash memory module), the other flash memory or other memory modules modules have the same characteristics.

[0120] 图3是根据本发明第一范例实施例所示出的存储器控制电路单元的概要方块图。 [0120] FIG. 3 is a schematic block diagram of the memory shown embodiment of the control circuit unit according to a first exemplary embodiment of the present invention.

[0121] 请参照图3与图2,存储器控制电路单元104包括存储器管理电路202、主机接口204与存储器接口206。 [0121] Referring to FIG. 2 and FIG. 3, the memory control circuit unit 104 comprises a memory management circuitry 202, host interface 204 and the memory interface 206.

[0122] 存储器管理电路202用以控制存储器控制电路单元104的整体运作。 [0122] The memory management circuit 202 for controlling the overall operation of the memory control circuit unit 104. 具体来说,存储器管理电路202具有多个控制指令,并且在存储器存储装置100运作时,此些控制指令会被执行以进行数据的写入、读取与抹除等运作。 Specifically, a memory management circuit 202 having a plurality of control instructions, and a memory storage device 100 when the operation of such control instruction is executed to write the data in, erasing and reading operation and the like.

[0123] 在本范例实施例中,存储器管理电路202的控制指令是以固件型式来实现。 [0123] In the present exemplary embodiment, the control circuit 202 of the memory management command is implemented firmware version. 例如,存储器管理电路202具有微处理器单元(未示出)与唯读存储器(未示出),并且此些控制指令是被刻录至此唯读存储器中。 For example, memory management circuitry 202 has a microprocessor unit (not shown) and a read only memory (not shown), and is of such a control instruction read only memory burning point. 当存储器存储装置100运作时,此些控制指令会由微处理器单元来执行以进行数据的写入、读取与抹除等运作。 When operating a memory storage device 100, the control of such commands will be performed in the data writing, reading and erasing the like operated by a microprocessor unit.

[0124] 在本发明另一范例实施例中,存储器管理电路202的控制指令也可以程序码型式存储在可复写式非易失性存储器模块106的特定区域(例如,存储器模块中专用于存放系统数据的系统区)中。 [0124] In another exemplary embodiment of the present invention, the control instruction memory management circuit 202 may also be in a particular region rewritable nonvolatile memory module 106 (e.g., secondary memory module for storing a system program stored in code form, the system data area) of. 此外,存储器管理电路202具有微处理器单元(未示出)、唯读存储器(未示出)及随机存取存储器(未示出)。 In addition, memory management circuitry 202 has a microprocessor unit (not shown), read only memory (not shown) and a random access memory (not shown). 特别是,此唯读存储器具有驱动码,并且当存储器控制电路单元104被致能时,微处理器单元会先执行此驱动码段来将存储在可复写式非易失性存储器模块106中的控制指令载入至存储器管理电路202的随机存取存储器中。 In particular, this drive having a read only memory code, and when the memory control circuit unit 104 is enabled, the microprocessor first performs this driving unit code segments stored in the rewritable nonvolatile memory module 106 Loading control command to the memory management circuitry 202 of the random access memory. 之后,微处理器单元会运转此些控制指令以进行数据的写入、读取与抹除等运作。 Thereafter, the microprocessor unit will command the operation of such a control for data writing, reading and erasing operation and the like.

[0125] 主机接口204是耦接至存储器管理电路202并且用以耦接至连接接口单元102,以接收与识别主机系统1000所传送的指令与数据。 [0125] The host interface 204 is coupled to the memory management circuitry 202 and 102 for coupling to, a host system to receive the identification instruction data is transmitted in the 1000 interface unit. 也就是说,主机系统1000所传送的指令与数据会通过主机接口204来传送至存储器管理电路202。 That is, instructions and data transmitted by the host system 1000 will be sent to the memory manager 204 to 202 through the host interface circuit. 在本范例实施例中,主机接口204是符合SATA标准。 In the present exemplary embodiment, the host interface 204 is in line with the SATA standard. 然而,必须了解的是本发明不限于此,主机接口204也可以是相容于PATA标准、IEEE1394标准、PCI Express标准、USB标准、UHS-1接口标准、UHS-1I接口标准、SD标准、MS标准、MMC标准、CF标准、IDE标准或其他适合的数据传输标准。 However, it must be understood that the present invention is not limited thereto, the host interface 204 may be compatible with standard PATA, IEEE1394 standard, PCI Express standard, USB standard, UHS-1 interface standard, UHS-1I interface standard, SD standard, the MS standard, MMC standard, CF standard, IDE, or other suitable standard data transmission standards.

[0126] 存储器接口206是耦接至存储器管理电路202并且用以存取可复写式非易失性存储器模块106。 [0126] The memory interface 206 is coupled to the memory management circuitry 202 and for accessing the non-volatile rewritable memory module 106. 也就是说,欲写入至可复写式非易失性存储器模块106的数据会经由存储器接口206转换为可复写式非易失性存储器模块106所能接受的格式。 That is, to be written to the rewritable non-volatile memory 106 of data module 206 will be converted to non-volatile rewritable memory module 106 via a format acceptable to the memory interface.

[0127] 在本发明一范例实施例中,存储器控制电路单元104还包括缓冲存储器208、电源管理电路210与错误检查与校正电路212。 [0127] In an exemplary embodiment of the present invention, the memory control circuit unit 104 further includes a buffer memory 208, the power management circuit 210 and an error checking and correction circuit 212.

[0128] 缓冲存储器208是耦接至存储器管理电路202并且用以寄存来自于主机系统1000的数据与指令或来自于可复写式非易失性存储器模块106的数据。 [0128] buffer memory 208 is coupled to the memory for storage and managing circuit 202 from the host system 1000 from a data or instruction data rewritable nonvolatile memory module 106.

[0129] 电源管理电路210是耦接至存储器管理电路202并且用以控制存储器存储装置100的电源。 [0129] Power management circuit 210 is coupled to the memory management circuitry 202 and memory storage devices for controlling the power supply 100.

[0130] 错误检查与校正电路212是耦接至存储器管理电路202并且用以执行错误检查与校正程序以确保数据的正确性。 [0130] Error checking and correction circuit 212 is coupled to the memory management circuitry 202 and to perform error checking and correction process to ensure the correctness of the data. 具体来说,当存储器管理电路202从主机系统1000中接收到写入指令时,错误检查与校正电路212会为对应此写入指令的数据产生对应的错误检查与校正码(Error Checking and Correcting Code,简称ECC Code),并且存储器管理电路202会将对应此写入指令的数据与对应的错误检查与校正码写入至可复写式非易失性存储器模块106中。 Specifically, when the memory management circuit 202 receives the write command to the host system 1000, error checking and correction circuit 212 will correspond to the data write instruction to generate a corresponding error checking and correction code (Error Checking and Correcting Code , referred to as ECC code), and the memory management circuit 202 will write instruction corresponding to this data with the corresponding error checking and correcting code written to the rewritable non-volatile memory module 106. 之后,当存储器管理电路202从可复写式非易失性存储器模块106中读取数据时会同时读取此数据对应的错误检查与校正码,并且错误检查与校正电路212会依据此错误检查与校正码对所读取的数据执行错误检查与校正程序。 Thereafter, when the memory management circuitry 202 to read data from the rewritable non-volatile memory module 106 simultaneously reads the data corresponding to error checking and correction code, and the error checking and correction circuit 212 will be based on this error checking and performing an error correction code ECC procedure for the read data.

[0131] 图4A与图4B是根据第一范例实施例所示出的管理实体抹除单元的范例示意图。 [0131] FIG. 4A and 4B according to the first exemplary embodiment is shown a schematic view of a management entity exemplary erase unit.

[0132] 必须了解的是,在此描述可复写式非易失性存储器模块106的实体抹除单元的运作时,以“提取”、“分组”、“划分”、“关联”等词来操作实体抹除单元是逻辑上的概念。 [0132] to be understood that, when the entity described herein rewritable nonvolatile memory module 106 functioning erasing unit to "extract", "packet", "division", "association" and other words to operate physical erase unit is a logical concept. 也就是说,可复写式非易失性存储器模块的实体抹除单元的实际位置并未更动,而是逻辑上对可复写式非易失性存储器模块的实体抹除单元进行操作。 That is, the actual physical location of rewritable nonvolatile memory cells are not erased module modifiers, but logically erase unit operates the entity rewritable nonvolatile memory module.

[0133] 请参照图4A,存储器控制电路单元104 (或存储器管理电路202)会将实体抹除单元410 (O)〜410-(N)逻辑地分组为数据区502、闲置区504、系统区506与取代区508。 [0133] Referring to Figure 4A, the memory control circuit unit 104 (or the memory management circuit 202) will erase physical unit 410 (O) ~410- (N) logically grouped into the data area 502, unused area 504, system area regions 506 and 508 substituted.

[0134] 逻辑上属于数据区502与闲置区504的实体抹除单元是用以存储来自于主机系统1000的数据。 [0134] Data area 502 and the unused area 504 entities belonging to logical erasing unit 1000 is to store data from the host system. 具体来说,数据区502的实体抹除单元是被视为已存储数据的实体抹除单元,而闲置区504的实体抹除单元是用以替换数据区502的实体抹除单元。 Specifically, the entity data erase unit area 502 is regarded as an entity stored data erasing unit, and the real idle zone 504 is to replace physical erase unit 502 to erase the data area unit. 也就是说,当从主机系统1000接收到写入指令与欲写入的数据时,存储器管理电路202会从闲置区504中提取实体抹除单元,并且将数据写入至所提取的实体抹除单元中,以替换数据区502的实体抹除单兀。 That is, when receiving from the host system 1000 and a data write instruction to be written, the memory management circuit 202 will be extracted from the idle physical erase unit area 504, and writes data to a physical erase extracted unit to the replacement data area 502 entity erasing single Wu.

[0135] 逻辑上属于系统区506的实体抹除单元是用以记录系统数据。 [0135] belonging to the entity of the system area 506 is logically erasing means for recording system data. 例如,系统数据包括关于可复写式非易失性存储器模块的制造商与型号、可复写式非易失性存储器模块的实体抹除单元数、每一实体抹除单元的实体程序化单元数等。 For example, the system includes data about manufacturers and models rewritable non-volatile memory module, entity rewritable nonvolatile memory module number of erase units, each physical entity erase programmed number of units like unit .

[0136] 逻辑上属于取代区508中的实体抹除单元是用于坏实体抹除单元取代程序,以取代损坏的实体抹除单元。 [0136] belonging to a logical entity in the substituted region 508 erasure unit is a physical entity erase bad substituted program unit to replace the broken erase unit. 具体来说,倘若取代区508中仍存有正常的实体抹除单元并且数据区502的实体抹除单元损坏时,存储器管理电路202会从取代区508中提取正常的实体抹除单元来更换损坏的实体抹除单元。 Specifically, if the time zone is still substituted normal entity 508 and entity data erasing means erasing unit damaged area 502, memory management circuitry 202 extracts from normal entity substituent region 508 erasure unit to replace the damaged physical erase unit.

[0137] 特别是,数据区502、闲置区504、系统区506与取代区508的实体抹除单元的数量会依据不同的存储器规格而有所不同。 [0137] In particular, the data area 502, unused area 504, area 506 and the area of ​​the substitution system entity 508 by the number of erase units may vary depending on the different memory specification. 此外,必须了解的是,在存储器存储装置100的运作中,实体抹除单元关联至数据区502、闲置区504、系统区506与取代区508的分组关系会动态地变动。 Furthermore, it must be appreciated that, in the operation of a memory storage device 100, the entity to the data area erase association unit 502, idle region 504, 506 and the relationship between the packet zone 508 is substituted dynamically change the system area. 例如,当闲置区504中的实体抹除单元损坏而被取代区508的实体抹除单元取代时,则原本取代区508的实体抹除单元会被关联至闲置区504。 For example, when the idle region 504 erasure unit damaged entity in the entity area 508 is erased substituted means substituted, the substituent originally solid regions 508 are erased cells 504 associated to the idle zone.

[0138] 请参照图4B,如上所述,数据区502、闲置区504的实体抹除单元是以轮替方式来存储主机系统1000所写入的数据。 [0138] Referring to Figure 4B, as described above, the data area 502, physical inactivity erase unit area 504 is alternation way to store data written to the host system 1000. 在本范例实施例中,存储器控制电路单元104(或存储器管理电路202)会配置逻辑地址510 (O)〜510 (D)给主机系统1000,以映射至数据区502中部分的实体抹除单元414(0)〜410(F-1),以利于在以上述轮替方式来存储数据的实体抹除单元中进行数据存取。 In the present exemplary embodiment, the memory control circuit unit 104 (or the memory management circuit 202) configures logical address 510 (O) ~510 (D) to the host system 1000 to map to a physical portion of the data region 502 erasure unit 414 (0) ~410 (F-1), in order to facilitate data access unit in alternation above manner entity to store data erase. 特别是,主机系统1000会通过逻辑地址510 (O)〜510(D)来存取数据区502中的数据。 In particular, the host system 1000 will ~510 (D) to access data in the data area 502 by the logical address 510 (O). 此外,存储器控制电路单元104 (或存储器管理电路202)会建立逻辑地址-实体抹除单兀映射表(logical address-physical erasing unit mappingtable),以记录逻辑地址与实体抹除单元之间的映射关系。 Further, the memory control circuit unit 104 (or the memory management circuit 202) creates the logical address - physical mapping table to erase a single Wu (logical address-physical erasing unit mappingtable), in order to record the logical address and physical mapping relationship between the erasing unit . 此逻辑地址-实体抹除单元映射表还可以例如是记录逻辑地址与实体程序化单元、逻辑程序化单元与实体程序化单元及/或逻辑程序化单元与实体抹除单元之间的映射关系等各种逻辑与实体的对应关系,本发明不加以限制。 This logical address - physical erase unit mapping table may also be, for example, the program recorded logical address and physical unit, a mapping relationship between logical units and physical units procedural programming unit and / or the logic unit and erase other entity corresponding relationship between the various logical entities of the present invention is not limited thereto.

[0139] 图5A至图5B是根据本发明第一范例实施例所示出的将写入数据、对应于写入数据的错误检查与校正码以及用以记录奇偶信息的至少一标记写入至实体程序化单元的范例示意图。 [0139] Figures 5A-5B are exemplary embodiments of the present invention according to the first embodiment shown the write data, write to the write data corresponding to the error checking and correction code for recording mark and at least one parity information to sample application unit entities FIG.

[0140] 请参照图5A,在本范例实施例中,每一实体程序化单元会包括数据比特区520与冗余比特区540。 [0140] Referring to Figure 5A, in the present exemplary embodiment, each entity will include a programming unit 520 and the redundant data than the ratio of DC 540, DC. 其中,冗余比特区540包括第一记录区542及第二记录区544。 Wherein the ratio of the redundant DC 540 includes a first recording region 542 and the second recording region 544. 举例来说,当一个实体程序化单元的容量为8千字节(Kilobyte,简称KB)时,冗余比特区540的容量有22字节。 For example, when the capacity of the program entity is a unit of 8 kilobytes (Kilobyte, referred to as KB), there are 22 redundant bytes than the capacity of the SAR 540.

[0141] 具体而言,当主机系统1000传送写入指令与对应此写入指令的第一使用者数据Dl给存储器存储装置100时,存储器控制电路单元104(或存储器管理电路202)会判断第一使用者数据Dl的大小,并且根据第一使用者数据Dl的大小获得写入此第一使用者数据Dl所需的实体程序化单元的数目。 [0141] Specifically, when the host system transmits 1000 a write command corresponding to this write command to the first user data Dl memory storage device 100, the memory control circuit unit 104 (or the memory management circuit 202) determines a first a size of the user data Dl, and obtains the program number of write physical unit is required for this first user data Dl according to the size of the first user data Dl. 在此,假设需两个实体程序化单元来写入此第一使用者数据D1。 Here, assuming two entities need to write the program unit of this first user data D1. 因此,如图5A所示,存储器控制电路单元104(或存储器管理电路202)会产生对应第一使用者数据Dl-1与D1-2的错误检查与校正码ECCl-1与ECC1-2以及对应第一使用者数据Dl-1与D1-2的管理信息Sl-1与S1-2 (例如,实体程序化单元的好坏标记等),并且自闲置区504提取实体抹除单元410 (F)作为替换实体抹除单元。 Thus, as shown in FIG. 5A, the memory control circuit unit 104 (or the memory management circuit 202) corresponding to a first user generated data Dl-1 and D1-2 is error checking and correcting code and ECCl-1 and the corresponding ECC1-2 Dl-1 first user data and management information D1-2 and S1-2 Sl-1 (e.g., good or bad of tagged entities programming unit, etc.), and the extracting area 504 from the unused physical erase unit 410 (F) as an alternative physical erase unit. 之后,存储器控制电路单元104(或存储器管理电路202)会将此些第一使用者数据、对应此些第一使用者数据的管理信息,以及对应此些第一使用者数据的多个错误检查与校正码依序地写入至实体抹除单元410(F)的第O个与第I个实体程序化单元中。 Thereafter, the memory control circuit unit 104 (or the memory management circuitry 202) the first user data will be some of this, the management information corresponding to a first user of such data, and a corresponding plurality of such error checking data of the first user correction code sequentially written to a physical erase unit 410 (F) of O I th and entities programming unit. 在此假设此些第一使用者数据所写入的实体程序化单元为第一实体程序化单元602,也就是说,第一使用者数据Dl-1与D1-2是被程序化至第一实体程序化单元602的数据比特区520中,且对应此些第一使用者数据的错误检查与校正码ECCl-1与ECC1-2是被程序化至第一实体程序化单元602中冗余比特区540的第二记录区544。 Such an entity is assumed here that the program unit of the first user data is written to a first physical programming unit 602, that is, the first user data Dl-1 and D1-2 is programmed to a first program unit 602 data entity than the SAR 520, and corresponds to the first user of such data with error check and correction code ECC1-2 ECCl-1 is programmed to the first entity redundancy programming unit 602 than a second recording area 540, DC 544. 特别是,当主机系统1000欲从存储器存储装置100中读取第一使用者数据Dl时,存储器控制电路单元104 (或存储器管理电路202)会从第一实体程序化单元602中读取错误检查与校正码ECCl-1与ECC1-2,并且错误检查与校正电路212会分别地依据错误检查与校正码ECCl-1与ECC1-2,来对第一使用者数据Dl-1与D1-2进行错误检查与校正程序。 In particular, when the host system 1000 to be read from the first user data Dl stored in the memory device 100, the memory control circuit unit 104 (or the memory management circuit 202) reads the program from the first entity error check unit 602 and correction code ECCl-1 and ECC1-2, and the error checking and correction circuit 212 will be respectively based on the error checking and correction code ECCl-1 and ECC1-2, to the first user data Dl-1 and D1-2 error checking and correction procedures. 基此,在错误检查与校正电路212的错误校正能力范围内,错误检查与校正电路212可校正数据中的错误比特,由此确保数据的正确性。 By virtue of this, in the error checking and correction circuit 212 in the range of the error correction capability, the error checking and correction circuit 212 may correct the error bit data, thereby ensuring the correctness of data.

[0142] 在本范例实施例中,假设一第一数据包括第一使用者数据以及对应第一使用者数据的管理信息,因此,当存储器存储装置100接收到上述第一使用者数据并且产生对应第一使用者数据Dl-1与D1-2的管理信息Sl-1与S1-2后,存储器控制电路单元104 (或存储器管理电路202)会依据此第一数据(即,第一使用者数据Dl-1与D1-2与对应于第一使用者数据Dl-1与D1-2的管理信息Sl-1与S1-2)产生一奇偶信息P。 [0142] In the present exemplary embodiment, assume that a first data comprises a first user data and the management information corresponding to the first user data, and therefore, when the memory storage device 100 receives the user data and generates a corresponding first after the first user management information S1-2 Sl-1 and Dl-1 and D1-2 data, the memory control circuit unit 104 (or the memory management circuit 202) will be based on this first data (i.e., a first user data Dl-1 D1-2 to user data corresponding to the first and D1-2 Dl-1 Sl-1 management information and S1-2) produces a parity information P. 此外,在另一范例实施例中,第一数据包括使用者数据、对应该使用者数据的管理信息以及对应使用者数据的错误检查与校正码,也就是说,存储器控制电路单元104 (或存储器管理电路202)会根据整个实体程序化单元来产生奇偶信息,例如,存储器控制电路单元104(或存储器管理电路202)会依据第一使用者数据Dl-1与D1-2、对应第一使用者数据Dl-1与D1-2的管理信息Sl-1与S1-2以及对应第一使用者数据Dl-1与D1-2的错误检查与校正码ECCl-1与ECC1-2来产生奇偶信息。 Further, in another exemplary embodiment, the first data including user data, the management information for user data to be corresponding to the user data and the error checking and correcting code, i.e., the memory control circuit unit 104 (or memory management circuit 202) will be generated parity information in accordance with a program unit the entire body, e.g., the memory control circuit unit 104 (or the memory management circuit 202) will be based on the first user and D1-2 data Dl-1, corresponding to a first user Dl-1 D1-2 data and management information and S1-2 Sl-1 corresponding to a first user and data Dl-1 and D1-2 is error checking and correcting code and ECC1-2 ECCl-1 generates parity information. 值得一提的是,在本范例实施例中,第一数据为两笔第一使用者数据以及对应此些第一使用者数据的管理信息所组成(即,第一使用者数据Dl-1与D1-2与对应于第一使用者数据Dl-1与D1-2的管理信息Sl-1与S1-2),然而,本发明并不加以限制第一数据的大小,例如,在另一范例实施例中,第一数据可为一笔或多笔第一使用者数据以及对应第一使用者数据的管理信息所组成,或是由一笔或多笔第一使用者数据、对应第一使用者数据的管理信息以及对应第一使用者数据的错误检查与校正码所组成。 It is worth mentioning that, in the present exemplary embodiment, the first data is two strokes corresponding to a first user data and management information of such user data is composed of a first (i.e., a first user data and Dl-1 D1-2 example, in another example of the user management data corresponding to the first and D1-2 Dl-1 Sl-1 information and S1-2), however, the present invention is not limited by the size of the first data, embodiment, the first data may be one or a plurality of user data and a first management information corresponding to the first user data being composed of one or a plurality or a first user data, corresponding to a first use data management information by a first user data and corresponding error check and correction code formed. 值得注意的是,本发明并不限制奇偶信息的产生时间点与产生方式,具体而言,在本范例实施例中,所产生的奇偶信息可以是奇偶校正码(parity checking code)、通道编码(channel coding)或是其他类型。 It is noted that the present invention is not limited generation time point information and parity generation mode, specifically, in the present exemplary embodiment, the generated parity information may be parity correction code (parity checking code), channel coding ( channel coding) or other types. 例如,汉明码(hamming code)、低密度奇偶检查码(low density parity checkcode,简称LDPC code)、润旋码(turbo code)或里德-所罗门码(Reed-solomon code,简称RS code) 0特别是,在另一范例实施例中,存储器控制电路单元104(或存储器管理电路202)也可以使用异或(XOR)运算来为第一数据产生的奇偶信息。 For example, a Hamming code (hamming code), low-density parity-check code (low density parity checkcode, referred to as LDPC code), a spin-run code (turbo code) or a Reed - Solomon code (Reed-solomon code, referred to as RS code) 0 Special that in another exemplary embodiment, the memory control circuit unit 104 (or the memory management circuitry 202) using the parity information may be an exclusive-oR (XOR) operation to the first data generated.

[0143] 请再参照图5A,存储器控制电路单元104 (或存储器管理电路202)会将奇偶信息P程序化至实体抹除单元410 (F)的实体程序化单元之中的第2个实体程序化单元(即,第二实体程序化单元604)。 [0143] Referring again to Figure 5A, the memory control circuit unit 104 (or the memory management circuit 202) sets the parity information P programmed to erase the second entity among entities program unit 410 (F) entities programming unit unit (i.e., the second entity programming unit 604). 值得一提的是,在上述将第一使用者数据、对应第一使用者数据的管理信息与对应第一使用者数据的错误检查与校正码程序化至实体程序化单元之中的第一实体程序化单元602的操作中,存储器控制电路单元104 (或存储器管理电路202)会将至少一标记程序化至实体抹除单元410 (F)的第I个实体程序化单元的冗余比特区的第一记录区542 ( S卩,图5A中所示第一标记Ml),并且此第一标记Ml会指示奇偶信息P被程序化至实体抹除单元410 (F)的第二实体程序化单元604中。 It is worth mentioning that, the above-described first entity in the first user data, the user data corresponding to the first management information corresponding to the first user data error checking and correction code to the programming unit programming entities unit operation program 602, the memory control circuit unit 104 (or the memory management circuit 202) will be at least one marker to the physical erasing programmed redundancy cell 410 (F) I-th physical units is programmed, DC the first recording area 542 (S Jie, as shown in FIG. 5A first marker Ml), Ml and this flag indicates a first parity information P is programmed to a physical erase unit 410 (F) a second entity means programmed 604.

[0144] 特别是,第二实体程序化单元604是排列于第一实体程序化单元602之中的最后一个实体程序化单元之后,并且第一标记Ml会指示第二实体程序化单元604存储奇偶信息P。 After [0144] In particular, the second entity is a programming unit 604 arranged in the last physical unit in the first program entity programming unit 602, and the first flag indicates that the second entity will Ml programming unit 604 store parity information P.

[0145] 请参照图5B,当主机系统1000传送另一个写入指令与对应此写入指令的第二使用者数据D2给存储器存储装置100时,存储器控制电路单元104 (或存储器管理电路202)也会判断第二使用者数据D2的大小,并且根据第二使用者数据D2的大小获得写入此第二使用者数据D2所需的实体程序化单元的数目。 [0145] Referring to Figure 5B, another write command when the host system transmits the second user data 1000 corresponding to this write command to the memory storage device D2 100, the memory control circuit unit 104 (or the memory management circuitry 202) also determines the size of the second user data D2, and the number of data required for this second user entity D2 written in the second programming unit user data D2 obtained in accordance with the size. 在此,假设需一个实体程序化单元来写入此第二使用者数据D2。 Here, assume that an entity needs to write to this program unit of the second user data D2. 因此,如图5B所示,存储器管理电路202会产生对应第二使用者数据D2的错误检查与校正码ECC2以及对应第二使用者数据D2的管理信息S2。 Thus, shown in Figure 5B, memory management circuitry 202 generates user data D2 corresponding to the second error checking and correction code ECC2 and user management information corresponding to the second data D2 S2. 之后,存储器控制电路单元104(或存储器管理电路202)会将此第二使用者数据、对应此第二使用者数据的管理信息,以及对应此第二使用者数据的错误检查与校正码写入至实体抹除单元410(F)的第3个实体程序化单元(B卩,第三实体程序化单元606)中。 Thereafter, the memory control circuit unit 104 (or the memory management circuit 202) will this second user data, the management information corresponding to this second user data and second user data corresponding to this error checking and correcting code into to a physical erase unit 410 (F) to the third entities programming unit (B Jie, a third entity programming unit 606) in the. 在存储器控制电路单元104 (或存储器管理电路202)将对应此第二使用者数据D2的管理信息S2写入至实体抹除单元410(F)的第三实体程序化单元606中的同时,存储器控制电路单元104(或存储器管理电路202)会将一第二标记M2程序化至第三实体程序化单元606的冗余比特区540的第一记录区542中,其中第三实体程序化单元606是排列在第二实体程序化单元604之后,并且第二标记M2也会指示第二实体程序化单元604存储奇偶信息P。 While the third entity programming unit 606 in the memory control circuit unit 104 (or the memory management circuit 202) corresponding to this second user data D2 is written to the management information S2 physical erase unit 410 (F) in the memory the control circuit unit 104 (or the memory management circuit 202) sets a second mark M2 to a third entity programmed redundancy programming unit 606 than the first recording area 542, DC 540, wherein a third entity programming unit 606 entity is arranged after the second programming unit 604, and a second mark M2 indicates that the second entity will programming unit 604 stores parity information P.

[0146] 此后,当存储器控制电路单元104 (或存储器管理电路202)接收到主机系统1000所传送的欲读取上述第一使用者数据Dl的读取指令时,存储器控制电路单元104(或错误检查与校正电路212)会依据所读取的错误检查与校正码对所读取的第一使用者数据Dl-1与D1-2进行上述的错误检查与校正程序。 When [0146] Thereafter, when the memory control circuit unit 104 (or the memory management circuit 202) to the host system receives the read command to be read, the first user data communicated Dl 1000, the memory control circuit unit 104 (or error error checking and correcting code of the read checking and correction circuit 212) will be based on the first user data Dl-1 and D1-2 of the above read error checking and correction process. 举例而言,在本发明范例实施例中,上述第一数据包括一第二数据以及一错误检查与校正码,其中第二数据可仅包括第一使用者数据,或是同时包括第一使用者数据与对应第一使用者数据的管理信息,而错误检查与校正码即为对应第一使用者数据的错误检查与校正码。 For example, in the exemplary embodiment of the present invention, the data comprises a first data and a second error checking and correcting code, wherein the second data may include only the first user data, comprising a first user or simultaneously the management information data corresponding to the first user data, and error checking and correction code is the error checking and correction code corresponding to the first user data. 当无法通过使用对应第一使用者数据的错误检查与校正码来校正所述第二数据时,存储器控制电路单元104(或存储器管理电路202)会根据上述至少一标记获得记录奇偶信息的至少一第二实体程序化单元的地址,并从至少一第二实体程序化单元中读取奇偶信息以及依据所读取的该奇偶信息来校正第二数据。 When it is impossible to correct the second data corresponding to the first user data by using the error checking and correction code, the memory control circuit unit 104 (or the memory management circuit 202) will receive parity information recorded according to at least one of the at least one marker address of the program unit of the second entity, and reads the parity information from the at least one second entity based on the program in the read unit of the second parity information to correct the data. 例如,倘若无法通过使用第一使用者数据Dl-1与D1-2的错误检查与校正码(即,ECC1、ECC2)来校正第一使用者数据Dl-1与D1-2时,存储器控制电路单元104 (或存储器管理电路202)会根据上述的至少一标记来获得记录奇偶信息P的第二实体程序化单元604的地址,并从第二实体程序化单元604中读取此奇偶信息P以及依据所读取的第一奇偶信息P来校正第一使用者数据D1。 For example, if the first user data can not be corrected Dl-1 and D1-2 by using the first user data Dl-1 and D1-2 code error checking and correction (i.e., ECC1, ECC2), the memory control circuit unit 104 (or the memory management circuit 202) to obtain the address of the second entity may program P parity information recording unit 604 based on the at least one marker, P parity information and reads this program from the second entity unit 604 and P according to the first read parity information to correct the first user data D1. 例如,当无法通过使用第一使用者数据Dl-1的错误检查与校正码ECCl来校正第一使用者数据Dl-1时,存储器控制电路单元104 (或存储器管理电路202)会先从第一实体程序化单元602中邻近于第一使用者数据Dl-1所在的第O个实体程序化单元的实体程序化单元(例如,实体抹除单元410 (F)的第I个实体程序化单元)中获得第一标记M1,并由此来识别存储奇偶信息P的地址。 For example, when a first user can not be corrected 1 Dl-user data by using the first data Dl-1 ECCl code error checking and correction, the memory control circuit unit 104 (or the memory management circuit 202) will start a first programmatic entity in an entity unit 602 adjacent to the first programming unit programming entities O unit of the first user where the data Dl-1 (e.g., physical erase unit 410 (F) of the program unit I entities) obtaining first mark M1, and thereby to identify the address of the store parity information P. 在另一范例实施例中,倘若无法通过使用第一使用者数据D1-2的错误检查与校正码ECC2来校正第一使用者数据D1-2且无法从对应于第一使用者数据D1-2的冗余比特区的第一记录区获得第一标记值Ml时,存储器控制电路单元104(或存储器管理电路202)则会从邻近于第一使用者数据D1-2所在的第I个实体程序化单元的实体程序化单元(例如,实体抹除单元410 (F)的第O个实体程序化单元、第二实体程序化单元604与第三实体程序化单元606)中寻找以获得位于第三实体程序化单元606中的第二标记M2,并由此来识别存储有奇偶信息P的实体程序化单元的地址。 In another exemplary embodiment, if the first user data can not be corrected by using the first user data D1-2 is error checking and correction code ECC2 D1-2 and not from the first user data D1-2 corresponding to when the first flag value obtained Ml redundancy than the first recording area SAR, the memory control circuit unit 104 (or the memory management circuit 202) will be from the I-th program entities located adjacent to the first user data D1-2 unitized solid programming unit (e.g., physical erase unit 410 (F) of the program entities O unit, a program unit 604 of the second entity and a third entity programming unit 606) to obtain a third find the second mark M2 solid programming unit 606, and thereby identify the address of the entity storing a program unit P is parity information.

[0147] 在本范例实施例中,可复写式非易失性存储器模块106为多层单元MLC NAND型快闪存储器模块,因此,每一存储单元可存储多个比特。 [0147] In the present exemplary embodiment, the non-volatile rewritable memory module 106 is a multi-level cell MLC NAND flash memory module, therefore, each memory cell may store a plurality of bits. 具体来说,在对SLC NAND型快闪存储器模块的存储单元进行程序化时仅能执行单层的程序化,因此每一存储单元仅能存储一个比特。 Specifically, when the memory cell SLC NAND flash memory modules is executed procedural programming only a single layer, thus each memory cell can store only one bit. 而MLC NAND型快闪存储器模块的实体抹除单元的程序化可分为多层。 And the program entity MLC NAND type flash memory module can be divided into a multilayer erase unit. 例如,以2层存储单元为例,实体程序化单元的程序化可分为2阶段。 For example, two-layer storage unit as an example, programming unit programming entities can be divided into two stages. 第一阶段是下实体程序化单元的写入部分,其物理特性类似于单层存储单元SLC NAND快闪存储器,在完成第一阶段之后才会程序化上实体程序化单元,其中下实体程序化单元的写入速度会快于上实体程序化单元。 The first stage of the program write unit is in solid, its physical properties similar to the memory cell monolayer SLC NAND flash memory, after completion of the first stage of the program until a programmed entity unit, wherein the programmatic entity unit will write speed faster than the entity programming unit. 因此,每一实体抹除单元的实体程序化单元可区分为慢速实体程序化单元(即,上实体程序化单元)与快速实体程序化单元(即,下实体程序化单元)。 Thus, each physical erase unit solid programming unit can be divided into solid slow programming unit (i.e., physically programming unit) and Quick solid programming unit (i.e., the programming unit entity).

[0148] 图6是根据本发明第一范例实施例所示出的将写入数据、对应于写入数据的错误检查与校正码以及用以记录奇偶信息的至少一标记写入至实体程序化单元的另一个范例示意图。 [0148] FIG. 6 is a first exemplary embodiment of the present invention is shown to write data corresponding to write procedural entities write data error checking and correcting code and at least one mark for recording information to parity another example of a schematic section.

[0149] 在另一范例实施例中,存储器控制电路单元104 (或存储器管理电路202)也可以将第一使用者数据Dl-1与D1-2、对应第一使用者数据Dl-1与D1-2的管理信息Sl-1与S1-2以及错误检查与校正码ECCl-1与ECC1-2程序化至实体程序化单元之中的多个实体程序化单元中。 [0149] In another exemplary embodiment, the memory control circuit unit 104 (or the memory management circuitry 202) may be a first user and D1-2 data Dl-1, corresponding to the first user data D1 with Dl-1 management information Sl-1 and -2 S1-2 and error checking and correction code ECCl-1 and ECC1-2 programmed to a program unit in the plurality of physical entities programming unit. 例如,存储器控制电路单元104 (或存储器管理电路202)会将第一使用者数据Dl-1与D1-2、对应第一使用者数据Dl-1与D1-2的管理信息Sl-1与S1-2以及对应第一使用者数据Dl-1与D1-2的错误检查与校正码ECCl-1与ECC1-2仅程序化至第一实体程序化单元702中的快速实体程序化单元。 For example, the memory control circuit unit 104 (or the memory management circuitry 202) the first user will Dl-1 and D1-2 data, corresponding to the first user data Dl-1 and D1-2 of the management information and S1 Sl-1 -2 user data and the corresponding first error check Dl-1 and D1-2 and rapid programming unit corrects the entity code and ECC1-2 ECCl-1 only to the first entity procedural programming unit 702. 因此,如图6所示,存储器控制电路单元104 (或存储器管理电路202)会将第一使用者数据D1-1、管理信息Sl-1以及错误检查与校正码ECCl-1程序化至实体抹除单元410 (F)的第O个实体程序化单元,并且将第一使用者数据D1-2、管理信息S1-2、第一标记Ml以及错误检查与校正码ECC1-2程序化至实体抹除单元410 (F)的第2个实体程序化单元。 Thus, shown in Figure 6, the memory control circuit unit 104 (or the memory management circuitry 202) the first user data will D1-1, Sl-1 management information, and error checking and correction code ECCl-1 programmed to a physical applicator in addition to unit 410 (F) of the program entities O unit, and the first user data D1-2, S1-2 management information, and the first mark Ml error checking and correction code programmed to the physical wiping ECC1-2 in addition to unit 410 (F) of the second unit program entities. 此外,存储器控制电路单元104 (或存储器管理电路202)会产生对应于第一使用者数据D1-UD1-2与对应于第一使用者数据D1-UD1-2的管理信息Sl-1、S1-2的奇偶信息P,并且将此奇偶信息P写入至第二实体程序化单元704中的快速实体程序化单元(即,实体抹除单元410 (F)的第4个实体程序化单元)。 Further, the memory control circuit unit 104 (or the memory management circuit 202) corresponding to the first user generated data D1-UD1-2 corresponding to the first user data D1-UD1-2 management information Sl-1, S1- 2 parity information P, and this parity information is written to the second entity P programming unit 704 quickly entity programming unit (i.e., physical erase unit 410 (F) the fourth unit program entities). 之后,当主机系统1000传送另一个写入指令与对应此写入指令的第二使用者数据D2给存储器存储装置100时,存储器控制电路单元104(或存储器管理电路202)会将其所产生的对应第二使用者数据D2的错误检查与校正码ECC2、对应第二使用者数据D2的管理信息S2以及一第二标记M2写入至实体抹除单元410(F)的第三实体程序化单元706中的快速实体程序化单元(B卩,实体抹除单元410(F)的第6个实体程序化单元)。 Thereafter, when a host system 1000 further transmits a write command corresponding to this write command to the second data D2 user memory storage device 100, the memory control circuit unit 104 (or the memory management circuit 202) will it produce a third entity corresponding to the second user data D2 is error checking and correction code ECC2, D2 corresponding to the second user data management information and a second mark M2 S2 is written to a physical erase unit 410 (F) a program unit 706 fast solid programming unit (B Jie, physical erase unit 410 (F) 6 entity of the program unit). 在此,相同于图5A与图5B所示的范例,第一标记Ml与第二标记M2都会指示第二实体程序化单元704中的快速实体程序化单元存储有奇偶信息P。 Here, identical to the example shown in FIG 5A and FIG 5B, the first mark and the second mark M2 Ml second entity will indicate a programmed cell 704 entity rapid programming unit stores parity information P.

[0150] 也就是说,在本范例实施例中,倘若无法通过使用第一使用者数据Dl-1的错误检查与校正码ECCl来校正第一使用者数据Dl-1时,存储器控制电路单元104 (或存储器管理电路202)会先从第一实体程序化单元702中接近于第一使用者数据Dl-1所在的第O个实体程序化单元的快速实体程序化单元(例如,实体抹除单元410 (F)的第2个实体程序化单元)中获得第一标记M1,并由此来识别存储奇偶信息P的地址。 [0150] That is, in the present exemplary embodiment, if unable to correct the first user 1 Dl-user data by using the first data Dl-1 ECCl code error checking and correction, the memory control circuit unit 104 Dl-1 O fast entity of entity programmed cell where programming unit (or memory management circuit 202) will be close to the first user data 702 to start the program unit first entity (e.g., entity erase unit 410 (F) of two entities programming unit obtains the first mark M1) in, and thereby to identify the address of the store parity information P. 在另一范例实施例中,倘若无法通过使用第一使用者数据D1-2的错误检查与校正码ECC1-2来校正第一使用者数据D1-2且无法从对应于第一使用者数据D1-2的冗余比特区的第一记录区获得第一标记值Ml时,存储器控制电路单元104(或存储器管理电路202)则会从接近于第一使用者数据D1-2所在的第2个实体程序化单元的快速实体程序化单元(例如,实体抹除单元410 (F)的第O个实体程序化单元、实体抹除单元410 (F)的第4个实体程序化单元与实体抹除单元410 (F)的第6个实体程序化单元)中寻找以获得位于第三实体程序化单元706的快速实体程序化单元中的第二标记M2,并由此来识别存储奇偶信息P的地址。 In another exemplary embodiment, if the first user data can not be corrected by using the first user data D1-2 is error checking and correction code ECC1-2 D1-2 corresponding to the first and not the user data D1 obtaining a first redundant -2 Ml flag value than the first recording area SAR, the memory control circuit unit 104 (or the memory management circuit 202) will be close to the first user data from the second location D1-2 rapid physical entities programming unit programming means (e.g., physical erase unit 410 (F) of the program entities O unit, physical erase unit 410 (F) the fourth program entities and physical erase unit unit 410 (F) a sixth entities programming means) to find a second mark M2 to obtain a solid fast programming unit is located in a third entity in the program unit 706, and thus to identify the address of the store parity information P .

[0151] 值得一提的是,在此范例实施例中,由于用以记录奇偶信息所属的实体程序化单元地址的实体程序化单元会分别是位于奇偶信息所属的实体程序化单元的之前与之后的实体程序化单元,因此,倘若当用以记录奇偶信息所属的实体程序化单元地址的实体程序化单元中的其中一个损坏时(即,实体抹除单元中数据比特区所记录的数据与冗余比特区所记录的标记及错误检查与校正码遗失或损坏时),存储器控制电路单元104 (或存储器管理电路202)可还通过相邻于或接近于此笔所读取的数据的另一个实体程序化单元来识别出奇偶信息所属的实体程序化单元的地址。 [0151] It is worth mentioning that, in this exemplary embodiment, since the programming unit to be solid substance program recording unit address information belongs parity are programmed before the solid unit belongs to the parity information is located after the entities programming unit, therefore, if the time when the substance program unit for programming the recording unit address parity information entity belongs to one fails (i.e., the entity with the redundant data erase unit than the SAR data recorded another mark and the error checking and correction code is lost or damaged), the memory control I ratio recorded SAR circuit unit 104 (or the memory management circuitry 202) may be adjacent to or near the through this data read pen solid programming unit recognizes the address of the entity program parity information unit belongs. 据此,在数据无法通过错误检查与校正码来校正时,通过实体程序化单元中所存储的标记可有效地识别出存储此笔数据的奇偶信息的地址并且获取此奇偶信息,由此使用所获取的奇偶信息来校正数据中的错误比特。 Accordingly, when the data can not be corrected by the error checking and correcting code, by marking substance program stored in the unit can efficiently identify the address data stored in this pen parity information and parity obtain this information, thereby using the obtaining parity information to correct errors in the data bits.

[0152] 图7是根据本发明的第一范例实施例所示出的数据存储方法的流程图。 [0152] FIG. 7 is a flowchart of a data storage method according to the first embodiment illustrated exemplary embodiment of the present invention.

[0153] 请参照图7,在步骤S701中,存储器控制电路单元(或存储器管理电路)会依据一第一数据产生一奇偶信息。 [0153] Referring to FIG 7, in step S701, the memory control circuit unit (or memory management circuit) generates a parity information based on a first data. 在步骤S703中,存储器控制电路单元(或存储器管理电路)会将第一数据程序化至第一实体程序化单元。 In step S703, the memory control circuit unit (or memory management circuitry) will be programmed to a first data unit of the first program entity. 接着,在步骤S705中,存储器控制电路单元(或存储器管理电路)会将至少一标记程序化至所述第一实体程序化单元之中的冗余比特区,并且在步骤S707中,存储器控制电路单元(或存储器管理电路)将所述奇偶信息程序化至排列在所述第一实体程序化单元之后的至少一第二体程序化单元中,其中上述至少一标记会指示所述奇偶信息被程序化至所述至少一第二实体程序化单元中。 Next, in step S705, the memory control circuit unit (or memory management circuitry) will at least to a tag programmed redundancy among the first entity than the SAR program unit, and in step S707, the memory control circuit at least one second body unit programming unit (or memory management circuitry) the parity information programmed to said first entity arranged after programming unit, wherein the at least one marker indicating that the parity information is programmed of the at least one second entity to the programming unit.

[0154][第二范例实施例] [0154] [Second exemplary embodiment]

[0155] 本发明第二范例实施例的存储器存储装置与主机系统本质上是相同于第一范例实施例的存储器存储装置与主机系统,其中差异在于第二范例实施例的存储器控制电路单元(或存储器管理电路)会建立一奇偶信息地址对应表,并且同时使用实体程序化单元与奇偶信息地址对应表来记录一个奇偶信息所属的实体程序化单元地址。 [0155] is identical to the memory storage device and the host system is essentially a second exemplary embodiment of the present invention, a first exemplary memory storage device and the host system of the embodiment, wherein the difference is a second exemplary embodiment of the memory control circuit unit (or memory management circuitry) creates a parity address correspondence table, and at the same time using the programming unit entity parity information table to record the physical address corresponding to the program unit address information belongs to a parity. 以下将使用图1A、图2与图3的装置结构来描述第二范例实施例与第一范例实施例的差异部分。 Below using FIGS. 1A, Fig. 2 shows the structure of part of an embodiment 3 of the difference between the first exemplary embodiment and a second exemplary embodiment will be described.

[0156] 图8A与图SB是根据本发明第二范例实施例所示出的将写入数据、对应于写入数据的错误检查与校正码以及用以记录奇偶信息的至少一标记写入至实体程序化单元的范例示意图。 [0156] FIGS. 8A and SB is a second exemplary embodiment according to the present invention embodiment shown the write data, corresponding to an error checking and correction code to the write data, and means for recording at least one mark parity information is written to the sample application unit entities FIG.

[0157] 请参照图8A与图SB,其中图8A所示的将第一使用者数据、对应于第一使用者数据的错误检查与校正码、用以记录奇偶信息的地址的第一标记以及对应于第一使用者数据及其管理信息的奇偶信息写入至实体程序化单元的方法是相同于图5A所示的方法,在此不再重复。 [0157] Referring to FIGS. 8A and SB, the first user data shown in FIG. 8A in which, corresponding to the error checking and correction code to the first user data to a first address mark parity information is recorded and method of writing parity data corresponding to the first user and the program management information to the physical unit is identical to the method shown in FIG. 5A, will not be repeated. 其不同之处在于,在本范例实施例中,在将第一使用者数据Dl-1与D1-2以及对应第一使用者数据Dl-1与D1-2的错误检查与校正码ECCl-1与ECC1-2程序化至实体程序化单元之中的第一实体程序化单元602,并且将对应第一使用者数据Dl-1与D1-2与第一使用者数据Dl-1与D1-2的管理信息Sl-1与S1-2的奇偶信息P程序化至实体程序化单元之中的第二实体程序化单元604的操作中,存储器控制电路单元104 (或存储器管理电路202)会建立一奇偶信息地址对应表800 (如图8B所示)。 The difference is that, in the present exemplary embodiment, the first user data Dl-1 corresponding to a first user and with D1-2 data Dl-1 and D1-2 is error checking and correction code ECCl-1 ECC1-2 programmed to the first entity among entities programming unit programming unit 602, and the data corresponding to the first user Dl-1 and D1-2 of the first user data Dl-1 and D1-2 Sl-1 management information and parity information P S1-2 programmed to operate in a second physical entity procedural programming unit cell 604, the memory control circuit unit 104 (or the memory management circuit 202) creates a parity address correspondence table 800 (FIG. 8B). 例如,奇偶信息地址对应表800会被存储在缓冲存储器208或随机存取存储器1104中。 For example, parity information corresponding to the address in the buffer memory 208 or a random access memory 1104 in table 800 are stored. 特别是,存储器控制电路单元104 (或存储器管理电路202)会将第三标记M3记录在奇偶信息地址对应表800中,其中第三标记M3也会指示第二实体程序化单元604存储有奇偶信息P。 In particular, the memory control circuit unit 104 (or the memory management circuit 202) will correspond to the third mark M3 in the recording table 800 in the address parity information, wherein the third mark M3 indicating that the second entity will programming unit 604 stores parity information P.

[0158] 在本范例实施例中,在图8A中所示将第一使用者数据Dl-1与D1-2以及对应第一使用者数据Dl-1与D1-2的错误检查与校正码ECCl-1与ECC1-2程序化至实体程序化单元之中的第一实体程序化单元602,并且将对应第一使用者数据Dl-1与D1-2与其管理信息Sl-1与S1-2的奇偶信息P程序化至实体程序化单元之中的第二实体程序化单元604的操作之后,主机系统1000又再传送另一个写入指令与对应此写入指令的第二使用者数据D2给存储器存储装置100。 [0158] In the present exemplary embodiment, as shown in FIG. 8A of the first user data Dl-1 corresponding to a first user and with D1-2 data Dl-1 error checking and correcting code and D1-2 ECCl 1 and ECC1-2 programmed into the entity to the first entity programming unit programming unit 602, and the data corresponding to the first user and D1-2 thereto Dl-1 Sl-1 and the management information of S1-2 after the parity information P programmed to operate in a second physical entity programming unit programming unit 604, the host system 1000 again transmit another write instruction corresponding to this write command to the second user data memory D2 the memory device 100. 此时,倘若在存储器控制电路单元104 (或存储器管理电路202)将此第二使用者数据、对应此第二使用者数据的管理信息、指示奇偶信息P位于第二实体程序化单元604的第三标记M3以及对应此第二使用者数据的错误检查与校正码写入第三实体程序化单元606之前,主机系统1000或存储器存储装置100发生断电时,会造成用以记录奇偶信息P所在地址的第三标记M3无法被写入第三实体程序化单元606,或是造成第一实体程序化单元602中的数据遗失或损坏。 At this time, if the control circuit unit 104 (or the memory management circuit 202) in the second user data of this memory, this second management information corresponding to the user data, the parity information P indicating a second entity located in a first program unit 604 when the three previous mark M3 and the second user data corresponding to this error checking and correcting code into a third entity programming unit 606, the host system memory 1000 or storage device 100 is a power failure will cause the parity information P for recording where the third mark M3 can not be written to address a third entity programming unit 606, a first entity of data or results of a program unit 602 of loss or damage.

[0159] 在上述排列在第二实体程序化单元604之后的第三实体程序化单元606为空实体单元或因断电所造成的第一实体程序化单元602中的数据遗失或损坏的情况下,并且当存储器控制电路单元104(或存储器管理电路202)接收到主机系统1000所传送的欲读取上述第一使用者数据Dl-1与D1-2的读取指令时,存储器管理电路202 (或错误检查与校正电路212)会依据所读取的错误检查与校正码对所读取的第一使用者数据Dl-1与D1-2进行上述的错误检查与校正程序。 [0159] In the case where the second entity arranged after the programming unit 604 to the third entity programming unit 606 is lost or damaged data programming unit 602 due to power outages caused by the first entity in the empty or solid element and when receiving the memory control circuit unit 104 (or the memory management circuit 202) when the first user data to be read Dl-1 and D1-2 of the read instruction, the memory management circuitry 202 transmits the host system 1000 ( error checking and correcting code of the read or error checking and correction circuit 212) will be based on the first user data Dl-1 and D1-2 of the above read error checking and correction process. 倘若无法通过使用第一使用者数据Dl-1与D1-2的错误检查与校正码(即,ECCl-U ECC1-2)来校正第一使用者数据Dl-1与D1-2时,存储器控制电路单元104(或存储器管理电路202)会还用以根据上述的至少一标记来获得记录奇偶信息P的第二实体程序化单元604的地址,并从第二实体程序化单元604中读取此奇偶信息P以及依据所读取的奇偶信息P来校正第一使用者数据Dl-1与D1-2。 When the first user if the data can not be corrected Dl-1 and D1-2 by using the first user data Dl-1 and D1-2 code error checking and correction (i.e., ECCl-U ECC1-2), the memory control circuit unit 104 (or the memory management circuit 202) may also be used to obtain the address of the second entity P parity information recording unit 604 is a program based on the at least one marker, and read this program from the second physical unit 604 P parity information and parity information P based on the read user data to correct the first Dl-1 and D1-2. 举例而言,存储器管理电路202会先判断所读取的实体抹除单元410 (F)中对应于第一使用者数据D1-2的冗余比特区的第一记录区是否具有第一标记Ml,倘若此第一标记Ml存在并且可通过其得知奇偶信息P所在的地址,则存储器控制电路单元104(或存储器管理电路202)会根据此奇偶信息P来校正第一使用者数据Dl-1或D1-2。 For example, memory management circuitry 202 first determines the physical erasing the read unit 410 (F) corresponding to the first user data redundancy than the D1-2 recording region of the first SAR whether first marker Ml , if this first marker Ml exists and that the address parity information P by its location, then the memory control circuit unit 104 (or the memory management circuitry 202) based on this P parity information to correct the first user data Dl-1 or D1-2. 反之,倘若第一标记Ml不存在或是记录此第一标记Ml的冗余比特区损坏,则存储器管理电路202会读取上述奇偶信息地址对应表800并且根据奇偶信息地址对应表800中的第三标记M3获得奇偶信息P所在的实体程序化单元的地址。 Conversely, if the first marker Ml is absent or redundant recording of this first marker Ml ratio SAR damaged, then the memory management circuit 202 reads an address corresponding to the above-described parity information corresponding to the first table 800 and table 800 in accordance with the address parity information three address parity information P obtained mark M3 is located entities programming unit.

[0160][第三范例实施例] [0160] [Third exemplary embodiment]

[0161] 本发明第三范例实施例的存储器存储装置与主机系统本质上是相同于第一范例实施例的存储器存储装置与主机系统,其中差异在于第三范例实施例的存储器控制电路单元(或存储器管理电路)会根据每一笔写入数据所需写入的实体程序化单元的个数将标记值记录在此些实体程序化单元中,并且通过此些标记值来获得奇偶信息所属的实体程序化单元地址。 [0161] is identical to the memory storage device and the host system is essentially a third exemplary embodiment of the present invention, a first exemplary embodiment of the memory storage device and the host system of the embodiment, wherein the difference of the third exemplary embodiment in that the memory control circuit unit embodiment (or memory management circuitry) based on the number of the program write unit is required for each entity write data sum value of the flag recorded in the entity of such programming unit and belongs to the parity information is obtained by the entity of such tag value programmed cell address. 以下将使用图1A、图2与图3的装置结构来描述第三范例实施例与第一范例实施例的差异部分。 Below using FIGS. 1A, Fig. 2 shows the structure of part of an embodiment 3 differences of the third exemplary embodiment and the first exemplary embodiment will be described.

[0162] 相同于第一范例实施例,当主机系统1000传送写入指令与对应此写入指令的第一使用者数据Dl给存储器存储装置100时,存储器控制电路单元104(或存储器管理电路202)会判断第一使用者数据Dl的大小,并且根据第一使用者数据Dl的大小获得写入此第一使用者数据Dl所需的实体程序化单元的数目。 [0162] identical to the first exemplary embodiment, when the host system transmits 1000 a write command corresponding to this write command to the first user data Dl memory storage device 100, the memory control circuit unit 104 (or the memory management circuitry 202 ) will determine the size of a first user data Dl, and the number programmed in this unit, the first user entity required to write data Dl Dl according to the size of the first user data is obtained. 在此,假设需四个实体程序化单元来写入此第一使用者数据Dl。 Here, assuming four entities need to write the program unit of this first user data Dl. 在此范例中,存储器控制电路单元104 (或存储器管理电路202)会产生对应第一使用者数据Dl-1〜D1-4的错误检查与校正码ECCl-1〜ECC1-4以及对应第一使用者数据Dl-1〜D1-4的管理信息Sl-1〜S1-4。 In this example, the memory control circuit unit 104 (or the memory management circuit 202) corresponding to a first user generated data Dl-1~D1-4 error checking and correcting code and corresponding first ECCl-1~ECC1-4 use those data Dl-1~D1-4 management information Sl-1~S1-4. 特别是,存储器控制电路单元104 (或存储器管理电路202)在接收到上述第一使用者数据Dl时,并不会立刻将此第一使用者数据Dl写入至实体抹除单元中。 In particular, the memory control circuit unit 104 (or the memory management circuit 202) when the user receives the first data Dl, and this is not the first user data is immediately written to a physical erase Dl cells. 举例而言,存储器控制电路单元104 (或存储器管理电路202)会继续等待主机系统1000传送其他写入指令与对应此些指令的第二使用者数据D2与第三使用者数据D3给存储器存储装置100,并且计数此第二使用者数据D2与第三使用者数据D3所需写入的实体程序化单元的个数。 For example, the memory control circuit unit 104 (or the memory management circuit 202) will continue to wait for the host system 1000 and the second write instruction transmitted to other users of such data corresponding to the third user instruction D2 and D3 data to the memory storage device 100, and counts the number of physical elements of this second programming user data D2 and the third desired user data D3 written. 在此假设本范例实施例中的存储器控制电路单元104(或存储器管理电路202)会在写入每三个实体程序化单元后,对此三个实体程序化单元中的数据产生一个奇偶信息。 In this embodiment is assumed that the memory control circuit unit 104 (or the memory management circuit 202) will be written in each of the three entities programming unit, this data entity three programming unit generates a parity present exemplary embodiment. 在此范例实施例中,存储器控制电路单元104(或存储器管理电路202)会判断写入第二使用者数据D2与第三使用者数据D3所需的实体程序化单元的个数都为两个,并且存储器控制电路单元104(或存储器管理电路202)还会根据每一笔数据所需写入的实体程序化单元的个数以及每一笔数据被接收的先后顺序,将欲写入每一实体程序化单元的此些数据如图9中排序900所示的顺序来排序。 In this exemplary embodiment, the memory control circuit unit 104 (or the memory management circuit 202) determines user data written in the second and third user data entity programmed number of elements required for the D3 and D2 are two and the memory control circuit unit 104 (or the memory management circuit 202) will be based on the number of programming units required to write each of the entity, and a packet of data for each order received a packet of data, each to be written Such data entities programming unit 9 sort order 900 shown in FIG ordered.

[0163] 在另一范例实施例中,也可以在写入三个以上或三个以下的实体程序化单元后,对此三个以上或三个以下的实体程序化单元中的数据产生一个奇偶信息,本发明不加以限制。 [0163] In another exemplary embodiment, after writing it may also be three or more of the following three entities or the programming unit, or three or more of this data to the following procedure three entities unit generating a parity information, the present invention is not limited thereto. 此外,存储器控制电路单元104(或存储器管理电路202)等待主机系统1000所传送的其他写入指令与对应此些指令的数据笔数也不限于三笔。 Further, the memory control circuit unit 104 (or the memory management circuitry 202) waits for the other host system 1000 transmits a write command corresponding to such instructions and data items is not limited to three items.

[0164] 图9是根据本发明第三范例实施例所示出的根据写入数据欲写入的每一实体程序化单元的个数将其排列与记录标记值的范例,且图10是根据本发明第三范例实施例所示出的将写入数据、对应于写入数据的错误检查与校正码与用以记录奇偶信息的至少一标记写入至实体程序化单元的另一范例示意图。 [0164] FIG. 9 is an exemplary embodiment of the recording mark arrangement which is in accordance with the number of programmed values ​​of each physical unit write data to be written in accordance with a third embodiment illustrated example of the present invention, and FIG. 10 is a the third exemplary embodiment of the present invention is shown to write data, the write data corresponding to the error checking and correction code for recording with a schematic parity information written to the tag at least a sample application unit further entity.

[0165] 请参照图9,如上所述,由于存储器控制电路单元104(或存储器管理电路202)会在写入每三个实体程序化单元后,对每三个实体程序化单元中的数据产生一个奇偶信息,因此存储器控制电路单元104 (或存储器管理电路202)会进一步地根据排序900为欲写入每一实体程序化单元的此些数据记录一标记值。 [0165] Referring to FIG 9, as described above, will be written in the programming unit every three entities, data of each of the three entities for generating programming unit since the memory control circuit unit 104 (or the memory management circuitry 202) a parity information, the memory control circuit unit 104 (or the memory management circuitry 202) may further be written 900 to the program of such a data recording unit of each entity a tag value according to a ranking. 具体而言,第一使用者数据Dl-1的标记值会被记录为3,第一使用者数据D1-2的标记值会被记录为2,第一使用者数据D1-3的标记值会被记录为1,第一使用者数据D1-4的标记值会被记录为3,以及第二使用者数据D2-1的标记值会被记录为2且第二使用者数据D2-2的标记值会被记录为I。 Specifically, the first user data Dl-1 flag value is recorded as 3, a first user data D1-2 flag value will be recorded as 2, a first user data flag value will D1-3 1 is recorded, the value of the first user data marks will be recorded as a D1-4 3, user data and a second flag value is recorded D2-1 is marked 2 and the second user's data D2-2 value will be recorded as I. 特别是,其余的第三使用者数据D3所需写入的实体程序化单元仅有两个,因此,存储器管理电路202会将第三使用者数据D3-1的标记值会被记录为2并且将第三使用者数据D3-2的标记值会被记录为I。 In particular, the program entity unit remaining third desired user data D3 written only two, and therefore, the memory management circuitry 202 of user data will be the third flag value is recorded as the D3-1 and 2 the third flag value D3-2 user data will be recorded is I.

[0166] 之后,存储器控制电路单元104(或存储器管理电路202)会自闲置区504提取实体抹除单元410(F+1)作为替换实体抹除单元,并且根据图9中所示的排序,将此些数据、对应此些数据的管理信息,以及对应此些数据的多个错误检查与校正码依序地写入至实体抹除单元410(F+1)。 After the [0166] memory control circuit unit 104 (or the memory management circuit 202) will be idle from the solid extraction region 504 erasure unit 410 (F + 1) as shown and ordering a replacement physical erase unit according to FIG. 9, some of this data, corresponding to the management information of such data, and a corresponding plurality of error checking and correction code of such data is sequentially written to a physical erase unit 410 (F + 1).

[0167] 请参照图10,存储器控制电路单元104(或存储器管理电路202)会将第一使用者数据Dl-1〜D1-3与对应此些第一使用者数据的管理信息Sl-1〜S1-3,以及对应此些第一使用者数据的多个错误检查与校正码ECCl-1〜ECC1-3依序地写入至实体抹除单元410 (F+1)的第O个至第2个实体程序化单元中,其中在存储器控制电路单元104 (或存储器管理电路202)将对应第一使用者数据Dl-1〜D1-3的管理信息Sl-1〜S1-3写入实体抹除单元410 (F+1)中第O个至第2个实体程序化单元的冗余比特区中第一记录区的同时,存储器控制电路单元104(或存储器管理电路202)还会根据先前为第一使用者数据Dl-1〜D1-3所记录的标记值,在对应于第一使用者数据Dl-1〜D1-3的实体程序化单元的冗余比特区的第一记录区中记录此些标记值。 [0167] Referring to FIG 10, the memory control circuit unit 104 (or the memory management circuitry 202) the first user data will Dl-1~D1-3 management information corresponding to a first user of such data Sl-1~ S1-3, and a corresponding plurality of such error checking and correction code ECCl-1~ECC1-3 the first user data is sequentially written to a physical erase unit 410 (F + 1) th to the first O two entities programming unit, wherein the control circuit in the memory unit 104 (or the memory management circuit 202) corresponding to a first user data Dl-1~D1-3 management information writing entity wiping Sl-1~S1-3 in addition to unit 410 (F + 1) th redundancy of O to the second entity simultaneously programmed cells than the SAR of the first recording area, the memory control circuit unit 104 (or the memory management circuit 202) is also based on a previous Dl-1~D1-3 first user data recorded flag value, than the first recording area is recorded in the redundancy SAR program unit corresponding to the first entity is a user of the data Dl-1~D1-3 Such tag value. 此外,存储器控制电路单元104(或存储器管理电路202)会产生对应于第一使用者数据Dl-1〜D1-3与对应于第一使用者数据Dl-1〜D1-3的管理信息Sl-1〜S1-3的第一奇偶信息P1。 Further, the memory control circuit unit 104 (or the memory management circuit 202) corresponding to the first user generates the data Dl-1~D1-3 corresponding to the first user data management information Dl-1~D1-3 Sl- 1~S1-3 first parity information P1. 举例来说,在此假设第一使用者数据Dl-1〜D1-3所写入的实体抹除单元410 (F+1)中第O个至第2个实体程序化单元为第一实体程序化单元802,则存储器管理电路202会将应于第一使用者数据Dl-1〜D1-3及其管理信息Sl-1〜S1-3的奇偶信息Pl写入至实体抹除单元410 (F+1)中第3个实体程序化单元,在此假设实体抹除单元410 (F+1)中的第3个实体程序化单元为第二实体程序化单元804,即,存储器控制电路单元104 (或存储器管理电路202)会将对应于第一使用者数据Dl-1〜D1-3及其管理信息Sl-1〜S1-3的第一奇偶信息Pl写入排列在第一实体程序化单元802之中的最后一个实体程序化单元(即,实体抹除单元410 (F+1)中的第2个实体程序化单元)之后的第二实体程序化单元804。 For example, a first entity is assumed here that the user data written Dl-1~D1-3 erase unit 410 (F + 1) th to the first O 2 unit is a first physical entity programmed procedures unit 802, the memory management circuitry 202 will be written to a physical erase unit 410 (F in the first user data and parity information Dl-1~D1-3 Pl management information of Sl-1~S1-3 1) the first entity programming unit 3, the entity is assumed here that the erasing unit 410 (F + 1) the third entity to the second entity programming unit programming unit 804, i.e., the memory control circuit unit 104 (or the memory management circuit 202) will correspond to the first user data and first parity Dl-1~D1-3 information Sl-1~S1-3 Pl management information writing program arranged in the first physical unit the second entity after the programming unit (second unit program entities i.e., physical erase unit 410 (F + 1) in the) last entity programmed cell among 802,804. 并且,以此类推,存储器控制电路单元104 (或存储器管理电路202)会根据图9中的排序900接续地以第一使用者数据D1-4、第二使用者数据D2-1与第二使用者数据D2-2为一组,将对应此欲写入三个实体程序化单元中的数据的三个管理信息、三个错误检查与校正码以及奇偶信息分别且依序地写入实体抹除单元410 (F+1)中的第三实体程序化单元806与第四实体程序化单元808中。 And, so, the memory control circuit unit 104 (or the memory management circuit 202) will be successively 900 D1-4 data to the user in accordance with a first sort in FIG. 9, the second user using the second data D2-1 D2-2 data is set by the three management information corresponding to data to be written this three entities programming unit, the three error checking and correcting codes and parity information are written sequentially and erase entity unit 410 (F + 1) in the program the third entity and the fourth entity unit 806 programming unit 808. 特别是,由于其余的第三使用者数据D3欲写入的实体程序化单元的个数为2,因此存储器控制电路单元104 (或存储器管理电路202)仅会以第三使用者数据D3-1与第三使用者数据D3-2为一组,并且将对应此欲写入两个实体程序化单元中的数据的两个管理信息、两个错误检查与校正码以及奇偶信息分别且依序地写入实体抹除单元410 (F+1)中的第五实体程序化单元810与第六实体程序化单元812 中。 In particular, since the number of the rest of the program unit of the third entity to be written user data D3 is 2, so the memory control circuit unit 104 (or the memory management circuit 202) to only the third user data D3-1 and a third set of user data D3-2, and write information management two two entities programming unit data corresponds to this desire, two error checking and correcting codes and parity information are respectively and sequentially writing entity erase unit 410 (F + 1) in the fifth entity unit 810 in the sixth procedural programming unit 812 in the entity.

[0168] 具体而言,分别位于实体抹除单元410 (F+1)的第一实体程序化单元802、第三实体程序化单元806与第五实体程序化单元810中的第一标记值为1,第二标记值为2以及第三标记值为3。 [0168] Specifically, the first entity are located in the program unit 802 entity erase unit 410 (F + 1), the third entity is a first marking unit 806 and the fifth program entity programming unit 810 1, the second mark and a third mark value of 2 is 3. 请再参照图10,第一标记值会被记录在第一实体程序化单元802之中的最后一个实体程序化单元(即,实体抹除单元410 (F+1)中的第2个实体程序化单元)中冗余比特区的第一记录区,第二标记值会被记录在第一实体程序化单元802之中相邻且排列在最后一个实体程序化单元之前的实体程序化单元(即,实体抹除单元410 (F+1)中的第I个实体程序化单元)的冗余比特区中,以及第三标记值会被记录在第一实体程序化单元802之中相邻且排列在记录第二标记值的实体程序化单元之前的实体程序化单元(即,实体抹除单元410(F+1)中的第O个实体程序化单元)的冗余比特区中。 Referring again to FIG 10, a first mark value is recorded last physical unit in the first program entity programming unit 802 (i.e., the second physical entity erase program unit 410 (F + 1) in the unit) than the first redundant recording area SAR, the second flag value is recorded and arranged adjacent to the program unit in the entity prior to the last physical unit in the first program entity programming unit 802 (i.e. , physical erase unit 410 (F + 1) in the I-th redundant entity programmed cell) than in the SAR, and the third flag value is recorded in a program unit 802 of the first entity and arranged adjacent entity before the programming unit programming unit of the second physical mark value recorded (i.e., physical erase unit 410 (F + 1) in the first unit program entities O) ratio of redundancy in the SAR. 并且,以此类推,第三实体程序化单元806中的标记值会以图10中所示的排列方式排序。 And, so, the value of the third entity tag programming unit 806 is sorted in the arrangement shown in Figure 10. 值得一提的是,第三使用者数据D3仅须写入两个实体程序化单元,因此,第五实体程序化单元810中仅会有第一标记值与第二标记值。 It is worth mentioning that the third data D3 user only has to write two entities programming unit, therefore, the fifth solid programming unit 810 will mark only the first value and the second value tag.

[0169] 之后,倘若存储器控制电路单元104(或存储器管理电路202)接收到主机系统1000所传送的欲读取上述第一使用者数据Dl的读取指令时,存储器管理电路202 (或错误检查与校正电路212)会依据所读取的错误检查与校正码对所读取的第一使用者数据Dl进行上述的错误检查与校正程序。 After the time [0169], the control circuit if the memory unit 104 (or the memory management circuit 202) receiving a read command to the first user data to be read Dl 1000 received from the host system, memory management circuitry 202 (or error checking error checking and correction code correction circuit 212) will be based on the first read of the read user data subjected to the above Dl error checking and correction process. 倘若无法通过使用第一使用者数据Dl-1〜D1-4的错误检查与校正码(即,ECCl-1〜ECC1-4)来校正第一使用者数据Dl-1〜D1-4时,存储器控制电路单元104 (或存储器管理电路202)会根据上述的至少一个标记值来获得记录第一奇偶信息Pl与第二奇偶信息P2的实体程序化单元的地址。 If not corrected the first user data Dl-1~D1-4, the memory by the user using the first error check data with Dl-1~D1-4 correction code (i.e., ECCl-1~ECC1-4) the control circuit unit 104 (or the memory management circuit 202) will be programmed to obtain the address of the entity of the unit recording information is a first parity and the second parity information Pl and P2 based on the at least one tag value. 在此假设当无法通过使用第一使用者数据D1-2的错误检查与校正码ECC1-2来校正第一使用者数据D1-2且无法从对应于第一使用者数据D1-2的冗余比特区的第一记录区获得第二标记值时,存储器控制电路单元104 (或存储器管理电路202)会从第一实体程序化单元802中邻近于第一使用者数据D1-2所在的第I个实体程序化单元的实体程序化单元(例如,实体抹除单元410 (F+1)的第O个或第2个实体程序化单元)中获得至少一个标记值。 And it can not be assumed here that when the redundancy data can not be corrected by the first user using the first user data D1-2 is error checking and correcting code from ECC1-2 D1-2 D1-2 data corresponding to the first user obtaining second mark recording area than the first value of the SAR, the memory control circuit unit 104 (or the memory management circuit 202) will be adjacent to the first user data from the first entity in the program unit 802 of D1-2 where I (O the first entity or the second programmable means e.g., physical erase unit 410 (F + 1)) of a solid substance program unit programming unit obtaining at least one tag value. 在此假设存储器控制电路单元104 (或存储器管理电路202)是从第一实体程序化单元802中的第2个实体程序化单元获得其冗余比特区的标记值为1,则存储器控制电路单元104(或存储器管理电路202)会判断对应于第一使用者数据Dl-1〜D1-3的第一奇偶信息Pl所在的地址即为相邻于第一实体程序化单元802之中的最后一个实体程序化单元的实体程序化单元(即,第二实体程序化单元804),并且存储器控制电路单元104 (或存储器管理电路202)会读取此第一奇偶信息Pl以及依据所读取的第一奇偶信息Pl来校正第一使用者数据D1。 It is assumed here that the memory control circuit unit 104 (or the memory management circuitry 202) which is obtained from the first entity redundancy programming unit 802 in the second unit is programmable entities labeled SAR than 1, then the memory control circuit unit 104 (or the memory management circuit 202) determines the address corresponding to the first user data Dl-1~D1-3 first parity information is the Pl is located adjacent to the first entity in the last programming unit 802 solid programming unit programming unit entity (i.e., the second entity programming unit 804), and the memory control circuit unit 104 (or the memory management circuit 202) reads this first Pl and parity information based on the read a Pl parity information to correct the first user data D1. 此外,假设存储器控制电路单元104 (或存储器管理电路202)也可以从第一实体程序化单元802中的第O个实体程序化单元获得其冗余比特区的标记值为3,则存储器控制电路单元104 (或存储器管理电路202)会判断对应于第一使用者数据Dl-1〜D1-3的第一奇偶信息Pl所在的地址即为距离本身(即,第一实体程序化单元802中的第O个实体程序化单元)3个的实体程序化单元的第二实体程序化单元804。 Further, assume that the memory control circuit unit 104 (or the memory management circuit 202) may also be obtained from the first entity redundant program unit 802 of the program entities O unit 3 to mark the SAR value, then the memory control circuit unit 104 (or the memory management circuit 202) determines the address information corresponding to the first user data is located Pl Dl-1~D1-3 a first parity (i.e., a first program unit 802 is the entity itself, the distance the program unit of the second entity entities O program unit) 3 entities programming unit 804. 接着,存储器控制电路单元104(或存储器管理电路202)会读取此第一奇偶信息Pl以及依据所读取的第一奇偶信息Pl来校正第一使用者数据Dl。 Next, the memory control circuit unit 104 (or the memory management circuit 202) reads this information first parity Pl Pl and the first parity information is corrected based on the read first user data Dl. 据此,倘若对应每一实体化程序单元中的数据无法通过各自的错误检查与校正码而被校正时,或是每一实体化程序单元中的数据所对应的用以记录标记值的区域部分损坏时,存储器控制电路单元104 (或存储器管理电路202)可根据相邻的实体程序化单元来获得用以指示奇偶信息的地址的标记值,由此也可以有效的预防所读取的数据发生无法校正的情况。 Accordingly region part, if the time data corresponding to each entity of the program unit can not be corrected by the respective error checking and correcting code or data recording mark value for each entity of the program corresponding to the unit when damaged, the memory control circuit unit 104 (or the memory management circuitry 202) may be obtained as a value to indicate an address parity information based on adjacent solid programming unit, whereby data may be effective in preventing the occurrence of the read the situation can not be corrected.

[0170][第四范例实施例] [0170] [Fourth exemplary embodiment]

[0171] 本发明第四范例实施例的存储器存储装置与主机系统本质上是相同于第一范例实施例的存储器存储装置与主机系统,其中差异在于第四范例实施例的存储器控制电路单元(或存储器管理电路)会建立一奇偶信息地址对应表,并且使用此奇偶信息地址对应表来记录每一奇偶信息所属的实体程序化单元地址。 [0171] is identical to the memory storage device and the host system is essentially a fourth exemplary embodiment of the present invention a first exemplary memory storage device and the host system of the embodiment, wherein the difference is a fourth exemplary embodiment of the memory control circuit unit (or memory management circuitry) creates a parity address correspondence table, and uses this parity information table to record the physical address corresponding to the program address of each parity information unit belongs. 以下将使用图1A、图2与图3的装置结构来描述第四范例实施例与第一范例实施例的差异部分。 Below using FIGS. 1A, Fig. 2 shows the structure of part of an embodiment 3 of the difference from the first exemplary embodiment of the fourth exemplary embodiment will be described.

[0172] 图11是根据本发明第四范例实施例所示出的将写入数据、对应于写入数据的错误检查与校正码程序化至实体程序化单元以及将用以记录奇偶信息的至少一标记记录在奇偶信息地址对应表的范例示意图。 [0172] FIG. 11 is an exemplary embodiment of the present invention according to the fourth embodiment shown the write data corresponding to the error checking and correction code programmed to write data to the entity and the programming unit for recording at least parity information an example of mark recording in the address parity information table corresponding to FIG.

[0173] 请参照图11,图11所示的将第一使用者数据、对应于第一使用者数据的错误检查与校正码以及对应于第一使用者数据的奇偶信息写入至实体程序化单元的方法是相同于第一范例实施例中的图5A与图5B所示的方法,在此不再重复。 [0173] Referring to FIG 11, the first user data shown in FIG. 11, corresponding to the first user data and the error checking and correction code corresponding to the first parity information is written to the user data entity programmed the method is the same unit in a first exemplary method embodiment shown in FIG. 5B in Figure 5A embodiment, will not be repeated. 其不同之处在于,在本范例实施例中,存储器控制电路单元104(或存储器管理电路202)会先建立一奇偶信息地址对应表110,并且奇偶信息地址对应表110会被存储在缓冲存储器208或随机存取存储器1104中。 The difference is that, in the present exemplary embodiment, the memory control circuit unit 104 (or the memory management circuit 202) will first establish a parity address correspondence table 110, and the parity information address correspondence table 110 is stored in buffer memory 208 1104 or random access memory. 并且在存储器控制电路单元104 (或存储器管理电路202)将第一使用者数据Dl-1与D1-2、对应第一使用者数据Dl-1与D1-2的管理信息Sl-1与S1-2以及对应第一使用者数据Dl-1与D1-2的错误检查与校正码ECCl-1与ECC1-2程序化至实体程序化单元之中的第一实体程序化单元602,以及将对应第一使用者数据Dl-1与D1-2及其管理信息Sl-1与S1-2的第一奇偶信息Pl程序化至实体程序化单元之中的第二实体程序化单元604的操作中,存储器控制电路单元104(或存储器管理电路202)不会将用以记录第一奇偶信息Pl的地址的第一标记Ml程序化至第一实体程序化单元602中的至少其中一个实体程序化单元,而是将第一标记Ml记录在先前所建立的奇偶信息地址对应表110。 And the control circuit 104 in the memory unit (or memory management circuitry 202) the first user data Dl-1 and D1-2, user management data corresponding to the first and D1-2 Dl-1 information and S1- Sl-1 2 and corresponds to the first user data Dl-1 and D1-2 is error checking and correction code ECCl-1 and ECC1-2 programmed to the first entity among entities programming unit programming unit 602, and the first correspondence a user data Dl-1 and D1-2 Sl-1 and the management information and the first parity Pl S1-2 programmed to operate the second entity among entities programming unit programming unit 604, the memory first marker Ml programming unit to a first entity 602 programmed control circuit unit 104 (or the memory management circuit 202) will not be used for recording the address of the first parity information Pl wherein the at least one entity in programmed cell, and Ml is a first recording mark in the address parity information previously established correspondence table 110. 在另一范例实施例中,倘若主机系统1000传送一个写入指令与对应此写入指令的第二使用者数据D2给存储器存储装置100时,存储器控制电路单元104(或存储器管理电路202)会将此第二使用者数据D2与其所产生的对应此第二使用者数据D2的错误检查与校正码ECC2以及对应第二使用者数据D2的管理信息S2写入至实体抹除单元410 (F)的第三实体程序化单元606中,特别是,存储器控制电路单元104(或存储器管理电路202)可以另外地提取一个实体抹除单元410 (F+1),并将对应第二使用者数据D2及其管理信息S2的第二奇偶信息P2程序化至实体抹除单元410(F+1)中的第一实体程序化单元802,此外,存储器控制电路单元104 (或存储器管理电路202)会将用以记录第二奇偶信息P2的地址的第二标记M2同样地记录在奇偶信息地址对应表110中。 In another exemplary embodiment, if the host system 1000 transmits a write instruction corresponding to this write command data D2 of the second user 100, the memory control circuit unit 104 (or the memory management circuit 202) to the memory storage device will this write data corresponding to the second user D2 produces this second user data error checking and correction code ECC2 D2, and D2 corresponding to the second user data management information to a physical erase unit S2 410 (F) the third entity in the program unit 606, in particular, the memory control circuit unit 104 (or the memory management circuitry 202) may additionally extract a physical erase unit 410 (F + 1), and the data D2 corresponding to the second user and the second parity information P2 S2 is programmed to a physical management information erasing unit 410 (F + 1) the first entity programming unit 802. in addition, the memory control circuit unit 104 (or the memory management circuit 202) will the second mark M2 to the second address parity information P2 is recorded in the same manner records correspondence table 110 in the address parity information. 值得一提的是,在本范例实施例中,并不加以限制奇偶信息所存放的实体抹除单元,即,存储器控制电路单元104 (或存储器管理电路202)所提取的用以记录奇偶信息的实体抹除单元也可以是不同于对应此奇偶信息的写入数据所在的实体抹除单元所对应的存储器晶粒。 It is worth mentioning that, in the present exemplary embodiment, parity information is not limited by the physical storage units of erased, i.e., the memory control circuit unit 104 (or the memory management circuit 202) for recording the extracted parity information entity erasing unit may be different from the corresponding entities in this write data parity information erasing unit is located corresponding memory die. 换言之,当无法通过使用第一使用者数据Dl-1与D1-2的错误检查与校正码ECC1-1、ECC1-2来校正第一使用者数据Dl-1或D1-2时,存储器控制电路单元104 (或存储器管理电路202)即可根据奇偶信息地址对应表110获得记录第一奇偶信息Pl的地址的第一标记M1,或是当无法通过使用第二使用者数据D2的错误检查与校正码ECC2来校正第二使用者数据D2时,存储器控制电路单元104 (或存储器管理电路202)即可根据奇偶信息地址对应表110获得记录第二奇偶信息P2的地址的第二标记M2,据此,存储器控制电路单元104 (或存储器管理电路202)可根据奇偶信息地址对应表110快速地获得奇偶信息是属于哪一个实体程序化单元。 In other words, when a user can not by using the first data Dl-1 and D1-2 is error checking and correction code ECC1-1, ECC1-2 user to correct the first or D1-2 data Dl-1, the memory control circuit unit 104 (or the memory management circuit 202) to the address correspondence table 110 to obtain a first parity information recording first mark M1 Pl is a parity address information, or when D2 is not user data by using the second error checking and correction ECC2 correcting code data D2 of the second user, the memory control circuit unit 104 (or the memory management circuit 202) corresponding to the second mark M2 to obtain records of the second table 110 in the address parity information P2 based on the address parity information, whereby the memory control circuit unit 104 (or the memory management circuit 202) correspondence table 110 can quickly obtain a solid which parity information is programmed according to the parity information belonging to the address unit.

[0174] 图12是根据本发明的第四范例实施例所示出的数据存储方法的流程图。 [0174] FIG. 12 is a flowchart illustrating a fourth example of the present invention, the data storage method shown in Example.

[0175] 请参照图12,在步骤S1201中,存储器控制电路单元(或存储器管理电路)会建立一奇偶信息地址对应表。 [0175] Referring to FIG 12, in step S1201, the memory control circuit unit (or memory management circuitry) creates a parity address correspondence table. 在步骤S1203中,存储器控制电路单元(或存储器管理电路)会依据第一数据产生一奇偶信息。 In step S1203, the memory control circuit unit (or memory management circuit) generates a parity information based on the first data. 接着,在步骤S1205中,存储器控制电路单元(或存储器管理电路)会将第一数据程序化至第一实体程序化单元的数据比特区。 Next, in step S1205, the memory control circuit unit (or memory management circuit) data will be programmed to a first data unit of the first entity than the SAR program. 在步骤S1207中,存储器控制电路单元(或存储器管理电路)将所述奇偶信息程序化至至少一第二实体程序化单元中。 In step S1207, the memory control circuit unit (or memory management circuitry) programming the parity information to the at least one second entity programming unit. 并且在步骤S1209中,存储器控制电路单元(或存储器管理电路)将至少一标记记录于所述奇偶信息地址对应表,其中所述至少一标记会指示所述奇偶信息被程序化至所述第二实体程序化单元中。 And in step S1209, the memory control circuit unit (or memory management circuitry) the at least one recording mark parity information to the address correspondence table, wherein said at least one marker indicating that the parity information is programmed to the second solid programming unit.

[0176] 综上所述,本发明范例实施例的数据存储方法、存储器控制电路单元与存储器存储装置会在写入数据的同时,将对应此些写入数据的奇偶信息的地址记录在至少一个标记中并且将此至少一标记写入所接收的数据所欲写入的至少一实体程序化单元,据此,当从可复写式非易失性存储器模块中读取的数据比特存在错误时,可以根据所述至少一标记,快速地获得奇偶信息是属于哪一个实体程序化单元,进而有效地增加错误校正的更正能力与效率。 The data storage method of Example [0176] In summary, the example of the present invention, the memory control circuit unit and the memory storage device while writing data will, of such parity information corresponding to the write address data recorded in at least a at least one physical programming unit at least one mark and this mark writing be written by the received data, whereby, when the data read from the rewritable non-volatile memory module of bit errors, said at least one marker can quickly obtain a solid which parity information is programming unit belongs, thereby effectively increasing the correcting capability of the error correcting efficiency. 此外,本发明范例实施例的用以校正读取数据的奇偶信息所写入的实体程序化单元是排列在所写入之数据所在的实体程序化单元之后,基此,通过本发明范例实施例的数据存储方法不需要将对应于多笔写入数据的奇偶信息放置在系统中的固定的存储器晶粒,以有效地避免存储器存储装置中存储空间的浪费。 In addition, solid unit for correcting the program reads the data parity information written exemplary embodiment of the present invention is arranged after the substance program unit where the data is written, this group, by way of example embodiments of the present invention the data storage method corresponding to a multi-pen does not need to write data parity information is placed in the system memory die fixed to effectively avoid wasting memory stored in the storage space.

[0177] 最后应说明的是:以上各实施例仅用以说明本发明的技术方案,而非对其限制;尽管参照前述各实施例对本发明进行了详细的说明,本领域的普通技术人员应当理解:其依然可以对前述各实施例所记载的技术方案进行修改,或者对其中部分或者全部技术特征进行等同替换;而这些修改或者替换,并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。 [0177] Finally, it should be noted that: the above embodiments only describe the technical solutions in embodiments of the present invention, rather than limiting;. Although the embodiments of the present invention has been described in detail, those of ordinary skill in the art should appreciated: it still may be made to the technical solutions described embodiments modifications, or to some or all of the technical features equivalents; as such modifications or replacements do not cause the essence of corresponding technical solutions to depart from embodiments of the present invention range of technical solutions.

Claims (21)

  1. 1.一种数据存储方法,其特征在于,用于可复写式非易失性存储器模块,该可复写式非易失性存储器模块包括多个实体抹除单元,且每一该些实体抹除单元包括多个实体程序化单元,其中每一该些实体程序化单元包括数据比特区与冗余比特区,该数据存储方法包括: 依据第一数据产生奇偶信息; 将该第一数据程序化至该些实体程序化单元之中的第一实体程序化单元中;以及将该奇偶信息程序化至该些实体程序化单元之中的至少一第二实体程序化单元中,其中该至少一第二实体程序化单元是排列在该第一实体程序化单元之后; 其中在上述将该第一数据程序化至该些实体程序化单元之中的该第一实体程序化单元的步骤包括:将至少一标记程序化至该第一实体程序化单元之中的冗余比特区,其中该至少一标记指示该奇偶信息被程序化至该至少一第二实体程 1. A data storage method, wherein a rewritable non-volatile memory module, the rewritable non-volatile memory module comprises a plurality of physical erase unit, and each of the entity erase programming unit includes a plurality of physical units, wherein each of the programming unit comprises a data entity than the SAR and SAR ratio of redundancy, the data storage method comprising: generating parity information based on a first data; programmed to the first data programming the first entity among the plurality of unit solid programming unit; at least one second entity, and the program unit programmed to parity information among the plurality of entity programmed unit, wherein the at least one second substance program unit is arranged after the first physical programming unit; wherein the first data in the above programming step programming unit to the first entity among the plurality of entity programmed unit comprises: at least one redundant programmed to mark the first entity in the program than the SAR unit, wherein the at least one marker indicating that the parity information is programmed to process the at least one second entity 序化单元中。 Ordering unit.
  2. 2.根据权利要求1所述的数据存储方法,其特征在于,该第一数据包括使用者数据与对应该使用者数据的管理信息; 其中该使用者数据被程序化至该第一实体程序化单元之中的数据比特区,其中对应该使用者数据的该管理信息被程序化至该第一实体程序化单元之中的冗余比特区。 2. The data storage method according to claim 1, wherein the first data comprises user data and management information corresponding to the user data; wherein the user data is programmed to the first programmed entity among the data units than the SAR, which should be on the management information to the user data is programmed into the first redundancy unit program entity than the SAR.
  3. 3.根据权利要求1所述的数据存储方法,其特征在于,该第一数据包括使用者数据、对应该使用者数据的管理信息以及对应该使用者数据的错误检查与校正码; 其中该错误检查与校正码是根据该使用者数据所产生的; 其中该使用者数据被程序化至该第一实体程序化单元之中的数据比特区,其中对应该使用者数据的该管理信息被程序化至该第一实体程序化单元之中的冗余比特区,其中对应该使用者数据的该错误检查与校正码被程序化至该第一实体程序化单元之中的冗余比特区。 3. The data storage method according to claim 1, wherein the first data comprises user data, the management information for user data should be and the user data to be error checking and correcting code; wherein the error checking and correction codes are generated based on the user data; wherein the user data is programmed to the data programmed into the first entity than the SAR unit, wherein the management information for the user should the data to be programmed redundant to the first entity in the program than the SAR unit, in which the error checking and correction should code the user data is programmed into the redundancy among the first physical unit than the SAR program.
  4. 4.根据权利要求2或3所述的数据存储方法,其特征在于,将该至少一标记程序化至该第一实体程序化单元之中的冗余比特区的步骤包括: 将第一标记程序化至该第一实体程序化单元之中的最后一个实体程序化单元的冗余比特区,其中该至少一第二实体程序化单元是排列在该第一实体程序化单元之中的该最后一个实体程序化单元之后,其中该第一标记指示该至少一第二实体程序化单元存储该奇偶/[目息;以及将第二标记程序化至该些实体程序化单元之中的至少一第三实体程序化单元的冗余比特区,其中该至少一第三实体程序化单元是排列在该至少一第二实体程序化单元之后,其中该第二标记指示该至少一第二实体程序化单元存储该奇偶信息。 The data storage method according to claim 2 or claim 3, wherein the at least one marker is programmed into the first to the redundant entity procedural steps than the SAR unit comprises: a first labeling procedure redundant to the last entity of a program unit among the first physical unit than the SAR program, wherein the at least one programming unit is a second physical arrangement of the first entity among the units in the program of the last after the substance program unit, wherein the first flag indicates that the second entity a programming unit to store the parity / [mesh least information; and the second indicia programmed into the plurality of entities to the program unit, at least a third redundancy programming entities than the SAR unit, wherein the at least one third entity is a programming unit arranged after the at least one second entity programming unit, wherein the second flag indicates that the at least one second physical unit is stored a program the parity information.
  5. 5.根据权利要求4所述的数据存储方法,其特征在于,将该至少一标记程序化至该第一实体程序化单元之中的冗余比特区的步骤还包括: 建立奇偶信息地址对应表;以及将第三标记记录在该奇偶信息地址对应表,其中该第三标记指示该至少一第二实体程序化单元存储该奇偶信息。 The data storage method as claimed in claim 4, wherein the at least one marker to the redundant programmed into the programming unit than the first physical step D.C. further comprising: establishing an address parity information correspondence table ; and a third mark parity information is recorded in the address correspondence table, wherein the third flag indicates that the second entity a programming unit to store at least the parity information.
  6. 6.根据权利要求1所述的数据存储方法,其特征在于,将该至少一标记程序化至该第一实体程序化单元之中的冗余比特区的步骤包括: 计数该第一实体程序化单元的个数;以及根据该第一实体程序化单元的个数,在每一该第一实体程序化单元的冗余比特区中记录一标记值,其中记录在该第一实体程序化单元中的该标记值依据该第一实体程序化单元的排列依序地递减。 The data storage method according to claim 1, wherein the at least one marker is programmed into the first to the redundant entity procedural steps than the SAR unit comprises: a first count of the entity of the program the number of cells; and a program unit according to the number of the first entity, the redundancy in each of the programming unit of the first entity a recording mark than the value in the SAR, which is recorded in the first physical unit in the program the tag value decremented sequentially arranged according to the first program unit entities.
  7. 7.根据权利要求6所述的数据存储方法,其特征在于,该标记值之中的第一标记值为1,且该第一标记值被记录在该第一实体程序化单元之中的最后一个实体程序化单元的冗余比特区中,且该至少一第二实体程序化单元是排列在该第一实体程序化单元之中的该最后一个实体程序化单元之后; 其中该标记值之中的第二标记值为2,且该第二标记值被记录在该些第一实体程序化单元之中相邻且排列在该最后一个实体程序化单元之前的实体程序化单元的冗余比特区中; 其中该标记值之中的第三标记值为3,且该第三标记值被记录在该些第一实体程序化单元之中相邻且排列在记录该第二标记值的实体程序化单元之前的实体程序化单元的冗余比特区中。 The data storage method according to claim 6, wherein the first marker in the flag value is 1, and the first flag value is recorded in the first physical unit of the last program a redundancy entity than the SAR program unit, and the at least one second entity of the programming unit is the last entity in programmed cells arranged the first entity after the programming unit; wherein the value tag among 2 is a second marker, and the second flag value is recorded in the plurality of first entity and a program unit are arranged adjacent to the redundant entity prior to the last programming unit programming entities than the SAR unit ; wherein the third marker in the marker value is 3, and the third flag value is recorded and arranged adjacent to the recording of the program entities of the second mark value in the plurality of first entity programming unit redundancy program before the unit solid unit than in the SAR.
  8. 8.根据权利要求1所述的数据存储方法,其特征在于,该第一数据包括第二数据以及错误检查与校正码,该数据存储方法还包括: 当无法通过使用该错误检查与校正码来校正该第二数据时,根据该至少一标记获得记录该奇偶信息的该至少一第二实体程序化单元的地址,从该至少一第二实体程序化单元中读取该奇偶信息以及依据所读取的该奇偶信息来校正该第二数据。 8. The data storage method according to claim 1, wherein the data comprises first data and second error checking and correction code, the data storage method further comprises: when this can not be through the use of error checking and correcting code the second correction data, based on the obtained at least one marker of the at least one second physical address programming unit of the parity information is recorded, and reads the parity information from the at least according to a program unit in the read second entity take the second parity information to correct the data.
  9. 9.一种数据存储方法,其特征在于,用于可复写式非易失性存储器模块,该可复写式非易失性存储器模块包括多个实体抹除单元,且每一该些实体抹除单元包括多个实体程序化单元,其中每一该些实体程序化单元包括数据比特区与冗余比特区,该数据存储方法包括: 建立奇偶信息地址对应表; 依据第一数据产生奇偶信息; 将该第一数据程序化至该些实体程序化单元之中的第一实体程序化单元中; 将该奇偶信息程序化至该些实体程序化单元之中的至少一第二实体程序化单元中;以及将至少一标记记录在该奇偶信息地址对应表,其中该至少一标记指示该奇偶信息被程序化至该至少一第二实体程序化单元中。 A data storage method, wherein a rewritable non-volatile memory module, the rewritable non-volatile memory module comprises a plurality of physical erase unit, and each of the entity erase programming unit includes a plurality of physical units, wherein each of the programming unit comprises a data entity than the SAR and SAR ratio of redundancy, the data storage method comprising: establishing an address parity information correspondence table; generating parity information based on a first data; programming the first data to the first entity among the plurality of entities programming unit programming unit; programmed to the parity information among the plurality of entity programmed cell programming at least a second physical unit; and at least a mark parity information is recorded in the address correspondence table, wherein the at least one marker indicating that the parity information is programmed to the at least one second entity programming unit.
  10. 10.一种存储器控制电路单元,其特征在于,用于控制可复写式非易失性存储器模块,其中该可复写式非易失性存储器模块包括多个实体抹除单元,且每一该些实体抹除单元包括多个实体程序化单元,其中每一该些实体程序化单元包括数据比特区与冗余比特区,该存储器控制电路单元包括: 主机接口,用以f禹接至主机系统; 存储器接口,用以耦接至该可复写式非易失性存储器模块;以及存储器管理电路,耦接至该主机接口与该存储器接口; 其中该存储器管理电路用以依据第一数据产生奇偶信息; 其中该存储器管理电路还用以将该第一数据程序化至该些实体程序化单元之中的第一实体程序化单元中; 其中该存储器管理电路还用以将该奇偶信息程序化至该些实体程序化单元之中的至少一第二实体程序化单元中,其中该至少一第二实体程序化单元是排列 A memory control circuit means, characterized in that, for controlling the rewritable nonvolatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical erase unit, and each of the entity comprises a plurality of physical erase unit program unit, wherein each of the programming unit comprises a data entity than the SAR and SAR ratio of redundancy, the memory control circuit unit comprises: a host interface for f Yu to a host system; a memory interface for coupling to the rewritable non-volatile memory module; and a memory management circuit, coupled to the host interface and the memory interface; wherein the memory management circuitry for generating parity information based on a first data; wherein the memory management circuitry further programmed for converting the first data to the programming unit of the first entity among the plurality of entities programming unit; wherein the memory management circuitry is further configured to the parity information for the plurality of programming at least one second entity among entities programming unit programming unit, wherein the at least one programming unit is a second physical arrangement 在该第一实体程序化单元之后; 其中在上述将该第一数据程序化至该些实体程序化单元之中的该第一实体程序化单元的操作中,该存储器管理电路将至少一标记程序化至该第一实体程序化单元之中的冗余比特区,其中该至少一标记指示该奇偶信息被程序化至该至少一第二实体程序化单元中。 After programming the first physical unit; wherein in the above data is programmed to the first operation program of the first physical unit from among the plurality of entity programmed unit, the memory management circuit to the at least one labeling procedure among the first to the entity of the program than the SAR redundant unit, wherein the at least one marker indicating that the parity information is programmed to the at least one second entity programming unit.
  11. 11.根据权利要求10所述的存储器控制电路单元,其特征在于,该第一数据包括使用者数据与对应该使用者数据的管理信息; 其中该使用者数据被程序化至该第一实体程序化单元之中的数据比特区,其中对应该使用者数据的该管理信息被程序化至该些第一实体程序化单元之中的冗余比特区。 11. The memory according to claim 10, wherein the control circuit unit, wherein the first data comprises user data and management information corresponding to the user data; wherein the user data is programmed to the first entity program than the data within the SAR unit, wherein the management information for user data should be programmed to the first entity among the plurality of redundancy programming unit than the SAR.
  12. 12.根据权利要求10所述的存储器控制电路单元,其特征在于,该第一数据包括一使用者数据、对应该使用者数据的一管理信息以及对应该使用者数据的一错误检查与校正码; 其中该错误检查与校正码是根据该使用者数据所产生的; 其中该使用者数据被程序化至该第一实体程序化单元之中的数据比特区,其中对应该使用者数据的该管理信息被程序化至该第一实体程序化单元之中的冗余比特区,其中对应该使用者数据的该错误检查与校正码被程序化至该第一实体程序化单元之中的冗余比特区。 12. The memory according to claim 10, said control circuit unit, wherein the data includes a first user data, should a user data management information as well should a user error checking and correction code data ; wherein the error checking and correcting code is generated based on the user data; a data entity programmed into the first unit wherein the user data is programmed to the ratio of the SAR, to which should be managed by the user data to the redundant information is programmed into the first physical unit than the SAR program, which should be on the error checking and correction code to user data is programmed into the redundancy than the first physical unit program DC.
  13. 13.根据权利要求11或12所述的存储器控制电路单元,其特征在于,将该至少一标记程序化至该些第一实体程序化单元之中的冗余比特区的操作中,该存储器管理电路将第一标记程序化至该第一实体程序化单元之中的最后一个实体程序化单元的冗余比特区,其中该至少一第二实体程序化单元是排列在该第一实体程序化单元之中的该最后一个实体程序化单元之后,其中该第一标记指示该至少一第二实体程序化单元存储该奇偶信息; 其中该存储器管理电路还用以将第二标记程序化至该些实体程序化单元之中的至少一第三实体程序化单元的冗余比特区,其中该至少一第三实体程序化单元是排列在该至少一第二实体程序化单元之后,并且该第二标记指示该至少一第二实体程序化单元存储该奇偶信息。 13. The memory of claim 11 or 12, the control circuit unit as claimed in claim, wherein the at least one marker to the redundant programmed first entity among the plurality of operation programs than the SAR unit, the memory management the first marker circuit programmed to last a redundant entity programmed cell among the first physical unit than the SAR program, wherein the at least one programming unit is a second physical arrangement of the first entity in programmed unit after the last entity in the program unit, wherein the first flag indicates that the at least one second entity of the programming unit stores parity information; wherein the memory management circuitry further programmed for converting the second mark to the plurality of entities at least a third program redundancy unit among entities than the SAR program unit, wherein the at least one third entity is a programming unit arranged after the at least one second entity programming unit, and the second flag indicating the second entity a programming unit that stores at least the parity information.
  14. 14.一种存储器存储装置,其特征在于,包括: 连接接口单元,用以耦接至主机系统; 可复写式非易失性存储器模块,包括多个实体抹除单元,且每一该些实体抹除单元包括多个实体程序化单元,其中每一该些实体程序化单元包括数据比特区与冗余比特区;以及存储器控制电路单元,耦接至该连接接口单元与该可复写式非易失性存储器模块; 其中该存储器控制电路单元用以依据第一数据产生奇偶信息; 其中该存储器控制电路单元还用以将该第一数据程序化至该些实体程序化单元之中的第一实体程序化单元中; 其中该存储器控制电路单元还用以将该奇偶信息程序化至该些实体程序化单元之中的至少一第二实体程序化单元中,其中该至少一第二实体程序化单元是排列在该第一实体程序化单元之后; 其中在上述将该第一数据程序化至该些实体程序化单元 14. A memory storage device comprising: a connection interface unit to be coupled to the host system; rewritable non-volatile memory module comprising a plurality of physical erase unit, and each of the entity erasing means comprises a plurality of solid unit programs, wherein each of the programming unit comprises a data entity than the SAR and SAR redundancy ratio; and a memory control circuit means, coupled to the interface unit is connected to the non-volatile rewritable a volatile memory module; wherein the memory control circuit means for generating parity information based on a first data; wherein the memory control circuit unit further programmed for converting the first data to the first entity among the plurality of entity programmed unit programming unit; at least one second physical cell wherein programming the memory control circuit unit is further configured to programming the parity information among the plurality of entities programming unit, wherein the at least one second entity programming unit is arranged after the first physical programming unit; wherein the above-mentioned first data to the plurality of entity programmed means programmed 之中的该第一实体程序化单元的操作中,该存储器控制电路单元将至少一标记程序化至该第一实体程序化单元之中的冗余比特区,其中该至少一标记指示该奇偶信息被程序化至该至少一第二实体程序化单元中。 Procedure unit among the first entity, the memory control circuit unit to the at least one marker programmed into the first redundancy unit than the SAR program entity, wherein the at least one marker indicating that the parity information It is programmed to the at least one second entity programming unit.
  15. 15.根据权利要求14所述的存储器存储装置,其特征在于,每一该第一数据包括使用者数据与对应该使用者数据的管理信息; 其中该使用者数据被程序化至该第一实体程序化单元之中的数据比特区,其中对应该使用者数据的该管理信息被程序化至该些第一实体程序化单元之中的冗余比特区。 15. The memory storage device according to claim 14, wherein each of the first data comprises user data and management information corresponding to the user data; wherein the user data is programmed to the first entity among the program data than the SAR unit, wherein the management information for user data should be programmed to the first entity among the plurality of redundancy programming unit than the SAR.
  16. 16.根据权利要求14所述的存储器存储装置,其特征在于,该第一数据包括使用者数据、对应该使用者数据的管理信息以及对应该使用者数据的错误检查与校正码; 其中该错误检查与校正码是根据该使用者数据所产生的; 其中该使用者数据被程序化至该第一实体程序化单元之中的数据比特区,其中对应该使用者数据的该管理信息被程序化至该第一实体程序化单元之中的冗余比特区,其中对应该使用者数据的该错误检查与校正码被程序化至该第一实体程序化单元之中的冗余比特区。 16. The memory storage device according to claim 14, wherein the first data comprises user data, the management information corresponding to the user data and user data to be error checking and correcting code; wherein the error checking and correction codes are generated based on the user data; wherein the user data is programmed to the data programmed into the first entity than the SAR unit, wherein the management information for the user should the data to be programmed redundant to the first entity in the program than the SAR unit, in which the error checking and correction should code the user data is programmed into the redundancy among the first physical unit than the SAR program.
  17. 17.根据权利要求15或16所述的存储器存储装置,其特征在于,将该至少一标记程序化至该些第一实体程序化单元之中的冗余比特区的操作中,该存储器控制电路单元将第一标记程序化至该第一实体程序化单元之中的最后一个实体程序化单元的冗余比特区,其中该至少一第二实体程序化单元是排列在该第一实体程序化单元之中的该最后一个实体程序化单元之后,其中该第一标记指示该至少一第二实体程序化单元存储该奇偶信息; 其中该存储器控制电路单元还用以将第二标记程序化至该些实体程序化单元之中的至少一第三实体程序化单元的冗余比特区,其中该至少一第三实体程序化单元是排列在该至少一第二实体程序化单元之后,其中该第二标记指示该至少一第二实体程序化单元存储该奇偶信息。 17. The memory storage device of claim 15 or claim 16, wherein the at least one marker to the programmed redundant entity among the plurality of first program unit than the SAR operation, the memory control circuit a first unit programmed to mark the last entity programmed redundancy unit within the first program entity than the SAR unit, wherein the at least one programming unit is a second physical arrangement of the first entity in programmed unit after the last entity in the program unit, wherein the first flag indicates that the at least one second entity of the programming unit stores parity information; wherein the memory control circuit for converting the second unit is further programmed to the plurality of mark at least one redundant unit third program entity among entities than the SAR program unit, wherein the at least one third entity is a programming unit arranged after the at least one second entity programming unit, wherein the second marker indicating that a second entity of at least the programming unit stores parity information.
  18. 18.根据权利要求17所述的存储器存储装置,其特征在于,将该至少一标记程序化至该第一实体程序化单元之中的冗余比特区的操作中,该存储器控制电路单元建立奇偶信息地址对应表并且将第三标记记录在该奇偶信息地址对应表,其中该第三标记指示该至少一第二实体程序化单元存储该奇偶信息。 18. The memory storage device according to claim 17, wherein the at least one marker to the redundant programmed into the programming unit than the first physical operation of the SAR, the memory control circuit unit to establish a parity address correspondence table information and the third information mark recorded in the parity address correspondence table, wherein the third flag indicates that the second entity a programming unit to store at least the parity information.
  19. 19.根据权利要求14所述的存储器存储装置,其特征在于,将该至少一标记程序化至该些第一实体程序化单元之中的冗余比特区的操作中,该存储器控制电路单元计数该第一实体程序化单元的个数,并且根据该第一实体程序化单元的个数,在每一该第一实体程序化单元的冗余比特区中记录一标记值,其中记录在该第一实体程序化单元中的该标记值依据该第一实体程序化单元的排列依序地递减。 19. The memory storage device according to claim 14, wherein the at least one marker to the programmed redundant entity among the plurality of first program unit than the SAR operation, the memory control circuit unit counts the number of the first unit program entity, and the program according to the number of the first physical unit, each of the redundancy in the programming unit records a first entity tag values ​​than in the SAR, which is recorded in the second the value of an entity tag programming unit arranged sequentially decrement the program unit according to the first entity.
  20. 20.根据权利要求19所述的存储器存储装置,其特征在于,该标记值之中的第一标记值为1,且该第一标记值被记录在该第一实体程序化单元之中的最后一个实体程序化单元的冗余比特区中,且该至少一第二实体程序化单元是排列在该第一实体程序化单元之中的该最后一个实体程序化单元之后; 其中该标记值之中的第二标记值为2,且该第二标记值被记录在该些第一实体程序化单元之中相邻且排列在该最后一个实体程序化单元之前的实体程序化单元的冗余比特区中; 其中该些标记值之中的第三标记值为3,且该第三标记值被记录在该些第一实体程序化单元之中相邻且排列在记录该第二标记值的实体程序化单元之前的实体程序化单元的冗余比特区中。 20. The memory storage device according to claim 19, wherein the first marker in the flag value is 1, and the first flag value is recorded in the first physical unit of the last program a redundancy entity than the SAR program unit, and the at least one second entity of the programming unit is the last entity in programmed cells arranged the first entity after the programming unit; wherein the value tag among 2 is a second marker, and the second flag value is recorded in the plurality of first entity and a program unit are arranged adjacent to the redundant entity prior to the last programming unit programming entities than the SAR unit ; wherein the third mark from among the plurality of tag value is 3, and the third flag value is recorded in the plurality of first entity and a program unit are arranged adjacent to the second entity program recording flag value redundant before the unit solid than the programming unit in the SAR.
  21. 21.根据权利要求14所述的存储器存储装置,其特征在于,该第一数据包括第二数据以及错误检查与校正码,其中当无法通过使用该错误检查与校正码来校正该第二数据时,该存储器控制电路单元还用以根据该至少一标记获得记录该奇偶信息的该至少一第二实体程序化单元的地址,从该至少一第二实体程序化单元中读取该奇偶信息以及依据所读取的该奇偶信息来校正该第二数据。 21. The memory storage device according to claim 14, wherein the data comprises first data and second error checking and correcting code, wherein when the second data can not be corrected by using the error checking and correction code the memory control circuit unit is further configured to program the address of at least a second unit of the at least one entity obtaining the recording mark in accordance with the parity information, reads the parity information from the at least one programming unit and a second entity based on the parity information to correct the read second data.
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