CN105301859B - array substrate and liquid crystal display device - Google Patents
array substrate and liquid crystal display device Download PDFInfo
- Publication number
- CN105301859B CN105301859B CN201510830325.7A CN201510830325A CN105301859B CN 105301859 B CN105301859 B CN 105301859B CN 201510830325 A CN201510830325 A CN 201510830325A CN 105301859 B CN105301859 B CN 105301859B
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- array substrate
- cabling
- signal input
- switch element
- driving circuit
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Classifications
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
Abstract
The present invention provides a kind of array substrate, the array substrate includes gate driving circuit, source electrode drive circuit, a plurality of signal input cabling and multi-strip scanning line and multiple data lines, the a plurality of signal input cabling is respectively connected to multiple signal input parts of the gate driving circuit, which is respectively connected to multiple output ends of the gate driving circuit.The array substrate further includes a common bus and multiple switch element, the common bus is separately connected a plurality of signal by multiple switch element and inputs cabling, wherein, each bars input cabling connects the common bus by the corresponding switch element in multiple switch element.The array substrate can solve the problems, such as to be easy to happen " splashette " when existing liquid crystal display device is turned back on because of abnormal shutdown.The present invention also provides a kind of liquid crystal display devices of the application array substrate.
Description
Technical field
The present invention relates to LCD technology, more particularly to the liquid crystal display of a kind of array substrate and the application array substrate
Device.
Background technology
Liquid crystal display device has many advantages, such as frivolous, energy saving, radiationless, therefore is widely used in high-definition digital
In the electronic equipments such as TV, computer, personal digital assistant (PDA), mobile phone, digital camera.
Liquid crystal display device generally includes color membrane substrates, array substrate and is arranged between color membrane substrates and array substrate
Liquid crystal layer.Wherein, a plurality of scan line being mutually parallel and a plurality of data line being mutually parallel are provided in array substrate, this is a plurality of
Scan line and multiple data lines mutually insulated intersect to define multiple pixel units, and each pixel unit includes one and is arranged in battle array
Switch element on row substrate.The multi-strip scanning line is connected to gate driving circuit, which is connected to source electrode
Driving circuit, when liquid crystal display device is normally shown, which is used to successively provide for the multi-strip scanning line and sweep
Signal is retouched to open the switch element being connect with every scan line, and the source electrode drive circuit is used to be scanned in every scan line
When, the pixel electrode by the switch element of the multiple data lines and opening for corresponding pixel unit provides pixel voltage.It should
Pressure difference between common voltage on the public electrode of pixel voltage and pixel unit forms electric field, the electric field driven liquid crystal layer
Liquid crystal layer rotation is to control the light quantity for penetrating liquid crystal layer, to realize the display of liquid crystal display device.
However, existing liquid crystal display device carry out test or during normal use, if there is abnormal power-down,
Such as power remove, battery plate fall off the situation of abnormal shutdown, due to showing last before also remaining with shutdown in pixel unit
Charge left by width picture, having not enough time to release, then when being switched on, remaining charge can be to pixel unit weight in pixel unit
New charging has an impact, and makes pixel unit that cannot reach required voltage within a certain period of time, to which scintillation occur, i.e. institute
" splashette " of meaning.
Invention content
The purpose of the present invention is to provide the liquid crystal display devices of a kind of array substrate and the application array substrate, to solve
The problem of " splashette " is easy to happen when liquid crystal display device is turned back on because of abnormal shutdown in the prior art.
The embodiment of the present invention provides a kind of array substrate, the array substrate include gate driving circuit, source electrode drive circuit,
A plurality of signal input cabling and multi-strip scanning line and multiple data lines, a plurality of signal input cabling are respectively connected to the grid
Multiple signal input parts of driving circuit, the multi-strip scanning line are respectively connected to multiple output ends of the gate driving circuit,.It should
Array substrate further includes a common bus and multiple switch element, which is separately connected by multiple switch element
The a plurality of signal inputs cabling, wherein each bars input cabling is opened by corresponding one in multiple switch element
It closes element and connects the common bus.
Further, each switch element includes control terminal, the first path terminal and alternate path end, the control terminal and this
One path terminal is all connected with the common bus, which connects a corresponding bars and input cabling.
Further, multiple switch element is thin film transistor (TFT).
Further, multiple switch element be arranged in the array substrate positioned at the region of non-display area, it is multiple
Switch element is formed with the multiple switch element positioned at viewing area in the array substrate in same processing procedure.
Further, which is integrated among the array substrate.
Further, which includes clock signal input cabling, scan start signal input cabling
And grid low-voltage signal inputs cabling.
Further, which is a plurality of, when respectively including the first clock signal input cabling, second
Clock signal inputs cabling, third clock signal input cabling and the 4th clock signal input cabling.
Further, scan start signal input cabling is a plurality of, respectively includes the input of the first scan start signal and walks
Line, the second scan start signal input cabling, third scan start signal input cabling and the input of the 4th scan start signal
Cabling.
The embodiment of the present invention also provides a kind of liquid crystal display device, which includes above-mentioned array substrate,
When the liquid crystal display device is switched on and before normal display, which receives a high level signal so that a plurality of signal
Input cabling by the high level signal be supplied to the gate driving circuit with and meanwhile scan the multi-strip scanning line, the liquid crystal display
Device provides black plug picture when the multi-strip scanning line is scanned；When the liquid crystal display device is normally shown, the common bus
A low level signal is received so that multiple switch element is off.
Further, the time which scans the multi-strip scanning line simultaneously is 0.1 second.
Common bus is provided in the array substrate provided by the embodiment of the present invention, which is opened by multiple
Element is closed connect with a plurality of signal input cabling respectively, test carrying out when the liquid crystal display device of the application array substrate or
When person occurs abnormal power-down during normal use and causes to be switched on again after abnormal shutdown, it can be carried by the common bus
Made inside pixel unit with scanning multi-strip scanning line, while inserting black picture simultaneously to gate driving circuit for high level signal
Remaining charge discharges in time, to prevent the generation of " splashette ".
Description of the drawings
A kind of electrical block diagram for array substrate that Fig. 1 is provided by one embodiment of the invention.
Fig. 2 is that a plurality of signal of array substrate shown in FIG. 1 inputs the various input signals of cabling in an example
Input schematic diagram.
Fig. 3 is the structural schematic diagram of the gate driving circuit of array substrate shown in FIG. 1.
Fig. 4 is that the circuit structure of a shifting deposit unit of gate driving circuit shown in Fig. 3 in an example shows
It is intended to.
Specific implementation mode
It is of the invention to reach the technological means and effect that predetermined goal of the invention is taken further to illustrate, below in conjunction with
Attached drawing and preferred embodiment, to propose according to the present invention array substrate and liquid crystal display device its specific implementation mode, method,
Step, structure, feature and effect are described in detail as after.
For the present invention aforementioned and other technology contents, feature and effect, in following cooperation with reference to the preferable reality of schema
Applying in the detailed description of example to be clearly presented.It is predetermined when that can reach to the present invention by the explanation of specific implementation mode
The technological means and effect that purpose is taken be able to more deeply and it is specific understand, however institute's accompanying drawings be only to provide with reference to
Purposes of discussion is not intended to limit the present invention.
Referring to FIG. 1, a kind of electrical block diagram for array substrate that Fig. 1 is provided by one embodiment of the invention.
As shown in Figure 1, the array substrate 10 includes gate driving circuit 11, source electrode drive circuit 18, a plurality of signal input cabling 12, more
Bar scan line 13,14, common bus 15 of multiple data lines and multiple switch element 16.Wherein, the multi-strip scanning line 13
Arranged in parallel, the multiple data lines 14 are arranged in parallel and intersect with the multi-strip scanning line 13 insulation, and this plurality of is swept
It retouches line 13 to intersect with the multiple data lines 14 to define multiple pixel units 17, each pixel unit 17 includes being arranged in the array
The switch element 170 of infall on substrate 10, positioned at corresponding scan line 13 and respective data lines 14.The multiple data lines 14
It is connected to a source electrode drive circuit 18.
Preferably, which is integrated among the array substrate 10.The gate driving circuit 11, source electrode drive
Dynamic circuit 18, a plurality of signal input cabling 12, the common bus 15 and multiple switch unit 16 are arranged at the array
On substrate 10 positioned at the region of non-display area, it is preferable that multiple switch unit 16 is thin film transistor (TFT).Wherein, this is more
A switch unit 16 can be with the multiple switch element 170 of multiple pixel unit 17 positioned at viewing area in the array substrate 10
It is formed in same processing procedure.
The a plurality of signal input cabling 12 is respectively connected to multiple signal input parts 111 of the gate driving circuit 11, should
Multi-strip scanning line 13 is respectively connected to multiple output ends 112 of the gate driving circuit 11, and the common bus 15 is by multiple
Switch element 16 is separately connected a plurality of signal input cabling 12, and each bars input cabling 12 is switched by corresponding one
Element 16 connects the common bus 15.Wherein, each switch unit 16 (is not marked including control terminal (not indicating), the first path terminal
Show) and alternate path end (not indicating), the control terminal and first path terminal be all connected with the common bus 15, the alternate path end
Connect corresponding bars input cabling 12.
The a plurality of signal input cabling 12 includes clock signal input cabling, scan start signal input cabling and grid
Low voltage signal inputs cabling etc..Please also refer to Fig. 2, Fig. 2 is that a plurality of signal inputs in an example each of cabling 12
The input schematic diagram of kind input signal.As shown in Fig. 2, in this example, which is a plurality of, is respectively included
First clock signal input cabling, second clock signal input cabling, third clock signal input cabling and the 4th clock letter
Number input cabling, the first clock signal input cabling is for receiving and providing the first clock signal for the gate driving circuit 11
CLK1, second clock signal input cabling are used to receive and provide second clock signal CLK2 for the gate driving circuit 11,
The third clock signal input cabling is for receiving and providing third clock signal clk 3 for the gate driving circuit 11, and the 4th
Clock signal input cabling is for receiving and providing the 4th clock signal clk 4 for the gate driving circuit 11.In this example,
It is a plurality of that the scan start signal, which inputs cabling also, respectively includes the first scan start signal input cabling, the second sweep start
Signal inputs cabling, third scan start signal input cabling and the 4th scan start signal and inputs cabling, first scanning
For receiving and providing the first scan start signal STV1 for the gate driving circuit 11, this second sweeps enabling signal input cabling
Enabling signal input cabling is retouched for receiving and providing the second scan start signal STV2, the third for the gate driving circuit 11
Scan start signal input cabling is for receiving and providing third scan start signal STV3 for the gate driving circuit 11, this
Four scan start signals input cabling is for receiving and providing the 4th scan start signal STV4 for the gate driving circuit 11.This
Outside, grid low-voltage signal input cabling is for receiving and providing grid low-voltage signal VGL for the gate driving circuit 11.
Referring to FIG. 3, Fig. 3 is the structural schematic diagram of the gate driving circuit 11.As shown in figure 3, the gate driving circuit
11 include multiple shifting deposit unit R1, R2 ..., Rm, in an example, m is natural number, and m≤9.Each displacement is posted
Memory cell connects a corresponding scan line 13 via an output end 112.When the gate driving circuit 11 is for normally showing,
When the gate driving circuit 11 receives the first clock signal clk 1, second clock signal CLK2, third clock signal clk the 3, the 4th
Clock signal CLK4, the first scan start signal STV1, the second scan start signal STV2, third scan start signal STV3,
Four scan start signal STV4 and grid low-voltage signal VGL, and pass sequentially through multiple shifting deposit unit R1,
R2 ..., Rm be the multi-strip scanning line 13 scanning signal is provided one by one.
Please also refer to Fig. 4, Fig. 4 be a shifting deposit unit Rn of the gate driving circuit 11 in an example
Electrical block diagram.Referring to FIG. 4, in this example, shifting deposit unit Rn includes precharge section, bootstrapping pull-up portion
Divide, drop-down part and low level maintain part.Wherein, precharge section includes the first transistor T1, pull portion packet in bootstrapping
Second transistor T2 is included, pull-down section point includes third transistor T3 and the 4th transistor T4, and it includes the 5th that low level, which maintains part,
Transistor T5 to the 7th transistor T7, the first capacitance C1 and the second capacitance C2.The grid of the first transistor T1, which receives, comes from the shifting
The output voltage Gn-4 of fourth stage shifting deposit unit Rn-4 before the deposit unit Rn of position, source electrode receive the first clock signal
CLK1, drain electrode connecting node Q；The grid connecting node Q of second transistor T2, source electrode receive second clock signal CLK2, drain electrode
Output end vo as shifting deposit unit Rn is for exporting scanning signal；The grid of third transistor T3, which receives, comes from the shifting
The output voltage Gn+4 of fourth stage shifting deposit unit Rn+4 after the deposit unit Rn of position, source electrode receive third clock signal
CLK3, drain electrode connecting node Q；The grid of 4th transistor T4 receives the 4th clock signal clk 4, and source electrode connects low-voltage end Vl
For the extremely low voltage signal VGL of receiving grid, drain electrode connection output end vo；The grid of 5th transistor T5 and the 6th transistor T6's
The connection of the grid of drain electrode and the 7th transistor T7, source electrode connect output end vo, drain electrode connecting node Q；6th transistor T6's
Grid connects output end vo, and source electrode connects low-voltage end Vl；The source electrode of 7th transistor T7 connects low-voltage end Vl, drain electrode connection
Output end vo；First capacitance C1 is connected between the grid and output end vo of second transistor T2；Second capacitance C2 is connected to
Between the source electrode of two-transistor T2 and the grid of the 5th transistor T5.The output end vo is exporting scanning signal to corresponding scanning
When line 13, output voltage is high level, and low level is then kept at other moment.
The embodiment of the present invention also provides a kind of liquid crystal display device, which includes above-mentioned array substrate 10.
Fig. 1 and Fig. 2 are refer again to, when the liquid crystal display device is switched on and before normal display, it is high which receives one
Level signal STV5 opens all switch units 16, so that a plurality of signal input cabling 12 should by switch unit 16
High level signal STV5 be supplied to the gate driving circuit 11 with and meanwhile scan the multi-strip scanning line 13, it is preferable that the grid drive
The time that dynamic circuit 11 scans the multi-strip scanning line simultaneously is 0.1 second, and the liquid crystal display device passes through source electrode drive circuit at this time
18 provide the black corresponding pixel voltage signal of picture, to provide black plug picture when the multi-strip scanning line is scanned；And in the liquid
When crystal device is normally shown, which receives a low level signal so that multiple switch unit 16 is in disconnection
State, the gate driving circuit 11 via a plurality of signal input cabling 12 receive various clock signals, scan start signal with
And grid low-voltage signal etc..
Due to being provided with common bus 15 in the array substrate 11, which is distinguished by multiple switch element 16
It is connect with a plurality of signal input cabling 12, when the liquid crystal display device using the array substrate 11 test or just
When occurring abnormal power-down during being often used causes to be switched on again after abnormal shutdown, height can be provided by the common bus 15
Level signal STV5, to scan the multi-strip scanning line 13, while inserting black picture simultaneously, makes pixel to the gate driving circuit 11
The charge of 17 internal residual of unit discharges in time, to prevent the generation of " splashette ".
It the above is only presently preferred embodiments of the present invention, be not intended to limit the present invention in any form, although this
Invention is disclosed above with preferred embodiment, and however, it is not intended to limit the invention, any person skilled in the art,
It does not depart within the scope of technical solution of the present invention, when the technology contents using the disclosure above make a little change or are modified to equivalent
The equivalent embodiment of variation, as long as being without departing from technical solution of the present invention content, according to the technical essence of the invention to above real
Any simple modification, equivalent change and modification made by example are applied, in the range of still falling within technical solution of the present invention.
Claims (9)
1. a kind of array substrate, the array substrate include gate driving circuit, source electrode drive circuit, a plurality of signal input cabling and
Multi-strip scanning line and multiple data lines, a plurality of signal input cabling are respectively connected to multiple signals of the gate driving circuit
Input terminal, the multi-strip scanning line are respectively connected to multiple output ends of the gate driving circuit, which is characterized in that the array substrate
Further include a common bus and multiple switch element, which is separately connected a plurality of letter by multiple switch element
Number input cabling, wherein each bars input cabling passes through the corresponding switch element in multiple switch element and connects
Connect the common bus, a plurality of signal input cabling include clock signal input cabling, scan start signal input cabling and
Grid low-voltage signal inputs cabling.
2. array substrate as described in claim 1, which is characterized in that each switch element includes control terminal, the first path terminal
With alternate path end, the control terminal and first path terminal are all connected with the common bus, alternate path end connection corresponding one
Bars inputs cabling.
3. array substrate as described in claim 1, which is characterized in that multiple switch element is thin film transistor (TFT).
4. array substrate as claimed in claim 3, which is characterized in that multiple switch element is arranged in the array substrate
Positioned at the region of non-display area, multiple switch element is with the multiple switch element positioned at viewing area in the array substrate same
It is formed in one processing procedure.
5. array substrate as described in claim 1, which is characterized in that the gate driving circuit be integrated in the array substrate it
In.
6. array substrate as described in claim 1, which is characterized in that the clock signal input cabling is a plurality of, is respectively included
First clock signal input cabling, second clock signal input cabling, third clock signal input cabling and the 4th clock letter
Number input cabling.
7. array substrate as claimed in claim 6, which is characterized in that it is a plurality of, difference that the scan start signal, which inputs cabling,
It is walked including the first scan start signal input cabling, the second scan start signal input cabling, the input of third scan start signal
Line and the 4th scan start signal input cabling.
8. a kind of liquid crystal display device, which is characterized in that the liquid crystal display device includes such as any one of claim 1 to 7
The array substrate, when the liquid crystal display device is switched on and before normal display, which receives a high level
Signal so that a plurality of signal input cabling by the high level signal be supplied to the gate driving circuit with and meanwhile to scan this more
Scan line, the liquid crystal display device provide black plug picture when the multi-strip scanning line is scanned；The liquid crystal display device just
Often when display, which receives a low level signal so that multiple switch element is off.
9. liquid crystal display device as claimed in claim 8, which is characterized in that the gate driving circuit scans this simultaneously a plurality of to be swept
The time for retouching line is 0.1 second.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510830325.7A CN105301859B (en) | 2015-11-25 | 2015-11-25 | array substrate and liquid crystal display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510830325.7A CN105301859B (en) | 2015-11-25 | 2015-11-25 | array substrate and liquid crystal display device |
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| Publication Number | Publication Date |
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| CN105301859A CN105301859A (en) | 2016-02-03 |
| CN105301859B true CN105301859B (en) | 2018-09-18 |
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| CN201510830325.7A Active CN105301859B (en) | 2015-11-25 | 2015-11-25 | array substrate and liquid crystal display device |
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107886890A (en) * | 2017-12-28 | 2018-04-06 | 维沃移动通信有限公司 | Display panel circuit, the control method of display panel circuit and mobile terminal |
| CN108281118A (en) * | 2018-01-09 | 2018-07-13 | 昆山龙腾光电有限公司 | Display panel and liquid crystal display device |
| CN111402754A (en) * | 2020-05-20 | 2020-07-10 | 上海天马有机发光显示技术有限公司 | Display panel and display device |
| CN115240583A (en) * | 2022-09-23 | 2022-10-25 | 广州华星光电半导体显示技术有限公司 | Residual charge releasing circuit and display panel |
| CN115731896B (en) * | 2022-11-29 | 2023-11-17 | 惠科股份有限公司 | Control method of driving circuit, driving circuit and display device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101211036A (en) * | 2006-12-29 | 2008-07-02 | 群康科技(深圳)有限公司 | LCD device and its display method |
| CN101882430A (en) * | 2010-07-02 | 2010-11-10 | 深超光电（深圳）有限公司 | Method for driving liquid crystal display device |
| WO2013183531A1 (en) * | 2012-06-05 | 2013-12-12 | シャープ株式会社 | Display device and method for driving same |
| CN104616615A (en) * | 2015-02-10 | 2015-05-13 | 昆山龙腾光电有限公司 | Screen clearing circuit and display device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100796298B1 (en) * | 2002-08-30 | 2008-01-21 | 삼성전자주식회사 | Liquid crystal display |
-
2015
- 2015-11-25 CN CN201510830325.7A patent/CN105301859B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101211036A (en) * | 2006-12-29 | 2008-07-02 | 群康科技(深圳)有限公司 | LCD device and its display method |
| CN101882430A (en) * | 2010-07-02 | 2010-11-10 | 深超光电（深圳）有限公司 | Method for driving liquid crystal display device |
| WO2013183531A1 (en) * | 2012-06-05 | 2013-12-12 | シャープ株式会社 | Display device and method for driving same |
| CN104616615A (en) * | 2015-02-10 | 2015-05-13 | 昆山龙腾光电有限公司 | Screen clearing circuit and display device |
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Address after: 215301, 1, Longteng Road, Kunshan, Jiangsu, Suzhou Patentee after: Kunshan Longteng Au Optronics Co Address before: 215301, 1, Longteng Road, Kunshan, Jiangsu, Suzhou Patentee before: Kunshan Longteng Optronics Co., Ltd. |