CN105280574B - Embedded device package structure and a manufacturing method - Google Patents

Embedded device package structure and a manufacturing method Download PDF

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Publication number
CN105280574B
CN105280574B CN201410337955.6A CN201410337955A CN105280574B CN 105280574 B CN105280574 B CN 105280574B CN 201410337955 A CN201410337955 A CN 201410337955A CN 105280574 B CN105280574 B CN 105280574B
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dielectric layer
die
layer
package structure
carrier
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CN201410337955.6A
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Chinese (zh)
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CN105280574A (en
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李志成
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日月光半导体制造股份有限公司
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73267Layer and HDI connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect

Abstract

本发明涉及种元件嵌入式封装结构及其制造方法。 The present invention relates to an embedded device package structure and a manufacturing method thereof. 所述元件嵌入式封装结构包含:载体,所述载体具有上表面及相对于所述上表面的下表面;粘着层,其设置于所述载体的上表面上;至少个裸片,其通过所述粘着层附着于所述载体上,所述至少个裸片具有至少个接垫;第电介质层,其通过所述粘着层附着于所述载体上,所述第电介质层具有容纳所述至少个裸片的开口;以及第二电介质层,其设置在所述第电介质层上,其中至少部分所述第二电介质层填入所述开口且围绕所述至少个裸片,所述第二电介质层具有至少个开口,其露出所述至少个裸片的所述接垫。 The embedded device package structure comprising: a carrier having an upper surface and a lower surface with respect to said upper surface; adhesive layer disposed on the upper surface of the carrier; and at least one die, by the said adhesive layer adhered to said support, said at least one die having at least one pad; first dielectric layer by the adhesive layer adhered to said support, said first dielectric layer having at least one receiving opening the die; and a second dielectric layer disposed on the first dielectric layer, wherein at least a portion of said second dielectric layer and filling the opening at least around the dies, the second dielectric layer having at least one opening, which is exposed to the at least one die pad.

Description

元件嵌入式封装结构及其制造方法 Embedded device package structure and a manufacturing method

技术领域 FIELD

[0001]本发明涉及一种半导体封装及其制造方法。 [0001] The present invention relates to a semiconductor package and a manufacturing method.

背景技术 Background technique

[0002] 因应电子产品小尺寸及性能的需求,电子产品的关键组件,即半导体元件的设计渐趋复杂且被要求更加微型化。 [0002] In response to the demand for electronic products of small size and performance, critical components of electronic products, namely the design of the semiconductor device is required to become more complex and more miniaturized. 一般来说,半导体元件先经过封装,再安装于含有电路的衬底上但,如此一来,衬底上的空间便有部分为半导体封装件所占据。 In general, the first semiconductor element encapsulated, and then mounted on the substrate containing circuit but, this way, the space on the substrate there is a portion occupied by the semiconductor package. 此外,半导体封装、衬底制造及组装如果分开进行,可能会产生额外成本。 In addition, the semiconductor package substrate to manufacture and assemble, if carried out separately, may result in additional costs. 因此,在此背景之下,便有元件嵌入式封装结构的相关研宄提出,希望简化及合并半导体封装、衬底制造及组装等工艺,且期望进一步缩减电子产品的尺寸。 Thus, in this context, there correlation study based embedded package structure element proposed that simplify and combined semiconductor package substrate fabrication and assembly processes, and it is desirable to further reduce the size of electronic products. 目前一般常见的制造元件嵌入式封装结构的方法,可包含下列步骤:提供载体;设置裸片于所述载体上;施加B-stage的树脂或预浸材于所述载体上以包覆所述裸片;以及加热固化所述树脂或预浸材材料。 The general method for manufacturing a component-embedded common package structure, may comprise the steps of: providing a carrier; die disposed on the carrier; applying a B-stage resin or to the prepreg to cover the carrier die; and heat-curing the resin or the prepreg material. 然而,此加热固化的过程容易产生形变,导致良率下降。 However, such heat curing process prone to deformation, resulting in decreased yield. 此外,因树脂材料、裸片及载体的热膨胀系数不同,此加热固化的过程易造成衬底翘曲的问题。 Further, because the resin material, different thermal expansion coefficients of the die and the carrier, this heat curing process could easily lead to warping of the substrate in question. 有鉴于此,目前针对制造元件嵌入式封装结构的方法仍有改进的空间。 Therefore, there is a method for manufacturing a component-embedded package structure is still room for improvement.

发明内容 SUMMARY

[0003] 本发明的实施例涉及一种元件嵌入式封装结构,其包含:载体,所述载体具有上表面;粘着层,设置于所述载体的上表面上;至少一个裸片,通过所述粘着层附着于所述载体上,所述裸片具有至少一个接垫;第一电介质层,通过所述粘着层附着于所述载体上,所述电介质层具有容纳所述至少一个裸片的开口;以及第二电介质层,设置于所述第一电介质层上,其中至少部分的所述第二电介质层填入所述开口及围绕围绕所述至少一个裸片,所述第二电介质层具有至少一个开口,露出所述至少一个裸片的所述接垫。 [0003] Embodiments of the present invention relates to an embedded device package structure, comprising: a carrier having an upper surface; adhesive layer disposed on the upper surface of the support; the at least one die, by the an adhesive layer attached to said support, said die having at least one pad; a first dielectric layer, through the adhesive layer adhered to said support, said dielectric layer having at least one die receiving opening ; and a second dielectric layer disposed on the first dielectric layer, wherein the second dielectric layer at least partially filling the opening and the surrounding around the at least one die, the second dielectric layer has at least an opening exposing at least one of the die pad.

[0004] 本发明的另一实施例涉及一种制造元件嵌入式封装结构的方法,其包含:提供载体,所述载体具有上表面;设置粘着层于所述载体的上表面上;提供至少一个裸片,所述至少一个裸片通过所述粘着层附着于所述载体上;提供第一电介质层,所述第一电介质层通过所述粘着层附着于所述载体上,所述第一电介质层具有容纳所述至少一个裸片的开口; 以及设置第二电介质层于所述第一电介质层上,其中至少部分的所述第二电介质层填入所述开口及围绕所述至少一个裸片。 Another [0004] embodiment of the present invention is directed to a method of manufacturing a component-embedded package structure, comprising: providing a carrier having an upper surface; adhesive layer disposed on the upper surface of said carrier; providing at least one die, the die by said at least one adhesive layer attached to the carrier; providing a first dielectric layer, the dielectric layer through the first adhesive layer adhered to said support, said first dielectric receiving layer having at least one die opening; and a second dielectric layer disposed on the first dielectric layer, wherein at least part of the second dielectric layer filling the opening and around the at least one die .

附图说明 BRIEF DESCRIPTION

[0005] 图1展示本发明元件嵌入式封装结构的实施例的剖面图。 [0005] FIG. 1 shows a cross-sectional view of an embodiment of an embedded device package structure of the present invention.

[0006] 图2展示展示形成本发明元件嵌入式封装结构的第一电介质层后的实施例的俯视图。 [0006] FIG. 2 shows a plan view showing an embodiment of forming the first dielectric layer element embedded package structure of the present invention.

[0007] 图3展示展示形成本发明元件嵌入式封装结构的第一电介质层后的实施例的俯视图。 [0007] FIG. 3 shows a plan view showing an embodiment of forming the first dielectric layer element embedded package structure of the present invention.

[0_图5展兀一实酬的剖酬。 [0_ Wu FIG 5 show a cross-sectional real reward paid.

[0_图6,焚月^的另一实酬的剖酬。 [0_ 6, a cross-sectional burning pay another month ^ real remunerated. ==展S发明元件“式讎构咅S。 == invention show element S "type configuration Chou S. Pou

[0013]图9展示本发明元件嵌入式封装_4]图1Q展示本发明元件嵌人式封装结_5]图11展示本发明元件嵌人式雛纟自_力1肺_湎图。 [0013] FIG. 9 shows an embedded element of the present invention, the package 4] FIG 1Q embedded element of the present invention shows a package for formula _5] FIG. 11 shows the present invention child element embedded type Si from lung _ 1 _ force drunk FIG. _6]图12展示本发明元件嵌入式封装结构的另—实施例的顺图。 6] FIG. 12 shows another device package structure of the present invention is embedded - cis embodiment of FIG. ⑺ _7] ^13A至復展示本发明元件嵌入式封装结构的制造方法的实施例的示細。 ⑺ _7] ^ 13A to the multiplexing method of manufacturing display element embedded package structure of the present invention is shown an embodiment of the fine. _8]图14展示本发明元件嵌入式封装结构的第一电介质层开口设计的实施例的示意图。 _8] FIG. 14 shows a schematic view of an embodiment of the present invention, a first dielectric layer embedded device package structure of open design.

[0019]图15展示本发明元件嵌入式封装结构的第一电介质层开口设计的另一实施例的示意图。 A schematic view of another embodiment [0019] FIG 15 shows a first dielectric layer element embedded package structure of the embodiment of the present invention open design.

具体实施方式、、 Detailed ways,,

[0020]请参考图1,其展示本发明元件嵌入式封装结构的实施例的剖面图。 [0020] Please refer to FIG 1, there is shown a cross-sectional view of an embodiment of the present invention is an embedded device package structure. 所述兀件嵌入式封装结构1〇〇包括载体i〇2、裸片104、裸片垫106、第一图案化导电层108、粘着层110、第一电介质层112、第二电介质层114及第二图案化导电层116。 Wu said embedded member comprises a support package structure 1〇〇 i〇2, die 104, die pad 106, the first patterned conductive layer 108, the adhesive layer 110, a first dielectric layer 112, dielectric layer 114 and the second a second patterned conductive layer 116.

[0021]所述载体102具有上表面102a及相对于所述上表面102a的下表面102b。 [0021] The carrier 102 has an upper surface 102a and the lower surface 102b of the upper surface 102a with respect to. 如图1所示,在一实施例中,所述载体1〇2可包含设置于所述载体1〇2的上表面l〇2a上的裸片垫1〇6及第一图案化导电层,及设置于所述载体1〇2的下表面102b上的导电箔118。 As shown in FIG 1, in one embodiment, the carrier may comprise 1〇2 said carrier disposed on the upper surface of the die pad 1〇6 l〇2a 1〇2 and the first patterned conductive layer, and said carrier is provided on the lower surface of the conductive foil 118 1〇2 102b. 所述裸片塾106与所述第一图案化导电层在所述载体102的上表面l〇2a上界定出开口,供填入粘着层110。 Sook the die 106 and the first patterned conductive layer defining an opening, for the entry of the adhesive layer on the upper surface 110 of the carrier 102 l〇2a. 所述载体2可利用本发明领域中任何可用材料组成,例如可为芯材衬底。 The carrier 2 may be utilized in the present invention any available material, for example, a core material of the substrate. 芯材衬底的材质可为C阶段硬化材料(C-stage material)、ABF类(Ajinomoto build-up film)材料、双马来酰亚胺-三氮杂苯(Bismaleimide Triazine,BT)树脂材料或其类似物或其它合适材料。 The core material of the substrate may be a C-stage curing material (C-stage material), ABF class (Ajinomoto build-up film) material, bismaleimide - triazine (Bismaleimide Triazine, BT) resin material or analogs, or other suitable materials. 通过将所述载体102设置于所述裸片104相对于作用面104a的背面104b,可至少部分平衡所述裸片104与所述第一电介质层112及所述第二电介质层114因热膨胀系数不同所造成的热应力, 进而改进因所述热应力所造成的衬底翘曲问题,而改进衬底的机械稳定性。 By the carrier 102 is provided on the back surface of the die 104 with respect to the active surface 104a 104b, may be at least partially balanced by the die 104 and the first dielectric layer 112 and the second dielectric layer 114 due to thermal expansion coefficient caused by the different thermal stress, thereby improving the warping of the substrate due to problems caused by thermal stress, and to improve the mechanical stability of the substrate.

[0022] 所述裸片104具有作用面104a及相对于所述作用面的背面l〇4b。 [0022] The die 104 having a surface 104a and the rear surface l〇4b action with respect to the action plane. 所述裸片104可通过粘着层110附着于所述载体102上表面102a的芯片垫106上。 The die 104 by adhesive layer 110 may be attached to the carrier 102 on the upper surface 102a of the die pad 106.

[0023] 所述载体102的上表面102a上,所述芯片垫106的两侧可设置第一图案化导电层108,在所述载体102的上表面102a上实质侧向延伸。 [0023] The upper surface 102a of the carrier 102, both sides of the die pad 106 may be disposed a first patterned conductive layer 108, laterally extending the substance on the upper surface 102a of the carrier 102. 所述第一图案化导电层108可作为所述衬底100的内部走线用,在所述第一电介质层112与所述载体102间,或在所述裸片104的背面104b提供额外的线路设计弹性。 The first patterned conductive layer 108 of the substrate 100 may be used as an internal alignment with, the first dielectric layer 112 and the carrier 102, or 104 in the back surface 104b of the die to provide additional circuit design flexibility.

[0024]所述粘着层110具有上表面ll〇a及下表面ll〇b。 [0024] The adhesive layer 110 having an upper surface and a lower surface ll〇b ll〇a. 所述粘着层110填入所述芯片垫106与所述第一图案化导电层108所界定出的开口120。 The adhesive layer 110 filled in the opening 120 of the die pad 106 and the first patterned conductive layer 108 delimited. 如图1所示,在一实施例中,所述粘着层110围绕至少部分所述芯片垫106及所述第一图案化导电层108。 1, in one embodiment, the adhesive layer 110 surrounds at least a portion of the die pad 106 and the first patterned conductive layer 108. 在一实施例中,因所述载体102的上表面102a上另设有芯片垫1〇6及第一图案化导电层108,所述粘着层110仅有部分下表面110b与所述载体102的上表面l〇2a接触。 In one embodiment, because the upper surface 102a of the carrier 102 and the other with the die pad 1〇6 first patterned conductive layer 108, the adhesive layer 110 only part of the lower surface 110b of the carrier 102 l〇2a contact with the upper surface. 所述粘着层110可包含本发明领域中任何可用的粘性材料,例如环氧树脂、树脂或其它合适的材料。 The adhesive layer 110 may comprise any available field of the invention viscous material, such as epoxy, resin or other suitable materials. 所述粘性材料可具有导热功能,例如为导热胶。 The viscous material may have a function of thermal conductivity, for example, a thermally conductive adhesive. 当所述粘着层11 〇包含具有导热功能的粘性材料时,所述裸片104所产生的热便可经由所述粘着层110及所述裸片垫106散出。 When the adhesive layer 11 comprising a viscous material having a thermal conductivity square function, the heat generated by the die 104 via the adhesive layer 110 can be the die pad 106 and dissipated.

[0025]所述第一电介质层112具有上表面112a及下表面112b。 [0025] The first dielectric layer 112 has an upper surface 112a and a bottom surface 112b. 所述第一电介质层112的下表面112b邻设于所述粘着层120的上表面120a上,与所述粘着层120的上表面120a共平面。 The lower surface of the first dielectric layer 112, 112b disposed adjacent to the adhesive layer 120 on the upper surface 120a of the upper surface 120 of the adhesive layer 120a coplanar. 所述第一电介质层II2通过所述粘着层120附着于所述载体102上表面102a的芯片垫106及第一图案化导电层108上。 The first dielectric layer II2 via the adhesive layer 120 attached to the upper surface 102a of the carrier 102 of the die pad 106 and the first patterned conductive layer 108. 所述第一电介质层112具有开口112c,用以容置裸片108。 The first dielectric layer 112 has an opening 112c, 108 for accommodating the die. 所述开口112c的侧壁llM与所述裸片104侧边可具有空隙,供填入另外的电介质材料。 The opening of the die sidewall 104 llM sides 112c may have a gap, for the entry of additional dielectric material. 所述第一电介质层112需包含全固化的电介质材料,例如可为但不限于C阶段硬化材料、双马来酰亚胺-三氮杂苯树脂材料、玻璃纤维及树脂构成材料或其类似物或其它合适的材料。 The first dielectric layer 112 comprises a dielectric material for an all-curing, for example but not limited to C-staged material is cured, bismaleimide - triazine resin material, a glass fiber and resin material, or the like or other suitable material. 因所述第一电介质层112所利用者为全固化的电介质材料,其所形成的电介质层厚度较一致,均匀度较佳,使得后续如果要再形成电介质层于其上时,其电介质层总体厚度均匀度会较佳,且其厚度较易控制,进而,元件嵌入式封装结构的整体厚度及均匀度较佳且较易控制。 112 by the user of the first dielectric layer is fully cured dielectric material, the thickness of the dielectric layer formed therefrom more consistent, better uniformity, such that if a subsequent dielectric layer is again formed thereon, which is generally a dielectric layer the thickness uniformity would be preferred, and it is easier to control the thickness, and thus, the overall thickness and uniformity of the embedded device package structure of the preferred and easier to control. 此外,因所述第一电介质层需要形成开口以容纳裸片,其与第二电介质层的接触面积较小,可改进第二电介质层与第一电介质层因热膨胀系数不一致所导致的热应力,理论上,如果开口越大(即容纳裸片的数目越多),热应力改进的效果越明显。 Further, since the first dielectric layer is necessary to form an opening to receive a die, the smaller the second dielectric layer with the contact area, may improve the thermal stress of the second dielectric layer and the first dielectric layer due to inconsistencies caused by the thermal expansion coefficient, theoretically, if the larger opening (i.e., the more the number of receiving dies), the thermal stress significantly improved results. 此外,如果形成的开口可一次涵盖多个裸片,其可省去为个别裸片开口的工艺成本。 Further, if the opening is formed may encompass a plurality of dies, which can save the cost of the process for individual die openings.

[0026] 此外,因所述第一电介质层112直接通过粘着层106附着于载体102上,先前为附着在所述载体上的所述第一电介质层的粘着力便不需要特别要求,而可利用不具粘着力的电介质材料作为所述第一电介质层的材质。 [0026] In addition, since the first dielectric layer 112 via an adhesive layer 106 is directly adhered to the carrier 102, previously attached to the adhesion on the carrier of the first dielectric layer will be no special requirements, but may a dielectric material as a material non-adhesive to the first dielectric layer. 此外,因所述第一电介质层112设置于粘着层106 上时为全固化材料,先前为适当包覆固着裸片1〇4的所述第一电介质层的流变性质便不需要特别要求,而可利用流变性质较不佳的电介质材料作为所述第一电介质层的材质。 Further, since the first dielectric layer 112 is disposed on the adhesive layer 106 when the material is fully cured, a suitable coating for the previous fixing the rheological properties of the die 1〇4 first dielectric layer, it does not require special requirements, but may use more poor rheological properties of the dielectric material as the material of the first dielectric layer.

[0027] 所述第二电介质层114具有上表面114a及下表面114b。 [0027] The second dielectric layer 114 has an upper surface 114a and a lower surface 114b. 所述第二电介质层114设置于所述第一电介质层112的上表面112a及所述裸片104的作用面104a上。 The second dielectric layer 114 is disposed on the first dielectric layer 112 acts on the upper surface of the die face 104a 112a and 104. 所述第二电介质层114渗入并填满所述第一电介质层112的开口112c侧壁与裸片104侧边间的空隙。 The second dielectric layer 114 to penetrate and fill the gap between the opening 112c side of the side wall 104 and the die 112 of the first dielectric layer. 如图所示, 部分的所述第二电介质层114的表面与所述第一电介质层112的下表面112b共平面。 As shown, the lower surface portion of the surface of the second dielectric layer 114 and the first dielectric layer 112 is coplanar 112b. 因所述第二电介质层114包含半固化的电介质材料,其流动性较佳,在施加于所述第一电介质层10 i:时•,可渗入或填补第一电介质层112因开口112c宽度较裸片尺寸宽,或较硬化或较不具流动性所造成的与裸片间的空隙,围绕所述裸片1〇4,使所述裸片受到更佳的保护,因此,其与半固化的^ 一电介质层112搭配,可进一步改进机械稳定性且改进裸片的密封程度,进一步降低裸片受到外界环境,如湿气、空气氧化或灰尘的影响的可能性。 Because the second dielectric layer 114 comprises a dielectric prepreg material, better flowability, is applied to the first dielectric layer 10 i: • when, can penetrate or filled by the first dielectric layer 112 wider than the opening 112c wide die size, or more or less hardened with a gap between the dies and the flowability caused 1〇4 around the die so that the die be protected better, so that the semi-cured ^ with a dielectric layer 112 can be further improved mechanical stability and improved sealing of the die, and further reduce the possibility, as the influence of ambient moisture, dust or oxidation air being die. 所述第二电介质层与所述第一电介质层的材料可相同或不同,但如果所述第二电介质层114的材料与所述第一电介质层112的材料不同,所述第一电介质层112与所述第二电介质层114搭配,构成所述衬底的电介质层时,因所述电介质层由两种不同材料的电介质材料组成,根据所选择的材料,可减缓$膨胀系数的差异。 The second dielectric layer and the first dielectric layer material may be the same or different, but if the second dielectric material layer 114 and the material of the first dielectric layer 112 is different from the first dielectric layer 112 and the second dielectric layer 114 with, when the dielectric layer constituting the substrate, because the dielectric layer is made of two types of dielectric materials of different materials, depending on the material chosen, can reduce the difference in coefficient of expansion $. 所述第二电介质层114的材质可为半固化的电介质材料,可为预浸材(prepreg)衬底材料、abf类材料、树脂涂布铜箱(Resin coated copper,RCC)树脂材料、 液态电介质物质(如聚酰亚胺(PI)或聚苯并二恶唑(PB0))或其类似物或其它合适的材料。 The material of the second dielectric layer 114 may be a semi-cured dielectric material may be a prepreg (Prepreg) substrate material, ABF-based material, resin-coated copper box (Resin coated copper, RCC) resin material, a liquid dielectric substances (such as polyimide (PI) or polybenzobisoxazole (the PB0)) or analogs thereof, or other suitable materials. [0028]所述第二电介质层114可具有通孔,从所述第二电介质层114的上表面114a延伸到所述裸片104的接垫122,露出裸片104的接垫122,以供外部电性连接。 [0028] The second dielectric layer 114 may have a through hole extending from an upper surface 114a of the second dielectric layer 114 of the die 104 to contact pads 122, 104 of the exposed die pad 122, for external electrical connection. 所述开口中可设有电性互连件124。 The opening may be provided electrical interconnection member 124.

[0029]所述第二图案化导电层116设置于所述第二电介质层114的上表面114a上,在所述第二电介质层114的上表面114a上实质侧向延伸。 [0029] The second patterned conductive layer 116 disposed on the upper surface 114a of the second dielectric layer 114, laterally extending the substance 114a on the upper surface of the second dielectric layer 114. 所述第二图案化导电层116通过所述电性互连件124与所述接垫122电性连接。 The second patterned conductive layer 116 is connected through the electrical interconnection member 124 and the pad 122 electrically.

[0030]虽然图1绘示第一电介质层112和第二电介质层114作为嵌入式衬底的一部分,但事实上,所述第二电介质层114与所述第一电介质层112可无明显分界,即其可为同一材料组成。 [0030] While FIG 1 illustrates a first dielectric layer 112 and the second dielectric layer 114 is embedded as part of the substrate, but in fact, the second dielectric layer 114 and the first dielectric layer 112 may be no demarcation , i.e. it may consist of the same material. 虽然图1仅绘示一层第一电介质层112和一层第二电介质层114作为嵌入式衬底的一部分,但在其它实施例中,第一电介质层112和第二电介质层114可各由两层以上组成。 Although FIG. 1 shows only a schematic one first dielectric layer 112 and the layer of the second dielectric layer 114 as an embedded part of the substrate, but in other embodiments, the first dielectric layer 112 and the second dielectric layer 114 may be each composed of two or more layers.

[0031]前述的电性互连件124可利用本发明领域中任何可用的材料组成,例如由金属、金属合金、具有金属或金属合金散布于其中的材料或合适的导电材料所形成。 [0031] the electrical interconnection member 124 may utilize any useful material in the present invention composed, for example, a metal, a metal alloy, having a metal or metal alloy dispersed in the material or formed therein suitable electrically conductive material. 举例来说,所述电性互连件124的材料可包含铝、铜、钛或其组合。 For example, the material of the electrical interconnection member 124 may comprise aluminum, copper, titanium, or combinations thereof. 前述的芯片垫106、第一图案化导电层108 及第二图案化导电层116可利用本发明领域中任何可用的材料组成,例如由金属、金属合金、具有金属或金属合金散布于其中的材料或合适的导电材料所形成。 The die pad 106, the first patterned conductive layer 108 and the second patterned conductive layer 116 may utilize any useful material in the present invention composed, for example, a metal, a metal alloy, having a metal or metal alloy material dispersed therein or a suitable conductive material is formed. 举例来说,前述的芯片垫106、第一图案化导电层10S及第二图案化导电层116可包含铝、铜、钛或其组合。 For example, the die pad 106, the first patterned conductive layer 10S and the second patterned conductive layer 116 may comprise aluminum, copper, titanium, or combinations thereof. 所述电性互连件1M与所述芯片垫1〇6、第一图案化导电层108及第二图案化导电层116的材质可相同或不同。 The electrical interconnection member and the die pad 1〇6 1M, material of the first patterned conductive layer 108 and the second patterned conductive layer 116 may be the same or different.

[0032]参考图2,其展示第一电介质层212的实施例的俯视图,所述第一电介质层212具有露出多个裸片的至少一个开口212c。 [0032] Referring to Figure 2, which shows a top view of an embodiment of a first electrical dielectric layer 212, the first dielectric layer 212 is exposed a plurality of dies having at least one opening 212c. 在多个裸片204经过封装后,后续会经过例如沿着XI、 12丨3、¥1、¥2、¥3、¥4、¥5及¥6线切割后,以形成个别裸片的半导体封装。 After the plurality of packaged die 204, will follow along through e.g. XI, 12 Shu 3, ¥ 1, ¥ 2, ¥ 3, ¥ 4, and ¥ 6 ¥ 5 after cutting to form individual semiconductor dies package. 开口的尺寸可依尺寸及利用率而设计为容纳一个或数个裸片。 It may vary depending on the size and dimensions of the openings and designed to accommodate utilization of one or several dies. 如图所示,在一实施例中,所述开口可设计为涵盖单排5个裸片,以减少所述第一电介质层的开口数目。 As shown, in one embodiment, the opening may be designed to cover a single row of five dies to reduce the number of openings of the first dielectric layer. 此外,所述开口所涵盖的裸片数或裸片的排列(单排)可考量后续裸片封装完成切割后,所述裸片封装的相对两侧是否可呈现对称。 Further, the number of dies arranged in the die opening or covered (single row) may be considered after the completion of a subsequent cutting die package, opposite sides of the die presentation package whether symmetrical. 举例来说,所述开口可设计为涵盖单排单数个裸片。 For example, the opening may be designed to cover both the singular single row of dies. 如图2所示,开口设计为涵盖单排5个裸片时,其后续裸片封装完成沿着XI、X2、X3、Y1、¥2、¥3、¥4、丫5及丫6线切割后,所述裸片封装的相对两侧可呈现对称、一致的结构。 As shown, the opening 2 is designed to cover a single row of five dies, which follow die package is completed along XI, X2, X3, Y1, ¥ 2, ¥ 3, ¥ 4, 5 Ah 6 Ah and cutting after the die opposing sides of the package may be rendered symmetrical, consistent structure. 如图2所示,所述第一电介质层212可具有多个开口沿着所述第一电介质层212的短边排列。 The first dielectric layer 212 as shown in FIG. 2 may have a plurality of openings arranged along a short side of the first dielectric layer 212.

[0033]参考图3,其展示第一电介质层312的另一实施例的俯视图,所述第一电介质层312 具有露出多个裸片的至少一个开口312c。 [0033] Referring to Figure 3, a plan view showing the other embodiment of the first dielectric layer 312 of the embodiment, the first dielectric layer 312 is exposed a plurality of dies having at least one opening 312c. 在多个裸片304经过封装后,后续会经过例如沿着\4353637、¥7、¥8、¥9及丫10线切割后,以形成个别裸片的半导体封装。 After the plurality of packaged die 304, for example, it will pass along the subsequent \ 4353637, ¥ 7, ¥ 8, the ¥ 10 Ah. 9 and cutting, to form a semiconductor die package individually. 开口的尺寸可依尺寸及利用率,可为一个或数个裸片容纳于其中。 Size of the opening may vary depending on size and efficiency, which may be housed in one or several dies. 举例来说,如图所示,在一实施例中,所述开口可设计为涵盖单排3个裸片,以减少所述第一电介质层的开口数目。 For example, as shown, in one embodiment, the opening may be designed to cover a single row of three dies to reduce the number of openings of the first dielectric layer. 此外,所述开口所涵盖的裸片数或裸片的排列(单排)可考量后续裸片封装完成切割后,所述裸片封装的相对两侧是否可呈现对称。 Further, the number of dies arranged in the die opening or covered (single row) may be considered after the completion of a subsequent cutting die package, opposite sides of the die presentation package whether symmetrical. 举例来说,如图3所示,开口设计为涵盖单排3个裸片时,其后续裸片封装完成沿着乂43536“7、¥7、¥8、¥9及¥10线切割后,所述裸片封装的相对两侧可呈现对称、 一致的结构。如图3所示,所述第一电介质层312可具有多个开口沿着所述第一电介质层312 的长边排列 For example, when, as shown in FIG. 3, an opening designed to cover a single row of three dies, which follow die package is completed along qe 43536 "7, ¥ 7, ¥ 8, ¥ 9 ¥ 10, and the cutting line, the opposite sides of the die package can be rendered symmetrical, consistent with the structure shown in Figure 3, the first dielectric layer 312 may have a plurality of openings are arranged along the longer sides of the first dielectric layer 312

[0034]参考图4,其展示本发明元件嵌入式封装结构400的另一实施例的剖面图。 [0034] Referring to Figure 4, showing an embedded device package structure of the present invention a cross-sectional view of another embodiment 400 of the embodiment. 此实施例与图1的实施例的差别在于所述裸片404及所述第一电介质层412直接通过粘着层406附着于载体402上。 This embodiment different embodiment of FIG. 1 in that the die 404 and the first dielectric layer 412 directly by an adhesive layer is attached to the carrier 402,406. 本实施例的优点如先前所述。 Advantage of this embodiment is as previously described. 此外,因所述裸片404及所述第一电介质层412直接通过粘着层406附着于载体402上,其载体402的上表面402上未具有芯片塾或第一图案化导电层,所述粘着层的厚度较容易控制,且其厚度不需根据芯片垫或第一图案化导电层的厚度决定,粘着层406的厚度可较薄。 In addition, because the die 404 and the first dielectric layer 412 directly by an adhesive layer 406 is attached to the carrier 402, or not having a chip Sook first patterned conductive layer on its upper surface 402 of the carrier 402, the adhesive easier to control the thickness of the layer, and its thickness without depending on the thickness of the die pad or the first patterned conductive layer is determined, the thickness of the adhesive layer 406 may be thinner.

[0035] 参考图5,其展示本发明元件嵌入式封装结构500的另一实施例的剖面图。 [0035] Referring to Figure 5, there is shown a cross-sectional view of another embodiment of the present invention, an embedded device package structure 500 of the embodiment. 在此实施例中,所述载体502为引线框架(lead frame)。 In this embodiment, the carrier 502 is a lead frame (lead frame). 本实施例的优点如先前所述。 Advantage of this embodiment is as previously described. 此外,因引线框架为金属组成,其可提供较佳的散热效果。 Further, because the lead frame of metal, which may provide better heat dissipation effect. 此外,引线框架有成本较低等优点。 Further, the lead frame has a lower cost.

[0036] 参考图6,其展示本发明元件嵌入式封装结构600的另一实施例的剖面图。 [0036] Referring to Figure 6, there is shown a cross-sectional view of another embodiment of an embedded package structure 600 of the element of the present invention. 所述元件嵌入式封装结构600与图1所示者的差别主要在于所述第一电介质层612的上表面612a及下表面612b可分别另包含金属箔626a及626b,以帮助散热。 The difference element 600 embedded package configuration shown in Figure 1 by mainly upper surface 612a of the first dielectric layer 612 and the lower surface 612b may each further comprise a metal foil 626a and 626b, in order to help dissipate heat.

[0037] 参考图7,其展示本发明元件嵌入式封装结构700的另一实施例的剖面图。 [0037] Referring to Figure 7, there is shown a cross-sectional view of another embodiment of the present invention, an embedded device package structure 700 of the embodiment. 所述元件嵌入式封装结构700与图6所示者的差别主要在于所述元件嵌入式封装结构700的裸片704通过粘着层706设置在引线框架702上。 The difference element 700 embedded package structure as that shown in FIG. 6 mainly in that the element embedded die package structure 700 704706 702 disposed on the lead frame through the adhesive layer. 如先前所述,本实施例除具有先前所述的优点夕卜,还可具有引线框架的优点。 As previously described, the present embodiment has an advantage in addition to Xi Bu previously described, it may also have the advantage of the lead frame.

[0038] 请参考图8,其展示本发明元件嵌入式封装结构800的另一实施例的剖面图。 [0038] Please refer to FIG. 8, which shows another structure of the present invention is embedded package member 800 is a cross-sectional view of an embodiment. 所述元件嵌入式封装结构800与图6所不者的差别主要在于所述第一电介质层812的上表面812a 上设置有第三图案化导电层840,且所述第一电介质层812在对应于第一图案化导电层808 处具有通孔,从所述第一电介质层812的上表面812a (或金属箱826a)上延伸到第一电介质层812的下表面812b (或金属箔826b)上,露出第一图案化导电层808。 The difference element embedded package structure 800 of FIG. 6 are not provided by the primary comprising a third patterned conductive layer 840 on the upper surface 812a of the first dielectric layer 812, and the first dielectric layer 812 in the corresponding having a through hole extending from the upper surface of the first dielectric layer 812 812a (or 826a metal box) upper to the lower surface 812b of the first dielectric layer 812 (metal foil or 826b) on the first patterned conductive layer 808 to expose a first patterned conductive layer 808. 所述通孔中可设有电性互连件828。 The through holes may be provided electrical interconnection member 828. 所述第三图案化导电层S40可通过所述电性互连件828与所述第一图案化导电层808电性连接。 The third patterned conductive layer may be connected through S40 the electrical interconnects 828 and 808 of the first electrically conductive layer patterned. 所述电性互连件828与所述第三图案化导电层840的材质可如先前所述。 The electrical interconnection member 828 and the third patterned conductive layer 840 may be made as previously described.

[0039] 请参考图9,其展示本发明元件嵌入式封装结构900的另一实施例的剖面图。 [0039] Please refer to FIG 9, there is shown a cross-sectional view of another embodiment of the present invention, an embedded device package structure 900 of the embodiment. 所述元件嵌入式封装结构与图8所示者的差别主要在于所述元件嵌入式封装结构的裸片通过粘着层6设置在引线框架(leadframe) 18上。 The difference between those elements embedded package structure shown in FIG. 8 and FIG mainly in that the element embedded die package structure by an adhesive layer 6 disposed on the lead frame (leadframe) 18.

[0040] 请参考图10,其展示本发明元件嵌入式封装结构1000的另一实施例的剖面图。 [0040] Please refer to FIG. 10, which shows a cross-sectional view of another embodiment of the present invention, an embedded device package structure 1000 of FIG. 如图所示,本发明的元件嵌入式封装结构1000的第二图案化导电层1016上可另包含保护层1〇3〇。 As shown, the device package structure of the present invention embedded second patterned conductive layer may further comprise 10161000 1〇3〇 protective layer. 所述保护层1030具有至少一个开口显露出部分的所述图案化导电层1016,其中显露的部分可作为或形成球垫(ball pad) 1〇32,例如球栅阵列端点(ball grid array terminal),以供球栅阵列(ball grid array)焊球1034形成于其上。 The protective layer 1030 has at least one opening to reveal the patterned conductive layer portion 1016, wherein the exposed portion may be formed as a ball or pad (ball pad) 1〇32, such as a ball grid array terminal (ball grid array terminal) , for BGA (ball grid array) ball 1034 formed thereon. 在某些实施例中,所述保护层1030可为焊料掩膜(solder mask)或第三电介质层。 In certain embodiments, the solder mask 1030 may (solder mask) or the third layer protects the dielectric layer. 所述保护层1030的材料例如可为但不限于聚酰亚胺。 The material of the protective layer 1030 may be, for example, but not limited to polyimide.

[0041] 请参考图11,其展示本发明元件嵌入式封装结构1100的另一实施例的剖面图。 [0041] Please refer to FIG. 11, showing an embedded device package structure of the present invention a cross-sectional view of another embodiment 1100. 所述元件嵌入式封装结构1100与图10所不者的差别主要在于所述元件嵌入式封装结构1100 的裸片1104通过粘着层1116设置在引线框架11〇2上。 The difference between the embedded device 1100 and the package 10 are not in the view of the main element is that the embedded die package structure by an adhesive layer 11041100 1116 11〇2 disposed on the lead frame. 如先前所述,本实施例除具有先前所述的优点外,还可具有引线框架的优点。 As previously described, the present embodiment has an advantage in addition to the previously described, but also has the advantage of the lead frame.

[0042]请参考图I2,其展示本发明元件嵌入式封装结构1200的另一实施例的剖面图。 [0042] Please refer to FIG I2, which is a sectional view showing another embodiment of the present invention, an embedded device package structure 1200 of FIG. 如图所示,本发明的元件嵌入式封装结构1200的载体12〇2具有上表面120¾及下表面丨2〇2b。 As shown, the device package structure of the present invention embedded carrier 12〇2 1200 having an upper surface and a lower surface Shu 2〇2b 120¾. 所述载体1202的上表面1202a上设置有第一图案化导电层1238及所述载体1202的下表面l2〇2b上设置有第四图案化导电层12:38。 The carrier is provided with a first patterned conductive layer 1238 and is provided on a lower surface of the support 1202 l2〇2b fourth patterned conductive layer on the upper surface 1202a 12:38 1202. 所述第一电介质层m2在对应于第一图案化导电层1240处具有通孔,从所述第一电介质层1212的上表面1212a (或金属箔1226a)上延伸到第一电介质层1212的下表面1212b (或金属箱1226b)上,露出第一图案化导电层1208。 The first dielectric layer corresponding to m2 at a first patterned conductive layer 1240 has a through hole from the upper surface of the first dielectric layer 1212 1212a (or metal foil 1226a) extend to the first dielectric layer 1212 1212b upper surface (or a metal box 1226b), to expose the first patterned conductive layer 1208. 所述通孔中可设有电性互连件1228。 The through holes may be provided electrical interconnection member 1228. 所述第三图案化导电层1240可通过所述电性互连件1228与所述第一图案化导电层1208电性连接。 The third patterned conductive layer 1240 may be electrically connected by the interconnects 1228 and 1208 of the first electrically conductive layer patterned. 此外,所述载体1202具有通孔,从所述载体1202的第一图案化导电层1208延伸到所述载体1202的下表面1202b及从所述芯片垫1206延伸到所述载体1202的下表面l2〇2b。 Further, the carrier having a through-hole 1202, a first support extending from the conductive layer 1202 is patterned to a lower surface 1208 of the carrier 1202 and 1202b extending from the die pad to a lower surface 1206 of the carrier 1202 l2 〇2b. 所述通孔中可设有电性互连件1242。 The through holes may be provided electrical interconnection member 1242. 所述第一图案化导电层12〇8可通过所述电性互连件1242与所述第四图案化导电层1238电性连接,且所述芯片垫1206可通过所述电性互连件1242与所述第四图案化导电层1238连接。 The first patterned conductive layer 1242 12〇8 may be connected by the fourth patterned electrically conductive layer 1238 of the electrical interconnection member, and the die pad 1206 through the electrical interconnection member 1242 and the fourth patterned conductive layer 1238 is connected. 所述电性互连件1228及1242与所述第三及第四图案化导电层1208及1238的材质可如先前所述。 The electrical interconnection member 1228 and 1242 and the third and fourth material patterned conductive layer 1208 and 1238 may be as previously described. 通过在所述载体1202的上表面1202a设置第一图案化导电层1208及相对于所述上表面1202a的下表面1202b设置第四图案化导电层1238,及其中内部的电性连接,第四图案化导电层1238可作为外部电性连接垫,用来与其它元件,例如无源元件或有源元件连接,以形成系统模块。 By 1202a provided on a first surface of the support 1202 and the patterned conductive layer 1208 relative to the upper surface of the lower surface 1202b 1202a of a fourth patterned conductive layer 1238, and electrically connected to the inside of the fourth pattern conductive layer 1238 can serve as external electrical connection pads, used, for example, a passive element or an active element connected to the other elements, to form a system module. 此外,第四图案化导电层1238可包含散热金属层,借此,所述裸片1204所产生的热可通过所述芯片垫1206、所述电性互连件1242及所述第四图案化导电层1238导出。 Further, the fourth layer 1238 may be patterned conductive layer comprises a metal heat sink, whereby the heat of the die pad 1204 may be generated by the 1206 chip, the electrical interconnection member 1242 and the fourth patterned a conductive layer 1238 derived.

[0043] 参考图13A至13H,展示本发明元件嵌入式封装结构的制造方法的实施例的示意图。 [0043] with reference to FIGS. 13A to 13H, schematic diagram showing an embodiment of a method of manufacturing a device package structure of the present invention is embedded.

[0044] 参考图13A,提供载体102,所述载体102可具有在其上表面102a上的第一导电箱119及在其下表面102b上的第二导电箔118。 [0044] Referring to Figure 13A, providing a carrier 102, the carrier 102 may have on its upper surface 102a of the first conductive tank 119 and a second conductive foil on its lower surface 102b is 118. 如果所述载体2本身不具有导电箔于其表面,则所述第一导电箱119及第二导电箔118可视需要以层压(lamination)方式形成于所述载体102的表面上。 If the carrier 2 itself does not have a conductive foil surface thereof, said first conductive and second conductive foil 119 tank 118 to optionally laminate (Lamination) is formed on the upper surface 102 of the support.

[0045] 参考图13B,图案化所述第一导电箱119,以界定出可放置至少一个裸片的裸片垫106及第一图案化导电层108。 [0045] Referring to Figure 13B, the patterned first conductive tank 119, may be placed to define the at least one die of the die pad 106 and the first patterned conductive layer 108. 所述第一导电箱119可经图案化以形成可放置多个裸片的裸片垫106。 The first conductive tank 119 may be patterned to form a plurality of dies can be placed on the die pad 106. 所述图案化过程可通过光刻及蚀刻方法达成。 The patterning process can be achieved by photolithography and etching method. 参考图13C,填入粘着材料于所述裸片垫106与所述第一图案化导电层108所界定出的开口,以形成粘着层110。 Referring 13C, the adhesive material filled in the die pad 106 defining an opening 108 with the first conductive layer is patterned to form the adhesive layer 110. 至少一个裸片通过所述粘着层110附着于所述载体102上。 At least one die by the adhesive layer 110 adhered to the carrier 102. 所述第一电介质层112也通过所述粘着层110附着于所述图案化第一导电层108上,借此,可省去利用额外技术(例如额外施加粘胶等)将第一电介质层附着于所述载体102 (或所述图案化第一导电层108上)的步骤。 The first dielectric layer 112 through the adhesive layer 110 attached to the patterned first conductive layer 108, thereby, eliminating the need for using additional techniques (e.g., application of additional glue, etc.) adhered to the first dielectric layer to the carrier 102 (or 108 on the patterned first conductive layer) steps. 所述粘着层110可利用压合、旋转涂布、喷射涂布或其它方式施加于所述图案化第一导电层108上,填入所述裸片垫106与所述第一图案化导电层108所界定出的开口中。 The adhesive layer 110 may use the nip, spin coating, spray coating, or otherwise applied on the patterned first conductive layer 108, filling the die pad 106 and the first patterned conductive layer 108 defining an opening.

[0046] 所述裸片104的表面可具有接垫122,作为与外部电性连接用。 The surface of the [0046] 104 may have a die pad 122, is electrically connected to the external as used. 所述接垫122可利用本发明领域中可用的方式形成,举例来说,可包含上光致抗蚀剂、曝光显影、电镀及去光致抗蚀剂等步骤。 The contact pads 122 may be formed using the embodiment of the present invention is useful in the art, for example, may include a photoresist coating, exposure and development, and to electroplating a photoresist step.

[0047] 参考图13D,全固化的电介质膜通过所述粘着层110附着在所述载体102上,以形成所述第一电介质层112。 [0047] Referring to FIG 13D, fully cured dielectric film 110 is attached via the adhesive layer on the carrier 102, to form the first dielectric layer 112. 所述第一电介质层112具有开口112c,用以容置至少一个裸片108。 The first dielectric layer 112 has an opening 112c, for accommodating the at least one die 108. 如先前所述,所述开口的尺寸可依尺寸及利用率而设计为容纳一个或数个裸片。 As previously described, the size of the opening may vary depending on the size and utilization designed to accommodate one or several dies. 所述开口112c的侧壁112d与所述裸片104侧边可具有空隙,供另外的电介质材料填入。 The opening sidewall 112d and 112c of the die 104 may have a side gap for further dielectric material is filled. 所述电介质膜可利用层压方式及开口对应于裸片104的方向配置于所述载体102上,以形成所述第一电介质层112。 The dielectric film may be laminated using the method and corresponding to the opening direction of the die 104 disposed on the carrier 102, to form the first dielectric layer 112.

[0048] 所述第一电介质层112有厚度,此厚度可随着裸片的高度调整。 [0048] The first dielectric layer 112 has a thickness, this thickness can be adjusted as the height of the die. 因此,元件嵌入式封装结构的厚度可因此第一电介质层112的可调整厚度变小而变小;或是第一电介质层112 的可调整厚度可根据元件嵌入式封装结构的需求厚度改变。 Thus, the thickness of the element embedded package structure may be adjusted so the thickness of the first dielectric layer 112 becomes smaller and smaller; or adjust the thickness of the first dielectric layer 112 may be changed according to the needs of the thickness of the embedded device package structure. 第一电介质层112的厚度是可控制的,使得介于裸片104的上表面与第一电介质层112上表面112a之间的间距可趋近于可容忍值的倍数,如10微米、20微米、30微米、40微米、50微米、60微米、70微米、80微米、90微米或100微米。 The thickness of the first dielectric layer 112 is controlled, so that the upper surface of the first dielectric layer 104 interposed between the dies 112 may be the distance between the surface 112a close to multiples tolerable value, such as 10 microns, 20 microns , 30 microns, 40 microns, 50 microns, 60 microns, 70 microns, 80 microns, 90 microns, or 100 microns. 如果第一电介质层112的厚度过厚,因第一电介质层112与裸片104间的间距及空隙变大,则后续再施加的第二电介质层114便需要提供额外的电介质材料用以填补所述间距及空隙。 If the thickness of the first dielectric layer 112 is too thick, the second dielectric layer 114 by a first spacing and the space between the dielectric layer 112 and the die 104 is increased, the subsequent re-applied will need to provide additional dielectric material to fill the said spacing and voids. 此外,相较于在裸片周遭个别形成第一电介质层的方式,利用开口露出单排多个裸片的第一电介质层的方式来形成裸片周遭的电介质层,其不但能降低挖开口的成本, 因所述第一电介质层具有至少一个开口,此种第一电介质层有助于改进元件嵌入式封装结构中载体、裸片及第一电介质层与第二电介质层间的因热膨胀系数不一致所造成的衬底翘曲问题。 Moreover, compared to the respective embodiment forming a first dielectric layer around the die, the die is formed around the dielectric layer using the opening to expose the first dielectric layer is a single row of a plurality of dies manner, which not only reduce the opening dug cost, because the first dielectric layer having at least one opening, a first dielectric layer such elements embedded package structure helps improve inconsistency between the thermal expansion coefficient of the carrier, a first die and a second dielectric layer and the dielectric layer substrate warpage problem caused.

[0049]所述第一电介质层的开口可利用各种挖洞方式形成。 [0049] The opening of the first dielectric layer may be formed using various digging ways. 举例来说,所述第一电介质层的开口可利用铣床、激光或冲压方式形成。 For example, the opening of the first dielectric layer may be formed by milling, punching or laser mode. 开口的尺寸可视需要决定,可涵盖一个或数个裸片。 Optionally decide the size of the opening may be covered by one or several dies. 如图14或15所示,开口1412c及1512c的尺寸可设计为涵盖单排3个或5个裸片,以减少所述电介质膜的开口数目。 As shown in FIG. 14 or 15, the size of the opening 1412c and 1512c may be designed to cover a single row of three or five die in order to reduce the number of openings in the dielectric film. 此外,如图14所示,所述第一电介质层1412可具有多个开口沿着所述第一电介质层1412的长边及短边排列;且如图15所示,所述第一电介质层1512可具有多个开口沿着所述第一电介质层1512的长边排列。 Further, as shown in FIG. 14, the first dielectric layer 1412 may have a plurality of openings arranged along the sides of the first dielectric layer 1412 in the longer and shorter; and FIG. 15, the first dielectric layer 1512 may have a plurality of openings are arranged along the longer sides of the first dielectric layer 1512.

[0050] 参考图13E,半固化的电介质材料填入所述第一电介质层112与所述裸片104间的空隙及覆盖至少部分所述第一电介质层112的上表面112a及所述裸片104的作用面104a上, 以形成第二电介质层114。 [0050] Referring to FIG 13E, the semi-cured dielectric material and charged into the voids of the portion covering the upper surface of at least a first dielectric layer 112 between the first dielectric layer 112 and the die and the die 104 112a 104a 104 acts on the surface to form a second dielectric layer 114. 所述第二电介质层114的部分表面可与所述粘着层110的表面接触。 The second portion of the surface 114 of the dielectric layer 110 may be in contact with the surface of the adhesive layer. 在一实施例中,所述半固化电介质材料可利用层压方式填入所述第一电介质层112与所述裸片104间的空隙且覆盖至少部分所述第一电介质层112的上表面112a及所述裸片104的作用面104a,以形成第二电介质层114。 In one embodiment, the semi-cured dielectric material may be filled using a lamination manner gap between the first dielectric layer 112 and the die 104 covers the upper surface 112a and at least a portion of the first dielectric layer 112 and the role of the die surface 104 104a, to form a second dielectric layer 114. 因所述第二电介质层114的材质可为半固化硬化材料,如预浸材衬底材料、ABF类材料、树脂涂布铜箔树脂材料或其类似物或其它合适的材料等,故其可很容易地渗入并填补第一电介质层112与裸片104间的空隙,使所述裸片完全受到保护,避免外界环境的影响,且可增强元件嵌入式封装结构的机械性质。 Due to the material of the second dielectric layer 114 may be a semi-cured curable material, the substrate material such as prepreg, the ABF-based material, resin-coated copper foil or the like, resin material or other suitable material, so that it can easily penetrate and fill the voids between the first electrical dielectric layer 112 and the die 104, the die being completely protected from the external environment, and may enhance the mechanical properties of the embedded device package structure. 在施加所述半固化的电介质材料后,所述半固化的电介质材料可进行加热,以硬化形成全固化的电介质层。 After the dielectric material is applied to the semi-cured, the semi-cured dielectric material may be heated to form a cured fully cured dielectric layer. [0051]如图13E所示,所述第二电介质层114可具有至少一个开口125,以露出所述裸片104的接垫122。 [0051] FIG. 13E, the second dielectric layer 114 may have at least one opening 125, 104 to expose the die pad 122. 所述开口可利用各种方式形成。 The opening may be formed in various manners. 举例来说,所述开口可利用光亥U/蚀亥!]、激光钻孔或机械钻孔方式形成。 For example, the opening may be by light Hai U / etch Hai!], Laser drilling or mechanical drilling mode is formed. 在一实施例中,所述开口利用激光钻孔方式形成。 In one embodiment, the opening is formed by laser drilling mode. 所述开口可为任意形状,例如包含但不限于柱状或非柱状。 The opening may be any shape, for example, including but not limited columnar or columnar. 柱状例如是圆柱状、椭圆柱状、方形柱状或矩形柱状。 For example, a cylindrical columnar, oval columnar, square pillar-shaped or columnar rectangular. 非柱状例如是圆锥、漏斗或锥状。 For example the non-columnar conical, tapered or funnel. 所述开口的侧面边界也可以是曲线状或大体上呈特定形状。 Lateral boundary of the opening may be substantially curved or particular shape.

[0052] 所述第二电介质层114可另外进行去胶渣(desmear)工艺,使第二电介质层114表面粗糙化,以帮助后续形成第二图案化导电层116于其上。 [0052] The second dielectric layer 114 may be additionally desmearing (Desmear) process, the surface of the second dielectric layer 114 is roughened to assist in the subsequent formation of a second patterned conductive layer 116 thereon.

[0053] 请参考图13F,形成电性互连件124于所述开口的接垫122上,且形成第二图案化导电层116于所述第二电介质层114的上表面114a上。 [0053] Referring to FIG. 13F, formed on the pad member 122 are electrically interconnected to the opening 124, and 114a 114 formed on the upper surface of the second patterned conductive layer 116 on the second dielectric layer. 所述第二图案化导电层116经由所述电性互连件124与所述裸片104的接垫122电性连接。 The second patterned conductive layer 116 is connected to the electrical interconnection member 124 and the die pad 104 via 122 electrically. 前述电性互连件124由所述第二图案化导电层116实质上垂直延伸,可实质上填充开口。 The electrical interconnection member 124 extending from the second patterned conductive layer 116 is substantially vertical, can substantially fill the opening. 所述电性互连件124可用任意一种镀膜技术形战,例W电镀或填入由导电材料组成的糊状物。 The electrical interconnection member 124 may form any of a battle coating technology, for example, W or plating a conductive material filled paste. 所述第二图案化导电层116可以利用任意一种镀膜技术先形成于所述第二电介质层114的上表面丨丨如上,再利用光刻及蚀刻方式形成。 The second patterned conductive layer 116 may utilize any of a prior art film is formed on the surface of the second dielectric layer 114 Shushu above, and then etching is formed by photolithography.

[0054]参考图13G,保护层1130填入所述第二图案化导电层116所界定出的开口。 [0054] Referring to FIG. 13G, the protective layer 1130 filled into 116 defining the opening of the second patterned conductive layer. 接着,图案化所述保护层1130,以形成露出部分所述第二图案化导电层116的开口。 Subsequently, the protective layer 1130 is patterned to form an opening exposing a portion of the second patterned conductive layer 116. 参考图13H,显露的部分可作为或形成球垫1132,例如球栅阵列端点,以供球栅阵列焊球11:34形成于其上。 Referring to FIG 13H, the exposed portion may be formed as a ball or pad 1132, such as a ball grid array terminal, a solder ball for a ball grid array formed thereon 11:34. 形成焊球后,可对所述元件嵌入式封装结构进行个别元件的切割。 After the formation of solder balls, the individual elements can be cut to the embedded device package structure. 举例来说,可沿着锯切线进行单切步骤,以形成多个独立的芯片封装体,其中因所述多个裸片的排列方式,所述些芯片封装体经切割后所形成的几何结构相同(图2及3)。 For example, a single line may be cut along a cutting step to form a plurality of independent chip package, wherein due to the arrangement of the plurality of die, some of the chip package are formed after the cut geometry the same (FIGS. 2 and 3).

[0055]本案的说明书及图式仅用于阐释本发明,并非意图限制本发明的权利范围;此外, 本案图式中所绘示的各技术特征及元件仅用于使所属领域的技术人员更了解本发明,其绘示的尺寸及其对应关系未必表示其实际关系。 [0055] The case of the specification and drawings of the present invention for illustration only, not intended to limit the scope of the claimed invention; moreover, in this case technical drawings wherein depicted elements, and only for those skilled in the art to more understanding of the invention, which illustrates the size and the correspondence relationship thereof does not necessarily represent the actual relationship. 所属领域的技术人员应能根据本案所提供的权利要求书、发明说明及图式而了解本案权利要求书所涵盖的发明范围,本发明的权利范围当以本案权利要求书为准,涵盖所属领域的技术人员从本案的说明书及图式所能合理推知的范围。 Those skilled in the art can be provided according to claim case claims, drawings and description of the invention and to understand the scope of the invention encompassed by the book case as claimed in claim scope of the invention as claimed in claims and their equivalents case covers the art art from the specification and drawings of the present case can reasonably inferred range.

Claims (12)

1. 一种元件嵌入式封装结构,其包含: 载体,所述载体具有上表面; 粘着层,其设置于所述载体的上表面上; 至少一个裸片,其通过所述粘着层附着于所述载体上,所述裸片具有至少一个接垫; 第一电介质层,其通过所述粘着层附着于所述载体上,所述第一电介质层具有容纳所述至少一个裸片的开口;以及第二电介质层,其设置在所述第一电介质层上,其中至少部分的所述第二电介质层填入所述开口及围绕所述至少一个裸片,所述第二电介质层具有开口,其露出所述至少一个裸片的所述接垫。 An embedded device package structure, comprising: a carrier having an upper surface; adhesive layer disposed on the upper surface of the support; the at least one die, which is attached to the adhesive layer by the the above support, the die having at least one pad; a first dielectric layer, the adhesive layer by attached to said carrier, said first dielectric layer having at least one die receiving opening; and a second dielectric layer disposed on said first dielectric layer, wherein at least part of the second dielectric layer filling the opening and around the at least one die, the second dielectric layer having an opening, which exposing the at least one die pad.
2. 根据权利要求1所述的元件嵌入式封装结构,其进一步包含图案化导电层,其设置于所述第二电介质层的表面上,通过所述第二电介质层的所述开口与所述裸片的所述接垫电性连接。 The embedded device package structure according to claim 1, further comprising a patterned conductive layer, disposed on an upper surface of the second dielectric layer, through said opening and the second dielectric layer of the die pad are electrically connected.
3. 根据权利要求2所述的元件嵌入式封装结构,其进一步包含第三电介质层,其设置于所述第二电介质层上,覆盖所述图案化导电层,其中所述第三电介质层具有至少一个开口, 其露出部分所述图案化导电层。 3. The package structure according to an embedded device as claimed in claim 2, further comprising a third dielectric layer disposed on said second dielectric layer covering the patterned conductive layer, wherein the third dielectric layer having at least one opening, the exposed portion of the patterned conductive layer.
4. 根据权利要求1所述的元件嵌入式封装结构,其中所述第一电介质层的上下两面分别进一步包含金属箱。 4. The embedded device package structure according to claim 1, wherein said upper and lower surfaces, respectively, the first dielectric layer further comprises a metal box.
5. 根据权利要求4所述的元件嵌入式封装结构,其中所述金属箱为电性浮接。 The embedded device package structure according to claim 4, wherein the metal case is electrically floating.
6. 根据权利要求1所述的元件嵌入式封装结构,其中所述载体的上表面相对于所述至少一个裸片的位置具有芯片垫,所述至少一个裸片通过所述粘着层附着于所述芯片垫上。 The embedded device package structure according to claim 1, wherein the upper surface of the carrier with respect to said at least one die having a die pad, said at least one die by the adhesive layer is attached to the said chip pads.
7. 根据权利要求6所述的元件嵌入式封装结构,其进一步包含设置于所述载体的下表面上的散热金属层,所述散热金属层通过所述载体的至少一个通孔与所述芯片垫连接。 The embedded device package structure according to claim 6, further comprising a heat dissipation metal layer disposed on a lower surface of said carrier, said metal heat sink layer is formed by the carrier at least one through-hole and the chip pad connection.
8. 根据权利要求1所述的元件嵌入式封装结构,其中所述载体为引线框架。 8. A component-embedded package structure according to claim 1, wherein the carrier is a leadframe.
9. 根据权利要求1所述的元件嵌入式封装结构,其中部分的所述第二电介质层与所述粘着层接触。 9. The embedded device package structure according to claim 1, wherein the second portion of the dielectric layer in contact with the adhesive layer.
10. —种制造元件嵌入式封装结构的方法,其包含: 提供载体,所述载体具有上表面; 设置粘着层于所述载体的上表面上; 提供至少一个裸片,所述至少一个裸片通过所述粘着层附着于所述载体上; 提供全固化电介质层,所述全固化电介质层通过所述粘着层附着于所述载体上,所述全固化电介质层具有容纳所述至少一个裸片的开口;以及设置半固化电介质层于所述全固化电介质层上,其中至少部分的所述半固化电介质层填入所述开口及围绕所述至少一个裸片。 10. The - method of manufacturing an embedded device package structure, comprising: providing a carrier having an upper surface; adhesive layer disposed on the upper surface of said carrier; providing at least one die, the at least one die by the adhesive layer attached to the carrier; fully cured dielectric layer to provide a fully cured dielectric layer through the adhesive layer adhered to said support, said dielectric layer having a fully cured receiving said at least one die opening; and a prepreg dielectric layer to the fully cured dielectric layer, wherein at least part of the prepreg dielectric layer filling the opening and surrounding the at least one die.
11. 根据权利要求10所述的制造元件嵌入式封装结构的方法,其中提供至少一个裸片的步骤包含提供多个裸片,所述多个裸片采用单排的形式容纳在所述全固化电介质层的所述开口内。 11. The method of claim 10 for manufacturing an embedded device package structure according to claim, wherein the at least one die providing comprises providing a plurality of dice, the plurality of dies with a single row in the form housed in the fully cured the dielectric layer opening.
12. 根据权利要求11所述的制造元件嵌入式封装结构的方法,其中在设置所述半固化电介质层于所述全固化电介质层上的步骤后进一步包含沿着锯切线进行的单切步骤,以形成多个独立的芯片封装体,其中所述多个独立的芯片封装体几何结构相同。 12. The method for manufacturing an embedded device package structure according to claim, wherein said prepreg is provided in the dielectric layer after said step of fully cured dielectric layer further comprises a single step of cutting along cutting lines, to form a plurality of independent chip package, wherein the plurality of individual chips of the same package geometry.
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