CN105226025B - The forming method of semiconductor structure - Google Patents
The forming method of semiconductor structure Download PDFInfo
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- CN105226025B CN105226025B CN201410234793.3A CN201410234793A CN105226025B CN 105226025 B CN105226025 B CN 105226025B CN 201410234793 A CN201410234793 A CN 201410234793A CN 105226025 B CN105226025 B CN 105226025B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 105
- 238000000034 method Methods 0.000 title claims abstract description 46
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 201
- 229920005591 polysilicon Polymers 0.000 claims abstract description 200
- 239000000758 substrate Substances 0.000 claims abstract description 73
- 238000005530 etching Methods 0.000 claims abstract description 46
- 238000003860 storage Methods 0.000 claims abstract description 34
- 230000008878 coupling Effects 0.000 claims description 43
- 238000010168 coupling process Methods 0.000 claims description 43
- 238000005859 coupling reaction Methods 0.000 claims description 43
- 238000007667 floating Methods 0.000 claims description 36
- 230000015654 memory Effects 0.000 claims description 21
- 229920002120 photoresistant polymer Polymers 0.000 claims description 18
- 230000008569 process Effects 0.000 claims description 16
- 230000015572 biosynthetic process Effects 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 238000001020 plasma etching Methods 0.000 claims description 7
- 239000007789 gas Substances 0.000 claims description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 5
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 claims description 3
- 230000003628 erosive effect Effects 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 2
- 239000001301 oxygen Substances 0.000 claims 2
- 229910052760 oxygen Inorganic materials 0.000 claims 2
- 229910052581 Si3N4 Inorganic materials 0.000 claims 1
- 229910003978 SiClx Inorganic materials 0.000 claims 1
- 239000002210 silicon-based material Substances 0.000 abstract description 2
- 239000000463 material Substances 0.000 description 22
- 150000002500 ions Chemical class 0.000 description 10
- 125000006850 spacer group Chemical group 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 239000013078 crystal Substances 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 230000004044 response Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000035945 sensitivity Effects 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 229910001439 antimony ion Inorganic materials 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000007792 gaseous phase Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- -1 phosphonium ion Chemical class 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000010181 polygamy Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
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Abstract
A kind of forming method of semiconductor structure, including：Semiconductor substrate is provided, including logic region and some storage regions, each storage region include first area and second area；The first polysilicon layer is formed in storage region；Control gate dielectric layer is formed on the first polysilicon layer；Control on the second region in gate dielectric layer and form the first opening；The second polysilicon layer is formed on logic region and control gate dielectric layer, and fills the first opening；Etching removes the polysilicon layer of part second, control gate dielectric layer and the first polysilicon layer between neighbouring storage areas；The second opening for exposing control gate dielectric layer surface is formed in the second polysilicon layer between the first opening and second area, while the grid of logic transistor is formed in logic region；The first offset side wall is formed in the side wall of the grid of logic transistor, shallow doped region is formed in the grid semiconductor substrates on two sides of logic transistor.The residual of the second polycrystalline silicon material is prevented when forming the second opening.
Description
Technical field
The present invention relates to memory area, more particularly to a kind of forming method of semiconductor structure.
Background technology
In current semiconductor industry, IC products can be divided mainly into three major types type：Logic, memory and simulation
Circuit, wherein memory device account for sizable ratio in IC products.And in memory device, flash memory is deposited in recent years
The development of reservoir (flash memory) is particularly rapid.It is mainly characterized by can keep storing for a long time in the case of not powered
Information, there is high integrated level, faster access speed, be easy to wipe and the multiple advantages such as rewrites, thus in microcomputer, automate
The multinomial fields such as control are widely used.
With reference to figure 1, Fig. 1 is the structural representation of existing flash memories, including：Semiconductor substrate 100, positioned at described
Discrete memory transistor grid stacks and selection transistor gate stack, the memory transistor gate in Semiconductor substrate 100
Pole stack include positioned at the tunnel oxide 101 on the surface of Semiconductor substrate 100, the floating boom 102 on tunnel oxide 101,
Control gate dielectric layer 103 on floating boom 102 and the control gate 104 on control gate dielectric layer 103, the selection crystal
Tube grid, which stacks, to be included positioned at the selection gate dielectric layer 105 on the surface of Semiconductor substrate 100 and on selection gate dielectric layer 105
Selection grid 106；Also include stacking the Semiconductor substrate 100 between selection transistor gate stack positioned at memory transistor grid
Interior common source drain region 108, stacked positioned at memory transistor grid in the Semiconductor substrate 100 away from the side of common source drain region 108
Source region 107, the drain region in the Semiconductor substrate 100 of the remote side of common source drain region 108 of selection transistor gate stack
109。
The performance of existing flash memories still has much room for improvement.
The content of the invention
The present invention solves the problems, such as it is how to improve the performance of flush memory device.
To solve the above problems, the invention provides a kind of forming method of semiconductor structure, including：Semiconductor lining is provided
Bottom, the Semiconductor substrate include logic region and some storage regions, and each storage region includes first area and with first
The adjacent some second areas in region；The first polysilicon layer is formed in the Semiconductor substrate of storage region；In the first polysilicon
Control gate dielectric layer is formed on layer；The part control gate dielectric layer on second area is etched, the is formed in gate dielectric layer is controlled
One opening, first opening expose the first polysilicon layer surface of second area；Served as a contrast in the semiconductor of the logic region
The second polysilicon layer, full first opening of the second polysilicon layer filling are formed on bottom and on the control gate dielectric layer of storage region；Carve
Etching off removes part second polysilicon layer, control gate dielectric layer and the first polysilicon layer between neighbouring storage areas, exposure
Go out the first area of Semiconductor substrate and the part surface of second area；Part the between the opening of etching first and second area
Two polysilicon layers, form the second opening for exposing control gate dielectric layer surface in the second polysilicon layer, and the second opening is by the
The second polysilicon layer on the second polysilicon layer and second area on one region disconnects, in the Semiconductor substrate on second area
The polysilicon layer of part first and the second polysilicon layer form flush memory device coupling grid, the Semiconductor substrate top of first area
The first polysilicon layer is divided to form the floating boom of flush memory device, coupling grid are electrically connected with floating boom by the polysilicon layer of part first, and first
The second polysilicon layer on the control gate dielectric layer in region forms the control gate of flush memory device；Etch the second polycrystalline of logic region
Silicon layer, form the grid of logic transistor；The first offset side wall is formed in the side wall of the grid of the logic transistor, is being patrolled
Collect the shallow doped region that logic transistor is formed in the Semiconductor substrate of the logic region of the grid both sides of transistor；Coupling grid,
The second offset side wall is formed in the side wall of control gate and selection grid, the second area in the side of coupling grid, control gate and floating boom
With the shallow doped region that flush memory device is formed in the Semiconductor substrate of first area.
Optionally, the thickness of first offset side wall is less than the thickness of the second offset side wall.
Optionally, the shallow doped region of flush memory device is formed after the shallow doped region of logic transistor is formed.
Optionally, the thickness of second offset side wall is 20~700 angstroms.
Optionally, after the grid for coupling grid, control gate, floating boom and logic transistor of flush memory device is formed, coupling
Grid, control gate, the surface of grid of floating boom and logic transistor form oxide layer.
Optionally, the oxide layer is formed using boiler tube thermal oxidation technology.
Optionally, it is described control in gate dielectric layer the first opening forming process be：The shape on the control gate dielectric layer
Into the first patterned photoresist layer, the first patterned photoresist layer exposes the region that control gate dielectric layer needs to etch；
Using the described first patterned photoresist layer as mask, the control gate dielectric layer is etched, is formed in gate dielectric layer is controlled
One opening.
Optionally, etch the control gate dielectric layer and use plasma etching industrial, what plasma etch process used
Gas is CF4、C4F8、C5F8、C4F6、CH3F、CH2F2In one or more.
Optionally, when etching controls gate dielectric layer, the first polysilicon layer of over etching segment thickness, to be formed first is made
Opening portion is located in the first polysilicon layer.
Optionally, the thickness of the first polysilicon layer over etching is 20~100 angstroms.
Optionally, the forming process of second opening is：The photoetching of second graphical is formed on the second polysilicon layer
Glue-line, the photoresist layer of the second graphical expose the region that the second polysilicon layer needs to etch；With the second graph
The photoresist layer of change is mask, etches second polysilicon layer, and second is formed in the second polysilicon layer and is open, described second
Opening disconnects the second polysilicon layer on the second polysilicon layer and second area on first area.
Optionally, etch second polysilicon layer and use plasma etching industrial.
Optionally, the gas that the plasma etch process uses is HBr, Cl2、SF6In one or more.
Optionally, before the first polysilicon layer is formed, tunnel oxide is formed on a semiconductor substrate.
It is optionally, described that to control gate dielectric layer be multilayer lamination structure.
Optionally, it is described to control the three level stack structure that gate dielectric layer is silicon oxide layer-silicon nitride-silicon oxide layer.
Optionally, the first master wall is formed on the first offset side wall surface；Is formed on the second offset side wall surface
Two master walls.
Optionally, the Semiconductor substrate of the logic region of the first master wall both sides in coupling cascode logic transistor side wall
The interior deep doped region for forming coupling cascode logic transistor；The second master wall side on coupling grid, control gate and floating gate side walls
Second area and first area Semiconductor substrate in formed flush memory device deep doped region.
Optionally, each storage region also includes the 3rd region, and the 3rd region is located at remote the second of first area
The side in region.
Optionally, the first polysilicon layer, control gate dielectric layer and the second polysilicon layer cover the semiconductor lining in the 3rd region
Bottom, formed with the 3rd opening, the opening of the second polysilicon layer filling the 3rd in the control gate dielectric layer in the 3rd region；The 3rd is etched to open
The second polysilicon layer, control gate dielectric layer and the first polysilicon layer between mouth and second area, form in the 3rd region and select
Grid.
Compared with prior art, technical scheme has advantages below：
First etching removes the polysilicon layer of part second, forms the second opening, the second opening is by more than second on first area
The second polysilicon layer on crystal silicon layer and second area disconnects；After the second opening is formed, the side wall of the grid of logic transistor
The first offset side wall of upper formation, forms logic crystal in the Semiconductor substrate of the logic region of the grid both sides of logic transistor
The shallow doped region of pipe；The second offset side wall is formed in the side wall of coupling grid, control gate and selection grid, in coupling grid, control gate
It is real with the shallow doped region present invention of formation flush memory device in the second area of the side of floating boom and the Semiconductor substrate of first area
The second polysilicon layer that first area and second area are first disconnected in example is applied, then forms the first offset side wall and the second skew side
Wall, when forming the second opening in the second polysilicon layer, prevent the first offset side wall or the second offset side wall material to etching the
The influence of two polysilicon layer materials etching, prevent the residual of the second polysilicon layer material on the both ends of the second opening, it is therefore prevented that control
The leakage of electric current between grid processed and coupling grid.
Further, the thickness of first offset side wall is less than the thickness of the second offset side wall, is forming logic transistor
Shallow doped region after formed flush memory device shallow doped region so that after the shallow doped region of logic transistor and the shallow of flush memory device mix
Polygamy can be different, to meet that the electric property of the electric property of logic transistor and flush memory device differs.
Further, when etching controls gate dielectric layer, the first polysilicon layer of over etching segment thickness, to be formed first is made
Opening portion is located in the first polysilicon layer, prevents the residual of the control gate dielectric layer material in the first opening, influences follow-up shape
Into coupling grid electric property；The thickness of the first polysilicon layer over etching can be 20~100 angstroms, the first polysilicon layer
The too thick burden that can increase etching of over etching thickness, control gate Jie is easily caused if the first polysilicon layer over etching thickness is too thin
The residual of matter layer material.
Brief description of the drawings
Fig. 1~Fig. 4 is the structural representation of the flush memory device of prior art；
Fig. 5~Figure 12 is the structural representation of flush memory device forming process of the embodiment of the present invention.
Embodiment
Response speed is still slow at work for the flush memory device of prior art, and the performance of flush memory device is by larger shadow
Ring, in addition, the manufacture craft of the flush memory device of prior art would generally integrate with the manufacture craft of logic transistor, this will make
Into influencing each other between both manufacture crafts so that the device of formation produces defect.
The embodiments of the invention provide a kind of flush memory device, Fig. 2 refer to, the flush memory device, including：Semiconductor substrate
200, the Semiconductor substrate 200 includes first area 11 and the second area 12 adjacent with first area 11；Positioned at semiconductor
Tunnel oxide 201 on substrate 200, the first polysilicon layer 203 on tunnel oxide 201, positioned at the first polysilicon
Control gate dielectric layer 204 on layer 203, there is the first opening, first opening in the control gate dielectric layer 204 of first area
Expose the polysilicon layer 203 of first area 11 first；The second polysilicon layer 205 on control gate dielectric layer 204, described the
There is the second opening 206 for exposing control gate dielectric layer 204 surface, second opening 206 is by the in two polysilicon layers 205
Second polysilicon layer 205 in one region 11 and the second polycrystal layer 205 of second area 12 disconnect, wherein the portion on first area 11
Point floating boom of first polysilicon layer 203 as flush memory device, the second polysilicon layer 205 on first area 11 are used as flush memory device
Control gate, the first polysilicon layer of part 203 on the second polysilicon layer 205 and second area 12 on second area 12 forms
The coupling grid of flush memory device, grid are coupled on the second area 12 and pass through the part between first area 11 and second area 12 the
One polysilicon layer 203 is connected with the floating boom of first area 11, the coupling grid and floating boom and control gate dielectric layer 204 and control
Grid form capacitance structure, and capacitance structure is used to couple the voltage applied on control gate, adjusts the electric current of flash cell, carry
The speed of response of high flash cell and sensitivity.
The integrated manufacturing process of above-mentioned flush memory device and logic transistor is：
First, with reference to figure 2, there is provided Semiconductor substrate 200, the Semiconductor substrate 200 include logic region and some deposited
Storage area domain, each storage region include first area 11 and the second area 12 adjacent with first area 11；In Semiconductor substrate
Tunnel oxide 201 is formed on 200；The first polysilicon layer 203 is formed on the tunnel oxide 201 of storage region；First
Control gate dielectric layer 204 on polysilicon layer 203；The control gate dielectric layer 204 of second area 12 is etched, in second area 12
The first opening for exposing the surface of the first polysilicon layer 203 is formed in control gate dielectric layer 204；It is situated between in the control gate of storage region
The second polysilicon layer 205 is formed in the Semiconductor substrate 200 of matter layer 204 and logic region, second polysilicon layer 205 is filled
First opening；Etching removes the second polysilicon layer of part 205, the control gate dielectric layer 204 and first between neighbouring storage areas
Polysilicon layer 203, by the second polysilicon layer 205 between neighbouring storage areas, the control polysilicon layer of gate dielectric layer 204 and first
203 disconnect, and expose the part surface of first area 11 and second area 12；First area 11 upon opening and second area
The second polysilicon layer 205 on 12, the skew of formation first side in the side wall of the control polysilicon layer 203 of gate dielectric layer 204 and first
Wall 207.
Then, with reference to referring to figs. 2 and 3 the overlooking the structure diagram that, Fig. 3 is Fig. 2, Fig. 2 is Fig. 3 along line of cut AB directions
Cross-sectional view, be mask with first offset side wall 207, to the He of first area 11 of the side of offset side wall 207
The Semiconductor substrate 200 of second area 12 carries out shallow Doped ions injection, in the first area 11 of the side of the first offset side wall 207
With the shallow doped region (not shown) that flush memory device is formed in the 12 of second area Semiconductor substrate 200；Forming flash memory
After the shallow doped region of device, etching removes the second polysilicon layer of part 205 between first area 11 and second area 12, the
The second opening 206 is formed in two polysilicon layers 205, second opening 206 exposes control gate dielectric layer 204 surface, described
Second opening 206 disconnects the second polysilicon layer 205 of the second polysilicon layer 205 of first area 11 and second area 12, its
Part 203 floating boom as flush memory device of the first polysilicon layer on middle first area 11, the second polycrystalline on first area 11
Control gate of the silicon layer 205 as flush memory device, the part on the second polysilicon layer 205 and second area 12 on second area 12
First polysilicon layer 203 forms the coupling grid of flush memory device, and grid are coupled on the second area 12 and pass through first area 11 and the
The polysilicon layer of part first between two regions 12 is connected with the floating boom of first area 11；The part on logic region is etched simultaneously
Second polysilicon layer, form the grid of logic transistor.
The second offset side wall is formed on the gate lateral wall of logic transistor, the semiconductor in the second offset side wall both sides serves as a contrast
The shallow doped region of logic transistor is formed on bottom.
With reference to being cross-sectional views of the Fig. 3 along line of cut CD directions with reference to figure 3 and Fig. 4, Fig. 4, the He of first area 11
The formation of the grid of the disconnection of second polysilicon layer 205 of second area 12 and the logic transistor of logic region is in same technique
Step is completed, but when etching removes the material of the second polysilicon layer of part 205 and forms the second opening 206, due to the second polycrystalline
The both ends sidewall surfaces along line of cut CD directions of silicon layer 205 are covered by the first offset side wall 207, with the first offset side wall 207
The material of the second polysilicon layer of part 205 of contact position is difficult to be removed, and causes the residual 209 of the material of the second polysilicon layer 205, the
The residual 209 of the material of two polysilicon layer 205 easily causes control gate and couples the leakage of electric current between grid, have impact on flush memory device
Performance.
To solve the above problems, the embodiments of the invention provide a kind of forming method of semiconductor structure, first is first disconnected
Region and the second polysilicon layer of second area, then form the first offset side wall and the second offset side wall, in the second polysilicon
When forming the second opening in layer, prevent the first offset side wall or the second offset side wall material from being carved to the second polysilicon layer material of etching
The influence of erosion, prevent the residual of the second polysilicon layer material on the both ends of the second opening, it is therefore prevented that between control gate and coupling grid
The leakage of electric current.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.When the embodiment of the present invention is described in detail, for purposes of illustration only, schematic diagram can disobey general proportion
Make partial enlargement, and the schematic diagram is example, and it should not be limited the scope of the invention herein.In addition, in reality
The three-dimensional space of length, width and depth should be included in making.
Fig. 5~Figure 12 is the structural representation of flush memory device forming process of the embodiment of the present invention.
With reference to figure 5, there is provided Semiconductor substrate 300, the Semiconductor substrate 300 include first area 11 and with the firstth area
The adjacent second area 12 in domain 11；The first polysilicon is formed on the first area 11 of Semiconductor substrate 300 and second area 12
Layer 303；Control gate dielectric layer 304 is formed on the first polysilicon layer 303.
The material of the Semiconductor substrate 300 can be silicon (Si), germanium (Ge) or SiGe (GeSi), carborundum (SiC)；
Can also be silicon-on-insulator (SOI), germanium on insulator (GOI)；Or can also be other materials, such as GaAs etc.
III-V compounds of group.The Semiconductor substrate 300 can also inject certain Doped ions to change electricity according to design requirement
Parameter.Fleet plough groove isolation structure (not shown), the shallow trench isolation junction are also formed with the Semiconductor substrate 300
Structure is used to isolate adjacent flash cell.
The Semiconductor substrate 300 includes logic region (not shown) and some storage regions, the logic region
On be subsequently formed the grid of logic transistor, some storage regions are distributed in Semiconductor substrate 300 in ranks, each memory block
A memory cell of flush memory device is subsequently formed on domain, each storage region includes first area 11 and first area 11 is adjacent
Second area 12, the floating boom and control gate of flush memory device, semiconductor lining are subsequently formed on the first area of Semiconductor substrate 300
The coupling grid of flush memory device are subsequently formed on the second area 12 at bottom 300.It should be noted that for convenience of explanation, this implementation
Example is only used as using a storage region in Semiconductor substrate 300 in example.
Each storage region in the Semiconductor substrate 300 also includes the 3rd region (not shown), the 3rd region
Positioned at the side of the remote second area 12 of first area 11, flash memories are subsequently formed on the 3rd region of Semiconductor substrate 300
The selection grid of part.
Flash memory is formed on each first area 11 and the adjacent region of second area 12 and the 3rd in Semiconductor substrate 300
The flash cell of device.
Tunnel oxide 301 is formed in the Semiconductor substrate 300.The tunnel oxide 301 passes through chemical gaseous phase
Depositing operation or thermal oxidation technology are formed, and the thickness of tunnel oxide 301 is 20~150 angstroms.
After tunnel oxide 301 is formed, the first polysilicon layer 303 is formed on the tunnel oxide 301 of storage region,
The first polysilicon layer of part 303 of first area 11 is subsequently formed the floating boom of flush memory device, the part more than first of second area 12
Crystal silicon layer 303 is subsequently formed the coupling grid of flush memory device, the polysilicon of part first between first area 11 and second area 12
Layer 303 is used to connect coupling grid and floating boom, first polysilicon layer in the 3rd region are subsequently formed the selection grid of flush memory device.
First polysilicon layer 303 is formed by chemical vapor deposition method, and the thickness of the first polysilicon layer 303 is
500~1500 angstroms, after the first polysilicon layer is formed in Semiconductor substrate 300, remove the first polysilicon layer of logic region.
Control gate dielectric layer 304 is formed on first polysilicon layer 303, control is formed in Semiconductor substrate 300
After gate dielectric layer, the control gate dielectric layer of logic region is removed.
The control gate dielectric layer 304 can be single or multiple lift stacked structure (multilayer refers to more than or equal to two layers).
In one embodiment, the control gate dielectric layer 304 is three layers of heap of silicon oxide layer-silicon nitride-silicon oxide layer
Stack structure.
With reference to figure 6, the part control gate dielectric layer 304 on second area is etched, the is formed in gate dielectric layer 304 is controlled
One opening 302, first opening 302 expose the surface of the first polysilicon layer 303 of second area 12.
Before the control gate dielectric layer 304 is etched, formation first is patterned on the control gate dielectric layer 304
Photoresist layer, the first patterned photoresist layer expose the region that control gate dielectric layer 304 needs to etch；With first figure
The photoresist layer of shape is mask, the control gate dielectric layer 304 is etched, in the control gate dielectric layer 304 of second area 12
Form the first opening 302.
Etch the control gate dielectric layer 304 and use plasma etching industrial, the gas that plasma etch process uses
For CF4、C4F8、C5F8、C4F6、CH3F、CH2F2In one or more.
In one embodiment, when etching controls gate dielectric layer 304, the first polysilicon layer 303 of over etching segment thickness,
The first 302 parts of opening for making to be formed are located in the first polysilicon layer 303, prevent the control gate dielectric layer material in the first opening
Residual, the electric property for the coupling grid for influenceing to be subsequently formed.
The too thick burden that can increase etching of the over etching thickness of first polysilicon layer 303, the over etching of the first polysilicon layer 303 are thick
Easily cause the residual of the control material of gate dielectric layer 304 if degree is too thin, in the present embodiment, the mistake of the first polysilicon layer 303
The thickness of etching can be 20~100 angstroms.Subsequently when forming the second polysilicon layer on controlling gate dielectric layer 304, described first
Opening 302 is follow-up as the second polysilicon layer of second area 12 and the interface channel of the first polysilicon layer 303, second area 12
On the first polysilicon layer for linking together and the second polysilicon layer be subsequently formed coupling grid.
In one embodiment, while etching part control gate dielectric layer 304 of second area 12, the 3rd region of etching
Part control gate dielectric layer, in the control gate dielectric layer in the 3rd region formation expose first polysilicon layer in the 3rd region
3rd opening, subsequently when forming the second polysilicon layer on controlling gate dielectric layer 304, the 3rd opening is as the 3rd region
The interface channel of second polysilicon layer and the first polysilicon layer, the first polysilicon layer and second to link together on the 3rd region
Polysilicon layer is subsequently formed selection grid.
With reference to figure 7, the second polysilicon layer 305 is formed on the control gate dielectric layer 304, the second polysilicon layer 305 is filled out
Full of the first 302 (with reference to figures 6) of opening.
Second polysilicon layer 305 is formed by chemical vapor deposition method, the second polysilicon layer 305 filling full the
One opening, the second polysilicon layer 305 of second area 12 are connected by the first opening with the first polysilicon layer 303.
In one embodiment, formed in the control gate dielectric layer on full 3rd region of the filling of the second polysilicon layer 305
Second opening.
The surface of the second polysilicon layer also Semiconductor substrate of covering logic region (not shown).Logic region
The second polysilicon layer be subsequently formed the grid of logic transistor.
It is Fig. 8 overlooking the structure diagram with reference to figure 8 and Fig. 9, Fig. 9, Fig. 8 is section knots of the Fig. 9 along line of cut AB directions
Structure schematic diagram, etching remove part second polysilicon layer 305, control gate dielectric layer 304 and between neighbouring storage areas
First polysilicon layer 303, expose the part surface of first area 11 and second area 12.
Etch second polysilicon layer 305, control the technique of the polysilicon layer 303 of gate dielectric layer 304 and first for it is each to
The dry etching of the opposite sex, for example can be plasma etching.
Break by the second polysilicon layer 305 between storage region, the control polysilicon layer 303 of gate dielectric layer 304 and first
While opening, etching removes the polycrystalline of part second between the 3rd opening of the region (not shown) of first area 11 and the 3rd
Silicon layer 305,303 layers of 304 and first polysilicon layer of control gate dielectric layer, flash memories are formed in the Semiconductor substrate in the 3rd region
The selection grid of part, the selection grid include：On first polysilicon layer and the first polysilicon layer the first polycrystalline is opened on by the 3rd
Second polysilicon layer of silicon layer connection.
In the embodiment of the present invention, selection grid is that two-layer polysilicon layer forms (the first polysilicon layer and the second polysilicon layer),
The grid for the logic transistor being subsequently formed is that one layer of polysilicon layer forms (the second polysilicon layer), i.e., the thickness of selection grid can be big
In the thickness of logic gate, to realize the regulation of different threshold voltages.
Also include：The doped N-type foreign ion in the polysilicon layer of part second of logic region, the N-type impurity ion
For adjusting the reaction rate of the N-type logic transistor and p-type logic transistor that are formed subsequently through the second polysilicon layer of etching,
The grid of N-type logic transistor wherein is formed doped with the second polysilicon layer of N-type impurity ion, undoped with N-type impurity ion
The second polysilicon layer formed p-type logic transistor grid.
The N-type impurity ion is the one or more in phosphonium ion, arsenic ion, antimony ion.
It is cross-sectional views of the Figure 10 along line of cut AB directions with reference to figure 10 and Figure 11, Figure 11, the opening of etching first
The second polysilicon layer of part 305 between 302 and second area 12, formed in the second polysilicon layer 305 and expose control gate
Second opening 306 on the surface of dielectric layer 304, the second opening 306 is by the second polysilicon layer 305 on first area 11 and the secondth area
The second polysilicon layer 305 on domain 12 disconnects, the polysilicon layer of part first in the Semiconductor substrate 300 on second area 12
303 and second polysilicon layer 305 form coupling grid, the first polysilicon layer of upper part 303 of Semiconductor substrate 300 of first area 11
Floating boom is formed, grid is coupled and floating boom is electrically connected by the first polysilicon layer of part 303 between first area 11 and second area 12
Connect, the second polysilicon layer 305 on the control gate dielectric layer 304 of first area 11 forms control gate.
It is described second opening 306 forming process be：The photoresist of second graphical is formed on the second polysilicon layer 305
Layer (not shown), the photoresist layer of the second graphical expose the region that the second polysilicon layer 305 needs to etch；With
The photoresist layer of the second graphical is mask, etches second polysilicon layer 305, the shape in the second polysilicon layer 305
Into the second opening 306, second opening 306 is by the second polysilicon layer 305 and second area 12 on first area 11
Second polysilicon layer 305 disconnects.
The coupling grid form capacitance structure with floating boom and control gate dielectric layer and control gate, and capacitance structure is used for control
The voltage applied on grid processed is coupled, and adjusts the electric current of flash cell, improves the speed of response and the sensitivity of flash cell.
Etch second polysilicon layer 305 and use plasma etching industrial, what the plasma etch process used
Gas is HBr, Cl2、SF6In one or more.
In the present embodiment, etch the second polysilicon layer 305 formed second opening 306 before, due to second opening 306
Spacer material is not formed in the both ends side wall of second polysilicon layer 305 of corresponding region, therefore is etching the second polysilicon layer
During 305, spacer material will not have an impact to etching process, and form the second polycrystalline at the both ends of the second opening 306
The residual of silicon materials.
While the second opening 306 is formed in the second polysilicon layer 305, the second polysilicon layer of logic region is etched,
The grid of logic transistor is formed in the Semiconductor substrate of logic region.The control of the grid and flush memory device of logic transistor
Grid and part coupling grid are all to etch to be formed using the polysilicon layer of same layer second, the thickness phase of the second polysilicon layer to be etched
Together, thus the formation of the second opening and the etching of grid of logic transistor use same step etching technics, reduction etching technics
Otherness, reduce cost of manufacture.
The logic transistor includes N-type transistor and P-type transistor, and the logic transistor may be constructed control circuit
The operations such as reading, write-in and erasing to flush memory device are controlled.
Also include：After the grid for coupling grid, control gate, floating boom and logic transistor of flush memory device is formed, coupling
Grid, control gate, the surface of grid of floating boom and logic transistor form oxide layer, to repair the damage in etching process.
With reference to figure 12, the second offset side wall 308 is formed in the side wall of coupling grid, control gate and selection grid, coupling grid,
The shallow of flush memory device is formed in the second area 12 of the side of control gate and floating boom and the Semiconductor substrate 300 of first area 11 to mix
Miscellaneous area's (not shown).
Because the electric property of logic transistor and the electric property of flush memory device differ, thus logic transistor is shallow
Doped region with the distance, Doped ions type and depth of grid and the shallow doped region of flush memory device and floating boom and couple grid away from
Differed from, Doped ions type and depth, thus the shallow doped region of flush memory device formation and logic transistor it is shallow
The formation of doped region is different steps.
In the present embodiment, before the second offset side wall is formed, formed in the side wall of the grid of the logic transistor
First offset side wall (not shown), formed and patrolled in the Semiconductor substrate of the logic region of the grid both sides of logic transistor
Collect the shallow doped region of transistor.
The forming process of first offset side wall is：Form the Semiconductor substrate for covering the storage region and logic is brilliant
First spacer material layer of the grid of body pipe；Without the first spacer material layer described in mask etching, in the gate electrode side of logic transistor
The first offset side wall is formed on wall.
After the first offset side wall is formed, ion implanting is carried out to the Semiconductor substrates of the first offset side wall both sides, the
The shallow doped region of logic transistor is formed in the Semiconductor substrate of one offset side wall both sides.
In one embodiment, when forming the first offset side wall in the both sides of the logic transistor of logic region, storage region
Coupling grid, control gate and floating boom side wall on can also form the first offset side wall, the first skew side of the storage region
A part of the wall as the second offset side wall.
In another embodiment, when forming the first offset side wall in the both sides of the logic transistor of logic region, memory block
Coupling grid, control gate and the floating boom in domain are covered by photoresist mask, will not be formed in the side wall of coupling grid, control gate and floating boom
First offset side wall.
After forming the shallow doped region of the first offset side wall and logic transistor, the second offset side wall 308 and flash memories are formed
The shallow doped region of part, the thickness of second offset side wall 308 are more than the thickness of the first offset side wall.
The forming process of second offset side wall 308 is：Formed the covering coupling grid, control gate and floating boom surface with
And the second spacer material layer on the surface of Semiconductor substrate 300 of storage region；Without the second spacer material layer described in mask etching,
Couple in the second area 12 of the side of grid, control gate and floating boom and the Semiconductor substrate 300 of first area 11 and form flash memories
The shallow doped region of part.
Also include：The first master wall (not shown) is formed on the first offset side wall surface；In the second offset side wall
The second master wall (not shown) is formed on 308 surfaces；The first master wall both sides in coupling cascode logic transistor side wall
Semiconductor substrate 300 in formed coupling cascode logic transistor deep doped region (not shown)；Coupling grid, control gate and
Flash memories are formed in the second area 12 of the second master wall side on floating gate side walls and the Semiconductor substrate 300 of first area 11
The deep doped region (not shown) of part.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, this is not being departed from
In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope of restriction is defined.
Claims (20)
- A kind of 1. forming method of semiconductor structure, it is characterised in that including：Semiconductor substrate is provided, the Semiconductor substrate includes logic region and some storage regions, and each storage region includes First area and the second area adjacent with first area；The first polysilicon layer is formed in the Semiconductor substrate of storage region；Control gate dielectric layer is formed on the first polysilicon layer；The part control gate dielectric layer on second area is etched, the first opening is formed in gate dielectric layer is controlled, described first opens Mouth exposes the first polysilicon layer surface of second area；The second polysilicon layer is formed in the Semiconductor substrate of the logic region and on the control gate dielectric layer of storage region, the Full first opening of two polysilicon layers filling；Etching removes part second polysilicon layer, control gate dielectric layer and the first polysilicon between neighbouring storage areas Layer, exposes the first area of Semiconductor substrate and the part surface of second area；The polysilicon layer of part second between the opening of etching first and first area, formed in the second polysilicon layer and expose control Second opening on gate dielectric layer surface processed, second is open second on the second polysilicon layer and second area on first area Polysilicon layer disconnects, the polysilicon layer of part first and the second polysilicon layer composition flash memory in Semiconductor substrate on second area The coupling grid of device, the polysilicon layer of Semiconductor substrate upper part first of first area form the floating boom of flush memory device, couple grid Electrically connected with floating boom by the polysilicon layer of part first, the second polysilicon layer on the control gate dielectric layer of first area, which is formed, to be dodged The control gate of memory device；The second polysilicon layer of logic region is etched simultaneously, forms the grid of logic transistor；The first offset side wall is formed in the side wall of the grid of the logic transistor, in patrolling for the grid both sides of logic transistor Collect the shallow doped region that logic transistor is formed in the Semiconductor substrate in region；The second offset side wall is formed in the side wall of coupling grid, control gate and selection grid, the one of coupling grid, control gate and floating boom The shallow doped region of flush memory device is formed in the second area of side and the Semiconductor substrate of first area.
- 2. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the thickness of first offset side wall Less than the thickness of the second offset side wall.
- 3. the forming method of semiconductor structure as claimed in claim 2, it is characterised in that mixed forming the shallow of logic transistor The shallow doped region of flush memory device is formed behind miscellaneous area.
- 4. the forming method of semiconductor structure as claimed in claim 2, it is characterised in that the thickness of second offset side wall For 20~700 angstroms.
- 5. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that forming the coupling of flush memory device Grid, control gate, floating boom and logic transistor grid after, in the table of the grid of coupling grid, control gate, floating boom and logic transistor Face forms oxide layer.
- 6. the forming method of semiconductor structure as claimed in claim 5, it is characterised in that the oxide layer uses the hot oxygen of boiler tube Chemical industry skill is formed.
- 7. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that first in the control gate dielectric layer The forming process of opening is：The first patterned photoresist layer, the first patterned light are formed on the control gate dielectric layer Photoresist layer exposes the region that control gate dielectric layer needs to etch；Using the described first patterned photoresist layer as mask, etching The control gate dielectric layer, the first opening is formed in gate dielectric layer is controlled.
- 8. the forming method of semiconductor structure as claimed in claim 7, it is characterised in that the etching control gate dielectric layer is adopted With plasma etching industrial, the gas that plasma etch process uses is CF4、C4F8、C5F8、C4F6、CH3F、CH2F2In one Kind is several.
- 9. the forming method of semiconductor structure as claimed in claim 7, it is characterised in that when etching controls gate dielectric layer, First polysilicon layer of over etching segment thickness, the first opening portion to be formed is set to be located in the first polysilicon layer.
- 10. the forming method of semiconductor structure as claimed in claim 9, it is characterised in that it's quarter pasts first polysilicon layer The thickness of erosion is 20~100 angstroms.
- 11. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the formation of second opening Cheng Wei：The photoresist layer of second graphical is formed on the second polysilicon layer, the photoresist layer of the second graphical exposes Second polysilicon layer needs the region etched；Using the photoresist layer of the second graphical as mask, second polycrystalline is etched Silicon layer, forms the second opening in the second polysilicon layer, and second opening is by the second polysilicon layer on first area and the The second polysilicon layer on two regions disconnects.
- 12. the forming method of semiconductor structure as claimed in claim 11, it is characterised in that etching second polysilicon layer Using plasma etching industrial.
- 13. the forming method of semiconductor structure as claimed in claim 12, it is characterised in that the plasma etch process The gas used is HBr, Cl2、SF6In one or more.
- 14. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that formed the first polysilicon layer it Before, tunnel oxide is formed on a semiconductor substrate.
- 15. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that described to control gate dielectric layer be more Layer stacked structure.
- 16. the forming method of semiconductor structure as claimed in claim 15, it is characterised in that described to control gate dielectric layer be oxygen The three level stack structure of SiClx layer-silicon nitride layer-silicon oxide layer.
- 17. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that on the first offset side wall surface Form the first master wall；The second master wall is formed on the second offset side wall surface.
- 18. the forming method of semiconductor structure as claimed in claim 17, it is characterised in that in coupling cascode logic transistor side The deep doped region of coupling cascode logic transistor is formed in the Semiconductor substrate of the logic region of the first master wall both sides on wall； Couple shape in grid, control gate and the second area of the second master wall side on floating gate side walls and the Semiconductor substrate of first area Into the deep doped region of flush memory device.
- 19. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that each storage region is also wrapped The 3rd region is included, the 3rd region is located at the side of the remote second area of first area.
- 20. the forming method of semiconductor structure as claimed in claim 19, it is characterised in that the first polysilicon layer, control gate Dielectric layer and the second polysilicon layer cover the Semiconductor substrate in the 3rd region, formed with the in the control gate dielectric layer in the 3rd region Three openings, the opening of the second polysilicon layer filling the 3rd；Etch the second polysilicon layer between the 3rd opening and second area, control Gate dielectric layer and the first polysilicon layer, selection grid is formed in the 3rd region.
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| CN1508874A (en) * | 2002-10-07 | 2004-06-30 | ǰѶϵͳ�ɷ�����˾ | Flash memory cells and fabrication process thereof |
| JP2006253709A (en) * | 2006-05-02 | 2006-09-21 | Toshiba Corp | Semiconductor device and manufacturing method therefor |
| CN102368479A (en) * | 2011-11-24 | 2012-03-07 | 上海宏力半导体制造有限公司 | Flash memory and manufacturing method thereof |
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| JP2003197781A (en) * | 2001-12-27 | 2003-07-11 | Toshiba Corp | Semiconductor device and its manufacturing method |
| CN1508874A (en) * | 2002-10-07 | 2004-06-30 | ǰѶϵͳ�ɷ�����˾ | Flash memory cells and fabrication process thereof |
| JP2006253709A (en) * | 2006-05-02 | 2006-09-21 | Toshiba Corp | Semiconductor device and manufacturing method therefor |
| CN102368479A (en) * | 2011-11-24 | 2012-03-07 | 上海宏力半导体制造有限公司 | Flash memory and manufacturing method thereof |
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