CN105137320B - Compatible compression method between the packet test vector to be reordered based on test pattern - Google Patents
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Abstract
The invention discloses the compatible compression method between a kind of packet test vector to be reordered based on test pattern, test pattern is carried out again to the test vector after compression to reorder, then the test vector after reorder such as carries out at point packet, so that the complete incompatible test vector packet after reordering reaches approximate compatible afterwards, and then carry out the further compression of test vector.The present invention has advantages below compared with prior art：This scheme need not be very big decompression circuit structure, compatible test data compression packet test vector is considered further that after being reordered test data, so using when being grouped that compatibility is to compress the test vector after reordering between test vector, it can preferably increase the compression ratio of test data.
Description
Technical field
The present invention relates to a kind of ic test technique, more particularly to a kind of compression method of data.
Background technology
With the continuous development of modern science and technology, the scale of IC is also increasingly increasing, and nowadays, has been developed as
Ultra-large integrated (the Very Large Scale Integrated of more than 10 hundred million transistors can be accommodated in an IC
Circuits, VLSI) circuit, and still in continuous increase.One of Intel (Intel) founder Gordon mole is 1965
Year proposes Moore's Law, and its content is：When price is constant, the upper open ended transistor sizes of IC, about every 18 months just
It can double, performance will also lift one times.Also expert thinks, the transistor feature size on IC is every year with about 10.5%
Speed reduce, increased every year with about 22.1% speed which results in the density of transistor.This imply that in circuit function
While stronger and stronger, the integrated level of circuit also increasingly increases, and circuit structure becomes increasingly sophisticated, thus also results in IC and answers
Polygamy is increased sharply.Under above-mentioned background, how to ensure digital IC reliability becomes people's research and the focus inquired into
Problem.And as one of deciding factor for ensureing circuit reliability, IC measuring technologies had both obtained long-range development, also ran into
Huge challenge.
DFT was referred under regular hour and cost reasons, by some designs, is reduced the difficulty of circuit test, is carried
The validity of height test.Pass through DFT, it is possible to control and observe that some are difficult to control and observed in primary circuit structure
Node.At present, DFT technique mainly has Scan Design (Scan Design), boundary scan testing (Boundary Scan
) and built-in self-test (BIST) etc. Test.Scan Design is one of widely used methods of DFT, and it, which can be greatly simplified, is
The test process of system, thus be increasingly taken seriously, a series of problems on sweep test also becomes the heat of people's research
Point, wherein, how effectively to reduce power consumptions of the digital IC during sweep test and have become academia in recent years and industrial quarters
The focal issue of common concern.
The main thought of Scan Design is to obtain the controllability and observability to sequential component.In Scan Design
In, all triggers series winding turns into shift register (being referred to as scan chain), and the logical value of trigger can be moved by scanning
Position observe, meanwhile, by scan shift, the logical value of any trigger can also be configured, inherently improved
The observability and controllability of test.In the Scan Design of actual circuit, all have scanning defeated if all of trigger
Enter output function, referred to as full scan designs；If only the trigger of part has scanning input/output function, referred to as portion
Divide Scan Design.Full scan design is one of most important DFT method, and it is connected all triggers by some logical devices
Pick up and, make all triggers that all there is full controllability and full observability, so as to add test pattern to circuit.In test mould
Under formula, whole triggers form one or more scan chain.Because trigger obtains its logical value realized by scanning displacement
, so whole triggers all can be configured to the logical value of any desired.Although full scan design can be from largely
The complexity of Self -adaptive is reduced, but also result in higher power consumption.In shifting process is scanned, substantial amounts of jump is generated
Become：Saltus step between saltus step, response and test and excitation inside test and excitation and combined as caused by saltus step inside scan chain
Circuit saltus step etc..Substantial amounts of saltus step makes full scan test have higher power consumption, and power problemses have become full scan test
One of sixty-four dollar question in research.
From the perspective of solving current problem, Scan Design is that test and excitation is swept into scan chain, enters circuit
Enter test pattern, test and excitation is input to by combinational circuit by scan chain, test response is captured in next clock cycle, with
Test response is scanned out into scan chain afterwards to be observed.Scan chain is swept into test and excitation and test response scans out the process of scan chain
In, the combinational circuit being connected inside scan chain and with it has substantial amounts of saltus step.
From the point of view of the effect of various Scan Design technologies, the scan chain technology that reorders passes through to test vector and scanning element
Resequenced, be a kind of good scheme.By selecting the path order of minimum cost come test pattern of resequencing, with
Reduce the power consumption of test.
Found by the research to source test set, quantify the degree of association between each scanning element；Then according to any two
The degree of association between scanning element is the degree of association figure this test set construction scanning element；Searched most using degree of association figure
Big hamiltonian circuit, then the maximum hamiltonian circuit found is interrupted, it is calculated to each Hamilton path of interruption
The cost needed；Finally using the Hamilton path order for having minimum cost come test pattern of resequencing.But arrange again
Between the good test vector of sequence, their compatibility is still very low.
The content of the invention
It is an object of the invention to overcome the deficiencies of the prior art and provide a kind of packet reordered based on test pattern
Compatible compression method between test vector, compress the test vector after reordering using compatibility is grouped between test vector
When, it can preferably increase the compression ratio of test data.
The present invention is achieved by the following technical solutions, a kind of packet test vector to be reordered based on test pattern it
Between compatible compression method, carry out test pattern again to the test vector after compression and reorder, the then survey after reorder
Examination vector such as carries out at point packet so that reaches approximate compatible after the complete incompatible test vector packet after reordering,
And then carry out the further compression of test vector.
Compatible compression scheme between the packet test vector to be reordered based on test pattern is comprised the following steps that：
Step 1. obtain test vector it is any two row between the degree of association, i.e., every two row test pattern of test vector it
Between the size of the degree of association be equal in test pattern cube, this two row test pattern possesses the number of identical logical values divided by every
The number of one row test pattern cube, because this degree of association decides the probability of the generation saltus step between this two row test pattern,
So the stronger test pattern of the degree of association will be arranged in adjacent position as far as possible, reduce and produce saltus step between test pattern
Probability；
Step 2. constructs degree of association figure, after the degree of association between obtaining test pattern, we just construct one it is complete undirected
Figure is referred to as degree of association figure, and degree of association figure includes the test pattern of the line, here vertex representation each column between summit and summit, even
The power of line is the degree of association of adjacent vertex；
Step 3. searches the hamiltonian circuit of maximum on associated diagram, and ours is TSP algorithms here, by continuous
Iteration eventually finds a maximum loop, as hamiltonian circuit, to this hamiltonian circuit, remembers adjacent test mould
The degree of association between formula, so that next step calculates；
Step 4. searches minimum between adjacent test pattern successively to the maximum hamiltonian circuit obtained in step 3
Power, and interrupt the two adjacent test patterns, that is, obtain a cost minimum Hamilton path of cost, here cost
The effect of minimum Hamilton path is the possibility that identity logic position is different between adjacent test pattern is reached minimum,
It is (power of 1- adjacent vertexs) power sums all between each adjacent vertex, to hamiltonian circuit, finds in this loop
Weigh for the adjacent vertex of minimum when, if it is all minimum to have the power of several adjacent vertexs, the adjacent vertex of foremost is selected, from selection
This adjacent vertex on interrupt the minimum Hamilton path in this loop, as selection；
Step 5. rearranges test vector using the sortord of the Hamilton path of minimum；
Each test vector of step 6. reorder etc. point packet, its purpose is to make completely incompatible test
Vector is by that can reach the compatibility between group after packet, equivalent to reach approximate segmentation between test vector compatible；
The data block (including data block backwards-compatible with it) of each respective column of step 7. statistical packet test vector
The frequency of occurrences, the referenced data block that the higher data block of the frequency of occurrences in its each respective column is arranged as this, when each column is all looked for
When to its referenced data block, just as the reference vector of this test data set, deposited herein with reference to test vector
In first memory, the test vector after compression is stored in second memory for storage；
Step 8. carries out coding compression with reference to reference vector by corresponding group of each packet test vector, with reference vector pair
The data block compatibility that should be organized then boil down to 0, backwards-compatible then boil down to 1, incompatible, former data block is marked so that source is surveyed
Examination data set reaches good compression ratio, and the test data of compression is stored in second memory, to decompress, Ran Houzai
Next packet Test Vectors Compression is stored in second memory.
The present invention has advantages below compared with prior art：This scheme need not be very big decompression circuit structure,
Compatible test data compression packet test vector is considered further that after being reordered test data, is so surveyed using packet
When compatibility is to compress the test vector after reordering between examination vector, it can preferably increase the compression ratio of test data.
Brief description of the drawings
Fig. 1 is the total indirected graph made according to the degree of association between any two row in table 1 of the invention.
Embodiment
Embodiments of the invention are elaborated below, the present embodiment is carried out lower premised on technical solution of the present invention
Implement, give detailed embodiment and specific operating process, but protection scope of the present invention is not limited to following implementation
Example.
The characteristics of patent of the present invention is to consider further that test pattern reorders to the test vector after compression, then reorder
Test vector afterwards such as carries out at point packet so that can reach after the complete incompatible test vector packet after reordering
Approximate compatible effect.Here first quantify test vector it is any two row between the degree of association, this degree of association decide this two
The probability of generation saltus step between row test pattern.
The specific step of the coding compression of compatible compression scheme between the packet test vector to be reordered based on test pattern
Suddenly：
Step 1. obtain test vector it is any two row between the degree of association, i.e., every two row test pattern of test vector it
Between the degree of association size be equal in test pattern cube, this two row test pattern possesses number divided by the survey of identical logical values
The number of die trial formula cube, because this degree of association decides the probability of the generation saltus step between this two row test pattern, so closing
The stronger test pattern of connection degree will be arranged in adjacent position as far as possible, reduce the probability of generation saltus step between test pattern；
Step 2. constructs degree of association figure, after the degree of association between obtaining test pattern, we just construct one it is complete undirected
Figure is referred to as degree of association figure, and degree of association figure includes the test pattern of the line, here vertex representation each column between summit and summit, even
The power of line is the degree of association of adjacent vertex；
Step 3. searches the hamiltonian circuit of maximum on associated diagram, and ours is TSP algorithms here, by continuous
Iteration eventually finds a maximum loop, as hamiltonian circuit, to this hamiltonian circuit, remembers adjacent test mould
The degree of association between formula, so that next step calculates；
Step 4. searches minimum between adjacent test pattern successively to the maximum hamiltonian circuit obtained in step 3
Power, and interrupt the two adjacent test patterns, that is, obtain a cost minimum Hamilton path of cost, here cost
The effect of minimum Hamilton path is the possibility that identity logic position is different between adjacent test pattern is reached minimum,
It is (power of 1- adjacent vertexs) power sums all between each adjacent vertex, to hamiltonian circuit, finds in this loop
Weigh for the adjacent vertex of minimum when, if it is all minimum to have the power of several adjacent vertexs, the adjacent vertex of foremost is selected, from selection
This adjacent vertex on interrupt the minimum Hamilton path in this loop, as selection；
Step 5. rearranges test vector using the sortord of the Hamilton path of minimum；Here Hamilton
Path is the relatively optimal sequence that the source test data found concentrates row, according to this Hamilton path by source
Each column test pattern rearrangement in test set, you can obtain a test set rearranged；
Each test vector of step 6. reorder etc. point packet, its purpose is to make completely incompatible test
Vector is by that can reach the compatibility between group after packet, equivalent to reach approximate segmentation between test vector compatible；
The data block (including data block backwards-compatible with it) of each respective column of step 7. statistical packet test vector
The frequency of occurrences, the referenced data block that the higher data block of the frequency of occurrences in its each respective column is arranged as this, when each column is all looked for
When to its referenced data block, just as the reference vector of this test data set, deposited herein with reference to test vector
In first memory, the test vector after compression is stored in second memory for storage；
Step 8. carries out coding compression with reference to reference vector by corresponding group of each packet test vector, with reference vector pair
The data block compatibility that should be organized then boil down to 0, backwards-compatible then boil down to 1, incompatible, former data block is marked so that source is surveyed
Examination data set reaches good compression ratio, and the test data of compression is stored in second memory, to decompress, Ran Houzai
Next packet Test Vectors Compression is stored in second memory.
Compatible example between the packet test vector to be reordered based on test pattern：
We select to include 5 test vectors with a less completely incompatible source test set, the source test set, often
The length of individual test vector is 12, and such as table 1, we calculate the degree of association between any two row of test vector, that is, test to
The size of the degree of association between every two row test pattern of amount is equal in test pattern cube, and this two row test pattern possesses phase
With the number of logical value divided by the number of each row test pattern cube, we are with the source test set in table 1 below here, meter
Exemplified by calculating the degree of association between the 1st row and the 2nd row, the digit for the identical logical values that first row possesses with secondary series is 2, this
A total of 5 test vectors of source test set, namely the test pattern cube number of each row are 5, then degree of association of this two row
It is 2/5=0.4 to calculate, therefore the degree of association of first row and secondary series is 0.4, because arranging, itself is originally identical, here need not
The degree of association of itself is arranged, so it is 0 to arrange the degree of association of itself, according to such a algorithm, obtains appointing for test vector as shown in table 2
The degree of association between the row of meaning two.
The source test set of table 1
101000101010
010001101010
101110000001
000011101010
111101100001
The degree of association between any two row of the test vector of table 2
| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | |
| 1 | 0 | 0.4 | 1 | 0.8 | 0.4 | 0.2 | 0.4 | 0.4 | 0.2 | 0.4 | 0.2 | 0.8 |
| 2 | 0.4 | 0 | 0.4 | 0.6 | 0.2 | 0.8 | 0.6 | 0.6 | 0.4 | 0.6 | 0.4 | 0.6 |
| 3 | 1 | 0.4 | 0 | 0.8 | 0.4 | 0.2 | 0.4 | 0.4 | 0.2 | 0.4 | 0.2 | 0.8 |
| 4 | 0.8 | 0.6 | 0.8 | 0 | 0.6 | 0.4 | 0.2 | 0.6 | 0 | 0.6 | 0 | 1 |
| 5 | 0.4 | 0.2 | 0.4 | 0.6 | 0 | 0.4 | 0.2 | 0.6 | 0.4 | 0.6 | 0.4 | 0.6 |
| 6 | 0.2 | 0.8 | 0.2 | 0.4 | 0.4 | 0 | 0.8 | 0.4 | 0.6 | 0.4 | 0.6 | 0.4 |
| 7 | 0.4 | 0.6 | 0.4 | 0.2 | 0.2 | 0.8 | 0 | 0.2 | 0.8 | 0.2 | 0.8 | 0.2 |
| 8 | 0.4 | 0.6 | 0.4 | 0.6 | 0.6 | 0.4 | 0.2 | 0 | 0.4 | 1 | 0.4 | 0.6 |
| 9 | 0.2 | 0.4 | 0.2 | 0 | 0.4 | 0.6 | 0.8 | 0.4 | 0 | 0.4 | 1 | 0 |
| 10 | 0.4 | 0.6 | 0.4 | 0.6 | 0.6 | 0.4 | 0.2 | 1 | 0.4 | 0 | 0.4 | 0.6 |
| 11 | 0.2 | 0.4 | 0.2 | 0 | 0.4 | 0.6 | 0.8 | 0.4 | 1 | 0.4 | 0 | 0 |
| 12 | 0.8 | 0.6 | 0.8 | 1 | 0.6 | 0.4 | 0.2 | 0.6 | 0 | 0.6 | 0 | 0 |
One total indirected graph, as associated diagram are made according to the degree of association between any two row in table 1, as shown in figure 1, this
In power in associated diagram in each edge just do not put on the diagram, the power of adjacent vertex is shown in Table 2.
In associated diagram in Fig. 1, we search the hamiltonian circuit of maximum with TSP algorithms, i.e., on adjacent edge
Power loop maximum after being added.Because TSP algorithms are NP- difficulty problems, so the hamiltonian circuit obtained every time is all
It is not to determine.Here after we to Fig. 1 degree of association figure by carrying out successive ignition, the Kazakhstan of a relative maximum is finally given
Milton loop is 1 → 3 → 4 → 2 → 11 → 7 → 6 → 9 → 5 → 10 → 8 → 12 → 1. maximum hamiltonian cycles for acquisition
Road, it is all that minimum power is 0.4 that we search between adjacent summit 2 → 11 and 9 → 5 successively, then we select foremost
One adjacent vertex 2 → 11, and this hamiltonian circuit is interrupted between this adjacent summit, it is minimum to obtain a cost
The order of Hamilton path is 11 → 7 → 6 → 9 → 5 → 10 → 8 → 12 → 1 → 3 → 4 → 2, and then we are just according to selection
Hamilton path put in order to rearrange the source test set in table 1, such as table 3 of the test vector after rearrangement.
Test vector after the rearrangement of table 3
110100001100
111100000001
000010011110
111110000000
011000011111
We have discovered that the compatibility in the test set to reorder between any two test vector is not very high, in order to
Increase test data compression rate, the test vector decile to reorder is first grouped into every group of 4 data by we, such as table 4, thus
Incompatible test vector completely can be made to reach the compatibility raising of corresponding group between two test vectors, so as to reach test to
Approximation between amount is compatible.
Test vector after the packet of table 4
Be grouped test data set after, we count first row data block 1111 and with its anti-phase compatible data block 0000
The frequency occurred together is 3 times, and data block 1101,0110 frequency of occurrences are all 1 time, but the frequency of occurrences of data block 1111 is high
In its backwards-compatible data block 0000, so compression ratio in order to better improve, selects ginseng of the data block 1111 for first row
Examine data block；The frequency of occurrences of secondary series 0000 is 2 times, and the frequency of occurrences of data block 1001,1000,0001 is respectively 1 time, so selection
Data block 0000 is the referenced data block of secondary series；3rd row 1111 and occur together with its backwards-compatible data block 0000
Frequency is 2 times, and 0001 and the frequency that occurs together with its anti-phase compatible data block 1110 are 2 times, remaining data block 1100
The frequency of occurrences be 1 time, then the optional high data block of the frequency of occurrences is tertial referenced data block, and we select number here
It is the 3rd row referenced data block according to block 0001.Therefore in summary, the reference vector of the test data set of this packet is
111100000001, and store it in first memory, so as to following compression and decompression.
With reference to the reference vector in memory, first Test Vectors Compression is 1,101 0 1100 by we, and will storage
In second memory, decompressed in decompression machine；Then second test vector is with reference in first memory
It is 000 with reference to vector compression, remains stored in second memory, for the decompression in decompression machine；By that analogy,
Three Test Vectors Compressions are 1 1,001 1, and the 4th Test Vectors Compression is 0 1,000 0000, and the 5th test vector is still
For 0,110 00011111, because this three groups of data blocks and corresponding group of reference vector are incompatible or backwards-compatible.After compression
Test data block reduces 21, significantly improves its compression ratio.
Decompression procedure to the data block of compression is a parallel procedure decompressed in compression, to be said here, right
When compressed test vector is conciliate in compression, there is two memories here, first memory be used for storage always with reference to test to
Amount, second memory are used for the test data for storing compression, are easy to decompress, and the test data in this memory is
Dynamic change.At first row test vector coding boil down to 1,101 0 1100, and store it in second memory
In, just 1,101 1,111 1100 are decompressed into reference to the reference vector in first memory during decompression；When first test vector
After compression, just second test vector is compressed as 000, and stored it in second memory, be easy to solve
Pressure, just 1,111 0,000 0001 are decompressed into reference to the reference vector in first memory during decompression；By that analogy, per second compression
When all referring to the reference vector in first memory, and by the data storage after compression in second memory, decompression according to
So with reference to the reference vector in first memory, the compression vector in second memory is decompressed, to next survey
Examination vector be compressed with decompression when still, until this compression test set decompress finish untill.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all essences in the present invention
All any modification, equivalent and improvement made within refreshing and principle etc., should be included in the scope of the protection.
Claims (2)
1. the compatible compression method between a kind of packet test vector to be reordered based on test pattern, it is characterised in that right
Test vector after compression carries out test pattern and reordered again, and then the test vector after reorder such as carries out at point packet, makes
Reaches approximate compatible after complete incompatible test vector packet after must reordering, and then carry out test vector enters one
Step compression；
Compatible compression scheme between the packet test vector to be reordered based on test pattern is comprised the following steps that：
Step 1. obtains the degree of association between any two row of test vector, i.e., between every two row test pattern of test vector
The size of the degree of association is equal in test pattern cube, and this two row test pattern possesses the number of identical logical values divided by each row
The number of test pattern cube；
Step 2. constructs degree of association figure, and after the degree of association between obtaining test pattern, just one total indirected graph of construction is referred to as closing
Lian Dutu, degree of association figure include the test pattern of the line, here vertex representation each column between summit and summit, and the power of line is
The degree of association of adjacent vertex；
Step 3. searches the hamiltonian circuit of maximum on associated diagram, to this hamiltonian circuit, remembers adjacent test mould
The degree of association between formula；
Step 4. searches minimum power between adjacent test pattern to the maximum hamiltonian circuit that is obtained in step 3 successively,
And the two adjacent test patterns are interrupted, that is, a cost minimum Hamilton path of cost are obtained, to hamiltonian cycle
Road, find in this loop power for minimum adjacent vertex when, if the power for having several adjacent vertexs is all minimum, select foremost
Adjacent vertex, the minimum Hamilton path in this loop, as selection is interrupted from this adjacent vertex of selection；
Step 5. rearranges test vector using the sortord of the Hamilton path of minimum；
Each test vector of step 6. reorder etc. point packet；
The data block of each respective column of step 7. statistical packet test vector includes the appearance frequency of the data block backwards-compatible with it
Rate, the referenced data block that the higher data block of the frequency of occurrences in its each respective column is arranged as this, when each column all finds its
When referenced data block, just as the reference vector of this test data set, is stored in herein with reference to test vector
In one memory；
Step 8. carries out coding compression with reference to reference vector by corresponding group of each packet test vector, corresponding with reference vector group
Data block compatibility then boil down to 0, backwards-compatible then boil down to 1, incompatible, former data block is marked, by the test of compression
Data storage is in second memory, and to decompress, next packet Test Vectors Compression is then stored in second again
In memory.
2. the compatible compression side between the packet test vector according to claim 1 to be reordered based on test pattern
Method, it is characterised in that in the step 3, calculate hamiltonian circuit using TSP algorithms, one is eventually found by continuous iteration
Individual maximum loop, as hamiltonian circuit.
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