CN105097897A - Gate electrode, semiconductor device and manufacturing method thereof - Google Patents
Gate electrode, semiconductor device and manufacturing method thereof Download PDFInfo
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- CN105097897A CN105097897A CN201410218947.XA CN201410218947A CN105097897A CN 105097897 A CN105097897 A CN 105097897A CN 201410218947 A CN201410218947 A CN 201410218947A CN 105097897 A CN105097897 A CN 105097897A
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Abstract
The invention discloses a gate electrode, a semiconductor device and a manufacturing method thereof, wherein the gate electrode comprises the components of a first gate part which is arranged on the substrate; and a second gate part which is arranged on the first gate part and furthermore the area of the upper surface of the first gate part is smaller than that of the lower surface of the second gate part. According to the gate electrode, through arranging the first electrode and the second electrode, the area of the external surface of the gate electrode is enlarged, and furthermore a coupling ratio between the gate electrode and a surrounding device is enlarged. Furthermore the performance of the semiconductor device is improved.
Description
Technical field
The application relates to semiconductor integrated circuit manufacture technology field, in particular to a kind of grid, semiconductor device and preparation method thereof.
Background technology
Along with the integrated level in semiconductor integrated circuit is more and more higher, the grid in semiconductor device is more and more less, causes the coupled ratio between grid and device around to decline, and then causes the hydraulic performance decline of semiconductor device.Such as, in the manufacturing process of nonvolatile memory, grid (comprise floating boom and be formed at coupling grid on floating boom) small-sized, causes capacity coupled scope between floating boom and coupling grid to reduce, and then reduces the read-write speed of nonvolatile memory.
Fig. 1 to Fig. 3 shows the manufacturing process at existing semiconductor device.In the making of existing semiconductor device, the step forming the groove isolation construction between grid and grid comprises: first, the middle formation shallow trench of substrate 10 ' 21 ' and be arranged in the isolation preparation layers 22 ' of shallow trench 21 ' ', wherein substrate 10 ' is also formed with oxide skin(coating) 30 ', and then forms basal body structure as shown in Figure 1; Then, adjacent isolation preparation layers 22 ' ' between substrate 10 ' formed on the surface grid preparation layers 50 ' ', and then form basal body structure as shown in Figure 2; Finally, planarized gate preparation layers 50 ' ' to form grid 50 ', and removal unit divide isolation preparation layers 22 ' ', form separator 22 ' and groove isolation construction 20 ', and then form basal body structure as shown in Figure 3.
In the manufacturing process of above-mentioned semiconductor device, form grid upper surface area be less than or equal to the lower surface area of grid, cause the coupled ratio between grid and peripheral devices less.At present, technical staff's trial is by increasing the size of grid to increase the coupled ratio between grid and peripheral devices.But the increase of grid size can reduce the integrated level of semiconductor device, and then limit further developing of semiconductor integrated circuit.
Summary of the invention
The application aims to provide a kind of grid, semiconductor device and preparation method thereof, with the coupled ratio increasing between neighboring gates or between grid and device around, and then improves the performance of semiconductor device.
To achieve these goals, according to an aspect of the application, provide a kind of grid, this grid comprises: first grid portion, is arranged on substrate; Second grid portion, is arranged in first grid portion, and the area of the upper surface of first grid is less than the area of the lower surface of second grid.
Further, in above-mentioned grid, the upper surface width in second grid portion is more than or equal to the width of its lower surface.
Further, in above-mentioned grid, the width of the upper surface in first grid portion is less than or equal to the width of its lower surface.
Further, in above-mentioned grid, first grid portion and second grid portion are hexahedron, are preferably prismatoid or cube.
Further, in above-mentioned grid, the height in first grid portion is 0.25 ~ 4:1 with the ratio of the height in second grid portion, is preferably 1.
Present invention also provides a kind of semiconductor device, this semiconductor device comprises: substrate; Groove isolation construction, is formed in substrate; First functional gate, is formed between adjacent trenches isolation structure on substrate surface, is the grid that the application is above-mentioned.
Further, in the semiconductor device that the application is above-mentioned, semiconductor device also comprises the second functional gate be formed on second grid portion and groove isolation construction exposed surface.
Further, in the semiconductor device that the application is above-mentioned, semiconductor device also comprises the dielectric layer be formed between first grid portion and substrate, and dielectric layer is preferably oxide skin(coating).
Present invention also provides a kind of manufacture method of semiconductor device, this manufacture method comprises: provide substrate; Form shallow trench and the isolation preparation layers being arranged in shallow trench in the substrate; Etching isolation preparation layers isolates transition zone and the first groove being positioned at types of flexure between adjacent isolation transition zone and the second groove to be formed, first groove and the second groove are formed successively along the direction away from substrate, and the area at the top of the first groove is less than the area of the bottom of the second groove; In the first groove and the second groove, fill grid material, to form first grid portion in the first groove, and form second grid portion in the second groove, first grid portion and second grid portion form the first functional gate jointly; Removal unit divides isolation transition zone, forms groove isolation construction.
Further, in the manufacture method of above-mentioned semiconductor device, before etching isolation preparation layers, between isolation preparation layers, substrate surface being formed can sacrificial material layer, and can the surface of sacrificial material layer lower than the surface of isolation preparation layers; After etching isolation preparation layers, removal can sacrificial material layer.
Further, in the manufacture method of above-mentioned semiconductor device, formed and can the step of sacrificial material layer comprise: before formation shallow trench, substrate is formed can expendable material preparation layers; Etching can expendable material preparation layers and substrate, forms shallow trench; To be formed in shallow trench and can the surface of expendable material preparation layers flush; Remove part can expendable material preparation layers formed upper surface lower than isolation preparation layers can sacrificial material layer.
Further, in the manufacture method of above-mentioned semiconductor device, removing can expendable material preparation layers and can the technique of sacrificial material layer be wet etching.
Further, in the manufacture method of above-mentioned semiconductor device, can before expendable material preparation layers in formation, substrate forms dielectric layer, and dielectric layer is preferably oxide skin(coating).
Further, in the manufacture method of above-mentioned semiconductor device, the technique of etching isolation preparation layers is wet etching and/or Ions Bombardment.
Further, in the manufacture method of above-mentioned semiconductor device, manufacture method is entered and is also comprised: in second grid portion and groove isolation construction exposed surface, form the second functional gate.
A kind of grid of technical scheme, semiconductor device and preparation method thereof of application the application, set gradually first grid portion and second grid portion on a semiconductor substrate, and the upper surface of first grid is the portion lower surface of described second grid.The exterior surface area of this grid structure is increased, and then increases the coupled ratio between grid and device around, improves the performance of semiconductor device.
Accompanying drawing explanation
The Figure of description forming a application's part is used to provide further understanding of the present application, and the schematic description and description of the application, for explaining the application, does not form the improper restriction to the application.In the accompanying drawings:
Fig. 1 shows in the manufacture method of existing semiconductor device, formed in the substrate shallow trench and be arranged in shallow trench isolated substance layer after the cross-sectional view of matrix;
Fig. 2 shows the cross-sectional view of the matrix after forming grid described in Fig. 1 between adjacent separator matter layer;
Fig. 3 shows and removes partial partition matter layer described in Fig. 2, and using residue isolated substance layer and the shallow trench cross-sectional view as the matrix after groove isolation construction;
Fig. 4 shows the cross-sectional view of the grid provided according to the execution mode of the application;
Fig. 5 shows the cross-sectional view of the semiconductor device provided according to the execution mode of the application;
Fig. 6 shows the schematic flow sheet of the manufacture method of the semiconductor device provided at the execution mode of the application;
Fig. 7 shows in the manufacture method of the semiconductor device provided at the execution mode of the application, provides the cross-sectional view of matrix after substrate;
Fig. 8 shows the isolation preparation layers forming shallow trench and be arranged in shallow trench in the substrate shown in Fig. 7, and substrate surface between adjacent isolation preparation layers is formed can the cross-sectional view of matrix after expendable material preparation layers;
Fig. 9 shows etching removal unit and divides the sacrificed preparation layers shown in Fig. 8 can the cross-sectional view of matrix after sacrificial material layer to be formed;
Figure 10 shows the isolation preparation layers of etching shown in Fig. 9, forms the cross-sectional view of the matrix after isolation transition zone;
Figure 11 show remove shown in Figure 10 can the cross-sectional view of matrix after sacrificial material layer;
Figure 12 shows the cross-sectional view substrate between the isolation transition zone be connected shown in Figure 11 being formed the matrix after comprising first functional gate in first grid portion and second grid portion;
Figure 13 shows the part isolation transition zone removed shown in Figure 12, forms the cross-sectional view of the matrix after groove isolation construction; And
Figure 14 shows the cross-sectional view of the matrix form the second functional gate in the second grid portion shown in Figure 13 and groove isolation construction exposed surface after.
Embodiment
It should be noted that, when not conflicting, the embodiment in the application and the feature in embodiment can combine mutually.Below with reference to the accompanying drawings and describe the application in detail in conjunction with the embodiments.
It should be noted that used term is only to describe embodiment here, and be not intended to the illustrative embodiments of restricted root according to the application.As used herein, unless the context clearly indicates otherwise, otherwise singulative is also intended to comprise plural form, in addition, it is to be further understood that, when use belongs to " comprising " and/or " comprising " in this manual, it indicates existing characteristics, step, operation, device, assembly and/or their combination.
For convenience of description, here can usage space relative terms, as " ... on ", " in ... top ", " at ... upper surface ", " above " etc., be used for the spatial relation described as a device shown in the figure or feature and other devices or feature.Should be understood that, space relative terms is intended to comprise the different azimuth in use or operation except the described in the drawings orientation of device.Such as, " in other devices or structure below " or " under other devices or structure " will be positioned as after if the device in accompanying drawing is squeezed, being then described as the device of " above other devices or structure " or " on other devices or structure ".Thus, exemplary term " in ... top " can comprise " in ... top " and " in ... below " two kinds of orientation.This device also can other different modes location (90-degree rotation or be in other orientation), and relatively describe space used here and make respective explanations.
Illustrative embodiments according to the application will be described in more detail below.But these illustrative embodiments can be implemented by multiple different form, and should not be interpreted as being only limited to execution mode set forth herein.Should be understood that, there is provided these execution modes be in order to make the application open thorough and complete, and the design of these illustrative embodiments is fully conveyed to those of ordinary skill in the art, in the accompanying drawings, for the sake of clarity, expand the thickness in layer and region, and use the device that identical Reference numeral represents identical, thus will omit description of them.
As what introduce in background technology, along with the integrated level in semiconductor integrated circuit is more and more higher, the grid in semiconductor device is more and more less, causes the coupled ratio between grid and device around to decline, and then causes the hydraulic performance decline of semiconductor device.Present inventor studies for the problems referred to above, proposes a kind of grid, semiconductor device and preparation method thereof.As shown in Figure 4, this grid comprises: first grid portion 51, arranges over the substrate 10; Second grid portion 52, is arranged in first grid portion 51, and the area of the upper surface of first grid is less than the area of the lower surface of second grid.The exterior surface area of above-mentioned grid is increased, and then increases the coupled ratio between grid and device around, improves the performance of semiconductor device.
In above-mentioned grid, the upper surface width in preferred second grid portion 52 is more than or equal to the width of its lower surface.When the upper surface width in second grid portion 52 is greater than the width of lower surface, second grid portion 52 can be trapezoidal; When the upper surface width in second grid portion 52 equals the width of lower surface, second grid portion 52 can be cube.The second grid portion 52 with above-mentioned shape has optimum surface area, makes the coupled ratio between grid and device around reach optimal value.
In above-mentioned grid, the width of the upper surface in preferred first grid portion 51 is less than or equal to the width of its lower surface.When the width of the upper surface in first grid portion 51 is less than the width of lower surface, first grid portion 51 can be trapezoidal; When the width of the upper surface in first grid portion 51 equals the width of lower surface, first grid portion 51 can be cube.The first grid portion 51 with above-mentioned shape can be combined with second grid portion 52 grid forming the exterior surface area with optimal value, makes the coupled ratio between grid and device around reach optimal value.
In above-mentioned grid, the height in first grid portion 51 and the aspect ratio in second grid portion 52 can affect the performance of semiconductor device.In a kind of preferred implementation of the application, the height in first grid portion 51 is 0.25 ~ 4:1 with the ratio of the height in second grid portion 52, is more preferably 1.The grid with aforementioned proportion has optimum exterior surface area, makes the coupled ratio between grid and device around reach optimal value.
Above-mentioned grid can also comprise other gate portion, such as the 3rd gate portion, the 4th gate portion, to increase the exterior surface area of grid further, and the coupled ratio between grid and device around.Certainly, along with the increase of gate portion quantity, the structure of grid becomes increasingly complex, make the technique of grid also more complicated, cost is higher.Alternatively, above-mentioned grid is only made up of first grid portion 51 and second grid portion 52, to average out between the performance and process costs of semiconductor device.
Dielectric layer 30 is comprised further, to form the thin insulating barrier of one deck between grid 50 and substrate 10 between above-mentioned grid 50 and substrate 10.Meanwhile, between adjacent grid 50, groove isolation construction 20 can be formed, the isolated substance layer 22 that above-mentioned groove isolation construction 20 comprises shallow trench 21 and is arranged in shallow trench 21.
Meanwhile, present invention also provides a kind of semiconductor device.As shown in Figure 5, this semiconductor device comprises substrate 10, be formed at groove isolation construction 20 in substrate 10, and be formed at the first functional gate 50 on substrate 10 surface between adjacent trenches isolation structure 20, wherein the grid that provides for the application is above-mentioned of the first functional gate 50.Coupled ratio in this semiconductor device between the first functional gate 50 and device is around improved, and then the performance of semiconductor device is improved.
Above-mentioned semiconductor device also comprises the second functional gate 60 be formed on second grid portion 52 and groove isolation construction exposed surface.Above-mentioned second functional gate 60 can be coupled with first grid portion 51, and forms stacked grid.Such as in memory, above-mentioned first functional gate 50 as floating boom, the second functional gate 60 as control gate or coupling grid, the grid of both stacked formation memory devices.
Above-mentioned semiconductor device also comprises the dielectric layer 30 be formed between first grid portion 51 and substrate 10, to form the thin insulating barrier of one deck between grid and substrate 10.Above-mentioned dielectric layer 30 can be dielectric material common in this area, and those skilled in the art can select the kind of dielectric layer 30 according to the actual performance demand of semiconductor device.Preferably, above-mentioned dielectric layer 30 is oxide skin(coating), such as SiO
2.Above-mentioned oxide skin(coating) has higher dielectric constant, can form good insulating barrier between first grid portion 51 and substrate 10, and oxide and good interface cohesion can be formed between substrate 10 and first grid portion 51.
The above-mentioned grid of the application (the first functional gate 50) can adopt rear grid technique to be formed, and namely first forms groove isolation construction and source-drain electrode, then forms grid.Below by for the manufacture method of semiconductor device, further illustrate the manufacture method of grid (the first functional gate 50).As shown in Figure 6, this making manufacture method comprises: provide substrate; Form shallow trench and the isolation preparation layers being arranged in shallow trench in the substrate; Etching isolation preparation layers isolates transition zone and the first groove being positioned at types of flexure between adjacent isolation transition zone and the second groove to be formed, first groove and the second groove are formed successively along the direction away from substrate, and the area at the top of the first groove is less than the area of the bottom of the second groove; In the first groove and the second groove, fill grid material, to form first grid portion in the first groove, and form second grid portion in the second groove, first grid portion and second grid portion form the first functional gate jointly; Removal unit divides isolation transition zone, forms groove isolation construction.
Above-mentioned manufacture method is by forming first grid portion and second grid portion successively on a semiconductor substrate, and the upper surface of first grid is the portion lower surface of described second grid, the exterior surface area of grid structure is increased, and then the coupled ratio increased between grid and device around, improve the performance of semiconductor device.
Fig. 7 to Figure 14 shows in the manufacture method of the semiconductor device that the application provides, the cross-sectional view of the matrix obtained after each step.Below in conjunction with Fig. 7 to Figure 14, further illustrate the manufacture method of the semiconductor device that the application provides.
First, substrate 10 is as shown in Figure 7 provided.Above-mentioned substrate 10 can be monocrystalline silicon (Si), monocrystalline germanium (Ge), SiGe (GeSi) or carborundum (SiC), also can be silicon-on-insulator (SOI), germanium on insulator (GOI), or can also be other material, the III-V such as such as GaAs.
After completing the step that substrate 10 is provided, in substrate 10, form shallow trench 21 and the isolation preparation layers 22 ' being arranged in shallow trench 21.In this step, a kind of preferred implementation is: being formed on the surface at substrate 10 can expendable material preparation layers 40 '; Etching can expendable material preparation layers 40 ' and substrate 10, forms shallow trench 21 in substrate 10; Formed in shallow trench 21 surface with can the isolation preparation layers 22 ' that flushes of the surface of expendable material preparation layers 40 ' and then the basal body structure that formed as shown in Figure 8.Can remove part after the above-mentioned isolation preparation layers 22 ' of formation can expendable material preparation layers 40 ', formed upper surface lower than isolation preparation layers 22 ' can sacrificial material layer 40, and then form basal body structure as shown in Figure 9.
In above-mentioned steps, the shape of the shallow trench 21 formed and isolation preparation layers 22 ' can for shape common in this area, such as prismatoid or cube.As illustrated embodiment, shallow trench 21 in this application and isolation preparation layers 22 ' are prismatoid.It should be noted that the shape of the grid (first grid portion 51 and second grid portion 52) of follow-up formation is relevant to the shape of isolation preparation layers 22 ', also can be prismatoid or cube.Exemplarily, first grid portion 51 in this application and second grid portion 52 are prismatoid.
In above-mentioned steps, formation above-mentioned can expendable material preparation layers 40 ' front, need first to form dielectric layer 30 over the substrate 10, to form the thin insulating barrier of one deck between grid and substrate 10.Preferably, dielectric layer 30 is oxide skin(coating), such as SiO
2.Above-mentioned oxide skin(coating) has higher dielectric constant, can form good insulating barrier between grid and substrate 10, and oxide and good interface cohesion can be formed between substrate 10 and grid.The technique forming above-mentioned dielectric layer 30 can be chemical vapour deposition (CVD), thermal oxidation etc., and those skilled in the art can select manufacture craft and technological parameter thereof according to actual process.
In above-mentioned steps, can expendable material preparation layers 40 ' and can sacrificial material layer 40 can be common in this area can expendable material, such as SiN, SiO
2deng, its manufacture craft can be chemical vapour deposition (CVD) or sputtering etc.Removal can the technique of expendable material preparation layers 40 ' can be wet etching, and etching liquid can be phosphoric acid solution etc.When adopt phosphoric acid etching removal can expendable material preparation layers 40 ' time, in a kind of Alternate embodiments, H in phosphoric acid solution
3pO
4and H
2the volume ratio of O is 1:200 ~ 500, and the temperature of etching is 20 ~ 45 DEG C, and the time of etching is 30 ~ 360s.
After completing the step of isolation preparation layers 22 ' forming shallow trench 21 and be arranged in shallow trench 21 in substrate 10, etching isolation preparation layers 22 ' with formed isolation transition zone 22 ' ', and then form basal body structure as shown in Figure 10.Preferably, the technique of etching isolation preparation layers 22 ' is wet etching and/or Ions Bombardment.When adopting wet etching isolation preparation layers 22 ', a kind of optional execution mode is; When adopting Ions Bombardment etching isolation preparation layers 22 ', a kind of optional execution mode is: with CF
4and CHF
3etching gas is, sputtering power is 400 ~ 1000 watts, and etching temperature is 25 ~ 60 DEG C, and etch period is 30 ~ 360 seconds.
The above-mentioned isolation transition zone of formation 22 ' ' after, need removal can sacrificial material layer 40, with adjacent isolation transition zone 22 ' ' between substrate 10 on form the first groove 71 and the second groove 72 successively along the direction away from substrate 10, and the area at the top of the first groove 71 is less than the area of the bottom of the second groove 72, and then form basal body structure as shown in figure 11.Removal can the technique of sacrificial material layer 40 can be wet etching, and etching liquid can be phosphoric acid solution etc.When adopt phosphoric acid remove can expendable material preparation layers 40 ' time, in a kind of Alternate embodiments, H in phosphoric acid solution
3pO
4and H
2the volume ratio of O is 1:200 ~ 500, and the temperature of etching is 20 ~ 45 DEG C, and the time of etching is 30 ~ 360s.
Complete etching isolation preparation layers 22 ' with formed isolation transition zone 22 ' ' and adjacent isolation transition zone 22 ' ' between substrate 10 on the first groove 71 and the second groove 72 step after, grid material is filled in the first groove and the second groove, to form first grid portion in the first groove, and second grid portion is formed in the second groove, first grid portion and second grid portion form the first functional gate jointly, and then form basal body structure as shown in figure 12.Above-mentioned first functional gate 50 can be polysilicon or metal (such as Cu), and the technique forming above-mentioned first functional gate 50 can be chemical vapour deposition (CVD) or plating.When adopting electroplating technology to form Cu, a kind of Alternate embodiments is: with Cu
2p
2o
7for the Cu source in electroplate liquid, the current density in electroplating process is 1 ~ 5A/dm
2, the temperature of electroplate liquid is 5 ~ 80 DEG C.
Complete after being formed and comprising the step of first functional gate 50 in first grid portion 51 and second grid portion 52, removal unit divide isolation transition zone 22 ' ', form groove isolation construction, and then form basal body structure as shown in fig. 13 that.Remove above-mentioned isolation transition zone 22 ' ' technique can be wet etching, those skilled in the art can select suitable technique and parameter thereof according to actual process demand.After it should be noted that removal unit divides isolation preparation layers 22 ', form separator 22 in groove isolation construction surface higher or lower than the surface of substrate 10, also can flush with the surface of substrate 10.
After the step forming above-mentioned groove isolation construction, above-mentioned manufacture method is entered and is also comprised: in second grid portion 52 and groove isolation construction exposed surface, form the second functional gate 60, and then forms basal body structure as shown in figure 14.Above-mentioned second functional gate 60 can be polysilicon or metal (such as Cu), and the technique forming above-mentioned second functional gate 60 can be chemical vapour deposition (CVD) or plating.When adopting electroplating technology to form Cu, a kind of Alternate embodiments is: with Cu
2p
2o
7for the Cu source in electroplate liquid, the current density in electroplating process is 1 ~ 5A/dm
2, the temperature of electroplate liquid is 5 ~ 80 DEG C.
As can be seen from the above description, the application's the above embodiments achieve following technique effect: set gradually first grid portion and second grid portion on a semiconductor substrate, and the upper surface of first grid is the portion lower surface of described second grid.The exterior surface area of above-mentioned grid is increased, and then increases the coupled ratio between grid and device around, improves the performance of semiconductor device.
The foregoing is only the preferred embodiment of the application, be not limited to the application, for a person skilled in the art, the application can have various modifications and variations.Within all spirit in the application and principle, any amendment done, equivalent replacement, improvement etc., within the protection range that all should be included in the application.
Claims (15)
1. a grid, is characterized in that, comprising:
First grid portion, is arranged on substrate;
Second grid portion, is arranged in described first grid portion, and the area of the upper surface in described first grid portion is less than the area of the lower surface in described second grid portion.
2. grid according to claim 1, is characterized in that, the upper surface width in described second grid portion is more than or equal to the width of its lower surface.
3. grid according to claim 1, is characterized in that, the width of the upper surface in described first grid portion is less than or equal to the width of its lower surface.
4. grid according to claim 1, is characterized in that, described first grid portion and second grid portion are hexahedron, is preferably prismatoid or cube.
5. grid according to claim 1, is characterized in that, the height in described first grid portion is 0.25 ~ 4:1 with the ratio of the height in described second grid portion, is preferably 1.
6. a semiconductor device, is characterized in that, described semiconductor device comprises:
Substrate;
Groove isolation construction, is formed in described substrate;
First functional gate, is formed between adjacent described groove isolation construction on substrate surface, the grid according to any one of claim 1 to 5.
7. semiconductor device according to claim 6, is characterized in that, described semiconductor device also comprises the second functional gate be formed on described second grid portion and described groove isolation construction exposed surface.
8. semiconductor device according to claim 6, is characterized in that, described semiconductor device also comprises the dielectric layer be formed between described first grid portion and described substrate, and described dielectric layer is preferably oxide skin(coating).
9. a manufacture method for semiconductor device, is characterized in that, described manufacture method comprises:
Substrate is provided;
Shallow trench and the isolation preparation layers being arranged in described shallow trench is formed in described substrate;
Etch described isolation preparation layers to form isolation transition zone and the first groove being positioned at described types of flexure between adjacent described isolation transition zone and the second groove, described first groove and the second groove are formed successively along the direction away from described substrate, and the area at the top of described first groove is less than the area of the bottom of described second groove;
In described first groove and the second groove, fill grid material, to form first grid portion in described first groove, and form second grid portion in described second groove, described first grid portion and second grid portion form the first functional gate jointly.
Remove the described isolation transition zone of part, form groove isolation construction.
10. manufacture method according to claim 9, it is characterized in that, before the described isolation preparation layers of etching, between described isolation preparation layers, substrate surface being formed can sacrificial material layer, and described can the surface of sacrificial material layer lower than the surface of described isolation preparation layers; After the described isolation preparation layers of etching, can sacrificial material layer described in removing.
11. manufacture methods according to claim 10, is characterized in that, form described can the step of sacrificial material layer comprising:
Before the described shallow trench of formation, being formed over the substrate can expendable material preparation layers;
Etching is described can expendable material preparation layers and substrate, forms described shallow trench;
Formed in described shallow trench with described can the described isolation preparation layers that flushes of the surface of expendable material preparation layers;
Remove part and expendable material preparation layers can form upper surface lower than can sacrificial material layer described in described isolation preparation layers.
12. want the manufacture method described in 11 according to right, it is characterized in that, remove described can expendable material preparation layers and can the technique of sacrificial material layer be wet etching.
13. manufacture methods according to claim 11, is characterized in that, formation is described can before expendable material preparation layers, form dielectric layer over the substrate, described dielectric layer is preferably oxide skin(coating).
14. manufacture methods according to claim 9, is characterized in that, the technique etching described isolation preparation layers is wet etching and/or Ions Bombardment.
15. manufacture methods according to claim 9, is characterized in that, described manufacture method is entered and also comprised: in described second grid portion and described groove isolation construction exposed surface, form the second functional gate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410218947.XA CN105097897A (en) | 2014-05-22 | 2014-05-22 | Gate electrode, semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410218947.XA CN105097897A (en) | 2014-05-22 | 2014-05-22 | Gate electrode, semiconductor device and manufacturing method thereof |
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| CN105097897A true CN105097897A (en) | 2015-11-25 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6376877B1 (en) * | 2000-02-24 | 2002-04-23 | Advanced Micro Devices, Inc. | Double self-aligning shallow trench isolation semiconductor and manufacturing method therefor |
| US6455440B1 (en) * | 2001-07-13 | 2002-09-24 | Macronix International Co., Ltd. | Method for preventing polysilicon stringer in memory device |
| WO2008135554A1 (en) * | 2007-05-03 | 2008-11-13 | Interuniversitair Microelektronica Centrum Vzw | Method for forming a planar stacked gate nonvolatile semiconductor memory device having a floating gate electrode and devices obtained thereof |
-
2014
- 2014-05-22 CN CN201410218947.XA patent/CN105097897A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6376877B1 (en) * | 2000-02-24 | 2002-04-23 | Advanced Micro Devices, Inc. | Double self-aligning shallow trench isolation semiconductor and manufacturing method therefor |
| US6455440B1 (en) * | 2001-07-13 | 2002-09-24 | Macronix International Co., Ltd. | Method for preventing polysilicon stringer in memory device |
| WO2008135554A1 (en) * | 2007-05-03 | 2008-11-13 | Interuniversitair Microelektronica Centrum Vzw | Method for forming a planar stacked gate nonvolatile semiconductor memory device having a floating gate electrode and devices obtained thereof |
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Application publication date: 20151125 |