CN105097709A - Forming method of flash memory - Google Patents

Forming method of flash memory Download PDF

Info

Publication number
CN105097709A
CN105097709A CN 201410219995 CN201410219995A CN105097709A CN 105097709 A CN105097709 A CN 105097709A CN 201410219995 CN201410219995 CN 201410219995 CN 201410219995 A CN201410219995 A CN 201410219995A CN 105097709 A CN105097709 A CN 105097709A
Authority
CN
Grant status
Application
Patent type
Prior art keywords
forming
layer
semiconductor substrate
gate
spacer
Prior art date
Application number
CN 201410219995
Other languages
Chinese (zh)
Inventor
胡建强
Original Assignee
中芯国际集成电路制造(上海)有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Abstract

The invention provides a forming method of a flash memory. The forming method comprises at least the following steps: a semiconductor substrate is provided; at least two grid stacking structures are formed on the semiconductor substrate; first side walls are formed at two sides of each grid stacking structure respectively; a nickel compound is formed on the semiconductor substrate between two adjacent grid stacking structures; second side walls are formed on the first side wall and the nickel compound. Through a way that the nickel compound between grid stacking structures is formed firstly and then the second side walls at the outer side are formed, the problem is avoided that the nickel layer cannot contact with the semiconductor substrate because of blocking of the second side walls during nickel layer deposition and therefore the nickel compound cannot be formed subsequently.

Description

快闪存储器的形成方法 A method of forming a flash memory

技术领域 FIELD

[0001] 本发明涉及半导体技术领域,特别是涉及一种快闪存储器的形成方法。 [0001] The present invention relates to semiconductor technology, and more particularly to a method of forming a flash memory.

背景技术 Background technique

[0002] 快闪存储器被广泛应用于电子产品中,其中,现有工艺中的快闪存储器的形成一般主要包括: [0002] Flash memories are widely used in electronic products, wherein the flash memory is formed in the conventional process typically includes:

[0003] 参考图1所示,提供半导体衬底100,在所述半导体衬底100上包括中心区域90和外围区域70。 [0003] Referring to FIG. 1, a semiconductor substrate 100, includes a central region 90 and peripheral region 70 on the semiconductor substrate 100. 其中,在所述中心区域90的半导体衬底100上形成多个快闪存储器的栅极堆栈结构20,所述栅极堆栈结构20的两侧形成有栅极堆栈结构20的第一侧墙31,所述第一侧墙31外侧形成有栅极堆栈结构20的第二侧墙32。 20, the gate stack structure formed on both sides of the gate stack structure wherein a plurality of flash memory is formed on a semiconductor substrate 100 in the central region 90 of the first sidewall 20 of the gate stack structure 20 31 the first spacer 31 is formed outside the second gate stack structure 32 of sidewall 20. 在所述外围区域70的半导体衬底100上形成有多个外围器件的栅极结构40,所述栅极结构40的两侧形成有栅极结构40的第一侧墙31,所述第一侧墙31的外侧形成有所述栅极结构40的第二侧墙32。 A plurality of peripheral devices 40 of a gate structure formed in the peripheral region 100 on the semiconductor substrate 70, formed on both sides of the gate structure 40 has a first sidewall spacer 40 of gate structure 31, the first the gate structure 40 has a second outer sidewall 31 of spacer 32 is formed.

[0004] 接下来,参考图2所示,在所述半导体衬底100、栅极堆栈结构20、栅极堆栈结构20 的第二侧墙31、栅极结构40和栅极结构40的第二侧墙32上形成镍层600,形成镍层600 的方式可以为沉积。 [0004] Next, with reference to Figure 31, the gate structure 40 and gate structure 100 of the 2, gate stack structure 20, a second sidewall gate stack structure 20 of the semiconductor substrate 40 of a second spacer 600 is formed on the nickel layer 32, a nickel layer 600 is formed so may be deposited.

[0005] 接下来,参考图3所示,对图2中所示的半导体结构进行退火,使得在栅极堆栈结构20和栅极结构40顶部的表面与相邻两栅极堆栈结构20或者相邻两栅极结构40之间的半导体衬底100的表面形成镍化物64、67,以形成欧姆接触,减小接下来形成在所述镍化物64、67上的接触电极的接触电阻。 [0005] Next, with reference to FIG. 3, the semiconductor structure shown in FIG. 2 annealing, so that the top surface of the gate stack structure 20 and the gate structure 40 and two adjacent gate stack structure 20 or with surface of the semiconductor substrate 40 between adjacent two gate structures 100 are formed of nickel compounds 64, 67, to form an ohmic contact, reducing contact resistance is formed next on the contact electrode 64 and 67 of the nickel compound. 另外,本步骤还包括去除未反应的镍层600的步骤。 Further, the present step further comprises the step of removing a nickel layer 600 unreacted.

[0006] 然而,随着发展高密度的,小尺寸的快闪存储器元件的发展,相邻的两栅极堆栈结构20之间的间距成倍缩小,而栅极堆栈结构20的高度并不会成相应比例的缩小,使得相邻的两栅极堆栈结构20之间的间距的高宽比非常大。 [0006] However, with the development of flash memory elements of the development of high-density, small size, the spacing 20 between the two adjacent gate stack structure exponentially reduced, while the height of the gate stack structure 20 and not reduced to the corresponding proportion, such that the two adjacent gate stack structure is a high aspect ratio between the spacing 20. 尤其在相邻的两栅极堆栈结构20之间的间距的高宽比大到超过4. 5后,相邻的栅极堆栈结构20的第二侧墙32连接在一起,阻挡镍层600接触到半导体衬底100的表面,也就不能在这相邻的两栅极堆栈结构20之间的半导体衬底100上形成镍化物64,不能使得后续形成的接触电极的接触电阻减小。 In particular, the large aspect ratio of the spacing 20 between adjacent two gate stack structure after more than 4.5, the gate stack structure adjacent the second sidewall 3220 are coupled together, the contact barrier layer of nickel 600 the surface of the semiconductor substrate 100, it is not a nickel compound 64 is formed on this two adjacent gate stack structure between the semiconductor substrate 20 is 100, so that the contact resistance of the contact electrodes can not be subsequently formed decreases. 这使得快闪存储器的性能大受影响。 This makes it greatly affects the performance of the flash memory.

发明内容 SUMMARY

[0007] 鉴于以上所述现有技术的缺点,本发明的目的在于提供一种快闪存储器的形成方法,用于解决现有技术中较小尺寸的快闪存储器的形成方法中,不能在相邻栅极堆栈结构之间形成镍化物的问题。 [0007] In view of the foregoing disadvantages of the prior art, an object of the present invention to provide a method of forming a flash memory, a method for forming the prior art to solve the smaller size of the flash memory can not be in phase problems of nickel compounds formed between phthalic gate stack structure.

[0008] 为实现上述目的及其他相关目的,本发明提供一种快闪存储器的形成方法,所述快闪存储器的形成方法至少包括: [0008] To achieve the above objects and other related objects, the present invention provides a method of forming a flash memory, a method of forming a flash memory comprising at least:

[0009] 提供半导体衬底; [0009] providing a semiconductor substrate;

[0010] 在所述半导体衬底上形成至少两个栅极堆栈结构; [0010] at least two gate stack structure formed on the semiconductor substrate;

[0011] 在每一所述栅极堆栈结构的两侧形成第一侧墙; [0011] a first spacer formed on each of both sides of the gate stack structure;

[0012] 在相邻两所述栅极堆栈结构之间的半导体衬底上形成镍化物; [0012] the nickel compound is formed on the semiconductor substrate between the two adjacent gate stack structure;

[0013] 在所述第一侧墙和所述镍化物上形成第二侧墙。 [0013] forming a second spacer on the first sidewall and said nickel compound.

[0014] 优选地,相邻两所述栅极堆栈结构之间间隙的高宽比大于4. 5。 [0014] Preferably, the two adjacent high aspect ratio gaps between the gate stack structure is greater than 4.5.

[0015] 优选地,所述第一侧墙的材质为氧化娃,厚度为loo: A。 [0015] Preferably, the first spacer is made of baby oxide thickness loo: A.

[0016] 优选地,所述栅极堆栈结构从下至上依次包括:栅氧化层、浮栅层、ONO层、控制栅层和氮化娃层。 [0016] Preferably, the gate stack structure includes, in order from bottom to top: a gate oxide layer, a floating gate layer, the ONO layer, a control gate layer and a nitride layer baby.

[0017] 相应的,本发明还提供一种快闪存储器的形成方法,所述快闪存储器的形成方法至少包括: [0017] Accordingly, the present invention also provides a method of forming a flash memory, a method of forming a flash memory comprising at least:

[0018] 提供半导体衬底,所述半导体衬底上包括中心区域和外围区域; [0018] providing a semiconductor substrate, comprising a central region and a peripheral region on said semiconductor substrate;

[0019] 在所述中心区域的半导体衬底上形成至少两个栅极堆栈结构,在所述外围区域的所述半导体衬底上从下至上依次形成栅氧化层和多晶硅层; [0019] at least two gate stack structure formed on the semiconductor substrate in the central region, from the bottom layer, forming a gate oxide and a polysilicon layer on the semiconductor substrate in the peripheral region;

[0020] 在所述栅极堆栈结构两侧形成第一侧墙; [0020] a first spacer formed on both sides of the gate stack structure;

[0021] 在相邻两所述栅极堆栈结构之间的半导体衬底上形成第一镍化物; [0021] The first nickel compound is formed on the semiconductor substrate between the two adjacent gate stack structure;

[0022] 在所述第一侧墙外侧形成第二侧墙; [0022] The second sidewall spacer is formed outside the first sidewall;

[0023] 对所述多晶硅层和氧化硅层进行选择性刻蚀,以在所述外围区域形成至少两个栅极结构; [0023] The polysilicon layer and the silicon oxide layer is selectively etched in the peripheral region to form at least two gate structures;

[0024] 在所述栅极结构两侧形成第三侧墙; [0024] forming a third sidewall spacer on the sides of the gate structure;

[0025] 在所述栅极结构的顶部以及两栅极结构之间的第三侧墙之间的半导体衬底上形成第二镍化物。 [0025] The second nickel compound is formed on the semiconductor substrate between the gate structure and the top of the third spacer between the two gate structures.

[0026] 优选地,在所述栅极堆栈结构两侧形成第一侧墙的步骤之前,还包括在在所述外围区域的多晶硅层上形成保护层的步骤,在所述第一侧墙和所述第一镍化物上形成第二侧墙的步骤之后,在对所述多晶硅层和氧化硅层进行选择性刻蚀的步骤之前,还包括去除所述保护层,以露出所述多晶硅层的步骤。 [0026] Preferably, before the step of forming a first spacer on both sides of the gate stack structure, further comprising the step of forming the protective layer on the polysilicon layer in the peripheral region, in the first sidewall and after the step of forming a second spacer on the first nickel compound, before the polysilicon layer and the silicon oxide layer by selective etching, further comprising removing the protective layer to expose said polysilicon layer, step.

[0027] 优选地,在所述栅极结构两侧形成第三侧墙的步骤包括:在所述第二侧墙层、所述外围区域的栅极结构和暴露出来的半导体衬底上形成第三侧墙层,所述第三侧墙层至少填满相邻两所述栅极堆栈结构之间的空隙。 [0027] Preferably, the step of forming a third sidewall spacer on both sides of the gate structure comprises: a second spacer layer, said semiconductor substrate region and the peripheral gate structure is formed on the exposed three spacer layer, said third spacer layer is at least a gap between the two gate stack structure adjacent fill.

[0028] 优选地,相邻两所述栅极堆栈结构之间间隙的高宽比大于4. 5。 [0028] Preferably, the two adjacent high aspect ratio gaps between the gate stack structure is greater than 4.5.

[0029] 优选地,所述第一侧墙的材质为氧化娃,厚度为丨00 A~300 A" [0029] Preferably, the first spacer is made of oxide baby, Shu a thickness of 00 A ~ 300 A "

[0030] 优选地,所述第二侧墙的材质为氮化娃,厚度为300 A~400 A。 [0030] Preferably, the second spacer is made of baby nitride, having a thickness of 300 A ~ 400 A.

[0031] 如上所述,本发明的快闪存储器的形成方法,具有以下有益效果: [0031] As described above, the method of forming a flash memory of the present invention has the following advantages:

[0032] 本发明通过先形成好栅极堆栈结构之间的镍化物,再形成外侧的第二侧墙的方式,避免了沉积镍层时,由于第二侧墙的阻挡,镍层接触不到半导体衬底的问题,导致后续不能形成镍化物的问题。 [0032] The present invention is by first forming a nickel compound between a good gate stack structure, the second spacer is further formed to the outer side, while avoiding deposition of a nickel layer, since the second side wall barrier layer of nickel reach problems of the semiconductor substrate, a nickel compound lead to subsequent problems can not be formed.

附图说明 BRIEF DESCRIPTION

[0033] 图1至图3显示为现有技术中的快闪存储器的形成方法的示意图。 [0033] Figures 1 to 3 show a schematic view of the prior art method of forming a flash memory.

[0034] 图4至图8显示为本发明的实施例一中提供的快闪存储器的形成方法的示意图。 [0034] FIGS. 4 to 8 show a schematic view of a method of forming a flash memory according to an embodiment of the present invention.

[0035] 图9至图14显示为本发明的实施例二中提供的快闪存储器的形成方法的示意图。 [0035] Figures 9 to 14 show a schematic view of a method of forming a flash memory according to the second embodiment provided in the present invention.

[0036] 元件标号说明 [0036] DESCRIPTION OF REFERENCE NUMERALS element

[0037] 100 半导体衬底 [0037] The semiconductor substrate 100

[0038] 90 中心区域 [0038] The central region 90

[0039] 70 外围区域 [0039] 70 peripheral area

[0040] 31 第一侧墙 [0040] The first sidewall 31

[0041] 20 栅极堆栈结构 [0041] The gate stack structure 20

[0042] 600 镍层 [0042] The nickel layer 600

[0043] 64、67 镍化物 [0043] Nickel compounds 64 and 67

[0044] 32 第二侧墙 [0044] The second sidewall 32

[0045] 100' 半导体衬底 [0045] 100 'of the semiconductor substrate

[0046] 31' 第一侧墙 [0046] 31 'of the first spacer

[0047] 20' 栅极堆栈结构 [0047] 20 'gate stack structure

[0048] 600' 镍层 [0048] 600 'nickel layer

[0049] 79' 镍化物 [0049] 79 Nickel compounds

[0050] 250' 氮化硅层 [0050] 250 'of silicon nitride layer

[0051] 32' 第二侧墙 [0051] 32 'of the second spacer

[0052] 100" 半导体衬底 [0052] 100 "of the semiconductor substrate

[0053] 90" 中心区域 [0053] 90 "central region

[0054] 70" 外围区域 [0054] 70 "peripheral region

[0055] 250" 氮化硅层 [0055] 250, "the silicon nitride layer

[0056] 110" 栅氧化层 [0056] 110 "gate oxide

[0057] 500" 多晶硅层 [0057] 500 "polysilicon layer

[0058] 31" 第一侧墙 [0058] 31 "first spacer

[0059] 600" 镍层 [0059] 600 "nickel layer

[0060] 79" 第一镍化物 [0060] 79 "first nickel compound

[0061] 32" 第二侧墙 [0061] 32, "the second spacer

[0062] 20" 栅极结构 [0062] 20 "the gate structure

[0063] 33 " 第三侧墙 [0063] 33 "third spacer

[0064] 330" 第三侧墙层 [0064] 330 "of the third spacer layer

[0065] 77" 第二镍化物 [0065] 77 "second nickel compound

[0066] SlO ~S15 步骤 [0066] SlO ~ S15 step

[0067] S20 ~S28 步骤 [0067] S20 ~ S28 step

具体实施方式 detailed description

[0068] 以下通过特定的具体实例说明本发明的实施方式,本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。 [0068] Hereinafter, an embodiment of the present invention by certain specific examples, those skilled in the art disclosed in this specification may readily understand the content of other advantages and effects of the present invention. 本发明还可以通过另外不同的具体实施方式加以实施或应用,本说明书中的各项细节也可以基于不同观点与应用,在没有背离本发明的精神下进行各种修饰或改变。 The present invention may also be implemented or applied through other different specific embodiments, the details of the specification may be carried out in various modified or changed without departing from the spirit of the invention based on various concepts and applications.

[0069] 请参阅图4至图14。 [0069] Please refer to FIG. 4 to FIG 14. 需要说明的是,本实施例中所提供的图示仅以示意方式说明本发明的基本构想,遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制,其实际实施时各组件的型态、数量及比例可为一种随意的改变,且其组件布局型态也可能更为复杂。 Incidentally, the present embodiment illustrates a schematic manner only examples provided to illustrate the basic idea of ​​the invention, then the drawings shows only related to the present invention, the number of components in the assembly when not in accordance with the actual embodiment, the shape and drawn to scale, its actual implementation of each component type, number and proportion of changes may be as a free, and the layout of the components may also be more complex patterns.

[0070] 实施例一 [0070] Example a

[0071] 参考图4所示,结合图5至图8所示,本实施例提供一种快闪存储器的形成方法, 具体如下: [0071] Referring to FIG 4, in conjunction with FIGS. 5 to 8, the present embodiment provides a method of forming a flash memory, as follows:

[0072] 步骤Sll :提供半导体衬底; [0072] Step Sll: providing a semiconductor substrate;

[0073] 参考图5所7K,在本实施例中,所述半导体衬底1〇〇'为娃衬底,在其它实施方式中,所述半导体衬底100'还可以为锗硅衬底、三五族化合物衬底、金刚石衬底以及其它。 [0073] Referring to FIG 5 7K, in the present embodiment, the semiconductor substrate 1〇〇 'is baby substrate, in other embodiments, the semiconductor substrate 100' may also be a silicon germanium substrate, III-V compound substrate, a diamond substrate, and other.

[0074] 步骤S12 :在所述半导体衬底上形成至少两个栅极堆栈结构; [0074] Step S12: the at least two gate stack structure formed on the semiconductor substrate;

[0075] 参考图5所示,在所述半导体衬底100'上形成至少两个栅极堆栈结构20'。 As shown in [0075] Referring to Figure 5, 'at least two are formed on the gate stack structure 20' in the semiconductor substrate 100. 在本实施例中,所述栅极堆栈结构为ETOX(Electron Tunneling Oxide,隧穿氧化层)NOR Flash 中的栅极堆栈结构,从下至上依次包括:栅氧化层、浮栅层、ONO层和控制栅层(未标示)。 In the present embodiment, the gate stack structure is ETOX (Electron Tunneling Oxide, tunneling oxide layer) gate stack structure in NOR Flash, from bottom to top comprises: a gate oxide layer, a floating gate layer, the ONO layer, and a control gate layer (not shown). 其中,在所述控制栅层的表面,还形成有氮化硅层250'作为保护层。 Wherein the surface of the control gate layer 250 is also formed with a 'silicon nitride layer as the protective layer.

[0076] 本实施例中,所述栅极堆栈结构20'之间的间距为500,4~1000 A,所述栅极堆栈结构的高度为3000 A~5000 A. [0076] In this embodiment, the distance between the gate stack structure 20 'is 500,4 ~ 1000 A, the height of the gate stack structure is 3000 A ~ 5000 A.

[0077] 步骤S13 :在每一所述栅极堆栈结构的两侧形成第一侧墙; [0077] Step S13: a first spacer formed on each of both sides of the gate stack structure;

[0078] 继续参考图5所示,形成第一侧墙31'。 [0078] With continued reference to FIG. 5, a first spacer 31 'is formed. 本实施例中,所述第一侧墙31'为一薄层氧化硅层,其形成方法可以为:首先,在所述半导体衬底100'和所述氮化硅层250'上沉积一薄层氧化硅层,然后,利用等离子体刻蚀工艺刻蚀所述半导体衬底100'表面和所述氮化硅层250'上的氧化硅层,以形成位于所述栅极堆栈结构20'两侧的第一侧墙31'。 In this embodiment, the first sidewall 31 'is a thin silicon oxide layer formed by the process may be: First, the semiconductor substrate 100' is deposited on a thin silicon nitride layer 250 'and the layer of silicon oxide layer, then using a plasma etching process for etching the semiconductor substrate 100 'and a surface of the silicon nitride layer 250' on the silicon oxide layer to form a gate stack structure 20 is in the 'two the first side of the spacer 31 '.

[0079] 所述第一侧墙31的厚度为100 A~A:,非常的薄,故在形成所述第一侧墙31' 后,对相邻两栅极堆栈结构的之间间距的高宽比的改变不是很大。 The thickness of [0079] the first sidewall 31 is 100 A ~ A :, very thin, it is formed in the first sidewall 31 ', the gate stack structure between two adjacent high pitch aspect ratio change is not great.

[0080] 步骤S14 :在相邻两所述栅极堆栈结构之间的半导体衬底100'上形成镍化物; [0080] Step S14: forming a nickel compound semiconductor substrate between the two adjacent gate stack structure 100 ';

[0081] 参考图6和图7所示,首先,在所述半导体衬底100'上、所述氮化硅层250'上和所述第一侧墙31'的表面沉积镍层600' ;再次,进行退火,使得所述镍层600'和相邻两所述栅极堆栈结构20'之间暴露出来的半导体衬底100发生反应,以在半导体衬底100'的表面生成镍化物79' ;然后,去除多余的镍层600'。 [0081] Referring to FIG 6 and FIG 7, first, the semiconductor substrate 100 ', the silicon nitride layer 250' and on the first sidewall 31 'of the surface of the deposited nickel layer 600'; again, annealing, such that the nickel layer 600 'and the two adjacent gate stack structure 20' of the semiconductor substrate 100 exposed between the reaction, to the semiconductor substrate 100 'generates a nickel surface of 79' ; then, to remove excess nickel layer 600 '.

[0082] 在这一步骤中,由于相邻两栅极堆栈结构的之间仅仅形成有很薄的第一侧墙31', 所述相邻两栅极堆栈结构的之间的间距的高宽比还是比较大,所述镍层600能够顺利的沉积到所述半导体衬底100'的表面上。 [0082] In this step, since only the gate stack structure is formed between two adjacent first sidewall 31 with a thin ', the spacing between two adjacent gate stack structure height to width ratio is relatively large, the nickel layer 600 is deposited onto the smooth surface of the semiconductor substrate 100 '.

[0083] 步骤S15 :在所述第一侧墙和所述镍化物上形成第二侧墙。 [0083] Step S15: forming a second spacer on the first sidewall and said nickel compound.

[0084] 参考图8所示,形成第二侧墙32'。 As shown in [0084] Referring to Figure 8, a second spacer 32 'is formed. 本实施例中,所述第二侧墙32'的形成方法可以为:首先,在所述半导体衬底1〇〇'、第一侧墙31'和所述氮化硅层250'上沉积氮氧化硅层,然后,利用等离子体刻蚀工艺刻蚀所述半导体衬底100表面和所述氮化硅层250'上的氮氧化硅层,以形成位于所述栅极堆栈结构20'两侧的第二侧墙32'。 In this embodiment, the second spacer 32 'may be formed by a method as follows: First, the semiconductor substrate 1〇〇', a first spacer 31 'and the silicon nitride layer 250' is deposited on the nitrogen a silicon oxide layer, then using a process of etching the surface of the semiconductor substrate 100, and plasma etching the silicon nitride layer 250 'layer on the silicon oxynitride, positioned to form the gate stack structure 20' on both sides a second spacer 32 '.

[0085] 实施例二 [0085] Second Embodiment

[0086] 参考图9所示,结合图10至图14所示,本实施例提供一种快闪存储器的形成方法,具体如下: [0086] Referring to FIG 9, in conjunction with FIGS. 10 to 14, the present embodiment provides a method of forming a flash memory, as follows:

[0087] 步骤S21 :提供半导体衬底,所述半导体衬底上包括中心区域和外围区域; [0087] Step S21: providing a semiconductor substrate, comprising a central region and a peripheral region on said semiconductor substrate;

[0088] 如图10所示,提供半导体衬底100",所述半导体衬底上包括中心区域(cell)90" 和外围区域(periphery) 70"。本领域技术人员能够理解,在所述中心区域90"上形成存储阵列,在所述外围区域70"形成存储器的外围电路。在本实施例中,所述存储阵列为ETOX(Electron Tunneling Oxide,隧穿氧化层)NOR Flash。 [0088] As shown in FIG. 10, a semiconductor substrate 100 "includes a central region 90 (cell) on the semiconductor substrate" in the present art can be understood in the art and a peripheral region (periphery) 70 "., In the center region 90 'is formed on the memory array, the peripheral region 70' formed in a peripheral circuit of the memory. in the present embodiment, the memory array is ETOX (Electron tunneling oxide, tunneling oxide layer) NOR Flash.

[0089] 步骤S22 :在所述中心区域的半导体衬底上形成至少两个栅极堆栈结构,在所述外围区域的所述半导体衬底上从下至上依次形成栅氧化层和多晶硅层; [0089] Step S22: the at least two gate stack structure formed on the semiconductor substrate in the central region, from the bottom layer, forming a gate oxide and a polysilicon layer on the semiconductor substrate in the peripheral region;

[0090] 继续参考图10所示,在所述半导体衬底100"的中心区域90"上形成至少两个栅极堆栈结构20"。在本实施例中,所述栅极堆栈结构为ETOX(Electron Tunneling Oxide, 隧穿氧化层)NOR Flash中的栅极堆栈结构,从下至上依次包括:栅氧化层、浮栅层、ONO层和控制栅层(未标示)。其中,在所述控制栅层的表面,还形成有氮化硅层250"作为保护层。 [0090] With continued reference to FIG. 10, is formed on the semiconductor substrate 100 "in the central region 90" at least two gate stack structure 20. "In the present embodiment, the gate stack structure is ETOX ( Electron tunneling oxide, tunneling oxide layer) gate stack structure in NOR Flash, from bottom to top comprises: a gate oxide layer, a floating gate layer, the ONO layer and a control gate layer (not shown) wherein the control gate. surface layer, a silicon nitride layer 250 is also formed with a "protective layer. 本实施例中,所述栅极堆栈结构20"之间的间距为500Α~1000 Α,所述栅极堆栈结构的闻度为3000 Λ;~5(ΚΜ)Α<). In this embodiment, the distance "between the gate stack structure 20 is 500Α ~ 1000 Α, the audibility of the gate stack structure 3000 Λ; ~ 5 (ΚΜ) Α <).

[0091] 在所述半导体衬底100"的外围区域70形成栅氧化层110"和多晶硅层500"。在本实施例中,所述多晶硅层500"上还形成有氮化硅层250作为保护层。 [0091] The substrate 100 "of the peripheral region 70 is formed the gate oxide layer 110 'and the polysilicon layer 500 in the semiconductor." In the present embodiment, the polysilicon layer 500' is also formed on the silicon nitride layer 250 as a protective Floor.

[0092] 步骤S23 :在所述栅极堆栈结构两侧形成第一侧墙; [0092] Step S23: a first spacer formed on both sides of the gate stack structure;

[0093] 继续参考图10所示,形成第一侧墙31"。所述形成第一侧墙31"的实施方式与实施例一的步骤S13类似。 [0093] With continued reference to FIG. 10, a first spacer 31 ". The first spacer 31 is formed" in an embodiment of a process similar to Example S13 embodiment. 所述第一侧墙31"的厚度为100 A~300 A,非常的薄,故在形成所述第一侧墙31"后,对相邻两栅极堆栈结构的之间间距的高宽比的改变不是很大。 The first spacer 31 'thickness is 100 A ~ 300 A, very thin, so that in forming the first sidewall 31 ", the gate stack structure between two adjacent pitch aspect ratio the change is not great.

[0094] 步骤S24 :在相邻两所述栅极堆栈结构之间的半导体衬底上形成第一镍化物; [0094] Step S24: forming a first nickel compound on the semiconductor substrate between the two adjacent gate stack structure;

[0095] 参考图10和图11所示,类似实施例一中的步骤S14,在所述半导体衬底100"上、 所述氮化硅层250"上和所述第一侧墙31"的表面沉积镍层600",进行退火,在相邻两所述栅极堆栈结构之间的半导体衬底1〇〇"的表面生成第一镍化物79"。 [0095] with reference to FIGS. 10 and 11, in an embodiment similar to the embodiment of step S14, the semiconductor substrate 100 "on the silicon nitride layer 250 'and on the first sidewall 31" nickel layer deposited on the surface 600 ', annealing the semiconductor substrate adjacent to the gate stack structure 1〇〇 between the two "a nickel compound 79 to generate a first surface."

[0096] 在这一步骤中,由于中心区域90"上相邻两栅极堆栈结构的之间仅仅形成有很薄的第一侧墙31",所述相邻两栅极堆栈结构的之间的间距的高宽比还是比较大,所述镍层600"能够顺利的沉积到所述半导体衬底100"的表面上。 [0096] In this step, since the central region 90 'only is formed between two adjacent gate stack structure on which a thin first spacer 31', between two adjacent gate stack structure aspect ratio of the pitch is relatively large, the nickel layer 600 'can be smoothly deposited onto the semiconductor substrate 100 "on the surface.

[0097] 步骤S25 :在所述第一侧墙外侧形成第二侧墙; [0097] Step S25: the second spacer is formed outside the first sidewall;

[0098] 参考图12,类似实施例以中步骤S15,在所述中心区域90"的极堆栈结构外侧形成第二侧墙32",所述第二侧墙32"的材质为氮化硅,厚度为300 A~400 A,. [0098] Referring to FIG 12, embodiments similar to the step S15, "the second spacer 32 is formed outside of the electrode stack structure" in the central region 90, a material of the second spacer 32 "is silicon nitride, a thickness of 300 A ~ 400 A ,.

[0099] 步骤S26 :对所述多晶硅层和氧化硅层进行选择性刻蚀,以在所述外围区域形成至少两个栅极结构; [0099] Step S26: selectively etching the polysilicon layer and silicon oxide layer to form at least two gate structures in the peripheral region;

[0100] 参考图13所示,本步骤中,还包括先去除所述外围区域70"的氮化硅层250",以露出所述多晶硅层500"的步骤。在露出所述多晶硅层500"之后,对所述多晶硅层500"和栅氧化层110"进行选择性刻蚀,以形成外围区域70"上外围器件的栅极结构(未标示)。 [0100] With reference to FIG 13, in this step, further comprising removing said first peripheral region 70 'of silicon nitride layer 250', to expose the polysilicon layer 500 "steps in the polysilicon layer 500 is exposed." Thereafter, the 500 "and the gate oxide layer 110 'of the polysilicon layer is selectively etched to form a gate structure of the peripheral region 70' on the periphery of the device (not shown).

[0101] 步骤S27 :在所述栅极结构两侧形成第三侧墙; [0101] Step S27: forming a third sidewall spacer on the sides of the gate structure;

[0102] 继续参考图13所示,在所述栅极结构两侧形成第三侧墙33"的步骤包括:在所述中心区域90"和所述外围区域70"上沉积第三侧墙层330",其中,在所述中心区域90",所述第三侧墙层330"至少填满相邻两所述栅极堆栈结构20"之间的空隙。 [0102] With continued reference to FIG., The third spacer 33 is formed on the sides of the gate structure 13 'comprises the step of: in the central region 90 "and the peripheral region 70" of the third layer is deposited on the spacer 330 ", wherein, in the central region 90", the third spacer layer 330 is a gap between "at least two of said gate stack structure 20 adjacent to the fill."

[0103] 在沉积第三侧墙层330"之后,在所述外围区域70"进行各向异性等离子刻蚀,使得所述第三侧墙层330"形成所述外围区域70"上栅极结构两侧的第三侧墙33"。 [0103] In depositing a third spacer layer 330 ", the peripheral region 70 in the" anisotropic plasma etching, so that the third spacer layer 330 'forming the peripheral region 70 "on the gate structure third spacer 33 on both sides. "

[0104] 步骤S28 :在所述栅极结构的顶部以及两栅极结构之间的第三侧墙之间的半导体衬底上形成第二镍化物77"。 [0104] Step S28: second nickel compound is formed on the semiconductor substrate between the gate structure and the top of the third spacer 77 between the two gate structures. "

[0105] 参考图14所示,形成第二镍化物77"的方式,包括:首先,在所述中心区域90"和所述外围区域70"上沉积镍层;再次,进行退火,使得所述镍层和外围区域70"上相邻两所述栅极结构20"之间暴露出来的半导体衬底100"发生反应,以在半导体衬底100"的表面生成第二镍化物77" ;然后,去除多余的镍层。 [0105] Referring to FIG. 14, 77 form a second nickel compound "mode, comprising: first, in the central region 90" and the peripheral region 70 'is deposited on the nickel layer; again, annealing, such that the nickel layer and the peripheral region 70 'of the two adjacent gate structure 20' is exposed between the semiconductor substrate 100 'reacts to the semiconductor substrate 100 "generates a second surface of the nickel 77"; and then, removing excess nickel layer.

[0106] 综上所述,本发明通过先形成好栅极堆栈结构之间的镍化物,再形成外侧的第二侧墙的方式,避免了沉积镍层时,由于第二侧墙的阻挡,镍层接触不到半导体衬底1〇〇"的问题,导致后续不能形成镍化物的问题。 [0106] As described above, when the present invention by first forming a nickel compound between a good gate stack structure, the second spacer is further formed to the outer side, depositing a nickel layer is avoided, since the second side wall barrier, problems 1〇〇 reach the semiconductor substrate "nickel layer, a nickel compound lead to subsequent problems can not be formed.

[0107] 所以,本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。 [0107] Therefore, the present invention effectively overcomes the drawbacks of the prior art with the use of highly industrial value.

[0108] 上述实施例仅例示性说明本发明的原理及其功效,而非用于限制本发明。 [0108] the above-described embodiments are only to illustrate the principle and efficacy of the present invention, the present invention is not intended to be limiting. 任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下,对上述实施例进行修饰或改变。 Any person skilled in this art can be made at without departing from the spirit and scope of the present invention, the above-described embodiments can be modified or changed. 因此,举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变,仍应由本发明的权利要求所涵盖。 Thus, one skilled in the art that whenever all having ordinary knowledge in the technical ideas and spirit of the present invention is disclosed without departing from the completed equivalent modified or altered, yet the claims shall be encompassed by the present invention.

Claims (10)

  1. 1. 一种快闪存储器的形成方法,其特征在于,所述快闪存储器的形成方法至少包括: 提供半导体衬底; 在所述半导体衬底上形成至少两个栅极堆栈结构; 在每一所述栅极堆栈结构的两侧形成第一侧墙; 在相邻两所述栅极堆栈结构之间的半导体衬底上形成镍化物; 在所述第一侧墙和所述镍化物上形成第二侧墙。 1. A method of forming a flash memory, wherein the method of forming a flash memory includes at least: providing a semiconductor substrate; forming at least two gate stack structure on the semiconductor substrate; each the gate stack structure is formed on both sides of a first spacer; form a nickel compound on the semiconductor substrate between the two adjacent gate stack structure; forming on the first sidewall and said nickel compound The second side wall.
  2. 2. 根据权利要求1所述的快闪存储器的形成方法,其特征在于:相邻两所述栅极堆栈结构之间间隙的高宽比大于4. 5。 2. A method for forming a flash memory according to claim 1, characterized in that: an aspect ratio gap between adjacent two of said gate stack structure is greater than 4.5.
  3. 3. 根据权利要求1所述的快闪存储器的形成方法,其特征在于:所述第一侧墙的材质为氧化硅,厚度为100A~300A< 3. The method for forming a flash memory according to claim 1, characterized in that: the first spacer is made of silicon oxide, having a thickness of 100A ~ 300A <
  4. 4. 根据权利要求1所述的快闪存储器的形成方法,其特征在于:所述栅极堆栈结构从下至上依次包括:栅氧化层、浮栅层、0N0层、控制栅层和氮化硅层。 4. The method of forming a flash memory according to claim 1, wherein: said gate stack structure includes, in order from bottom to top: a gate oxide layer, a floating gate layer, layer 0n0, the control gate and the silicon nitride layer, Floor.
  5. 5. -种快闪存储器的形成方法,其特征在于,所述快闪存储器的形成方法至少包括: 提供半导体衬底,所述半导体衬底上包括中心区域和外围区域; 在所述中心区域的半导体衬底上形成至少两个栅极堆栈结构,在所述外围区域的所述半导体衬底上从下至上依次形成栅氧化层和多晶硅层; 在所述栅极堆栈结构两侧形成第一侧墙; 在相邻两所述栅极堆栈结构之间的半导体衬底上形成第一镍化物; 在所述第一侧墙外侧形成第二侧墙; 对所述多晶硅层和氧化硅层进行选择性刻蚀,以在所述外围区域形成至少两个栅极结构; 在所述栅极结构两侧形成第三侧墙; 在所述栅极结构的顶部以及两栅极结构之间的第三侧墙之间的半导体衬底上形成第二镍化物。 5. - The method for forming a flash memory, wherein the method of forming a flash memory includes at least: providing a semiconductor substrate, on the semiconductor substrate comprising a central region and a peripheral region; in the central region at least two gate stack structure formed on a semiconductor substrate, forming a gate from the bottom oxide layer and a polysilicon layer on the peripheral region of said semiconductor substrate; forming a first side of the stack on both sides of the gate structure wall; a first nickel compound is formed on the semiconductor substrate between the two adjacent gate stack structure; forming a second sidewall spacer on the outer side of the first sidewall; the polysilicon layer and silicon oxide layer is selected etchable to form at least two gate structures in the peripheral region; forming a third sidewall spacer on both sides of the gate structure; a third between the top of the gate structure and the gate structure of two It is formed on the second nickel compound semiconductor substrate between the spacers.
  6. 6. 根据权利要求5所述的快闪存储器的形成方法,其特征在于:在所述栅极堆栈结构两侧形成第一侧墙的步骤之前,还包括在在所述外围区域的多晶硅层上形成保护层的步骤,在所述第一侧墙和所述第一镍化物上形成第二侧墙的步骤之后,在对所述多晶硅层和氧化硅层进行选择性刻蚀的步骤之前,还包括去除所述保护层,以露出所述多晶硅层的步骤。 6. The method of claim 5 formed of a flash memory as claimed in claim, characterized in that: before the step of forming a first spacer on both sides of the gate stack structure, further comprising on said polysilicon layer in the peripheral region after the step of forming the protective layer, the step of forming a second spacer on said first sidewall and said first nickel compound, before the polysilicon layer and the silicon oxide layer by selective etching, further comprising removing the protective layer to expose said polysilicon layer step.
  7. 7. 根据权利要求5所述的快闪存储器的形成方法,其特征在于:在所述栅极结构两侧形成第三侧墙的步骤包括:在所述第二侧墙层、所述外围区域的栅极结构和暴露出来的半导体衬底上形成第三侧墙层,所述第三侧墙层至少填满相邻两所述栅极堆栈结构之间的空隙。 7. The method of forming a flash memory according to claim 5, wherein: the step of forming a third sidewall spacer on both sides of the gate structure comprises: the second spacer layer in the peripheral region forming a third spacer layer and the gate structure on the semiconductor substrate exposed, said third spacer layer to at least fill the gap between the two adjacent gate stack structure.
  8. 8. 根据权利要求5所述的快闪存储器的形成方法,其特征在于:相邻两所述栅极堆栈结构之间间隙的高宽比大于4. 5。 8. A method of forming a flash memory 5 according to claim, wherein: the aspect ratio of the gap between adjacent two of said gate stack structure is greater than 4.5.
  9. 9. 根据权利要求5所述的快闪存储器的形成方法,其特征在于:所述第一侧墙的材质为氧化硅,厚度为100A-3001 9. A method of forming a flash memory 5 according to the claim, characterized in that: the first spacer is made of silicon oxide, having a thickness of 100A-3001
  10. 10. 根据权利要求5所述的快闪存储器的形成方法,其特征在于:所述第二侧墙的材质为氮化娃,厚度为30.0A~40.01 5 10. The method of forming the flash memory according to claim, wherein: the second spacer is made of baby nitride, having a thickness of 30.0A ~ 40.01
CN 201410219995 2014-05-22 2014-05-22 Forming method of flash memory CN105097709A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 201410219995 CN105097709A (en) 2014-05-22 2014-05-22 Forming method of flash memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 201410219995 CN105097709A (en) 2014-05-22 2014-05-22 Forming method of flash memory

Publications (1)

Publication Number Publication Date
CN105097709A true true CN105097709A (en) 2015-11-25

Family

ID=54577830

Family Applications (1)

Application Number Title Priority Date Filing Date
CN 201410219995 CN105097709A (en) 2014-05-22 2014-05-22 Forming method of flash memory

Country Status (1)

Country Link
CN (1) CN105097709A (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040061169A1 (en) * 2002-09-30 2004-04-01 Heon-Heoung Leam Non-volatile memory device and method of manufacturing the same
KR100660074B1 (en) * 2003-10-10 2006-12-26 가부시끼가이샤 도시바 Semiconductor memory device with mos transistors having floating gate and control gate
CN101388411A (en) * 2007-09-12 2009-03-18 株式会社东芝 Semiconductor device and method for manufacturing the same
CN103208458A (en) * 2012-01-11 2013-07-17 华邦电子股份有限公司 Manufacturing method of embedded flash memory

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040061169A1 (en) * 2002-09-30 2004-04-01 Heon-Heoung Leam Non-volatile memory device and method of manufacturing the same
KR100660074B1 (en) * 2003-10-10 2006-12-26 가부시끼가이샤 도시바 Semiconductor memory device with mos transistors having floating gate and control gate
CN101388411A (en) * 2007-09-12 2009-03-18 株式会社东芝 Semiconductor device and method for manufacturing the same
CN103208458A (en) * 2012-01-11 2013-07-17 华邦电子股份有限公司 Manufacturing method of embedded flash memory

Similar Documents

Publication Publication Date Title
US20140070302A1 (en) Three-dimensional semiconductor memory device and method for fabricating the same
US20150380431A1 (en) Semiconductor device having vertical channel and air gap, and method of manufacturing thereof
US20140162420A1 (en) Method of fabricating semiconductor devices having vertical cells
US20110316165A1 (en) Semiconductor Device and Method of Fabricating the Same
US20130049072A1 (en) Arrays Of Recessed Access Devices, Methods Of Forming Recessed Access Gate Constructions, And Methods Of Forming Isolation Gate Constructions In The Fabrication Of Recessed Access Devices
US20130307050A1 (en) Nonvolatile memory device and method for fabricating the same
US20120049377A1 (en) Semiconductor device and method of double photolithography process for forming patterns of the semiconductor device
JP2011211200A (en) Three-dimensional semiconductor device
US7985667B2 (en) Method for patterning semiconductor device having magnetic tunneling junction structure
US20140061780A1 (en) Semiconductor device including a gate dielectric layer
US20110189796A1 (en) Uniformity in the Performance of MTJ Cells
US20100252875A1 (en) Structure and fabricating process of non-volatile memory
US20130328199A1 (en) Semiconductor device with spacers for capping air gaps and method for fabricating the same
US20130299916A1 (en) Semiconductor devices and methods for fabricating the same
US20140159193A1 (en) Semiconductor device and method for fabricating the same
US20120326214A1 (en) Semiconductor device and method for fabricating the same
CN102629591A (en) Manufacturing method of array substrate, array substrate and display thereof
US20100096693A1 (en) Semiconductor device with vertical gate and method for fabricating the same
US20130099303A1 (en) Memory and manufacturing method thereof
JP2008205180A (en) Semiconductor device and its manufacturing method
US20130105983A1 (en) Semiconductor device and method forming patterns with spaced pads in trim region
US8273625B2 (en) Structure for flash memory cells
US20150325478A1 (en) Method of fabricating a semiconductor device and a semiconductor device fabricated by the method
CN102263057A (en) A method of forming a contact hole in a semiconductor device
US8916447B2 (en) Method of fabricating semiconductor device

Legal Events

Date Code Title Description
C06 Publication
C10 Entry into substantive examination