CN105049116A - Embedded optical time domain reflectometer based on FPGA and wireless communication technology - Google Patents
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Abstract
The invention provides an embedded optical time domain reflectometer based on a FPGA and a wireless communication technology, solves the problems of the existing optical time domain reflectometer, such as high cost, poor function expansion, inconvenience in software upgrading and small memory space, and belongs to the technical field of optical fibre communication. The optical time domain reflectometer comprises a FPGA control module, an Ethernet interface module, a wireless communication module, a laser device, a directional coupler, a photoelectric detector, a signal conditioning unit, an A/D conversion module, an optical fibre connector, a power supply and a SRAM unit; and the FPGA control module comprises an A/D conversion controller, a Nios II processor, a SRAM controller, a filter, an Avalon internal exchange bus, a laser device control module, a wireless communication controller and an Ethernet interface controller. The embedded optical time domain reflectometer based on FPGA and wireless communication technology has the characteristics of small volume, low cost, high reliability, strong expandability, convenience in software upgrading, and the like.
Description
Technical field
The present invention relates to a kind of optical time domain reflectometer, belong to technical field of optical fiber communication.
Background technology
Optical time domain reflectometer (OpticalTimeDomainReflectometer, be called for short OTDR) be scattering when utilizing light to transmit in a fiber and reflection and the precision instrument made, it is widely used in the field monitor of Fiber connection and junction loss and measures and evaluate.Among the maintenance of lightguide cable link, construction, repairing, OTDR can carry out the measurement of the aspects such as fiber lengths, Optical Fiber Transmission decay, joint decay and fault location more accurately.
Usually the parts such as optical path, Signal acquiring and processing circuit, display module are concentrated on one in traditional OTDR.There is the deficiencies such as cost is high, Function Extension is poor, software upgrading is inconvenient, memory space is little in the ODTR of this structure.In addition, their display resolution is general not high, and weight, volume are bigger than normal, and it is constant to carry operation.Some OTDR carries out communication by serial line interface (UART or USB) and PC, and PC carries out test parameter setting and test data display.Although their function expansibility is better, data space is also very large, but carries inconvenience when testing at the scene, and cost is higher.
Summary of the invention
For solving the problems such as optical time domain reflectometer cost is high, Function Extension is poor, software upgrading is inconvenient, memory space is little in prior art, the invention provides the embedded optical time domain reflectometer based on FPGA and wireless communication technique, the technical scheme taked is as follows:
The object of the present invention is to provide a kind of embedded optical time domain reflectometer based on FPGA and wireless communication technique, described embedded optical time domain reflectometer comprises: FPGA control module 1, ethernet interface module 2, wireless communication module 3, laser 4, directional coupler 5, photodetector 6, signal condition unit 7, A/D modular converter 8, the optical fiber connector 9, power supply 10 and SRAM memory cell 11;
The Ethernet control signal I/O mouth of described FPGA control module 1 is connected with the control signal input/output port of ethernet interface module 2; The wireless communication signal I/O mouth of described FPGA control module 1 is connected with the control signal input/output port of wireless communication module 3; The wireless data output port of described wireless communication module 3 is connected with the receive data by wireless port of intelligent terminal platform with wireless communication mode; The laser control signal output port of described FPGA control module 1 is connected with the control signal input port of laser 4; The storage control signal I/O mouth of described FPGA control module 1 is connected with the control signal input/output port of SRAM memory cell 11;
The light pulse signal output port of described laser 4 is connected with the optical signal input mouth of directional coupler 5; The light signal output end mouth a of described directional coupler 5 is connected with the optical signal input mouth of the optical fiber connector 9, and the light signal output end mouth b of described directional coupler 5 is connected with the optical signal input mouth of photodetector 6; The other end of the described optical fiber connector 9 connects testing fiber; The light signal output end mouth of described photodetector 6 is connected with the signal input port of signal condition unit 7; The signal output port of described signal condition unit 7 is connected with the signal input port of A/D modular converter 8; The signal output port of described A/D modular converter 8 is connected with the digital signal input end mouth of described FPGA control module 1.
Preferably, described FPGA control module 1 for controlling the operation to described ethernet interface module 2, wireless communication module 3, laser 4, directional coupler 5, photodetector 6, signal condition unit 7, A/D modular converter 8, the optical fiber connector 9 and SRAM memory cell 11, and inputs data to described ethernet interface module 2, wireless communication module 3, A/D modular converter 8 and SRAM memory cell 11 and processes; Described ethernet interface module 2 transmits for the Ethernet mode of data; Described wireless communication module 3 transmits for the wireless communication mode of data; Described laser 4 is for generation of the light pulse signal of certain pulse duration, and described pulse duration is that 5ns ~ 2us can select; Described directional coupler 5 for by scattering and reverberation directional transmissions in photodetector 6; The rayleigh backscattering produced when described photodetector 6 is for transmitting light pulse signal in a fiber and the light signal of Fresnel reflection are converted to the signal of telecommunication; Signal condition unit 7, for exporting the conditioning of the signal of telecommunication to described photodetector 6, makes the described signal of telecommunication meet the input standard of A/D modular converter 8; Described A/D modular converter 8 is for being converted into digital signal by analog electrical signal; Described SRAM memory cell 11 is for storing the test data of described FPGA control module 1.
Preferably, described laser 4 is semiconductor laser.
Preferably, described FPGA control module 1 comprises: A/D switching controller 1-1, NiosII processor 1-2, SRAM controller 1-3, filter 1-4, Avalon inner exchanging bus 1-5, laser control module 1-6, wireless communication controller 1-7, ethernet controller 1-8;
The data-signal transmit port of described NiosII processor 1-2, SRAM controller 1-3, filter 1-4, laser control module 1-6, wireless communication controller 1-7 and ethernet controller 1-8 is all connected with Avalon inner exchanging bus 1-5;
The control signal input port of described A/D switching controller 1-1 is the digital signal input end mouth of described FPGA control module 1, and the control signal output port of described A/D switching controller 1-1 is connected with the signal input port of filter 1-4;
The control signal output port of described SRAM controller 1-3 is the storage control signal output port of described FPGA control module 1;
The control signal output port of described laser control module 1-6 is the laser control signal output port of described FPGA control module 1;
The control signal output port of described wireless communication controller 1-7 is the wireless communication signal output port of described FPGA control module 1;
The control signal output port of described ethernet controller 1-8 is the Ethernet control signal output port of described FPGA control module 1.
Preferably, described A/D switching controller 1-1 for generation of the control signal to described A/D modular converter 8, the operation of control A/D modular converter 8, and receive A/D modular converter 8 export digital signal; Described NiosII processor 1-2 for controlling width and the time of described light pulse signal, and to the data analysis after filter 1-4 process; Described SRAM controller 1-3 is for controlling the operation of SRAM memory cell 11; Described filter 1-4 is used for the interference signal in filtering A/D switching controller 1-1 output signal; Described laser control module 1-6, for generation of laser 4 control signal, controls the operation of described laser 4; Described wireless communication controller 1-7 is for controlling the operation of wireless communication module 3; Described ethernet controller 1-8 is used for the operation of Control ethernet interface module 2.
Preferably, described FPGA control module 1 utilizes hardware description language to develop light pulse signal control module, and described light pulse signal control module hangs on Avalon inner exchanging bus 1-5, for generation of and output optical pulse signal.
Preferably, described intelligent terminal platform comprises optical time domain reflectometer application software and embedded database; Described application software is for showing measurement data and the result of described optical time domain reflectometer; Described embedded database is for storing described test data and result.
Preferably, described application software has test operation function, the real-time Presentation Function of test result, historical test data query function, event analysis printing interface, test data network sharing functionality and system parameter setting function.
Preferably, described optical time domain reflectometer separates with intelligent terminal platform display section, and test result and data are outwards sent to intelligent terminal platform with message format by described wireless communication module 3.
Beneficial effect of the present invention:
1. the embedded OTDR device with wireless communication function, due to without display screen, reduces the cost of system, and decreases system power dissipation significantly, extend the power-on time of battery.
2. adopt single fpga chip to realize the controlling functions of light source, data acquisition, transfer of data, improve the reliability of system, stability.
3. test optical fiber part is separated with result display section, utilizes smart mobile phone or flat board to realize test result display, alleviates the labour intensity (smart mobile phone or dull and stereotyped weight ratio lighter) of operating personnel.
4. flexible working mode, be easy to expansion, an intelligent terminal can control multiple work with the embedded OTRD device of wireless communication function simultaneously.
5.OTDR system needs the signal obtaining whole piece optical fiber usually, and data volume is huge.Adopt FPGA to carry out data processing, improve the data-handling capacity of system and decrease the time of transfer of data.In a sense, improve the certainty of measurement (identical Measuring Time) of OTDR.
This device has the features such as volume is little, cost is low, reliability is high, autgmentability is strong, software function upgrading is convenient.Utilize it can carry out fiber lengths, Optical Fiber Transmission decay, joint decay and fault location to measure, measure the fermentation such as evaluation at the field monitor of Fiber connection and junction loss and play a significant role.
Accompanying drawing explanation
Fig. 1 is the structural representation of the embedded optical time domain reflectometer based on FPGA and wireless communication technique of the present invention;
Fig. 2 is the internal structure schematic diagram of FPGA control module 1 of the present invention.
Embodiment
Below in conjunction with specific embodiment, the present invention will be further described, but invention is not by the restriction of embodiment.
Fig. 1 is the structural representation of the embedded optical time domain reflectometer based on FPGA and wireless communication technique of the present invention, Fig. 2 is the internal structure schematic diagram of described FPGA control module 1, as can be seen from Fig. 1 to Fig. 2, this embedded optical time domain reflectometer is by lithium battery power supply, be control core with FPGA, do not use display module., described embedded optical time domain reflectometer comprises: FPGA control module 1, ethernet interface module 2, wireless communication module 3, laser 4, directional coupler 5, photodetector 6, signal condition unit 7, A/D modular converter 8, the optical fiber connector 9, power supply 10 and SRAM memory cell 11; The Ethernet control signal I/O mouth of described FPGA control module 1 is connected with the control signal input/output port of ethernet interface module 2; The wireless communication signal I/O mouth of described FPGA control module 1 is connected with the control signal input/output port of wireless communication module 3; The wireless data output port of described wireless communication module 3 is connected with the receive data by wireless port of intelligent terminal platform with wireless communication mode, wherein, intelligent terminal platform can select the smart mobile phone or panel computer with wireless communication function, user can select voluntarily, installs corresponding software and can realize the functions such as test data display; The laser control signal output port of described FPGA control module 1 is connected with the control signal input port of laser 4; The storage control signal I/O mouth of described FPGA control module 1 is connected with the control signal input/output port of SRAM memory cell 11;
The light pulse signal output port of described laser 4 is connected with the optical signal input mouth of directional coupler 5; The light signal output end mouth a of described directional coupler 5 is connected with the optical signal input mouth of the optical fiber connector 9, and the light signal output end mouth b of described directional coupler 5 is connected with the optical signal input mouth of photodetector 6; The other end of the described optical fiber connector 9 connects testing fiber; The light signal output end mouth of described photodetector 6 is connected with the signal input port of signal condition unit 7; The signal output port of described signal condition unit 7 is connected with the signal input port of A/D modular converter 8; The signal output port of described A/D modular converter 8 is connected with the digital signal input end mouth of described FPGA control module 1.
Described FPGA control module 1 for controlling the operation to described ethernet interface module 2, wireless communication module 3, laser 4, directional coupler 5, photodetector 6, signal condition unit 7, A/D modular converter 8, the optical fiber connector 9 and SRAM memory cell 11, and inputs data to described ethernet interface module 2, wireless communication module 3, A/D modular converter 8 and SRAM memory cell 11 and processes; Described ethernet interface module 2 transmits for the Ethernet mode of data; Described wireless communication module 3 transmits for the wireless communication mode of data; Described laser 4 is semiconductor laser, and for generation of the light pulse signal of certain pulse duration, described pulse duration is that 5ns ~ 2us can select; Described directional coupler 5 for by scattering and reverberation directional transmissions in photodetector 6; The rayleigh backscattering produced when described photodetector 6 is for transmitting light pulse signal in a fiber and the light signal of Fresnel reflection are converted to the signal of telecommunication; Signal condition unit 7, for exporting the conditioning of the signal of telecommunication to described photodetector 6, makes the described signal of telecommunication meet the input standard of A/D modular converter 8; Described A/D modular converter 8 is for being converted into digital signal by analog electrical signal; Described SRAM memory cell 11 is for storing the test data of described FPGA control module 1.
As can be seen from Figure 2, described FPGA control module 1 comprises: A/D switching controller 1-1, NiosII processor 1-2, SRAM controller 1-3, filter 1-4, Avalon inner exchanging bus 1-5, laser control module 1-6, wireless communication controller 1-7, ethernet controller 1-8;
The data-signal transmit port of described NiosII processor 1-2, SRAM controller 1-3, filter 1-4, laser control module 1-6, wireless communication controller 1-7 and ethernet controller 1-8 is all connected with Avalon inner exchanging bus 1-5; The control signal input port of described A/D switching controller 1-1 is the digital signal input end mouth of described FPGA control module 1, and the control signal output port of described A/D switching controller 1-1 is connected with the signal input port of filter 1-4; The control signal output port of described SRAM controller 1-3 is the storage control signal output port of described FPGA control module 1; The control signal output port of described laser control module 1-6 is the laser control signal output port of described FPGA control module 1; The control signal output port of described wireless communication controller 1-7 is the wireless communication signal output port of described FPGA control module 1; The control signal output port of described ethernet controller 1-8 is the Ethernet control signal output port of described FPGA control module 1.
Described A/D switching controller 1-1 for generation of the control signal to described A/D modular converter 8, the operation of control A/D modular converter 8, and receive A/D modular converter 8 export digital signal; Described NiosII processor 1-2 for controlling width and the time of described light pulse signal, and to the data analysis after filter 1-4 process; Described SRAM controller 1-3 is for controlling the operation of SRAM memory cell 11; Described filter 1-4 is used for the interference signal in filtering A/D switching controller 1-1 output signal; Described laser control module 1-6, for generation of laser 4 control signal, controls the operation of described laser 4; Described wireless communication controller 1-7 is for controlling the operation of wireless communication module 3; Described ethernet controller 1-8 is used for the operation of Control ethernet interface module 2.
Described FPGA control module 1 utilizes hardware description language to develop light pulse signal control module, and described light pulse signal control module hangs on Avalon inner exchanging bus 1-5, for generation of and output optical pulse signal.Described intelligent terminal platform comprises optical time domain reflectometer application software and embedded database; Described application software is for showing measurement data and the result of described optical time domain reflectometer; Described embedded database is for storing described test data and result.Described application software has test operation function, the real-time Presentation Function of test result, historical test data query function, event analysis printing interface, test data network sharing functionality and system parameter setting function.The part of detecting of described embedded optical time domain reflectometer separates with data display unit, by described wireless communication module 3, test result and data is outwards sent to intelligent terminal platform with message format.
Described FPGA control module 1 utilizes hardware designed language HDL or C language to develop light pulse signal control module, and described light pulse signal control module hangs on Avalon inner exchanging bus 1-5; Width and the time of described light pulse signal control module output optical pulse signal control by NiosII processor 1-2.Light pulse signal control module controls the light signal that semiconductor laser (LD) 4 produces one fixed width, and through directional coupler 5, light pulse signal is injected in fiber optic network to be measured.Test result and data are outwards sent to intelligent terminal with message format by described wireless communication module 3.
Described FPGA control module 1 controls the light pulse signal that semiconductor laser (LD) 4 produces one fixed width, be injected in optical fiber to be tested by light signal after directional coupler 5, rayleigh backscattering and Fresnel reflection is produced when light transmits in a fiber, utilize photodetector 6 that the light signal of scattering and reflection is converted to the signal of telecommunication, by the A/D switching controller 1-1 control A/D modular converter 8 of FPGA control module 1 inside, analog electrical signal is converted to digital quantity, and digital quantity is inputted FPGA control module 1, test data is kept in SRAM memory cell 11 after filter 1-4.Then NiosII processor 1-2 analyzes the test data after filter 1-4 process, and test result and test data is sent by WiFi/ bluetooth/Zigbee or other wireless communication modes.In addition, device also with ethernet interface module 2, also can by wired mode extraneous communication test data is sent in network data base.
In order to show the test result of described embedded optical time domain reflectometer (OTDR), the invention of this reality proposes to adopt Application and Development software (APP) on intelligent terminal (as smart mobile phone or panel computer) platform to show the method for test data.The wireless communication function opening intelligent terminal receives the test data that OTDR sends, by analysis after process in sharpness screen display measurement result, and test result to be kept in the embedded database in terminal.
Described laser control module 1-6, A/D switching controller 1-1, filter 1-4 are all inner at fpga chip, and fpga chip selects the family chip of the support NiosII soft-core processor of altera corp.Described wireless communication mode can be WiFi, bluetooth, Zigbee or other wireless communication methods.FPGA controls wireless communication module and the information such as test result, test data is outwards sent with message format.Meanwhile, Ethernet interface and the external world is utilized to carry out data interaction.
Test result display is implemented:
Main frame and lithium battery weight are less than 0.8kg, intelligent terminal platform (conventional smart mobile phone or panel computer) weight is less than 150g, test data collection part is separated with display section, only needs hand-held display section during user operation, more convenient operation, flexibly; Main frame stream time was more than 20 hours.Use and there is the smart mobile phone of WiFi or Bluetooth function or the panel computer intelligent display terminal as test data (if OTDR end uses Zigbee or other wireless communication modes, the additional receiver module of OTG function of smart mobile phone or panel computer is then utilized to realize transfer of data), the speed of this Wireless Data Transmission mode is much larger than the communication speed of serial mode.Open WiFi or the Bluetooth function of intelligent terminal, be connected with above-mentioned OTDR device.After successful connection, utilize special APP to carry out data communication, realize the real-time display of test data, historical test data inquiry, test parameter setting, the functions such as test data network is shared.The test data of intelligent terminal for reception can be forwarded to database server in the Internet, carries out test data analysis, and analysis result is turned back to intelligent terminal by the technical staff of skilful service.Such working experience is not that the operating personnel enriched very much also can carry out on-the-spot test.
Realization event analytic function embodiment one:
In the existing event analysis functional module of FPGA inside exploitation, real-time analysis is carried out to test data, analysis result is sent to intelligent terminal by wireless transmission method and shows.
Realization event analytic function embodiment two:
The test data of OTDR is directly sent to intelligent terminal by wireless network, intelligent terminal platform can select the smart mobile phone or panel computer with wireless communication function, user can select voluntarily, installs corresponding software and can realize the functions such as test data display, event analysis.
Although the present invention with preferred embodiment openly as above; but it is also not used to limit the present invention, any person skilled in the art, without departing from the spirit and scope of the present invention; can do various change and modification, what therefore protection scope of the present invention should define with claims is as the criterion.
Claims (9)
1. based on the embedded optical time domain reflectometer of FPGA and wireless communication technique, it is characterized in that, comprising: FPGA control module (1), ethernet interface module (2), wireless communication module (3), laser (4), directional coupler (5), photodetector (6), signal condition unit (7), A/D modular converter (8), the optical fiber connector (9), power supply (10) and SRAM memory cell (11); The Ethernet control signal I/O mouth of described FPGA control module (1) is connected with the control signal input/output port of ethernet interface module (2); The wireless communication signal I/O mouth of described FPGA control module (1) is connected with the control signal input/output port of wireless communication module (3); The wireless data output port of described wireless communication module (3) is connected with the receive data by wireless port of intelligent terminal platform with wireless communication mode; The laser control signal output port of described FPGA control module (1) is connected with the control signal input port of laser (4); The storage control signal I/O mouth of described FPGA control module (1) is connected with the control signal input/output port of SRAM memory cell (11); The light pulse signal output port of described laser (4) is connected with the optical signal input mouth of directional coupler (5); Light signal output end mouth (a) of described directional coupler (5) is connected with the optical signal input mouth of the optical fiber connector (9), and light signal output end mouth (b) of described directional coupler (5) is connected with the optical signal input mouth of photodetector (6); The other end of the described optical fiber connector (9) connects testing fiber; The light signal output end mouth of described photodetector (6) is connected with the signal input port of signal condition unit (7); The signal output port of described signal condition unit (7) is connected with the signal input port of A/D modular converter (8); The signal output port of described A/D modular converter (8) is connected with the digital signal input end mouth of described FPGA control module (1).
2. optical time domain reflectometer according to claim 1, it is characterized in that, comprising: FPGA control module (1), ethernet interface module (2), wireless communication module (3), laser (4), directional coupler (5), photodetector (6), signal condition unit (7), A/D modular converter (8), the optical fiber connector (9), power supply (10) and SRAM memory cell (11); The Ethernet control signal I/O mouth of described FPGA control module (1) is connected with the control signal input/output port of ethernet interface module (2); The wireless communication signal I/O mouth of described FPGA control module (1) is connected with the control signal input/output port of wireless communication module (3); The wireless data output port of described wireless communication module (3) is connected with the receive data by wireless port of intelligent terminal platform with wireless communication mode; The laser control signal output port of described FPGA control module (1) is connected with the control signal input port of laser (4); The storage control signal I/O mouth of described FPGA control module (1) is connected with the control signal input/output port of SRAM memory cell (11); The light pulse signal output port of described laser (4) is connected with the optical signal input mouth of directional coupler (5); Light signal output end mouth (a) of described directional coupler (5) is connected with the optical signal input mouth of the optical fiber connector (9), and light signal output end mouth (b) of described directional coupler (5) is connected with the optical signal input mouth of photodetector (6); The other end of the described optical fiber connector (9) connects testing fiber; The light signal output end mouth of described photodetector (6) is connected with the signal input port of signal condition unit (7); The signal output port of described signal condition unit (7) is connected with the signal input port of A/D modular converter (8); The signal output port of described A/D modular converter (8) is connected with the digital signal input end mouth of described FPGA control module (1).
Described FPGA control module (1) for controlling the operation to described ethernet interface module (2), wireless communication module (3), laser (4), directional coupler (5), photodetector (6), signal condition unit (7), A/D modular converter (8), the optical fiber connector (9) and SRAM memory cell (11), and processes described ethernet interface module (2), wireless communication module (3), A/D modular converter (8) and SRAM memory cell (11) input data; Described ethernet interface module (2) transmits for the Ethernet mode of data; Described wireless communication module (3) transmits for the wireless communication mode of data; Described laser (4) is for generation of the light pulse signal of certain pulse duration, and described pulse duration is 5ns ~ 2us; Described directional coupler (5) for by scattering and reverberation directional transmissions in photodetector (6); The rayleigh backscattering produced when described photodetector (6) is for transmitting light pulse signal in a fiber and the light signal of Fresnel reflection are converted to the signal of telecommunication; Signal condition unit (7), for exporting the conditioning of the signal of telecommunication to described photodetector (6), makes the described signal of telecommunication meet the input standard of A/D modular converter (8); Described A/D modular converter (8) is for being converted into digital signal by analog electrical signal; Described SRAM memory cell (11) is for storing the test data of described FPGA control module (1).
3. optical time domain reflectometer according to claim 2, it is characterized in that, described laser (4) is semiconductor laser.
4. optical time domain reflectometer according to claim 2, it is characterized in that, described FPGA control module (1) comprising: A/D switching controller (1-1), NiosII processor (1-2), SRAM controller (1-3), filter (1-4), Avalon inner exchanging bus (1-5), laser control module (1-6), wireless communication controller (1-7), ethernet controller (1-8); Described NiosII processor (1-2), SRAM controller (1-3), filter (1-4), laser control module (1-6), wireless communication controller (1-7) is all connected with Avalon inner exchanging bus (1-5) with the data-signal transmit port of ethernet controller (1-8);
The control signal input port of described A/D switching controller (1-1) is the digital signal input end mouth of described FPGA control module (1), and the control signal output port of described A/D switching controller (1-1) is connected with the signal input port of filter (1-4);
The control signal output port of described SRAM controller (1-3) is the storage control signal output port of described FPGA control module (1);
The control signal output port of described laser control module (1-6) is the laser control signal output port of described FPGA control module (1);
The control signal output port of described wireless communication controller (1-7) is the wireless communication signal output port of described FPGA control module (1);
The control signal output port of described ethernet controller (1-8) is the Ethernet control signal output port of described FPGA control module (1).
5. optical time domain reflectometer according to claim 2, it is characterized in that, described A/D switching controller (1-1) is for generation of the control signal to described A/D modular converter (8), the operation of control A/D modular converter (8), and the digital signal receiving that A/D modular converter (8) exports; Described NiosII processor (1-2) is for controlling width and the time of described light pulse signal, and the data analysis after filter (1-4) is processed; Described SRAM controller (1-3) is for controlling the operation of SRAM memory cell (11); Described filter (1-4) is for the interference signal in filtering A/D switching controller (1-1) output signal; Described laser control module (1-6), for generation of laser (4) control signal, controls the operation of described laser (4); Described wireless communication controller (1-7) is for controlling the operation of wireless communication module (3); Described ethernet controller (1-8) is for the operation of Control ethernet interface module (2).
6. optical time domain reflectometer according to claim 2, it is characterized in that, described FPGA control module (1) utilizes hardware description language to develop light pulse signal control module, described light pulse signal control module hangs in valon inner exchanging bus (1-5), for generation of and output optical pulse signal.
7. optical time domain reflectometer according to claim 2, it is characterized in that, described optical time domain reflectometer separates with intelligent terminal platform display section, by described wireless communication module (3), test result and data is sent to the display of intelligent terminal platform with message format.
8. optical time domain reflectometer according to claim 2, it is characterized in that, described intelligent terminal platform comprises optical time domain reflectometer application software and embedded database; Described application software is for showing measurement data and the result of described optical time domain reflectometer; Described embedded database is for storing described test data and result.
9. optical time domain reflectometer according to claim 7, it is characterized in that, described application software has test operation function, the real-time Presentation Function of test result, historical test data query function, event analysis printing interface, test data network sharing functionality and system parameter setting function.
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