CN105024005A - Pluggable electric connection structure of wafer level semiconductor device - Google Patents
Pluggable electric connection structure of wafer level semiconductor device Download PDFInfo
- Publication number
- CN105024005A CN105024005A CN201410175210.4A CN201410175210A CN105024005A CN 105024005 A CN105024005 A CN 105024005A CN 201410175210 A CN201410175210 A CN 201410175210A CN 105024005 A CN105024005 A CN 105024005A
- Authority
- CN
- China
- Prior art keywords
- semiconductor device
- wafer level
- level semiconductor
- electric connection
- connection structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
The present invention discloses a pluggable electric connection structure of a wafer level semiconductor device. The structure comprises an insulating substrate and an elastic conductive mechanism. The elastic conductive mechanism is fixedly connected with the insulating substrate. An elastic clamping structure used for clamping and fixing the wafer level semiconductor device is formed between a selected position and the insulating substrate on one end or between two ends of the elastic conductive mechanism. When the wafer level semiconductor device is inserted in the elastic clamping structure, the selected position on one end or between two ends of the elastic conductive mechanism electrically contacts with the cathode or the anode of the wafer level semiconductor device. The wafer level semiconductor device comprises a wafer level substrate and a plurality of functional unit cells formed by direct machining an epitaxial layer on a surface of the substrate. The pluggable electric connection structure is easy to process and low in cost. In installation, exchanging, and maintaining, simple plugging operation is needed, the operation is convenient, and the wafer level semiconductor device would not be damaged. Personal safety of operating personnel is effectively ensured.
Description
Technical field
The present invention relates to a kind of semiconductor device, particularly a kind of plug-in electric connection structure being applied to wafer level semiconductor device.
Background technology
The power of people to LED illumination proposes more and more higher requirement in recent years.For obtaining high power light source, current industry is normally assembled in integrated for the multiple small size LED chips made with traditional handicraft in a device.And conduct wherein a kind of typical scheme, with reference to CN103137643A, CN103107250A etc., researcher is by being fixedly assembled in a substrate by multiple small size LED chip by the mode such as bonding, and adopt certain circuit form to be electrically connected by the plurality of LED chip, thus form high power LED device.By this type of technique, really high power LED device can be obtained, but wherein the operation such as requisite chip package, the system integration and installation procedure is all very complicated, thus total manufacturing cost of device is made sharply to promote, limit applying of high power LED device, and its job stability is generally poor.
The area increasing LED component chip is one of the most direct approach realizing great power LED, but for obtaining the product with desirable yield, still has many technical problems to need to solve.Inventor once proposed a kind of wafer level semiconductor device before this, if but in this wafer level semiconductor device, still adopt the electrical connection of conventional LED devices to design, then its not only making and installation difficulty, and damage after be usually difficult to change or maintenance, this will improve the use cost of consumer greatly.
Summary of the invention
In view of the deficiencies in the prior art, main purpose of the present invention is to provide a kind of Novel electric syndeton being applicable to wafer level semiconductor device.
For achieving the above object, present invention employs following technical scheme:
A kind of plug-in electric connection structure of wafer level semiconductor device, comprise insulating body and elastic conduction mechanism, described elastic conduction mechanism is fixedly connected with insulating body, selected position between wherein said elastic conduction mechanism one end or two ends and be formed between insulating body can for the resilient clamp structure gripping described wafer level semiconductor device, when described wafer level semiconductor device is inserted described resilient clamp structure, selected position between described elastic conduction mechanism one or both ends also with the negative electrode of described wafer level semiconductor device or anode in electrical contact.
Further, described wafer level semiconductor device comprises:
The wafer scale substrate of diameter more than 2 inches,
Be formed at substrate surface and the multiple series connection groups be arranged in parallel, each series connection group comprises be arranged in series multiple and joint group, each and joint group comprise the multiple function unit cells be arranged in parallel, wherein each function unit cell is all the separate functional units be processed to form by the semiconductor layer being directly epitaxially grown in described substrate surface
And wire, its be at least electrically connected in each series connection group one selected and between joint group and an electrode of described semiconductor device and/or two selected and between joint group, in order to make the conducting voltage of all series connection groups basically identical.
Further, described wafer level semiconductor device is also fixedly connected with at least one radiating shell, be provided with in described radiating shell to store up and receive the cavity of heat-conducting medium, and at least corresponding to the described function unit cell regional area of at least described wafer level semiconductor device one side is exposed in described cavity.
Further, described wafer level semiconductor device is light emitting semiconductor device, and the exiting surface of described light emitting semiconductor device is also distributed with anti-reflection mechanism.
Compared with prior art, the present invention has that structure is simple, low cost, is convenient to preparation and installs, be easy to the advantages such as replacing, maintenance.
Accompanying drawing explanation
In order to make the object of the invention, technical scheme and advantage clearly understand, below in conjunction with drawings and the specific embodiments, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
Fig. 1 a-Fig. 1 b is structural representation and the close-up schematic view of a kind of wafer level semiconductor device in one embodiment of this invention respectively;
Fig. 2 is the plug-in electric connection structure schematic diagram of a kind of wafer level semiconductor device in the present invention one typical embodiments;
Fig. 3 is a kind of structural representation with the wafer level semiconductor device of radiator structure in the present invention one typical embodiments;
Fig. 4 a-Fig. 4 b be in the present invention one typical embodiments a kind of there is the wafer level semiconductor device of radiator structure structural representation and A-A to cutaway view;
Fig. 5 a-Fig. 5 b is the structural representation of the cooling mechanism of wafer level semiconductor device in the some exemplary embodiments of the present invention respectively;
Fig. 6 is the radiator structure schematic diagram of a kind of wafer level semiconductor device in the present invention one typical embodiments;
Fig. 7 is the radiator structure schematic diagram of a kind of wafer level semiconductor device in the present invention one typical embodiments;
Fig. 8 a-8c is the schematic diagram of anti-reflection structure in the some exemplary embodiments of the present invention respectively;
Fig. 9 is the radiator structure schematic diagram of a kind of wafer level semiconductor device in the present invention one typical embodiments;
Description of reference numerals: wafer scale substrate 11, function unit cell 12, n-type semiconductor 121, p-type semiconductor 122, luminous quantum well 123, dielectric 124, interconnecting metal 13, negative electrode 14, anode 15, reflector 16, fin-shaped fin 171, thermal column 172, cavity 21, radiating shell 22, phase-change heat shell 23, radiating fin 24, insulating body 31, metal lead wire 32, metal spring leaf 33, solder layer 34, photon crystal structure 421, large lens 422, lenslet group 423, briquetting 51, sealing ring 53, bolt 52, phase-change heat liquid 61, phase transformation steam 62.
Embodiment
Purport of the present invention is the plug-in electric connection structure providing a kind of wafer level semiconductor device, it comprises insulating body and elastic conduction mechanism, described elastic conduction mechanism is fixedly connected with insulating body, selected position between wherein said elastic conduction mechanism one end or two ends and be formed between insulating body can for the resilient clamp structure gripping described wafer level semiconductor device, when described wafer level semiconductor device is inserted described resilient clamp structure, selected position between described elastic conduction mechanism one or both ends also with the negative electrode of described wafer level semiconductor device or anode in electrical contact,
Consult Fig. 1 a, the plural function unit cell 12 that aforementioned wafer level semiconductor device comprises wafer scale substrate 11 and is directly processed to form by the epitaxial loayer of growth in described substrate one side.
In the present invention, aforesaid " wafer scale " means that the diameter of substrate is more than 2 inches, and the material of described substrate can be selected from sapphire wafer, SiC wafer, Si wafer etc., and is not limited thereto.
In the present invention, aforementioned unit cell refers to the device cell with independent completion function, and the conductive semiconductor layer of any two unit cells is kept apart, and makes in arbitrary unit cell electricity independent; By metal interconnected, make multiple unit cell realize electricity and connect, form larger device, realize higher device performance, as: power increase etc.
Further, aforementioned wafer level semiconductor device can comprise:
Wafer scale substrate;
Be formed at substrate surface and the multiple series connection groups be arranged in parallel, each series connection group comprises be arranged in series multiple and joint group, each and joint group comprise the multiple function unit cells be arranged in parallel, and wherein each function unit cell is all the separate functional units be processed to form by the semiconductor layer being directly grown in described substrate surface; And,
Wire, its be at least electrically connected in each series connection group one selected and between joint group and an electrode of described semiconductor device and/or two selected and between joint group, in order to make the conducting voltage of all series connection groups basically identical.
Semiconductor device described in the present invention, it can be light emitting semiconductor device, such as LED, LD etc., can also for having other semiconductor function element.
Aforesaid epitaxial loayer, can also be called as " epitaxial layer ", " semiconductor function layer " etc., it comprises by dissimilar semi-conducting material usually, the heterostructure etc. that such as GaN, AlGaN etc. are formed.
Such as, for LED component, refer to Fig. 1 b, aforesaid epitaxial loayer can comprise p type semiconductor layer 122, n-type semiconductor layer 121 and active layer (luminous quantum well 123) etc.
For making this wafer scale LED chip be able to normal work, also interconnecting metal 13 etc. should be set between each unit cell, and make it be electrically connected with negative electrode 14, anode 15 etc.
Further, for wafer scale LED chip, it can have following design:
1) electricity independently LED unit cell is formed in chip;
2) first by parallel for the grouping of these unit cells, lost efficacy to prevent open circuit;
3) these and joint group are connected into some series connection groups, to prevent short-circuit failure; The progression of series connection limits by practical power, because if series connection progression is excessive, as 500 grades of series connection, 3.5 volts every grade, then the voltage of driving power needs to reach 1750 volts, in reality be difficult to realize and cost is very large, so and joint group be together in series, the rated voltage of each series connection group is comparatively rational scheme close to 110V, 220V or 380V of supply of electric power;
4) more some series connection groups are together in parallel, form large area, high-power LED chip.
Further, following optimization also can be adopted to relate to: in series connection group, design some redundant levels, in series connection group, redundant level is with the difference of parallel level in group of connecting, the electrode of redundant level is comparatively large, probe can be utilized to be in contact with it, carry out electrical testing, after chip manufacturing completes, electrical testing is done to series connection group and redundant level thereof, then according to the principle that cut-in voltage is consistent, wire jumper is carried out to redundant level and is connected to output electrode.In order to the cut-in voltage of each series connection group of exact matching and redundant level thereof more, adopt the mode of contact resistance, the operating current according to setting mates further.
" wire jumper " described herein, it is interpreted as: in order to the wire two demand points specific in circuit, particularly series circuit be directly electrically connected, and be separated with more than one between these two demand points in order to form the function element of this series circuit, such as more than one aforementioned and joint group.
Further, the technique of aforementioned wafer level semiconductor device mainly comprises following process: after growth forms epitaxial loayer on wafer scale substrate, through processes, thus on substrate, directly form multiple unit cells of the arrangement in array format.
Than the encapsulation procedure of conventional semiconductor chip or integrated semiconductor device, aforesaid wafer level semiconductor device processing procedure is at least thinning without the need to what comprise substrate, the operations such as cutting and sliver, also encapsulate without the need to a pair small size semiconductor chip, more after small size semiconductor chip is bonded to transfer substrates one by one, just follow-up operation can be carried out, and only once encapsulate, the agent structure of large power semiconductor device can be constructed, easy and simple to handle, cost is low, and evade and manyly may to cause epitaxial wafer or the impaired operation link of unit cell, and substantially can not cause environmental pollution.
Certainly, for making described wafer level semiconductor device finally can normally work, also work electrode need be set in each unit cell, make it to be connected with power supply.But this type of operation arranging work electrode can be known by those skilled in the art the technological means known and realize, such as, metal evaporation technique, micro fabrication etc., and be not limited thereto.
Especially for light emitting semiconductor device, if transparent wafers such as the substrate system sapphire wafer selected, when then utilizing wafer level semiconductor device of the present invention to apply as flip device, the substrate be not thinned also can be used as light-emitting window, thus the luminous efficiency of further boost device.
Further, be the work enabling described wafer level semiconductor device more stable, inventor is also studied the electrical connection form of wherein each unit cell and puts into practice, and proposes the design of following circuit layout, comprising:
On-chip part unit cell will be formed in and be defined as normal unit cell, all the other are defined as redundancy unit cell, wherein, normal unit cell system is as this wafer level semiconductor device effective working cell operationally, and quite a few in redundancy unit cell is as working cell for subsequent use, therefore the quantity of normal unit cell should be many as much as possible, and are far longer than redundancy unit cell;
Then, by the multi-level unit group that the plurality of normal unit cell is divided into two or more to be arranged in parallel, arbitrary multi-level unit group comprises the two or more first joint group that are arranged in series,
Further, M selected in arbitrary multi-level unit group first joint group also with N number of second and joint group connect and form a string joint group, finally make the conducting voltage of each series connection group basically identical (generally speaking, within ± 10%).
Wherein, arbitrary first and joint group comprises the normal unit cell that two or more is arranged in parallel, arbitrary second and joint group comprises the two or more redundancy unit cell be arranged in parallel, M is positive integer, and N is 0 or positive integer.
Designed by aforementioned circuit, can avoid breaking down because of one or several unit cell and causing other normal unit cell to work, also can eliminate the defect that the conducting voltage of a certain tandem working circuit that performance and all the other normal cell because of one or more normal cell in a certain multi-level unit group exist deviation and cause and other tandem working circuit exist deviation and cannot normally work.
Particularly preferred, M first can be selected from arbitrary multi-level unit group and joint group directly through wire with N number of second also joint group connect and form a string joint group, and remaining one or more exception first joint group are isolated away from operating circuit, thus make the conducting voltage of each series connection group basically identical, ensure the job stability of device, promote its task performance.Certainly, in some cases, in a certain series connection group, also can not comprise second and joint group, and the part first chosen wherein joint group are directly electrically connected with the work electrode of described semiconductor device by wire.
And as another comparatively preferred embodiment, also can also be provided with at least one build-out resistor in each series connection group aforementioned, this build-out resistor can select the resistance with fixed resistance, its resistance can according to each series connection group to connect with all the other group conducting voltage difference and determine, certainly also preferably can adopt adjustable resistance.
As of the present invention one more specifically embodiment, the preparation method of this wafer level semiconductor device can also comprise:
(1) directly described semiconductor material layer is processed to form multiple multiple unit cells with set-up function, and is normal unit cell by the section sets in all unit cells of normal region, all the other are set as redundancy unit cell;
(2) by the multi-level unit group that all normal unit cells are divided into two or more to be arranged in parallel, arbitrary multi-level unit group comprises the two or more first that is arranged in series and joint group, and arbitrary first and joint group comprises the normal unit cell that two or more is arranged in parallel;
(3) conducting voltage of each multi-level unit group is tested, and according to test result, selected M first from each multi-level unit group joint group with N number of second also joint group connect and form a string joint group, and conducting voltage under making each series connection group is in working order basically identical
Wherein, described second and joint group comprises the two or more redundancy unit cell be arranged in parallel, M is positive integer, and N is 0 or positive integer.
Such as, for a kind of wafer scale LED component, its multiple unit cells that can comprise wafer scale substrate and be fixedly arranged on substrate top end face (" first surface "), the plurality of unit cell system is formed by the semiconductor layer segmentation being grown directly upon this substrate first surface.This LED unit cell ties up under a fixed working voltage drives, can the functional unit of normal luminous, and, should electric isolation mutually between each LED unit cell.
Further, aforementioned unit cell system comprises multiple normal unit cell and multiple redundancy unit cell,
Wherein, the plurality of normal unit cell is divided into some multi-level unit groups be arranged in parallel, arbitrary multi-level unit group comprises some first and joint group that are arranged in series, and, M selected in arbitrary multi-level unit group first joint group also through wire directly with N number of second also joint group connect and form a string joint group, and the conducting voltage of all series connection groups is all basically identical.
" basically identical " herein refers to that the deviation amplitude of the conducting voltage of each series connection group is within ± 10%.
Aforementioned arbitrary first and joint group comprises the normal unit cell that two or more is arranged in parallel, arbitrary second and joint group comprises the two or more redundancy unit cell be arranged in parallel, M is positive integer, and N is 0 or positive integer.
Such as, when N is 0, in each multi-level unit group, a specific site can be chosen directly be electrically connected with a work electrode of device through wire, that is with the also a string joint group of joint group series connection formation of part or all of first in each multi-level unit group, and finally make the conducting voltage of all series connection groups all basically identical.
Further, in another preferred embodiment of the present invention, also can in the circuit structure of aforesaid embodiment, at least one build-out resistor is accessed in each series connection group, this build-out resistor specifically can adjust according to the diversity factor of series connection group conducting voltage each in previous embodiment, and the final difference eliminating the conducting voltage of each series connection group, make obtained wafer scale LED component have best job stability and luminous efficiency.
Further, the conducting voltage of described series connection group can be 110V, 220V or 380V.
In the aforementioned embodiment, for realizing the electrical connection between unit cell, all kinds of metal evaporations that industry can be adopted to know know, deposition and micro-nano technology technique process the electrical interconnection between work electrode and unit cell on each unit cell.
Certainly, for making described wafer level semiconductor device finally can normally work, also work electrode need be set in each unit cell, make it to be connected with power supply.But this type of operation arranging work electrode can be known by those skilled in the art the technological means known and realize, such as, metal evaporation technique, micro fabrication etc., and be not limited thereto.
In addition, for aforesaid wafer scale LED component, its preparation work can comprise:
(1) described semiconductor material layer is processed to form multiple unit cells with set-up function, and is normal unit cell by the section sets in all unit cells of normal region, all the other are set as redundancy unit cell;
(2) by the multi-level unit group that all normal unit cells are divided into two or more to be arranged in parallel, arbitrary multi-level unit group comprises the two or more first that is arranged in series and joint group, and arbitrary first and joint group comprises the normal unit cell that two or more is arranged in parallel;
(3) conducting voltage of each multi-level unit group is tested, and according to test result, selected M first from each multi-level unit group joint group directly through wire with N number of second also joint group connect and form a string joint group, and conducting voltage under making each series connection group is in working order basically identical
Wherein, described second and joint group comprises the two or more redundancy unit cell be arranged in parallel, M is positive integer, and N is 0 or positive integer.
Further, also at least one build-out resistor can be set in each series connection group.
Further, then refer to Fig. 2, still for LED component, among a comparatively preferred embodiment, aforementioned flexible conductive mechanism comprises metal spring leaf 33, and described metal spring leaf one end is fixedly connected with insulating body 31, and the other end is movable end.
Among one more specifically case study on implementation, described metal spring leaf the other end has at least one arcuate structure, when wafer scale LED component is inserted aforementioned flexible clamp structure, wherein the top ends of at least one arcuate structure and the negative electrode of wafer scale LED component or anode in electrical contact.
Further, this elastic conduction mechanism is fixedly connected with an end of this insulating body, and the other end has a protuberance, forms this resilient clamp structure between the selected position between this protuberance and this elastic conduction mechanism one or both ends.
Wherein, when this wafer scale LED component is inserted this resilient clamp structure, this insulating body contacts with this substrate another side.
Among a feasible case study on implementation, this elastic conduction mechanism can be connected with power electric through the wire (metal lead wire 32) be distributed on this insulating body.
Refer to Fig. 3 again, as one of comparatively preferred embodiment, still for LED component, this wafer scale LED component is also fixedly connected with at least one radiating shell 22, the plural function unit cell 12 that this wafer scale LED chip comprises wafer scale substrate 11 and is directly processed to form by the epitaxial loayer of growth in described substrate one side, be provided with in described radiating shell to store up and receive the cavity 21 of heat-conducting medium, and the regional area corresponding to described function unit cell of described wafer level semiconductor device one side is exposed in described cavity.
Each unit cell aforementioned can comprise n-type semiconductor, p-type semiconductor, the luminous structure sheaf such as quantum well, dielectric.
Further, the one side being exposed in described cavity of this wafer scale LED chip also can be connected with reflector 16, and aforementioned function unit cell is distributed on the another side of this wafer scale LED chip.
Further, refer to Fig. 4 a-4b, in an embodiment of the present invention, also can be distributed with cooling mechanism on the regional area being exposed to the one side in described cavity of described wafer level semiconductor device.
Further, refer to Fig. 5 a, described cooling mechanism can comprise be connected to described wafer level semiconductor device one side on some fin-shaped fin 171, and the another side of this wafer level semiconductor device is distributed with function unit cell.
Further, refer to Fig. 5 b, described cooling mechanism can comprise the some thermal columns 172 in the one side being connected to described wafer level semiconductor device, and the another side of this wafer level semiconductor device is distributed with function unit cell.
Further, in an exemplary embodiments, consult Fig. 6, in aforementioned radiator structure, also briquetting 51 can be set, wherein the circumference of wafer level semiconductor device is fastened is held between described briquetting and radiating shell, and the circumference of described wafer level semiconductor device and be also respectively equipped with seal between described briquetting and radiating shell, as O RunddichtringO 53.Securing member such as bolt 52 grade wherein also can be utilized described briquetting and radiating shell to be fastenedly connected.
And in an exemplary embodiments, and as another kind of feasible embodiment, also described radiating shell and described wafer level semiconductor device can be welded and fixed.Such as, refer to Fig. 9, can utilize solder between substrate and radiating shell, form solder layer 34, thus substrate and radiating shell are sealedly and fixedly connected, the structure of this device so can be made more simply compact.
Aforesaid heat-conducting medium can adopt the material of flow morphology, such as water, heat conduction wet goods.
For increasing heat transfer efficiency, the heat-conducting medium entrance and exit with described cavity connects can be set on radiating shell, so that heat-conducting medium can circulate fast.
Certainly, aforementioned heat-conducting medium also can adopt the phase-change material of other type, such as acetone, alcohol, etc., and described radiating shell can adopt closed design.Consult Fig. 7, in an exemplary embodiments, this phase-change heat sink shell 23 can be distributed with the radiating fin 24 of some hollow, when wafer level semiconductor devices function, phase-change heat liquid 61 between the thermal column 172 being filled in its back side is by thermosetting phase transformation steam 62, and entering radiating fin and extraneous heat-shift, cohesion is phase-change heat liquid backflow again then, realizes the conduction of heat.
As further preferred embodiment, for the devices such as LED, please refer to Fig. 8 a-Fig. 8 c, the structural design of back side bright dipping can also be adopted, and photon crystal structure 421, large lens 422, lenslet group 423 etc. are set on exiting surface, light extraction efficiency can be improved so on the one hand, active area also can be made to be exposed in heat-conducting medium on the other hand, thus shorten thermally conductive pathways further, improve radiating efficiency.Certainly, for realizing such design, LED component should adopt the transparent substrates such as sapphire.In addition, for safety and the consideration of the aspect such as service behaviour ensureing LED component, among this embodiment, heat-conducting medium preferably adopts insulated heat-conducting medium, as heat conduction wet goods.
The present invention replaces traditional electric deriving structure by adopting this plug-in electric connection structure, not only be easy to processing, with low cost, and in installation, change, during maintenance, only wafer level semiconductor device need be inserted or pull away the resilient clamp structure be made up of elastic conduction mechanism and insulating base, simple and convenient, wafer level semiconductor device can not be undermined, and operating personnel plug by insulating body, ensure that the personal safety of operating personnel on the one hand, it also avoid on the other hand and cause the problems such as wafer level semiconductor device damage because of factors such as static electricity on human body.
Should be appreciated that in addition to the implementation, the present invention can also have other execution modes.All employings are equal to the technical scheme of replacement or equivalent transformation formation, all drop on the protection range of application claims.
Claims (10)
1. the plug-in electric connection structure of a wafer level semiconductor device, it is characterized in that comprising insulating body and elastic conduction mechanism, described elastic conduction mechanism is fixedly connected with insulating body, selected position between wherein said elastic conduction mechanism one end or two ends and be formed between insulating body can for the resilient clamp structure gripping described wafer level semiconductor device, when described wafer level semiconductor device is inserted described resilient clamp structure, selected position between described elastic conduction mechanism one or both ends also with the negative electrode of described wafer level semiconductor device or anode in electrical contact,
Wherein said wafer level semiconductor device comprises:
The wafer scale substrate of diameter more than 2 inches,
Be formed at substrate surface and the multiple series connection groups be arranged in parallel, each series connection group comprises be arranged in series multiple and joint group, each and joint group comprise the multiple function unit cells be arranged in parallel, wherein each function unit cell is all the separate functional units be processed to form by the semiconductor layer being directly epitaxially grown in described substrate surface
And wire, its be at least electrically connected in each series connection group one selected and between joint group and an electrode of described semiconductor device and/or two selected and between joint group, in order to make the conducting voltage of all series connection groups basically identical.
2. the plug-in electric connection structure of wafer level semiconductor device according to claim 1, it is characterized in that described elastic conduction mechanism comprises metal spring leaf, described metal spring leaf one end is fixedly connected with insulating body, and the other end is movable end.
3. the plug-in electric connection structure of wafer level semiconductor device according to any one of claim 1-2, it is characterized in that described metal spring leaf the other end has at least one arcuate structure, when described wafer level semiconductor device is inserted described resilient clamp structure, wherein the top ends of at least one arcuate structure and the negative electrode of described wafer level semiconductor device or anode in electrical contact.
4. the plug-in electric connection structure of wafer level semiconductor device according to any one of claim 1-3, it is characterized in that described elastic conduction mechanism is fixedly connected with an end of described insulating body, the other end has a protuberance, forms described resilient clamp structure between the selected position between described protuberance and described elastic conduction mechanism one or both ends.
5. the plug-in electric connection structure of wafer level semiconductor device according to any one of claim 1-4, is characterized in that described elastic conduction mechanism is connected with power electric through the wire be distributed on described insulating body.
6. the plug-in electric connection structure of wafer level semiconductor device according to any one of claim 1-5, it is characterized in that, when described wafer level semiconductor device is inserted described resilient clamp structure, described insulating body contacts with described substrate another side.
7. the plug-in electric connection structure of wafer level semiconductor device according to any one of claim 1-6, it is characterized in that described wafer level semiconductor device is also fixedly connected with at least one radiating shell, be provided with in described radiating shell to store up and receive the cavity of heat-conducting medium, and at least corresponding to the described function unit cell regional area of at least described wafer level semiconductor device one side is exposed in described cavity.
8. the plug-in electric connection structure of wafer level semiconductor device according to any one of claim 1-7, the at least regional area being exposed to the one side in described cavity that it is characterized in that at least described wafer level semiconductor device is distributed with cooling mechanism, and described cooling mechanism comprises plural sheet in the one side being at least connected to described wafer level semiconductor device and/or column radiating part.
9. the plug-in electric connection structure of wafer level semiconductor device according to any one of claim 1-8, is characterized in that described radiating shell being also distributed with the heat-conducting medium entrance and exit with described cavity connects;
And/or described radiating shell also has plural hollow radiating fin, described radiating fin inner chamber and described cavity connects.
10. the plug-in electric connection structure of wafer level semiconductor device according to any one of claim 1-9, it is characterized in that described wafer level semiconductor device is light emitting semiconductor device, and the exiting surface of described light emitting semiconductor device is also distributed with anti-reflection mechanism.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410175210.4A CN105024005B (en) | 2014-04-28 | 2014-04-28 | The plug-in electric connection structure of wafer level semiconductor device |
| JP2016548038A JP6352430B2 (en) | 2014-01-23 | 2015-01-16 | Wafer level semiconductor device and manufacturing method thereof |
| EP15740811.3A EP3098852B1 (en) | 2014-01-23 | 2015-01-16 | Wafer level semiconductor device and manufacturing method thereof |
| PCT/CN2015/070836 WO2015109968A1 (en) | 2014-01-23 | 2015-01-16 | Wafer level semiconductor device and manufacturing method thereof |
| US15/111,675 US9780276B2 (en) | 2014-01-23 | 2015-01-16 | Wafer-level semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410175210.4A CN105024005B (en) | 2014-04-28 | 2014-04-28 | The plug-in electric connection structure of wafer level semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105024005A true CN105024005A (en) | 2015-11-04 |
| CN105024005B CN105024005B (en) | 2017-12-01 |
Family
ID=54413820
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410175210.4A Active CN105024005B (en) | 2014-01-23 | 2014-04-28 | The plug-in electric connection structure of wafer level semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105024005B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107514833A (en) * | 2017-09-05 | 2017-12-26 | 北京冠洁超能新能源科技有限公司 | A kind of attachment structure of semiconductor chilling plate |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101211996A (en) * | 2006-12-29 | 2008-07-02 | 富准精密工业(深圳)有限公司 | LED module group |
| US20080179602A1 (en) * | 2007-01-22 | 2008-07-31 | Led Lighting Fixtures, Inc. | Fault tolerant light emitters, systems incorporating fault tolerant light emitters and methods of fabricating fault tolerant light emitters |
| CN202058788U (en) * | 2011-05-20 | 2011-11-30 | 中达光电工业（吴江）有限公司 | Fixing device of photoelectric device |
| CN203983338U (en) * | 2014-04-28 | 2014-12-03 | 中国科学院苏州纳米技术与纳米仿生研究所 | The plug-in electric connection structure of wafer level semiconductor device |
-
2014
- 2014-04-28 CN CN201410175210.4A patent/CN105024005B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101211996A (en) * | 2006-12-29 | 2008-07-02 | 富准精密工业(深圳)有限公司 | LED module group |
| US20080179602A1 (en) * | 2007-01-22 | 2008-07-31 | Led Lighting Fixtures, Inc. | Fault tolerant light emitters, systems incorporating fault tolerant light emitters and methods of fabricating fault tolerant light emitters |
| CN202058788U (en) * | 2011-05-20 | 2011-11-30 | 中达光电工业（吴江）有限公司 | Fixing device of photoelectric device |
| CN203983338U (en) * | 2014-04-28 | 2014-12-03 | 中国科学院苏州纳米技术与纳米仿生研究所 | The plug-in electric connection structure of wafer level semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107514833A (en) * | 2017-09-05 | 2017-12-26 | 北京冠洁超能新能源科技有限公司 | A kind of attachment structure of semiconductor chilling plate |
| CN107514833B (en) * | 2017-09-05 | 2023-05-23 | 北京冠洁超能新能源科技有限公司 | Connection structure of semiconductor refrigeration piece |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105024005B (en) | 2017-12-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TW535307B (en) | Package of light emitting diode with protective diode | |
| JP4948535B2 (en) | Panel type semiconductor module | |
| CN101465347A (en) | Light source die set and method of manufacturing the same | |
| TW201440265A (en) | LED component by integrating epitaxial structure and package substrate together and method of manufacturing the same | |
| US9859331B2 (en) | Preparation method for high-voltage LED device integrated with pattern array | |
| CN104269735A (en) | Mechanical connection conducting cooling type semiconductor laser unit stack packaging structure | |
| CN203983338U (en) | The plug-in electric connection structure of wafer level semiconductor device | |
| CN105720478A (en) | Conductive cooling type semiconductor laser with replaceable chip and preparation method thereof | |
| US20160308106A1 (en) | Floating heat sink support with copper sheets and led package assembly for led flip chip package | |
| TW201330337A (en) | LED chip structure, LED package substrate, LED package structure and method of forming same | |
| CN203871335U (en) | Wafer-level semiconductor device | |
| CN105024005A (en) | Pluggable electric connection structure of wafer level semiconductor device | |
| CN102255011A (en) | Manufacturing method and structure of high-voltage direct current (DC) light-emitting diode (LED) chip | |
| CN102255012B (en) | Manufacturing method and structure of high-voltage direct-current light-emitting diode chip | |
| CN105023889B (en) | Radiator structure applied to wafer level semiconductor device | |
| CN204190157U (en) | A kind of mechanical connection Conduction cooled type semiconductor laser stacks encapsulating structure | |
| CN204118059U (en) | Be applied to the radiator structure of wafer level semiconductor device | |
| JP2012174911A (en) | Thermoelectric conversion module | |
| WO2015109968A1 (en) | Wafer level semiconductor device and manufacturing method thereof | |
| CN208874535U (en) | Thermal energy convection heat emission type photovoltaic module | |
| CN205622043U (en) | Can replace conduction cooling type semiconductor laser of chip | |
| CN104810380B (en) | Wafer level semiconductor device and preparation method thereof | |
| CN105023932A (en) | Vertical LED array element integrated with LED package substrate by being combined with LED epitaxial structures | |
| CN209744078U (en) | LED lamp bead capable of improving fracture force | |
| CN205122582U (en) | High power density encapsulation module of LED formal dress chip |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |