CN104980144B - Frequency interface device and its operating method - Google Patents
Frequency interface device and its operating method Download PDFInfo
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- CN104980144B CN104980144B CN201410799403.7A CN201410799403A CN104980144B CN 104980144 B CN104980144 B CN 104980144B CN 201410799403 A CN201410799403 A CN 201410799403A CN 104980144 B CN104980144 B CN 104980144B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/08—Clock generators with changeable or programmable clock frequency
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/10—Distribution of clock signals, e.g. skew
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/18—Auxiliary circuits, e.g. for writing into memory
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/225—Clock input buffers
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- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Electronic Switches (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
The invention discloses a kind of frequency interface device and its operating method, which includes：One integrated circuit includes multiple input terminals；One internal circuit；One frequency circuit, the frequency circuit is located on the integrated circuit, and to provide an internal frequency signal to the internal circuit, the frequency circuit includes that multiple frequency inputs are electrically connected to multiple input terminal, and the frequency circuit is to generate the internal frequency signal using different groups of multiple input terminal in response to a parameter；And a frequency reservoir, to provide the parameter.A configurable frequency circuit on integrated circuit, integrated circuit are, for example, an integrated circuit memory, can be used to generate an internal frequency using external multiphase frequency and external single phase frequency with a format compatible with internal circuit.
Description
Technical field
The invention relates to a kind of device, in particular to a kind of device comprising integrated circuit and frequency interface and
Its method of operating.
Background technique
Integrated circuit generally comprises the offer of foreign frequency signal to the endpoint of device.Foreign frequency signal is slow via a frequency
It rushes device or other frequency circuits is transmitted to internal signal.
The process of the system or device that are executed using integrated circuit generally includes connection integrated circuit to a bus system
Or other provide the communication structure of foreign frequency signal.Therefore, the property of foreign frequency signal can be according to the system used
And it is used for integrated circuit.It can't always be known in advance and what kind of system or what kind of external frequency can be used
Rate.
In a typical integrated circuit, the single phase frequency circuit use on device is provided to a dedicated single frequency
One foreign frequency of rate foot position, for generating internal frequency with the circuit and external bus system on synchronous integrated circuit.Another
One is typically available in the integrated circuit of high speed operation, and the frequency circuit use on device is provided to a pair of dedicated frequency
One differential external frequency of foot position, for generating internal frequency with the circuit and external bus system on synchronous integrated circuit.When
When bus system does not meet format one internal frequency of execution that integrated circuit is set with one, integrated circuit can be considered as and system
It designs incompatible.
Therefore in need to provide a kind of technology to solve compatibility issue caused by this environment.
Summary of the invention
A configuration frequency circuit on an integrated circuit is provided in technique described herein, such as can be used to outside needing
Multi-endpoint frequency interface is used when portion's multiphase frequency, such as uses single-ended dot frequency interface when needing external single phase frequency, is used
An internal frequency signal is generated with a format compatible with internal circuit.This technology, which can overcome, is likely encountered various foreign frequencies
Compatibility issue caused by source.
The memory device comprising a configuration frequency interface is described herein, this configuration frequency interface provides a frenquency signal
To internal circuit.Internal circuit include one or more memory devices on peripheral device, memory array or peripheral device and
Memory array.Internal circuit described herein includes the circuit on integrated circuit.Also, it is shared in more than one integrated circuit
In the embodiment of the multi-chip package of one frenquency signal, internal circuit described herein includes the circuit in integrated antenna package.
On the one hand, this technology provides a device.This device includes an integrated circuit, and integrated circuit includes input terminal and interior
Portion's circuit.A frequency circuit on integrated circuit provides an internal frequency signal to internal circuit.Frequency on frequency circuit is defeated
Enter end and is electrically connected to multiple input terminals.Frequency circuit includes multiple sub-circuits.Multiple sub-circuits are to use different groups more
A input terminal is to generate corresponding frenquency signal.A selection circuit on integrated circuit responds a configuration parameters.Selection circuit is rung
One of multiple sub-circuits should be selected to provide corresponding frenquency signal as internal frequency signal in configuration parameters.Configuration ginseng
Number is stored a frequency configuration reservoir on the integrated.One-time programming memory component can be used in frequency configuration reservoir
It executes, such as the not fuse of erasing circuit or flash cell (fuses or flash memory cells).Also,
Other kinds of memory cell can be used to execute.
In embodiment described herein, one first sub-circuit in multiple sub-circuits uses the single of multiple input terminals
A input terminal generates the frenquency signal of corresponding first sub-circuit, such as can provide a single phase frequency by an external source.Multiple sons
One second sub-circuit of circuit generates the frenquency signal of corresponding second sub-circuit using two input terminals of multiple input terminals, such as
A two-phase frequency can be provided by an external source.
In embodiment described herein, the sub-circuit in multiple sub-circuits is common with meet internal circuit needs one
Format generates corresponding frequency.For example, when configuration frequency circuit is arranged to using any one sub-circuit, configuration frequency
The internal frequency that circuit generates can be a single phase frequency.
In some embodiments, one or more sub-circuits are by a multiphase of this group of input terminal corresponding in multiple input terminals frequency
Rate is converted to a single phase frequency.
Also, a kind of method that a device is described herein, the method are connect using a frequency combination flow process with a frequency is arranged
Mouth operation is likely encountered the compatible demand in various foreign frequency sources to meet.
Other aspects and advantages of the present invention can be found out from appended schema, detailed description and claim.
Detailed description of the invention
Fig. 1 is painted the simplification block diagram of the device comprising configuration frequency circuit as described herein.
Fig. 2 is painted the simplification block diagram of the configuration frequency circuit suitable for integrated circuit memory devices.
Fig. 3 is painted the more detailed block diagram of an embodiment of the configuration frequency circuit of the configuration of one selection of explanation.
Fig. 4 is painted the block diagram such as the different selection of the explanation one of Fig. 3.
Fig. 5 is painted the block diagram of the configuration frequency circuit of another embodiment of explanation one such as Fig. 3.
【Symbol description】
121：Input buffer
122：I/O circuit
123：Configuration frequency circuit
124：Input buffer
140：Controller
149：Configuration registers
150：Command decoder
151：State machine
160：The array of memory cell
161：Address decoder
163：Page buffer
174：Other peripheral circuits
175,275：Integrated circuit
280,281：Frequency source
201,202：Frequency pad 1, frequency pad N
203：Frequency circuit
204：Selection circuit
205,206：Line
230：Single-ended frequency source
211,212：Frequency pad 1, frequency pad 2
213A,233A：Single phase frequency buffer
213B,233B：Two-phase frequency buffer
220：Selector
225：Configuration reservoir
250,251：The element of ellipse instruction
216：Internal frequency
231：Differential frequency source
Specific embodiment
Referring to Fig.1~Fig. 5 provides the detailed description of the embodiment of the present invention.
Fig. 1 is painted the simplification block diagram of the integrated circuit 175 comprising configuration frequency circuit 123.Multiple endpoints are connected to group
State frequency circuit 123 (CLK endpoint (1) arrives CLK endpoint (N)).In this instance, integrated circuit 175 includes input/output I/O electricity
Road 122 is connected to the endpoint of data address signal.Also, integrated circuit includes that an input buffer 121 is connected to control news
The endpoint of number CNTR.Another input buffer 124 is connected to the endpoint of chip selection signal CS.
These endpoints may include engagement pad on integrated circuit or contact feet position or other can be used as external circuit in
The connection structure of the signal path of portion's circuit.For example, integrated circuit, which is sometimes packaged into, is easily processed and is assembled into print
On printed circuit board.The foot position that this encapsulation provides is provided from the signal road of the weld pad on the external circuit to chip on circuit board
Diameter.In some other examples, integrated-circuit die may include that pad or convex block are set as being directly connected to substrate.Other connection knots
Structure can also be used to provide the endpoint of integrated circuit.
Integrated circuit 175 includes the array 160 of memory cell.Array 160 includes a flash array, and flash array is set
It is set to a NOR structure, NAND structure or other structures.
One address decoder 161 is couple to array 160.Address is supplied to integrated circuit 175 and provides and translates to address
Code device 161.Address decoder 161 may include word-line decoder, address provided by bit line decoder and other decodable codes and select
Select the suitable decoder of corresponding memory cell in array 160.
In this instance, the wordline in array 160 is couple to a page buffer 163, and page buffer 163 is couple to other peripheries
Circuit 174.Page buffer 163 can include one or more of storage element and be connected to each wordline.Address decoder 161 may be selected
And via the particular memory cell in the wordline coupling array 160 being correspondingly connected with to page buffer 163.Page buffer 163 can
Store the data for being written or reading from these particular memory cells.
Peripheral circuit includes being formed using logic circuit or analog circuit and the not circuit in array 160, such as
Address decoder 161, controller 140 etc..In this instance, the square 174 of other peripheral circuits may include such as one general place
Systemonchip (system-on-a-chip) functional module that reason device, proprietary application circuit or an offer array 160 are supported
Combination.
Controller 140 provides signal and executes the reading of multiple memorizers array 160 to control other circuits of integrated circuit 175
Take or be written the operation of data.Controller 140 includes a command decoder 150 and a state machine 151 or other sequences logic electricity
Road.Controller 140 can be used the logic circuit of known specific use and be performed.In another embodiment, controller includes
One general processor is to execute the operation that a computer program carrys out control device.In another embodiment, the execution of controller can
Use the combination of dedicated logic circuit and general processor.
Integrated circuit 175 also includes a configuration registers 149, in the configurating operation for device of configuration registers 149
Various uses.In this instance, configuration registers 149 include that a frequency configuration registers are couple to configuration frequency circuit 123.Configuration
Buffer 149 be one be adapted to provide for configuration parameters to configuration frequency circuit 123 configuration reservoir an example.
Configuration frequency circuit 123 has multiple frequency inputs that can receive frenquency signal, the end CLK from CLK endpoint (1) to (N)
Point (1) is to (N) to be configured frequency circuit 123 used as received frenquency signal.Other endpoints on device can be connected
Other inputs are connected to receive special power supply, ground connection, control signal and be not frequency circuit used as received frequency
Frequency input of signal etc..
Configuration frequency circuit 123 provides one internal frequency INT CLK of device, and internal frequency INTCLK is by least some inside
Circuit uses, such as controller, memory array, page buffer etc..
Configuration frequency circuit 123 include multiple sub-circuits, these sub-circuits to use different groups of multiple input terminals with
Generate corresponding frenquency signal.These sub-circuits in configuration frequency circuit 123 can unfolded element and as independent electrical
Road, or alternatively use at least some common elements.For example, the frequency input of configuration frequency circuit 123 can
Amplifier comprising being directly connected to endpoint.These amplifiers can be used by each sub-circuit, and constitute the element of overlapping.
Certainly, the configuration of miscellaneous sub-circuit can be performed.
Configuration frequency circuit 123 may include a selection circuit on the integrated, and selection circuit is cached in response to configuration
Configuration parameters in device 149.Selection circuit one of may be selected in multiple sub-circuits according to configuration parameters to provide correspondence
Frenquency signal as internal frequency signal INT CLK.Selection circuit may include switch or multiplexer, enable circuit or these
The combination of element.Switch or multiplexer can be operated to select the respective output of different sub-circuits.Enable circuit enable coupling
To the different sub-circuits of a shared output.
Configuration registers 149 include a frequency configuration reservoir, to provide configuration parameters to selection circuit.Frequency configuration
Reservoir may include one-time programming memory component, such as the not fuse or flash cell of erasing circuit.Also, group of frequencies
State reservoir may include other kinds of nonvolatile memory.In another embodiment, frequency configuration reservoir may include
SRAM and DRAM memory cell or other kinds of volatile memory elements.
Fig. 2 is painted the detailed of an embodiment of the configuration frequency circuit of the device suitable for the integrated circuit comprising Fig. 1
Thin schematic diagram.Square 275 represents the boundary of integrated circuit.Integrated circuit provides multiple endpoints, includes frequency pad 1 (201) to frequency
Rate pads N (202).Frequency pad 1 (201) is connected to frequency pad N (202) with the frequency source of the element 280 and 281 of icon, or
Person is connected to one or more square sources, and when manufacturing this device, the quantity and configuration in square source may be unknown.Frequency
Pad 1 (201) is connected to the frequency input of frequency circuit 203 to frequency pad N (202), and frequency circuit 203 is couple to selection circuit
204.The output of selection circuit 204 is the internal frequency signal INT CLK on line 206, and internal frequency signal INT CLK is mentioned
The internal frequency circuit being supplied on integrated circuit.Configuration parameters CONFIG is provided to selection circuit 204 by line 205 to control
Which circuit of frequency circuit is used.
Multiple sub-circuits are corresponding multiple to generate to use different groups of multiple input terminals (frequency pad 1, frequency pad N)
Frenquency signal.For example, a sub-circuit is to utilize single-frequency pad 1 (201), and another sub-circuit is multiple defeated to utilize
Enter two input terminals at end, such as frequency pad 1 (201) and a second frequency pad.Sub-circuit can be by comprising to use one or more
Input terminal and be set as one single-phase, two-phase, four phases and the input of other multiphase frequencies.Also, multiple sub-circuits can by comprising to
It is inputted in different input terminals using single phase frequency.It may include the group of miscellaneous sub-circuit to be suitble to specific implementation
It closes.
Fig. 3 has been painted two-end-point：Frequency pad 1 (211), frequency pad 2 (212) configuration frequency circuit detailed maps.
Frequency pad 1 (211) is electrically connected to the differential two-phase frequency buffer 213B of a single phase frequency buffer 213A and one, so as to pass
It is sent to both any frenquency signal electrical communications of frequency pad 211.One differential two-phase frequency can be considered as one 180 ° of different phases
The two-phase frequency of position.Other kinds of two-phase frequency can also be used, the two-phase frequency comprising different amounts of phase offset.Frequency pad
2 (212) are electrically connected to two-phase frequency buffer 213B, so as to be transmitted to any frenquency signal and the two-phase of frequency pad 212
Frequency buffer 213B electrical communication.
Single phase frequency buffer 213A is to generate frequency CLK1, and two-phase frequency buffer 213B is to generate frequency
CLK2, frequency CLK1 and frequency CLK2 are provided to selector 220.The output of selector 220 is an internal frequency 216, interior
Portion's frequency 216 is applied to internal circuit.
Single phase frequency buffer 213A and two-phase frequency buffer 213B includes circuit used with internal circuit it is one common
Format generates frequency.In some embodiments, this common format is a single phase frequency that can be provided that single signal line 206.
In other embodiments, this common format can be a differential, two-phase frequency or other multiphase frequency configurations.Frequency CLK1 and
The circuit that the frequency of frequency CLK2 can include according to frequency buffer 213A and 213B is identical to or arrives endpoint different from providing
Frenquency signal.For example, one or more sub-circuits may include frequency multiplier circuit to increase frequency, or include frequency division
Device is also to reduce frequency.
Configuration reservoir 225 stores a frequency interface and selects (CIS) parameter CIS [0:1], frequency interface selects in this instance
(CIS) parameter includes two.This two can be used to instruction selection CLK1 or CLK2.
Fig. 3 illustrates that configuration frequency circuit receives the one of a single-ended frequency from an external source 230 on frequency pad 1 (211)
Configuration.Configuration reservoir is set the sub-circuit (element comprising 250 instruction of ellipse) to select generation CLK1.Such as " X " institute
It indicates, and does not mind that is connected to frequency pad 2 (212).There is frequency input to be couple to the sub-circuit of frequency pad 2 (212)
It is in this configuration and unselected.
Fig. 4 is painted modified 3rd figure to illustrate configuration frequency circuit in frequency pad 1 (211) and in frequency pad 2 (212)
On from an external differential frequency source 231 receive a two-phase frequency, a configuration of differential frequency.In this instance, configuration parameters quilt
Set the sub-circuit (element comprising 251 instruction of ellipse) to select generation CLK2.
In the embodiment of Fig. 3 and Fig. 4, configuration parameters is used to control selections device 220.Selector 220 can be suitble to specific
Implementation by simply switching or more complex frequency multiplexing circuitry forms.
Fig. 5 is painted another embodiment, and what it is such as Fig. 3 and Fig. 4 includes two-end-point：Frequency pad 1 (211), frequency pad 2 (212)
Configuration frequency circuit.Frequency pad 1 (211) is electrically connected to a single phase frequency buffer 233A and a two-phase frequency buffer
233B, so as to be transmitted to both any frenquency signal electrical communications of frequency pad 211.Frequency pad 2 (212) is electrically connected to two-phase
Frequency buffer 233B, so that any frenquency signal for being transmitted to frequency pad 212 is only electrically logical with two-phase frequency buffer 233B
News.
Single phase frequency buffer 233A is to generate frequency CLK1, and two-phase frequency buffer 233B is to generate frequency
CLK2.Frequency CLK1 and frequency CLK2 be provided to the signal line 240 of an OR- line (wired-OR) to provide on online 206 in
Portion frequency INT CLK.
Configuration reservoir 225 is used to the sub-circuit selected in enable or disabled sub-circuit in this instance.Cause
This, the output of configuration reservoir 225 includes that an enable signal E1 and an enable signal E2, enable signal E1 are electrically connected to single-phase
Frequency buffer 233A, enable signal E2 are electrically connected to two-phase frequency buffer 233B.Selection circuit in this embodiment
Thus comprising circuit with enable and disabled frequency buffer, and include the signal line 240 of frequency CLK 1 and frequency CLK2.
In other embodiments, such as the multiplexer or switch of the enable of Fig. 3 and Fig. 4 or the output end of disabled circuit
Combination can be used to the selection circuit as configuration frequency circuit.In another embodiment, selection circuit may include being stored up by configuration
The switch of state modulator in storage, switch can open or close endpoint (such as frequency pad 1 (211) and frequency pad 2 (212)) with
Signal path between frequency buffer 233A and 233B.
The present invention provides a kind of method for operating a device, this device such as integrated circuit includes multiple input terminals and one
Internal circuit.The method includes：Read the configuration parameters on this device.This configuration parameters recognizes wherein the one of multiple input terminals
Group input terminal.This group of input terminal being wherein identified is the available combination being preset in equality circuit.Pass through group
State parameter generates an internal frequency signal using this group of input terminal being identified in multiple input terminals.The method further includes in offer
Portion's frenquency signal is to internal frequency circuit.
The step of generating internal frequency includes using one of one first sub-circuit or one second sub-circuit, the first son electricity
Road may include that a single phase frequency buffer is interrogated to use single a input terminal in multiple input terminals with generating a first frequency
Number, the second sub-circuit may include a differential frequency buffer to use two input terminals in multiple input terminals to generate one
Two frenquency signals.One of signal when first frequency signal or second frequency may be selected.
In some embodiments, it includes in multiple input terminals that the method, which can provide the input terminal of the group of configuration parameters identification,
One group and a single phase frequency is converted to produce by a multiphase frequency of this group of input terminal for being identified multiple input terminal
Raw internal frequency.
Although the present invention is disclosed above referring to preferred embodiment and example, so it should be understood that these examples are for using
It is bright rather than to limit the present invention.One skilled in the art is readily apparent that the modification and combination being expected, these changes
Type and combination are in the spirit and scope for not departing from the present invention and appended claims.
Claims (9)
1. a kind of frequency interface device, includes：
One integrated circuit includes multiple input terminals；
One internal circuit；
One frequency circuit, the frequency circuit are located on the integrated circuit, and to provide an internal frequency signal to inside this
Circuit, the frequency circuit include multiple frequency inputs be electrically connected to multiple input terminal, the frequency circuit in response to
One parameter generates the internal frequency signal using different groups of multiple input terminal；And
One frequency reservoir, to provide the parameter；
Wherein, which generates the internal frequency signal using different groups of multiple input terminal in response to a parameter,
The signal being based on is inputted from outside by different groups of input terminal；The frequency circuit includes multiple sub-circuits, this is more
A sub-circuit is to use different groups of multiple input terminals to generate corresponding frenquency signal；One first son of multiple sub-circuit
Circuit generates the frenquency signal of corresponding first sub-circuit, multiple son electricity using single a input terminal of multiple input terminal
One second sub-circuit on road generates the frenquency signal of corresponding second sub-circuit using two input terminals of multiple input terminal；
One group of a multiphase frequency of multiple input terminal is converted to one by least one of first sub-circuit and second sub-circuit
Single phase frequency.
2. the apparatus according to claim 1, wherein the frequency circuit also includes a selection circuit, the selection circuit in response to
The parameter is to select one of first sub-circuit or second sub-circuit.
3. device according to claim 1 or 2, wherein first sub-circuit includes a single phase frequency buffer, this second
Sub-circuit includes a multiphase frequency buffer.
4. a kind of frequency interface device, includes：
One integrated circuit includes multiple input terminals；
One memory array；
One internal circuit；
One frequency circuit, the frequency circuit are located on the integrated circuit, and to provide an internal frequency signal to inside this
Circuit, the frequency circuit include that multiple frequency inputs are electrically connected to multiple input terminal；Wherein, the frequency circuit in response to
One parameter generates the internal frequency signal using different groups of multiple input terminal, and the signal being based on derives from outside, and
It is inputted by different groups of input terminal；The frequency circuit includes multiple sub-circuits, and multiple sub-circuit is to use different groups
Multiple input terminal is to generate corresponding multiple frenquency signals；One first sub-circuit of multiple sub-circuit uses multiple input
Single a input terminal at end generates the frenquency signal of corresponding first sub-circuit, and one second sub-circuit of multiple sub-circuit makes
The frenquency signal of corresponding second sub-circuit is generated with two input terminals of multiple input terminal；First sub-circuit and this
One group of a multiphase frequency of multiple input terminal is converted to a single phase frequency by least one of two sub-circuits；
One selection circuit, the selection circuit are located on the integrated circuit, and the selection circuit is multiple in response to a parameter selection
One of sub-circuit is to provide the corresponding frenquency signal as the internal frequency signal；And
One frequency reservoir gives the selection circuit to provide the parameter.
5. device according to claim 4, wherein first sub-circuit includes a single phase frequency buffer with will be multiple
One single phase frequency of input terminal is converted to the frenquency signal of the corresponding single phase frequency buffer, the second sub-circuit packet
Containing a two-phase frequency buffer to be corresponding two-phase frequency buffering by two of a multiple input terminal two-phase frequency conversions
The frenquency signal of device.
6. a kind of operating method of frequency interface device, which includes multiple input terminals and an internal circuit, this method include：
Read the parameter on the device, wherein one group of input terminal of the multiple input terminal of the parameter identification；
An internal frequency signal is generated using this group of input terminal being identified in multiple input terminal in response to the parameter；And
The internal frequency signal is provided to the internal circuit；
Wherein, an internal frequency signal is generated using this group of input terminal being identified in multiple input terminal in response to the parameter,
The signal being based on is inputted from outside by different groups of input terminal；The device generates the step of the internal frequency signal
Rapid includes to use one of one first sub-circuit or one second sub-circuit, and first sub-circuit is to use multiple input terminal
In single a input terminal with generate a first frequency signal and, second sub-circuit is to use two in multiple input terminal
A input terminal is to generate a second frequency signal.
7. second son is electric according to the method described in claim 6, wherein first sub-circuit includes a single phase frequency buffer
Road includes a multiphase frequency buffer.
8. according to the method described in claim 6, wherein the internal circuit is to execute the generation internal frequency signal.
9. according to the method described in claim 6, wherein the input terminal of the group of the parameter identification includes in multiple input terminal
One group and a single phase frequency is converted to produce by a multiphase frequency of this group of input terminal for being identified multiple input terminal
The raw internal frequency.
Applications Claiming Priority (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201461979011P | 2014-04-14 | 2014-04-14 | |
| US61/979,011 | 2014-04-14 | ||
| US201462003750P | 2014-05-28 | 2014-05-28 | |
| US62/003,750 | 2014-05-28 | ||
| US14/448,573 US9489007B2 (en) | 2014-04-14 | 2014-07-31 | Configurable clock interface device |
| US14/448,573 | 2014-07-31 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104980144A CN104980144A (en) | 2015-10-14 |
| CN104980144B true CN104980144B (en) | 2018-11-30 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201410799403.7A Active CN104980144B (en) | 2014-04-14 | 2014-12-19 | Frequency interface device and its operating method |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US9489007B2 (en) |
| EP (2) | EP3358438B1 (en) |
| JP (1) | JP6053203B2 (en) |
| CN (1) | CN104980144B (en) |
| TW (1) | TWI554035B (en) |
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| US10396922B2 (en) * | 2017-02-07 | 2019-08-27 | Texas Instruments Incorporated | Apparatus and mechanism to support multiple time domains in a single soc for time sensitive network |
| US10339998B1 (en) * | 2018-03-27 | 2019-07-02 | Micron Technology, Inc. | Apparatuses and methods for providing clock signals in a semiconductor device |
| US10418081B1 (en) | 2018-10-10 | 2019-09-17 | Micron Technology, Inc. | Apparatuses and methods for providing voltages to conductive lines between which clock signal lines are disposed |
| US11789071B2 (en) * | 2021-01-12 | 2023-10-17 | Texas Instruments Incorporated | High speed integrated circuit testing |
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2014
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- 2014-12-19 CN CN201410799403.7A patent/CN104980144B/en active Active
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2015
- 2015-02-02 EP EP18156697.7A patent/EP3358438B1/en active Active
- 2015-02-02 EP EP15153429.4A patent/EP2933701A1/en not_active Ceased
- 2015-02-20 JP JP2015031738A patent/JP6053203B2/en active Active
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Also Published As
| Publication number | Publication date |
|---|---|
| TWI554035B (en) | 2016-10-11 |
| EP3358438A1 (en) | 2018-08-08 |
| EP2933701A1 (en) | 2015-10-21 |
| CN104980144A (en) | 2015-10-14 |
| JP2015204107A (en) | 2015-11-16 |
| US9489007B2 (en) | 2016-11-08 |
| JP6053203B2 (en) | 2016-12-27 |
| TW201541871A (en) | 2015-11-01 |
| EP3358438B1 (en) | 2020-12-09 |
| US20150293556A1 (en) | 2015-10-15 |
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