CN104979287A

CN104979287A - Diode and manufacturing method therefor

Info

Publication number: CN104979287A
Application number: CN201510272064.1A
Authority: CN
Inventors: 郑娅洁; 凌严; 朱虹
Original assignee: Shanghai Ruiaili Optoelectronic Technology Co Ltd
Current assignee: Shanghai Ruiaili Optoelectronic Technology Co Ltd
Priority date: 2015-05-25
Filing date: 2015-05-25
Publication date: 2015-10-14

Abstract

A diode and a manufacturing method therefor are provided. The manufacturing method of the diode comprises: providing an insulating substate; forming a first conductive layer covering the insulating substate; sequentially forming a first semiconductor layer and a second semiconductor layer on the first conductive layer to form a tube core, and doping types of the first semiconductor layer and the second semiconductor layer being different; forming a second conductive layer located on the tube core; and forming a protective layer covering the second conductive layer. According to the diode and the manufacturing method therefor, the diode is formed by adopting the insulating substate; the first conductive layer and the tube core are formed on the insulating substate; the insulating substate has an insulating property, so that current flowing through the substate can be inhibited and crosstalk between the diodes can be avoided; and therefore, the independence of the diode is improved and the isolation of the diode is improved.

Description

Diode and manufacture method thereof

Technical field

The present invention relates to field of semiconductor manufacture, particularly a kind of diode and manufacture method thereof.

Background technology

Diode is modern semiconductors field application a kind of semiconductor device very widely.Wherein Transient Suppression Diode (Transient Voltage Suppressor, TVS) is the high-effect circuit brake of one generally used in the world at present.Its external form is identical with general-purpose diode, but can absorb the surge power up to thousands of watts.

Under applied in reverse condition, when Transient Suppression Diode bears a high-octane large pulse, its working impedance can be down to extremely low conduction value immediately, thus allows big current to pass through, therefore, it is possible to voltage clamp at predeterminated level.

With reference to figure 1 and Fig. 2, wherein figure 1 illustrate Transient Suppression Diode application in circuit, Fig. 2 shows the clamping action of Transient Suppression Diode pulse voltage.

Transient Suppression Diode tvs is in parallel with load device load in circuit to be used.

When circuit normally works, Transient Suppression Diode tvs is in high impedance status, namely blocks state, does not affect the normal use of circuit; When abnormal overvoltage appears in circuit, namely when there is high energy pulse Vp in operating voltage Vw, pulse Vp reaches the puncture voltage of Transient Suppression Diode tvs, Transient Suppression Diode tvs becomes low impedance state from high impedance status rapidly, working impedance reduces immediately, there is provided Low ESR conducting loop to immediate current, namely allow big current to pass through, pulse Vp is clamped down within the level of a safety simultaneously.Voltage due to Transient Suppression Diode tvs is up to crest voltage Vc, and crest voltage Vc is less than the withstand voltage limit V of load device load _r.Therefore the voltage of load device load maintains its withstand voltage limit V _rbelow, thus realize the function of the voltage clamp of load device load at predeterminated level, protect load device load not by the impact of pulse Vp.When abnormal overvoltage disappears, Transient Suppression Diode tvs returns to high impedance status, and circuit recovers normal work.

The response time of Transient Suppression Diode is only 10 ^-12millisecond magnitude.So Transient Suppression Diode can protect the precision components in electronic circuit effectively.

Transient Suppression Diode can be divided into unidirectional and two-way two kinds.Unidirectional Transient Suppression Diode only oppositely absorbing instantaneous large pulse power, can clamp down on predeterminated level reverse voltage; Two-way Transient Suppression Diode can absorb instantaneous large pulse power in positive and negative both direction, and voltage clamp to predeterminated level.Unidirectional instantaneous twin zener dioder is mainly applicable to DC circuit, and two-way Transient Suppression Diode is mainly applicable to alternating current circuit.Therefore, Transient Suppression Diode have anti-lightning strike, anti-overvoltage, anti-interference, absorb the functions such as surge power, be a kind of desirable protection device.

Current Transient Suppression Diode has been widely used in the every field such as the protection such as computer system, communication apparatus, AC/DC power supply, I/O, USB, common mode/differential mode protection, RF coupling/IC driving reception protection, the suppression of electrode Electromagnetic Interference, audio/video input, transducer/speed changer, industry control loop, relay, contactor noise suppression.

But the diode manufactured by prior art has the larger problem of electric leakage.

Summary of the invention

The problem that the present invention solves is to provide a kind of diode and manufacture method thereof, reduces diode leakage current.

For solving the problem, the invention provides a kind of manufacture method of diode, comprising:

Insulated substrate is provided;

Form the first conductive layer covering described insulated substrate;

Described first conductive layer forms the first semiconductor layer and the second semiconductor layer successively to form tube core, described first semiconductor layer is different with the doping type of described second semiconductor layer;

Form the second conductive layer be positioned on described tube core;

Form the protective layer covering described second conductive layer.

Optionally, described insulated substrate is glass substrate.

Optionally, after the step forming the first conductive layer covering described insulated substrate, before the step of formation first semiconductor layer, described manufacture method also comprises: the insulating barrier forming cover part first conductive layer between adjacent tube core, to realize the electric isolution between neighboring diode.

Optionally, the step forming the insulating barrier of cover part first conductive layer between neighboring diode comprises: on described first conductive layer, form insulation material layer; Remove part insulation material layer, form the first opening exposing described first conductive layer, to form insulating barrier.

Optionally, described insulating layer material is silicon nitride or silica.

Optionally, described thickness of insulating layer is within the scope of 230nm ~ 270nm.

Optionally, the step described first conductive layer forming the first semiconductor layer and the second semiconductor layer successively comprises: the material of described first semiconductor layer and described second semiconductor layer is amorphous semiconductor.

Optionally, the step described first conductive layer forming the first semiconductor layer and the second semiconductor layer successively comprises: adopt the mode of chemical vapour deposition (CVD) to form described first semiconductor layer and the second semiconductor layer.

Optionally, after the step forming the second conductive layer be positioned on described tube core, before forming the step of the protective layer covering described second conductive layer, described manufacture method also comprises: etch described second conductive layer and described tube core and form the first groove exposing described first conductive layer; The step forming the protective layer covering described second conductive layer also comprises: described protective layer also covers bottom and the sidewall of described first groove.

Optionally, after the step forming the first conductive layer covering described insulated substrate, before described first conductive layer forms the step of the first semiconductor layer, described manufacture method also comprises: the insulating barrier forming cover part first conductive layer between adjacent tube core; The step forming described first groove comprises: on described insulating barrier, form described first groove, and makes described first channel bottom expose described insulating barrier.

Optionally, described first conductive layer forms the first semiconductor layer and the second semiconductor layer successively with after the step forming tube core, before forming the step of the second conductive layer be positioned on described tube core, described manufacture method also comprises: form the short circuit layer be positioned on described tube core; Etch described short circuit layer and described tube core, form the second groove that described insulated substrate is exposed in bottom; Form the separator covering described second trenched side-wall and bottom; The step forming the second conductive layer be positioned on described tube core comprises: form the second conductive layer covering described short circuit layer and separator.

Optionally, the step forming the short circuit layer be positioned on described tube core comprises: the material of described short circuit layer is metal or conductor metal oxide material.

Optionally, the step forming the separator covering described second trenched side-wall and bottom comprises: form the spacer material layer covering described short circuit layer and described second trenched side-wall and bottom; Removal unit divides spacer material layer, and formation exposes the second opening of described short circuit layer to form separator.

Optionally, after the step forming the first conductive layer covering described insulated substrate, before described first conductive layer forms the step of the first semiconductor layer, described manufacture method also comprises: the insulating barrier forming cover part insulated substrate between adjacent tube core, to realize the electric isolution between adjacent tube core; The step forming the insulating barrier of cover part first conductive layer between adjacent tube core comprises: remove part first conductive layer, to form the insulated openings that insulated substrate is exposed in bottom; Form the insulation material layer covering described first conductive layer and insulated substrate; Remove part insulation material layer, form the 3rd opening exposing described first conductive layer, to form insulating barrier; The step forming described second groove comprises: on described insulating barrier, form described second groove, and described insulating barrier is exposed in the bottom of described second groove.

Optionally, after described first conductive layer forms the step of the first semiconductor layer, before described first semiconductor layer forms the step of the second semiconductor layer, described manufacture method also comprises: form the intrinsic semiconductor layer covering described first semiconductor layer.

Optionally, the step forming the intrinsic semiconductor layer covering described first semiconductor layer comprises: the material of described intrinsic semiconductor layer is amorphous semiconductor.

Optionally, the step forming the intrinsic semiconductor layer covering described first semiconductor layer comprises: described intrinsic semiconductor layer is lightly doped N type semiconductor.

Optionally, the step forming the second conductive layer be positioned on described tube core comprises: described second conductive is metal or conductor metal oxide material.

Optionally, the step forming the protective layer covering described second conductive layer also comprises: described protective layer also covers the sidewall of described second conductive layer, described tube core and described first conductive layer.

Accordingly, the present invention also provides a kind of diode, comprising:

Insulated substrate;

Cover the first conductive layer of described insulated substrate;

Be positioned at the tube core on described first conductive layer, described tube core comprises and is positioned at the first semiconductor layer on described first conductive layer and the second semiconductor layer successively, and described first semiconductor layer is different with the doping type of described second semiconductor layer;

Be positioned at the second conductive layer on described tube core;

Cover the protective layer of described second conductive layer.

Optionally, described insulated substrate is glass substrate.

Optionally, described diode also comprises between the first conductive layer and the first semiconductor layer: between adjacent tube core and the insulating barrier of cover part first conductive layer, in order to realize the electric isolution between neighboring diode; Described tube core covers described insulating barrier and described first conductive layer.

Optionally, described insulating layer material is silica or silicon nitride.

Optionally, described first semiconductor layer and described second semiconductor layer material are amorphous semiconductor.

Optionally, described diode is two-way Transient Suppression Diode; Described diode also comprises: the first groove being arranged in described tube core and described second conductive layer, and described first groove exposes described first conductive layer; Described protective layer is also covered in bottom and the sidewall of described first groove.

Optionally, described diode also comprises between the first conductive layer and the first semiconductor layer: between adjacent tube core and the insulating barrier of cover part first conductive layer; The protective layer being covered in described first channel bottom contacts with described insulating barrier.

Optionally, described diode is two-way Transient Suppression Diode; Described diode also comprises: the short circuit layer covering described tube core; Be positioned at the second groove of described short circuit layer, described tube core and described first conductive layer, described second channel bottom exposes described insulated substrate; Be covered in the separator of described second trenched side-wall and bottom; Described second conductive layer is covered on described separator and described short circuit layer.

Optionally, described short circuit layer material is metal or conductor metal oxide material.

Optionally, described diode also comprises between described substrate and described first semiconductor layer: between adjacent tube core, and the insulating barrier of cover part insulated substrate, in order to realize the electric isolution between adjacent tube core; The separator being covered in described second channel bottom contacts with described insulating barrier.

Optionally, institute's tube core also comprises the intrinsic semiconductor layer between described first semiconductor layer and described second semiconductor layer.

Optionally, described intrinsic semiconductor layer is amorphous semiconductor.

Optionally, described intrinsic semiconductor layer is lightly doped n-type semiconductor.

Optionally, described second conductive is metal or conductor metal oxide material.

Optionally, described protective layer is also covered in the sidewall of described second conductive layer, described tube core and described first conductive layer.

Compared with prior art, technical scheme of the present invention has the following advantages:

The present invention forms diode by adopting insulated substrate, insulated substrate is formed the first conductive layer and tube core, due to the insulating properties of insulated substrate, the electric current through flow of substrates warp can be suppressed, the generation crosstalk between diode can be avoided, thus improve the independence of diode, improve the isolation of diode.

Optionally, in possibility of the present invention, between the first semiconductor layer and the second semiconductor layer, can also intrinsic semiconductor layer be set, to increase the width of diode depletion layer, increase the potential barrier of depletion layer, thus resistance when increasing diode reverse conducting, the leakage current of twin zener dioder thus.

Optionally, in possibility of the present invention, non-crystalline material can also be utilized to substitute crystalline material of the prior art and form diode, because in non-crystalline material, carrier mobility is less, therefore the application of non-crystalline material can the leakage current of twin zener dioder further.In addition, adopt amorphous technique to substitute crystal technique of the prior art, device fabrication difficulty can be effectively reduced, reduce process complexity, improve device and manufacture yields, reduce device cost.

Optionally; in possibility of the present invention; described protective layer also covers the sidewall of described second conductive layer, described tube core and described first conductive layer; for realizing the electric isolution between neighboring diode; effectively avoid the electric leakage between neighboring diode, improve independence and the isolation of diode.

Optionally; when described diode is two-way Transient Suppression Diode; in possibility of the present invention; described protective layer also covers the sidewall being positioned at described second conductive layer and described tube core internal channel; for realizing the isolation between adjacent tube core; effectively avoid the electric leakage between adjacent tube core, reduce the leakage current of diode.

Accompanying drawing explanation

Fig. 1 is Transient Suppression Diode application in circuit;

Fig. 2 is the clamping action schematic diagram of Transient Suppression Diode pulse voltage;

Fig. 3 is the structural representation of a kind of Transient Suppression Diode in prior art;

Fig. 4 to Figure 10 is the structural representation of each step of manufacture method first embodiment of diode of the present invention;

Figure 11 to Figure 13 is the structural representation of each step of manufacture method second embodiment of diode of the present invention;

Figure 14 to Figure 20 is the structural representation of diode fabricating method of the present invention 3rd each step of embodiment.

Embodiment

From background technology, there is the larger problem of leakage current in the diode of prior art manufacture.Now in conjunction with the reason of the larger problem of structural analysis leakage current of the diode of prior art manufacture:, be described for Transient Suppression Diode herein.

With reference to figure 3, show the structural representation of Transient Suppression Diode in prior art.

In prior art, the structure of Transient Suppression Diode and general diode-like are seemingly.The structure of the simplest Transient Suppression Diode is a simple PN junction.With reference to figure 3, semiconductor base 10 forms P type heavily doped layer 20 and N-type heavily doped layer 30 successively to form PN junction.For the Transient Suppression Diode of structure like this, when puncture voltage is generally between 10V ~ 50V, its leakage current is relatively little.But along with the reduction of puncture voltage, leakage current can increase, when puncture voltage is lower than 6V, the leakage current of the Transient Suppression Diode of this structure can significantly increase, and even may reach a milliampere magnitude.

In prior art, because substrate 10 is semiconductor.The conductivity of semiconductor is between insulator and conductor.Semiconductor only just has stronger insulating properties at low temperatures.When at room temperature, due to thermal excitation, semiconductor still can have certain conductivity.Can be there is the electric leakage through semiconductor base 10 in the diode be therefore formed on semiconductor base 10, can produce the crosstalk through semiconductor base 10 between different diodes.Isolation between diode and independence poor.

For solveing the technical problem, the invention provides a kind of manufacture method of diode, comprising the steps:

Insulated substrate is provided; Form the first conductive layer covering described insulated substrate; Described first conductive layer forms the first semiconductor layer and the second semiconductor layer successively to form tube core, described first semiconductor layer is different with the doping type of described second semiconductor layer; Form the second conductive layer be positioned on described tube core; Form the protective layer covering described second conductive layer.

For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.

With reference to figure 4 to Figure 10, show the structural representation of each step of manufacture method first embodiment of diode of the present invention.It should be noted that, be described to form Transient Suppression Diode in the present embodiment, the present invention should do not limited with this.

With reference to figure 4, provide insulated substrate 100.

Described insulated substrate 100 is the workbench of Subsequent semiconductor technique.Because the resistance of insulating material is comparatively large, the electric current flowing through substrate can be suppressed, avoid the follow-up tube core generation formed on described insulated substrate 100 through the electric leakage of substrate, improve the independence of diode, improve the isolation of diode.Concrete, in the present embodiment, described insulated substrate 100 is glass substrate.

With reference to figure 5, form the first conductive layer 110 covering described insulated substrate 100.

It should be noted that, in order to remove the pollutant on insulated substrate 100, improve the yields of subsequent technique, after the step that insulated substrate 100 is provided, before forming the step of the first conductive layer 110 covering described insulated substrate 100, in the present embodiment, described manufacture method also comprises the described insulated substrate 100 of cleaning.

Described first conductive layer 110 as the bottom crown of the diode of follow-up formation, and forms ohmic contact between the first semiconductor layer in the diode chip of follow-up formation.Described first conductive layer 110 can also in order to form leadframe pad (Pad) in order to realize the connection of diode chip and the external circuit formed.

Concrete, the material of described first conductive layer 110 can be metal material.In the present embodiment, the material of described first conductive layer 110 is the metal materials such as aluminium, aluminium niobium alloy or molybdenum, and the material of the present invention to the first conductive layer 110 does not limit.

In the present embodiment, the mode of physical vapour deposition (PVD) is adopted to form described first conductive layer 110.But the way adopting the mode of physical vapour deposition (PVD) to form described first conductive layer 110 is only an example, and the formation method of the present invention to described first conductive layer 110 does not limit.

With reference to figure 6 and Fig. 7, described first conductive layer 110 forms the first semiconductor layer 121 and the second semiconductor layer 122 successively to form tube core 120, described first semiconductor layer 121 is different with the doping type of described second semiconductor layer 122.

It should be noted that, in order to improve isolation and the independence of manufactured diode, insulating properties between the tube core 120 of guarantee neighboring diode, prevent the electric leakage between adjacent tube core 120, in the present embodiment, after the step forming the first conductive layer 110 covering described insulated substrate 100, before described first conductive layer 110 forms the step of tube core 120, described manufacture method also comprises: the insulating barrier 115 forming cover part first conductive layer between adjacent tube core 120, to realize the electric isolution between neighboring diode.

With reference to figure 6, concrete, the step forming the insulating barrier 115 of cover part first conductive layer 110 comprises:

Described first conductive layer 110 forms insulation material layer;

Remove part insulation material layer, form the first opening 116 exposing described first conductive layer 110, to form insulating barrier 115.

Described insulating barrier 115 is also in subsequent technique process, isolate the first conductive layer 110, avoid that the metal ion of the first conductive layer 110 is sputtered enters subsequent film, particularly form in the rete of diode chip 120, thus affect diode oppositely block performance.So, except being provided with except insulating barrier 115 between adjacent tube core 120, be not all coated with insulating barrier 115 by described first conductive layer 110 surface that diode chip 120 covers.

Described insulating barrier 115 material is silicon nitride or silica.Concrete, the mode of chemical vapour deposition (CVD) can be adopted on described first conductive layer 110 to form described insulation material layer.

It should be noted that, if insulating barrier 115 thickness is too small, the effect isolating described first conductive layer 110 cannot be realized in subsequent etching process; If insulating barrier 115 thickness is excessive, easily causes waste of material and increase technology difficulty.Therefore, in the present embodiment, described insulating barrier 115 thickness is within the scope of 230nm ~ 270nm.

Also it should be noted that, in order to obtain good etching effect, in the present embodiment, the step that removal part insulation material layer forms the first opening comprises: adopt dry etching to remove part insulation material layer and form the first opening 116, to form insulating barrier 115.

With reference to figure 7, form the first semiconductor layer 121 covering described insulating barrier 115 and described first conductive layer 110 and the second semiconductor layer 122 successively to form tube core 120, described first semiconductor layer 121 is different with the doping type of described second semiconductor layer 122.

It should be noted that, in order to reduce the leakage current of described diode, in the present embodiment, the material of described first semiconductor layer 121 and described second semiconductor layer 122 is amorphous semiconductor.Because the atom in amorphous semiconductor lacks long-range order, therefore there is a large amount of localized modes in material.The existence of a large amount of localized modes forms a large amount of potential barriers to charge carrier, thus have impact on the migration of charge carrier.Therefore in amorphous semiconductor, the mobility of charge carrier is less.So adopt amorphous semiconductor to form tube core 120, diode reverse conducting resistance can be increased, can the leakage current of twin zener dioder further.

In the present embodiment, described first semiconductor layer 121 is N type semiconductor, and described second semiconductor layer 122 is P type semiconductor.Concrete, the mode of chemical vapour deposition (CVD) can be adopted to form described first semiconductor layer 121 and described second semiconductor layer 122, to form tube core 120.

Because amorphous semiconductor technique is simple, therefore amorphous semiconductor is adopted to form tube core 120, the mode of chemical vapour deposition (CVD) can be adopted directly to form described first semiconductor 121 and described second semiconductor layer 122, can avoid adopting ion implantation technology, therefore process complexity can be reduced, reduce the technology difficulty that device manufactures, improve device and manufacture yields, reduce device manufacturing cost.

It should be noted that, in order to reduce the leakage current of diode further, in the present embodiment, after described first conductive layer 110 forms the step of the first semiconductor layer 121, before described first semiconductor layer 121 forms the step of the second semiconductor layer 122, described manufacture method also comprises: form the intrinsic semiconductor layer 123 covering described first conductive layer 121.Described first semiconductor layer 121, intrinsic semiconductor layer 123 and the second semiconductor layer 122 form the tube core 120 of PIN structural.Intrinsic semiconductor layer 123 is between the first semiconductor layer 121 and described second semiconductor layer 122, the width of diode depletion layer can be increased, thus increase depletion layer potential barrier, reduce resistance during diode reverse conducting, thus realize the function of twin zener dioder leakage current.

Similar, in the present embodiment, the step forming the intrinsic semiconductor layer 123 covering described first semiconductor layer 121 comprises: described intrinsic semiconductor layer 123 is amorphous semiconductor.Adopting amorphous semiconductor to form the effect of described intrinsic semiconductor layer 123 and aforementioned employing amorphous semiconductor, to form the reason of described first semiconductor layer 121 and described second semiconductor layer 122 similar, do not repeat them here.

It should be noted that, owing to using the reason such as material and processing technology, absolute intrinsic material is difficult to obtain, therefore described intrinsic semiconductor layer 123 be doping content very low, P-type material that resistivity is very high or n type material.Concrete, in the present embodiment, described intrinsic semiconductor layer 123 is the N type semiconductor that doping content is very low, and the mode of chemical vapour deposition (CVD) can be adopted to form the intrinsic semiconductor layer 123 covering described first conductive layer 121.

With reference to figure 8, form the second conductive layer 130 be positioned on described tube core 120.

Described second conductive layer 130 as the top crown of described diode, and forms ohmic contact between the second semiconductor layer 122 in tube core 120.Described second conductive layer 150 also for the formation of leadframe pad in order to realize the connection of tube core 120 and external circuit.

Concrete, the material of described second conductive layer 130 is metal material or conductor metal oxide material.The metal material forming described second conductive layer 130 can be aluminium, aluminium niobium alloy or molybdenum etc., and the conductor metal oxide material forming described second conductive layer 130 is generally indium tin oxide material (Indium TinOxide, ITO).The material of the present invention to the second conductive layer 130 does not limit.

In the present embodiment, the mode of physical vapour deposition (PVD) is adopted to form described second conductive layer 130.But the way adopting the mode of physical vapour deposition (PVD) to form described second conductive layer 130 is only an example, and the formation method of the present invention to described second conductive layer 130 does not limit.

With reference to figure 9 and Figure 10, form the protective layer 140 covered on described second conductive layer 130.Wherein, Fig. 9 is the vertical view of described diode, and Figure 10 is the cutaway view of A-A ' line in Fig. 9.

It should be noted that, with reference to figure 9, in order to the connection of the tube core 120 with external circuit that make described diode; after the step forming described second conductive layer 130; before forming the step of the protective layer 140 covering described second conductive layer 130, described manufacture method also comprises, and forms leadframe pad 150.Concrete, according to design needs, the first conductive layer 110 and the second conductive layer 130 form leadframe pad 150, to realize the electrical connection of tube core 120 and external circuit.

With reference to Figure 10, described protective layer 140 plays scratch resistant, anti-dirty, etch-proof protective effect.In the present embodiment, the material of described protective layer 140 is silicon nitride or silica, and the mode of chemical vapour deposition (CVD) can be adopted to form described protective layer 140.

It should be noted that, if protective layer 140 thickness is too small, cannot play a protective role; If protective layer 140 thickness is excessive, easily causes waste of material and increase technology difficulty.Therefore, in the present embodiment, the thickness of described protective layer 140 is within the scope of 600nm ~ 1000nm.

Also it should be noted that, described protective layer 140 also covers the sidewall of described second conductive layer 130, described tube core 120, described insulating barrier 115 and the first conductive layer 110, to realize the electric isolution between neighboring diode.The electric leakage that protective layer 140 can effectively avoid between neighboring diode is set at the sidewall of described second conductive layer 130, described tube core 120, described insulating barrier 115 and the first conductive layer 110, improves independence and the isolation of diode.

With reference to figures 11 to Figure 13, show the structural representation of each step of diode fabricating method second embodiment of the present invention.It should be noted that, in the present embodiment, be described to form two-way Transient Suppression Diode, the present invention should do not limited with this.

With reference to Figure 11; in order to form two-way Transient Suppression Diode; after the step forming the second conductive layer 230 covering described tube core 220; before forming the step of the protective layer 240 covering described second conductive layer 230; described manufacture method also comprises: etch described second conductive layer 230 and described tube core 220, forms the first groove 245 exposing described first conductive layer 210.

It should be noted that, in the present embodiment, after the step forming the first conductive layer 210 covering described insulated substrate 200, before described first conductive layer 210 forms the step of tube core 220, described manufacture method also comprises: the insulating barrier 215 forming cover part first conductive layer 210 between adjacent tube core 220.Therefore, the step forming described first groove 245 comprises: on described insulating barrier 215, form the first groove 245, and described insulating barrier 215 is exposed in the bottom of described first groove 245.

Also it should be noted that, in the present embodiment, after described first conductive layer 210 forms the step of the first semiconductor layer 221, before described first semiconductor layer 312 forms the step of the second semiconductor layer 222, described manufacture method also comprises: form the intrinsic semiconductor layer 223 covering described first semiconductor layer 221, described first semiconductor layer 223, intrinsic semiconductor layer 223 and the second semiconductor layer 222 form the tube core 220 of PIN structural.So the step forming described first groove comprises: the tube core 220 etching described second conductive layer 230 and PIN structural forms the first groove 245.

Concrete, in the present embodiment, adopt and be dry-etched in formation the first groove 245 in described second conductive layer 230 and tube core 220, bottom described first groove 245, expose described insulating barrier 215.The tube core 220 of two that are separated by described first groove 245 adjacent PIN structural realizes short circuit by the first conductive layer 210.

With reference to Figure 12 and Figure 13; wherein Figure 12 is the vertical view of described diode; Figure 13 is the cutaway view along B-B ' line in Figure 12, and the step forming the protective layer 240 covering described second conductive layer 230 also comprises: described protective layer 240 also covers bottom and the sidewall of described first groove 245.

It should be noted that; with reference to Figure 12, in order to make described two-way Transient Suppression Diode be connected with external circuit, after the step of formation second conductive layer 230; before forming the step of the protective layer 240 covering described second conductive layer 230, described manufacture method also comprises formation leadframe pad 250.

Concrete, because two tube cores 220 adjacent in two-way Transient Suppression Diode realize short circuit by the first conductive layer 210.Therefore according to design needs, in the present embodiment, the second conductive layer 230 of the first groove 245 both sides all forms a leadframe pad 250, to realize the connection of described diode and external circuit.

When described diode is two-way Transient Suppression Diode; in order to realize the isolation between adjacent tube core 220; avoid the electric leakage between tube core 220; except covering described second conductive layer 230; described protective layer 240 also covers bottom and the sidewall of described first groove 245; namely described protective layer 240 covers the sidewall of described tube core 220, and contacts with described insulating barrier 215 bottom described first groove 245, to realize the electric isolution between adjacent tube core 220.

It should be noted that, in the present embodiment, described first groove 245 is formed in the first semiconductor layer 221, intrinsic semiconductor layer 223 and the second semiconductor layer 222, and therefore described protective layer 240 covers the sidewall of the tube core 220 of described PIN structural.

In the present embodiment, realize the electrical connection between adjacent tube core 220 by the first conductive layer 210, and realize the connection of tube core 220 and external circuit by the leadframe pad 250 formed on the second conductive layer 230.Therefore described diode can absorb instantaneous large pulse power, voltage clamp to predeterminated level, to realize the protective effect to circuit in positive and negative both direction.

With reference to figs. 14 to Figure 20, show the structural representation of diode fabricating method of the present invention 3rd each step of embodiment.It should be noted that, in the present embodiment, be described to form two-way Transient Suppression Diode, the present invention should do not limited with this.

With reference to Figure 14 and Figure 15, insulated substrate 300 is provided, on described insulated substrate 300, forms the first conductive layer 310 afterwards, and the insulating barrier 315 forming cover part first conductive layer 310 between adjacent tube core is to realize the electric isolution between adjacent tube core.

Concrete, the step forming the insulating barrier 315 of cover part first conductive layer 310 between adjacent tube core comprises:

With reference to Figure 14, form the first conductive layer 310 covering insulated substrate 300.Afterwards, remove the first conductive layer 310 between adjacent tube core, to form the insulated openings 305 exposing insulated substrate 300.

With reference to Figure 15, form the insulation material layer covering described first conductive layer 310 and insulated substrate 300, remove the portions of insulating material layer on described first conductive layer 310, form the 3rd opening exposing described first conductive layer 310, to form insulating barrier 315.

Described insulating barrier 315 between adjacent tube core 320, both cover part insulated substrate 300 also cover part first conductive layers 310.The setting of described insulating barrier 315, can realize the electric isolution of the follow-up adjacent tube core formed on the first conductive layer 310, improves isolation and the independence of tube core.

With reference to Figure 16, described first conductive layer 310 and described insulating barrier 315 form tube core 320, described tube core 320 comprises the first semiconductor layer 321 and the second semiconductor layer 322 be positioned at successively on described first conductive layer 310 and described insulating barrier 315, and described first conductive layer 310 is different with the doping type of described insulating barrier 315.

It should be noted that, in the present embodiment, after described first conductive layer 310 forms the step of the first semiconductor layer 321, before described first semiconductor layer 321 forms the step of the second semiconductor layer 322, described manufacture method also comprises: form the intrinsic semiconductor layer 323 covering described first semiconductor layer 321.Therefore described tube core 320 is the PIN structural formed by described first semiconductor layer 321, intrinsic semiconductor layer 323 and the second semiconductor layer 322.

Afterwards, the short circuit layer 333 be positioned on described tube core 320 is formed.

Described short circuit layer 333 for forming the top crown of described diode together with the second conductive layer of follow-up formation, and form ohmic contact between the second semiconductor layer 322 in tube core 320, and the short circuit being realized tube core 320 by the second conductive layer is to form two-way Transient Suppression Diode.In addition, described short circuit layer 333 also for protecting tube core 320 from the damage of follow-up film forming and etching technics in subsequent technique, improves device yield.

The material of described short circuit layer 333 is metal material or conductor metal oxide material.Concrete, wherein metal material can be aluminium, aluminium niobium alloy or molybdenum etc., and conductor metal oxide material is generally indium tin oxide material (ITO).The material of the present invention to short circuit layer 333 does not limit.

In the present embodiment, the mode of physical vapour deposition (PVD) can be adopted to form described short circuit layer 333.But the way adopting the mode of physical vapour deposition (PVD) to form described short circuit layer 333 is only an example, and the formation method of the present invention to described short circuit layer 333 does not limit.

With reference to Figure 17, etch described short circuit layer 333 and described tube core 320, form the second groove 345 that described insulated substrate 300 is exposed in bottom.

It should be noted that, in the present embodiment, between adjacent tube core 320, be formed with insulating barrier 315.Therefore the step forming described second formation 345 comprises: on described insulating barrier 315, form described second groove 345, described insulating barrier 315 is exposed in the bottom of described second groove 345.

Also it should be noted that, in the present embodiment, described tube core 320 is the PIN structural comprising the formation of described first semiconductor layer 321, intrinsic semiconductor layer 323 and the second semiconductor layer 322.Described second groove 345 is positioned at the tube core 320 of described PIN structural.

Concrete, in the present embodiment, adopt and be dry-etched in formation the second groove 345 in short circuit layer 333 and tube core 320, bottom described second groove 345, expose described insulating barrier 315.

With reference to Figure 18, form the separator 336 covering described second groove 345 sidewall and bottom.

Described separator 336 is for realizing the electric isolution of adjacent tube core 320, described separator 336 is also for realizing the electric isolution between the second conductive layer of follow-up formation and the sidewall of described tube core 320, avoid the Contact of the first semiconductor layer 321 of the second conductive layer and described tube core 320, can also avoid, between the first semiconductor layer 321 of described tube core 320 and the second semiconductor layer 322, short circuit occurs.The material of described separator 336 can be silicon nitride or silica, and the mode of chemical vapour deposition (CVD) can be adopted to form described separator 336.

Concrete, the step forming described separator 336 comprises: form the spacer material layer covering described short circuit layer 333 and described second groove 345 sidewall and bottom; Remove the part spacer material layer be positioned on described short circuit layer 333, formation exposes the second opening 337 of described short circuit layer 333 to form separator 336.

It should be noted that, in order to obtain good etching effect, the step removing the part spacer material layer be positioned on described short circuit layer 333 in the present embodiment comprises: the method removal unit point insolated layer materials layer adopting dry etching, form the second opening 337 exposing described short circuit layer 333, to form separator 336.

With reference to Figure 19, form the second conductive layer 330 covering described separator 336 and described short circuit layer 333.

Concrete, in the present embodiment, described second conductive layer 330 realizes being electrically connected with the second semiconductor layer 322 of described tube core 320 by described short circuit layer 333.Described second conductive layer 330 forms the top crown of described diode together with described short circuit layer 333.Second semiconductor layer 322 of adjacent tube core 320 realizes short circuit to form two-way Transient Suppression Diode by described second conductive layer 330.

With reference to Figure 20, form the protective layer 340 covering described second conductive layer 330.

Concrete; in the present embodiment; described protective layer 340 covers the sidewall of described second conductive layer 330 and described second conductive layer 330, described separator 336, described short circuit layer 333, described tube core 320, described separator 315 and described first conductive layer 310, realizes the electric isolution between described diode.

It should be noted that, in order to make described two-way Transient Suppression Diode be connected with external circuit, after the step of formation second conductive layer 330, before forming the step of protective layer 340, described manufacture method also comprises formation leadframe pad.According to design needs, in the present embodiment, described first conductive layer 310 forms leadframe pad, to realize the connection of described tube core 320 and external circuit.

In the present embodiment, by forming by described second conductive layer 330 and described short circuit layer 333 electrical connection that top crown realizes the second semiconductor layer 322 in adjacent tube core 320, and on the first conductive layer 310, forming leadframe pad with to realize and the connection of external circuit, the neighbouring relations 320 that the second conductive layer 322 is connected form two-way Transient Suppression Diode.Therefore described diode can absorb instantaneous large pulse power, voltage clamp to predeterminated level, to realize the protective effect to circuit in positive and negative both direction.

Accordingly, the present invention also provides a kind of diode, comprising:

Insulated substrate; Cover the first conductive layer of described insulated substrate; Be positioned at the tube core on described first conductive layer, described tube core comprises and is positioned at the first semiconductor layer on described first conductive layer and the second semiconductor layer successively, and described first semiconductor layer is different with the doping type of described second semiconductor layer; Be positioned at the second conductive layer on described tube core; Cover the protective layer of described second conductive layer.

In conjunction with reference to figure 9 and Figure 10, show the structural representation of diode first embodiment of the present invention, wherein Figure 10 is the cutaway view of A-A ' line in Fig. 9.It should be noted that, in the present embodiment, be described for Transient Suppression Diode, the present invention should do not limited with this.

Described diode comprises:

Insulated substrate 100.

Described insulated substrate 100 is the workbench of Subsequent semiconductor technique.Because the resistance of insulating material is comparatively large, the electric current flowing through substrate can be suppressed, avoid the follow-up diode chip generation formed on described insulated substrate 100 through the electric leakage of substrate, improve the independence of diode, improve the isolation of diode.Concrete, in the present embodiment, described insulated substrate 100 is glass substrate.

Be covered in the first conductive layer 110 on described insulated substrate.

Described first conductive layer 110 as the bottom crown of the diode of follow-up formation, and forms ohmic contact between the first semiconductor layer in the diode chip of follow-up formation.Described first conductive layer 110 also in order to form leadframe pad, in order to the connection of the diode chip and external circuit that realize follow-up formation.

Described diode also comprises: be positioned at the tube core 120 on described first conductive layer 110, described tube core 120 comprises the first semiconductor layer 121 and the second semiconductor layer 122 be positioned at successively on described first conductive layer 110, and described first semiconductor layer 121 is different with the doping type of described second semiconductor layer 122.

It should be noted that, in order to improve isolation and the independence of described diode, insulating properties between the tube core 120 of guarantee neighboring diode, prevent the electric leakage between adjacent tube core 120, in the present embodiment, described diode also comprises: between adjacent tube core 120 and the insulating barrier 115 of cover part first conductive layer 110, in order to realize the electric isolution between neighboring diode.Described tube core 120 covers described insulating barrier 115 and described first conductive layer 110.

Described insulating barrier 115 is also for isolating the first conductive layer 110, avoid that the metal ion of the first conductive layer 110 in subsequent technique process is sputtered enters subsequent film (particularly forming in the rete of diode chip 120), thus affect tube core 120 oppositely block performance.So, except being provided with except insulating barrier 115 between adjacent tube core 120, be not all coated with insulating barrier 115 by described first conductive layer 110 surface that tube core 120 covers.Concrete, described insulating barrier 115 material can be silicon nitride or silica.

It should be noted that, if insulating barrier 115 thickness is too small, the effect isolating described first conductive layer 110 cannot be realized in subsequent etching process; If insulating barrier 115 thickness is excessive, easily causes waste of material and increase technology difficulty.Therefore, in the present embodiment, described insulating barrier 115 thickness is within the scope of 270nm ~ 230nm.

Continue with reference to Figure 10, described diode also comprises the tube core 120 be positioned on described first conductive layer 110.

Concrete, described tube core 120 comprises: be positioned at the first semiconductor layer 121 and the second semiconductor layer 122 on described first conductive layer 110 successively, described first semiconductor layer 121 is different with the doping type of described second semiconductor layer 122.

It should be noted that, in order to reduce the leakage current of described diode, in the present embodiment, the material of described first semiconductor layer 121 and described second semiconductor layer 122 is amorphous semiconductor.Due in amorphous semiconductor, because atomic structure lacks long-range order, therefore there is a large amount of localized modes in material.The existence of a large amount of localized modes forms a large amount of potential barriers to charge carrier, thus have impact on the migration of charge carrier.Therefore in amorphous semiconductor, the mobility of charge carrier is less.So adopt amorphous semiconductor to form tube core 120, diode reverse conducting resistance can be increased, can the leakage current of twin zener dioder further.

Concrete, in the present embodiment, described first semiconductor layer 121 is N type semiconductor, and described second semiconductor layer 122 is P type semiconductor, to form tube core 120.

Because amorphous semiconductor technique is simple, therefore amorphous semiconductor film-forming process is adopted directly to form described first semiconductor 121 and described second semiconductor layer 122 to form tube core 120, the mode of chemical vapour deposition (CVD) can be adopted directly to form described first semiconductor 121 and described second semiconductor layer 122, can avoid adopting ion implantation technology, therefore process complexity can be reduced, reduce the technology difficulty that device manufactures, improve device and manufacture yields, reduce device manufacturing cost.

It should be noted that, in order to reduce the leakage current of described diode further, in the present embodiment, described tube core 120 also comprises: the intrinsic semiconductor layer 123 between described first semiconductor layer 121 and described second semiconductor layer 122, and described first semiconductor layer 121, intrinsic semiconductor layer 123 and the second semiconductor layer 122 form the tube core 120 of PIN structural.Intrinsic semiconductor layer 123 is between the first semiconductor layer 121 and described second semiconductor layer 122, the width of diode depletion layer can be increased, thus increase depletion layer potential barrier, increase resistance during diode reverse conducting, thus realize the function of twin zener dioder leakage current.

Similar, in the present embodiment, described intrinsic semiconductor layer 123 is amorphous semiconductor.Adopting amorphous semiconductor to form the effect of described intrinsic semiconductor layer 123 and aforementioned employing amorphous semiconductor, to form the reason of described first semiconductor layer 121 and described second semiconductor layer 122 similar, do not repeat them here.

It should be noted that, owing to using the reason such as material and processing technology, absolute intrinsic material is difficult to obtain, therefore described intrinsic semiconductor layer 123 be doping content very low, P-type material that resistivity is very high or n type material.Concrete, in the present embodiment, described intrinsic semiconductor layer 123 is the N type semiconductor that doping content is very low.

Described diode also comprises: be positioned at the second conductive layer 130 on described tube core 120.

Concrete, the material of described second conductive layer 130 is metal material or conductor metal oxide material.Wherein metal material can be aluminium, aluminium niobium alloy or molybdenum etc., and conductor metal oxide material is generally indium tin oxide material.The material of the present invention to the second conductive layer 130 does not limit.

Described diode also comprises: the protective layer 140 covering described second conductive layer 130.

It should be noted that, in order to make the connection of described tube core 120 and external circuit, described diode also comprises leadframe pad 150.Concrete, according to design needs, described leadframe pad 150 lays respectively in described first conductive layer 110 and described second conductive layer 130, to realize the electrical connection of tube core 120 and external circuit.

Described protective layer 140 plays scratch resistant, anti-dirty, etch-proof protective effect.In the present embodiment, the material of described protective layer 140 is silicon nitride or silica.

It should be noted that, if protective layer 140 thickness is too small, cannot play a protective role; If protective layer 140 thickness is excessive, easily causes waste of material and increase technology difficulty.Therefore, in the present embodiment, the thickness of described protective layer is within the scope of 600nm ~ 1000nm.

Also it should be noted that, described protective layer 140 also covers the sidewall of described second conductive layer 130, described tube core 120 and the first conductive layer 110, to realize the electric isolution between neighboring diode.The described protective layer 140 being arranged on described second conductive layer 130, described tube core 120 and the first conductive layer 110 sidewall effectively can avoid the electric leakage between neighboring diode, improves independence and the isolation of diode.

With reference to Figure 12 and Figure 13, show the structural representation of diode second embodiment of the present invention.Wherein Figure 13 is the cutaway view of B-B ' line in Figure 12.

It should be noted that, in the present embodiment, be described for two-way Transient Suppression Diode, the present invention should do not limited with this.

Described diode also comprises: the first groove 245 being positioned at described tube core 220 and described second conductive layer 230, and described first groove 245 exposes described first conductive layer 210.

It should be noted that, in the present embodiment, described diode also comprises: between adjacent tube core 220, the insulating barrier 215 of cover part first conductive layer 210.Therefore, described first groove 245 is positioned on described insulating barrier 215.

Also it should be noted that, in the present embodiment, described tube core 220 is for form PIN structural by described first semiconductor layer 221, described intrinsic semiconductor layer 223 and described second semiconductor layer 222.Therefore, in the present embodiment, described first groove 245 is positioned at the tube core 220 of described PIN structural and described second conductive layer 230.

Concrete, in the present embodiment, described diode comprises the tube core 220 of two adjacent PIN structural of being separated by described first groove 245.Two adjacent tube cores 220 realize short circuit by the first conductive layer 210.

It should be noted that, in order to realize and being connected of external circuit, described diode also comprises leadframe pad 250.Concrete, because two tube cores 220 adjacent in described diode realize short circuit by the first conductive layer 210.Therefore according to design needs, in the present embodiment, described leadframe pad 250 lays respectively on the second conductive layer 230 of the first groove 245 both sides, to realize the electrical connection of described diode and external circuit.

When described diode is two-way twin zener dioder; in order to realize the isolation between adjacent tube core 220; avoid the electric leakage between tube core 220; except covering described second conductive layer 230; described protective layer 240 also covers bottom and the sidewall of described first groove 245, and namely described protective layer 240 covers the sidewall of described second conductive layer 230 and described tube core 220 to realize the electric isolution between neighboring diode.

It should be noted that; due in the present embodiment; described first groove 245 is positioned at the tube core 220 of the PIN structural be made up of the first semiconductor layer 221, intrinsic semiconductor layer 223 and the second semiconductor layer 222, and therefore described protective layer 240 covers the sidewall of the tube core 220 of described PIN structural.

In the present embodiment, described first conductive layer 210 realizes the electrical connection between adjacent tube core 220, and realizes the connection of tube core 220 and external circuit by the leadframe pad 250 formed on the second conductive layer 230.Therefore described diode can absorb instantaneous large pulse power, voltage clamp to predeterminated level, to realize the protective effect to circuit in positive and negative both direction.

With reference to Figure 20, show the structural representation of diode of the present invention 3rd embodiment.

The present embodiment and previous embodiment something in common repeat no more herein, the difference of the present embodiment is, described diode also comprises: between adjacent tube core 320, and the insulating barrier 315 of cover part insulated substrate 300, in order to realize the electric isolution between adjacent tube core 320.

Described insulating barrier 315 between adjacent tube core 320, i.e. cover part insulated substrate 300 also cover part first conductive layer 310.The setting of described insulating barrier 315 can realize the electric isolution between the adjacent tube core 320 that formed on described first conductive layer 310, improves isolation and the independence of adjacent tube core 320.

Described diode also comprises: the short circuit layer 333 covering described tube core 320.

Described short circuit layer 333 forms the top crown of described diode together for described second conductive layer 330, forms ohmic contact between the second conductive layer 322 in described short circuit layer 333 and described tube core 320.In addition, described short circuit layer 333 also for protecting tube core 320 from the damage of follow-up film forming and etching technics in subsequent technique, improves device yield.

Described diode also comprises the second groove 345 being positioned at described short circuit layer 333, described tube core 320 and described first conductive layer 310, exposes described insulated substrate 300 bottom described second groove 345.

It should be noted that, in the present embodiment, be provided with insulating barrier 315 between adjacent tube core 320 to improve isolation and the independence of adjacent tube core 320.Therefore, in the present embodiment, described second groove 345 is positioned on described insulating barrier 315, and described insulating barrier 315 is exposed in bottom.

Also it should be noted that, in the present embodiment, described diode also comprises: the intrinsic semiconductor 323 between described first semiconductor layer 321 and described second semiconductor layer 322, and described first semiconductor layer 321, intrinsic semiconductor 323 and described second semiconductor layer 322 form the tube core 320 of PIN structural.Therefore, described second groove 345 is positioned at the tube core 320 of described PIN structural and described short circuit layer 333.

Concrete, in the present embodiment, described diode comprises the tube core 320 of the adjacent PIN structural of two of being separated by the second groove 345.Adjacent tube core 320 is by insulating barrier 315 and be positioned at the second groove 345 on insulating barrier 315 and realize electric isolution.

Described diode also comprises the separator 336 covering described second groove 345 sidewall and bottom and partial shorts layer 333.

Described separator 336 is for realizing the electric isolution of adjacent tube core 320, described separator 336 also for realize the second conductive layer and described tube core 320 sidewall between electric isolution, avoid the Contact of the first semiconductor layer 321 of the second conductive layer and described tube core 320, can also avoid, between the first semiconductor layer 321 of described tube core 320 and the second semiconductor layer 322, short circuit occurs.The material of described separator 336 can be silicon nitride or silica.

It should be noted that, in the present embodiment, described second groove 345 is positioned on described insulating barrier 315, and described insulating barrier 315 is exposed in bottom.Therefore, the separator 336 be covered in bottom described second groove 345 contacts with described insulating barrier 315.

Continue with reference to Figure 20, described diode also comprises the second conductive layer be covered on described separator 336 and described short circuit layer 333.

In the present embodiment, described second conductive layer 330 covers described separator 336, described short circuit layer 333 and described second groove 345 sidewall and bottom.

Described second conductive layer 330 realizes being electrically connected with the second semiconductor layer 322 of described tube core 320 by described short circuit layer 333.Described second conductive layer 330 forms the top crown of described diode together with described short circuit layer 333.Second semiconductor layer 322 of adjacent tube core 320 realizes short circuit to form two-way Transient Suppression Diode by described second conductive layer 330.

It should be noted that, for making described diode be connected with external circuit, described diode also comprises leadframe pad.Concrete, two tube cores 320 adjacent due to described diode realize electrical connection by the second conductive layer 330.Therefore according to design needs, in the present embodiment, described second conductive layer 330 forms leadframe pad, to realize the electrical connection of described diode and external circuit.

In addition; in the present embodiment; described protective layer 340 covers the sidewall of described second conductive layer 330 and described second conductive layer 330, described separator 336, described short circuit layer 333, described tube core 320, described separator 315 and described first conductive layer 310, realizes the electric isolution between described diode.

In the present embodiment, the second semiconductor layer 322 in adjacent tube core 320 realizes electrical connection by being made up of top crown described second conductive layer 330 and described short circuit layer 333, and on the first conductive layer 310, forming leadframe pad to realize the connection with external circuit, the adjacent tube core 320 that the second conductive layer 322 is connected forms two-way Transient Suppression Diode.Therefore described diode can absorb instantaneous large pulse power, voltage clamp to predeterminated level, to realize the protective effect to circuit in positive and negative both direction.

To sum up, the present invention forms diode by adopting insulated substrate, insulated substrate is formed the first conductive layer and tube core, due to the insulating properties of insulated substrate, the electric current through flow of substrates warp can be suppressed, the generation crosstalk between diode can be avoided, thus improve the independence of diode, improve the isolation of diode.In addition, in possibility of the present invention, between the first semiconductor layer and the second semiconductor layer, can also intrinsic semiconductor layer be set, to increase the width of diode depletion layer, increase the potential barrier of depletion layer, thus resistance when increasing diode reverse conducting, the leakage current of twin zener dioder thus.And non-crystalline material can also be utilized to substitute crystalline material of the prior art and form diode, because in non-crystalline material, carrier mobility is less, therefore the application of non-crystalline material can the leakage current of twin zener dioder further.In addition, adopt amorphous technique to substitute crystal technique of the prior art, device fabrication difficulty can be effectively reduced, reduce process complexity, improve device and manufacture yields, reduce device cost.Further; in possibility of the present invention; described protective layer also covers the sidewall of described second conductive layer, described tube core and described first conductive layer; for realizing the electric isolution between neighboring diode; effectively avoid the electric leakage between neighboring diode, improve independence and the isolation of diode.When described diode is two-way Transient Suppression Diode; in possibility of the present invention; described protective layer also covers the sidewall being positioned at described second conductive layer and described tube core internal channel; for realizing the isolation between adjacent tube core; effectively avoid the electric leakage between adjacent tube core, reduce the leakage current of diode.

Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.

Claims

1. a manufacture method for diode, is characterized in that, comprising:

Insulated substrate is provided;

Form the first conductive layer covering described insulated substrate;

Form the second conductive layer be positioned on described tube core;

Form the protective layer covering described second conductive layer.

2. manufacture method as claimed in claim 1, it is characterized in that, described insulated substrate is glass substrate.

3. manufacture method as claimed in claim 1, it is characterized in that, after the step forming the first conductive layer covering described insulated substrate, before the step of formation first semiconductor layer, described manufacture method also comprises: the insulating barrier forming cover part first conductive layer between adjacent tube core, to realize the electric isolution between neighboring diode.

4. manufacture method as claimed in claim 3, it is characterized in that, the step forming the insulating barrier of cover part first conductive layer between neighboring diode comprises:

Described first conductive layer forms insulation material layer;

Remove part insulation material layer, form the first opening exposing described first conductive layer, to form insulating barrier.

5. manufacture method as claimed in claim 3, it is characterized in that, described insulating layer material is silicon nitride or silica.

6. manufacture method as claimed in claim 3, it is characterized in that, described thickness of insulating layer is within the scope of 230nm ~ 270nm.

7. manufacture method as claimed in claim 1, it is characterized in that, the step that described first conductive layer is formed the first semiconductor layer and the second semiconductor layer successively comprises: the material of described first semiconductor layer and described second semiconductor layer is amorphous semiconductor.

8. manufacture method as claimed in claim 1, it is characterized in that, the step that described first conductive layer is formed the first semiconductor layer and the second semiconductor layer successively comprises: adopt the mode of chemical vapour deposition (CVD) to form described first semiconductor layer and the second semiconductor layer.

9. manufacture method as claimed in claim 1, it is characterized in that, after the step forming the second conductive layer be positioned on described tube core, before forming the step of the protective layer covering described second conductive layer, described manufacture method also comprises: etch described second conductive layer and described tube core and form the first groove exposing described first conductive layer;

The step forming the protective layer covering described second conductive layer also comprises: described protective layer also covers bottom and the sidewall of described first groove.

10. manufacture method as claimed in claim 9, it is characterized in that, after the step forming the first conductive layer covering described insulated substrate, before described first conductive layer forms the step of the first semiconductor layer, described manufacture method also comprises: the insulating barrier forming cover part first conductive layer between adjacent tube core;

The step forming described first groove comprises: on described insulating barrier, form described first groove, and makes described first channel bottom expose described insulating barrier.

11. manufacture methods as claimed in claim 1, it is characterized in that, described first conductive layer forms the first semiconductor layer and the second semiconductor layer successively with after the step forming tube core, before forming the step of the second conductive layer be positioned on described tube core, described manufacture method also comprises:

Form the short circuit layer be positioned on described tube core;

Etch described short circuit layer and described tube core, form the second groove that described insulated substrate is exposed in bottom;

Form the separator covering described second trenched side-wall and bottom;

The step forming the second conductive layer be positioned on described tube core comprises: form the second conductive layer covering described short circuit layer and separator.

12. manufacture methods as claimed in claim 11, is characterized in that, the step forming the short circuit layer be positioned on described tube core comprises: the material of described short circuit layer is metal or conductor metal oxide material.

13. manufacture methods as claimed in claim 11, is characterized in that, the step forming the separator covering described second trenched side-wall and bottom comprises:

Form the spacer material layer covering described short circuit layer and described second trenched side-wall and bottom;

Removal unit divides spacer material layer, and formation exposes the second opening of described short circuit layer to form separator.

14. manufacture methods as claimed in claim 11, it is characterized in that, after the step forming the first conductive layer covering described insulated substrate, before described first conductive layer forms the step of the first semiconductor layer, described manufacture method also comprises: the insulating barrier forming cover part insulated substrate between adjacent tube core, to realize the electric isolution between adjacent tube core;

The step forming the insulating barrier of cover part first conductive layer between adjacent tube core comprises:

Remove part first conductive layer, to form the insulated openings that insulated substrate is exposed in bottom;

Form the insulation material layer covering described first conductive layer and insulated substrate;

Remove part insulation material layer, form the 3rd opening exposing described first conductive layer, to form insulating barrier;

The step forming described second groove comprises: on described insulating barrier, form described second groove, and described insulating barrier is exposed in the bottom of described second groove.

15. manufacture methods as described in claim 1,9 or 11, it is characterized in that, after described first conductive layer forms the step of the first semiconductor layer, before described first semiconductor layer forms the step of the second semiconductor layer, described manufacture method also comprises: form the intrinsic semiconductor layer covering described first semiconductor layer.

16. manufacture methods as claimed in claim 15, is characterized in that, the step forming the intrinsic semiconductor layer covering described first semiconductor layer comprises: the material of described intrinsic semiconductor layer is amorphous semiconductor.

17. manufacture methods as claimed in claim 15, is characterized in that, the step forming the intrinsic semiconductor layer covering described first semiconductor layer comprises: described intrinsic semiconductor layer is lightly doped N type semiconductor.

18. manufacture methods as claimed in claim 1, is characterized in that, the step forming the second conductive layer be positioned on described tube core comprises: described second conductive is metal or conductor metal oxide material.

19. manufacture methods as claimed in claim 1, is characterized in that, the step forming the protective layer covering described second conductive layer also comprises: described protective layer also covers the sidewall of described second conductive layer, described tube core and described first conductive layer.

20. 1 kinds of diodes, is characterized in that, comprising:

Insulated substrate;

Cover the first conductive layer of described insulated substrate;

Be positioned at the second conductive layer on described tube core;

Cover the protective layer of described second conductive layer.

21. diodes as claimed in claim 20, it is characterized in that, described insulated substrate is glass substrate.

22. diodes as claimed in claim 20, is characterized in that, described first semiconductor layer and described second semiconductor layer material are amorphous semiconductor.

23. diodes as claimed in claim 20, it is characterized in that, described diode also comprises between the first conductive layer and the first semiconductor layer: between adjacent tube core and the insulating barrier of cover part first conductive layer, in order to realize the electric isolution between neighboring diode;

Described tube core covers described insulating barrier and described first conductive layer.

24. diodes as claimed in claim 23, it is characterized in that, described insulating layer material is silica or silicon nitride.

25. diodes as claimed in claim 23, it is characterized in that, described thickness of insulating layer is within the scope of 230nm ~ 270nm.

26. diodes as claimed in claim 20, it is characterized in that, described diode is two-way Transient Suppression Diode;

Described diode also comprises:

Be arranged in the first groove of described tube core and described second conductive layer, described first groove exposes described first conductive layer;

Described protective layer is also covered in bottom and the sidewall of described first groove.

27. diodes as claimed in claim 26, it is characterized in that, described diode also comprises between the first conductive layer and the first semiconductor layer: between adjacent tube core and the insulating barrier of cover part first conductive layer;

The protective layer being covered in described first channel bottom contacts with described insulating barrier.

28. diodes as claimed in claim 20, it is characterized in that, described diode is two-way Transient Suppression Diode;

Described diode also comprises:

Cover the short circuit layer of described tube core;

Be positioned at the second groove of described short circuit layer, described tube core and described first conductive layer, described second channel bottom exposes described insulated substrate;

Be covered in the separator of described second trenched side-wall and bottom;

Described second conductive layer is covered on described separator and described short circuit layer.

29. diodes as claimed in claim 28, is characterized in that, described short circuit layer material is metal or conductor metal oxide material.

30. diodes as claimed in claim 28, it is characterized in that, described diode also comprises between described substrate and described first semiconductor layer: between adjacent tube core, and the insulating barrier of cover part insulated substrate, in order to realize the electric isolution between adjacent tube core;

The separator being covered in described second channel bottom contacts with described insulating barrier.

31. diodes as described in claim 20,26 or 28, it is characterized in that, described tube core also comprises the intrinsic semiconductor layer between described first semiconductor layer and described second semiconductor layer.

32. diodes as claimed in claim 31, it is characterized in that, described intrinsic semiconductor layer is amorphous semiconductor.

33. diodes as claimed in claim 31, it is characterized in that, described intrinsic semiconductor layer is lightly doped n-type semiconductor.

34. diodes as claimed in claim 31, is characterized in that, described second conductive is metal or conductor metal oxide material.

35. diodes as claimed in claim 20, is characterized in that, described protective layer is also covered in the sidewall of described second conductive layer, described tube core and described first conductive layer.