CN104977768B - Liquid crystal display panel and its pixel charging circuit - Google Patents
Liquid crystal display panel and its pixel charging circuit Download PDFInfo
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- CN104977768B CN104977768B CN201510458967.9A CN201510458967A CN104977768B CN 104977768 B CN104977768 B CN 104977768B CN 201510458967 A CN201510458967 A CN 201510458967A CN 104977768 B CN104977768 B CN 104977768B
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/13606—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit having means for reducing parasitic capacitance
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
- G02F1/136245—Active matrix addressed cells having more than one switching element per pixel having complementary transistors
Abstract
A kind of liquid crystal display panel of present invention offer and its pixel charging circuit, the pixel charging circuit include：Pixel circuit, including multiple sub-pixels, each sub-pixel include first switch connected to the gate line；Multiple selector, including multiple selecting modules, each selecting module include：Second switch；Clock signal control terminal；First switch is complimentary to one another with second switch, the error of caused data-signal when can be eliminated when pixel charging the signal saltus step of grid line and the output of clock signal control terminal.The pixel charging circuit of the embodiment of the present invention, utilize the characteristic of NMOS transistor and PMOS transistor complementation, under the premise of ensureing that pixel charges normal, significantly reduce the influence of the capacitance coupling effect of the parasitic capacitance due to transistor inherently, improve the charging ability of pixel, enable pixel to keep ideal current potential, promotes the display effect of liquid crystal display panel.
Description
Technical field
The present invention relates to technical field of liquid crystal display more particularly to a kind of liquid crystal display panels and its pixel charging circuit.
Background technology
Liquid crystal display has driving voltage and the series of advantages such as low in energy consumption, small, light-weight, radiationless, by
Extensive attention, development is very fast, has become the mainstream technology of flat-panel monitor.
In the pixel charging circuit of existing liquid crystal display, carries out door using simple NMOS tube or PMOS tube and open
When the control of pass, due to the influence of the capacitance coupling effect of the parasitic capacitance of transistor inherently, the output signal meeting of circuit
Certain deformation occurs so that the pixel of charging cannot keep ideal current potential, to influence the display effect of panel.
Therefore there is an urgent need for a kind of pixel charging circuits, under the premise of ensureing that pixel charges normal work, can effectively drop
The influence of the capacitance coupling effect of the low parasitic capacitance due to transistor inherently, to improve the display of liquid crystal display panel
Effect.
Invention content
The first technical problem to be solved by the present invention is to need offer one kind that can be effectively reduced due to transistor sheet
The influence of the capacitance coupling effect of the intrinsic parasitic capacitance of body, to improve the pixel charging circuit of display effect.
In order to solve the above-mentioned technical problem, the embodiment of the present invention provides firstly a kind of pixel charging circuit, including：Picture
Plain circuit comprising multiple sub-pixels, each sub-pixel include first switch connected to the gate line；Multiple selector, packet
Include multiple selecting modules, one end of the multiple selecting module is connect with same data signal output, the other end respectively with not
Same sub-pixel connection, each selecting module provide data-signal to corresponding sub-pixel after being strobed and carry out pixel charging,
Each selecting module includes：Second switch；Clock signal control terminal, output clock signal is to control opening for the second switch
It opens and closes；Wherein, the first switch and the second switch are complimentary to one another, can be eliminated when carrying out pixel charging described
The error of caused data-signal when the signal saltus step of grid line and clock signal control terminal output.
Preferably, the first switch is NMOS tft, and the second switch is PMOS thin film transistor (TFT)s.
Preferably, the first switch is PMOS thin film transistor (TFT)s, and the second switch is NMOS tft.
Preferably, the first switch and the second switch are NMOS tft or PMOS films based on LTPS
Transistor.
Embodiments herein additionally provides a kind of liquid crystal display panel comprising pixel charging circuit, the pixel are filled
Circuit includes：Pixel circuit comprising multiple sub-pixels, each sub-pixel include first switch connected to the gate line；It is more
Road selector comprising multiple selecting modules, one end of the multiple selecting module are connect with same data signal output, separately
One end is connected from different sub-pixel respectively, each selecting module after being strobed to corresponding sub-pixel provide data-signal into
Row pixel charges, and each selecting module includes：Second switch；Clock signal control terminal, output clock signal are described to control
The opening and closing of second switch；Wherein, the first switch and the second switch are complimentary to one another, when carrying out pixel charging
The error of caused data-signal when can eliminate the signal saltus step of the grid line and clock signal control terminal output.
Preferably, the first switch is NMOS tft, and the second switch is PMOS thin film transistor (TFT)s.
Preferably, the first switch is PMOS thin film transistor (TFT)s, and the second switch is NMOS tft.
Preferably, the first switch and the second switch are NMOS tft or PMOS films based on LTPS
Transistor.
Compared with prior art, one or more of said program embodiment can have the following advantages that or beneficial to effect
Fruit.
Pixel charging circuit provided in an embodiment of the present invention, using the mashed up designs of N/PMOS, using NMOS transistor and
The characteristic of PMOS transistor complementation significantly reduces under the premise of ensureing that pixel charges normal since transistor itself is solid
The influence of the capacitance coupling effect of some parasitic capacitances improves the charging ability of pixel so that pixel can keep ideal
Current potential promotes the display effect of liquid crystal display panel.
Other features and advantages of the present invention will be illustrated in the following description, also, partly becomes from specification
It obtains it is clear that being understood by implementing technical scheme of the present invention.The purpose of the present invention and other advantages can by
Specifically noted structure and/or flow are realized and are obtained in specification, claims and attached drawing.
Description of the drawings
Attached drawing is used for providing to the technical solution of the application or further understanding for the prior art, and constitution instruction
A part, wherein express technical side of the attached drawing of the embodiment of the present application together with embodiments herein for explaining the application
Case, but do not constitute the limitation to technical scheme：
Fig. 1 is the area distribution schematic diagram of the liquid crystal display panel of the embodiment of the present invention；
Fig. 2 is the structural schematic diagram of the pixel charging circuit of first embodiment of the invention；
Fig. 3 is the waveform timing chart of pixel charging circuit shown in Fig. 2；
Fig. 4 is the structural schematic diagram of the pixel charging circuit of second embodiment of the invention；
Fig. 5 is the waveform timing chart of pixel charging circuit shown in Fig. 4.
Specific implementation mode
To make the object, technical solutions and advantages of the present invention clearer, the present invention is made below in conjunction with attached drawing further
Ground is described in detail.
First embodiment
Fig. 1 is the area distribution schematic diagram of liquid crystal display panel.As shown in Figure 1, the region of the liquid crystal display panel includes：
The regions AA 10, the regions GOA 20 are fanned out to region (Fanout) 30, region multiple selector (Demux) 40, the regions WOA 50, the areas IC
Domain 60 and the regions FPC 70.
Wherein, the regions AA (Ative Area) 10 is effective display area domain, refers generally to the region for showing figure, region packet
Containing multiple sub-pixels.The regions GOA 20, i.e. Gate On Array, the gate drive signal for generating TFT in panel.Fanout
Region 30 is connect for IC with the cabling of the data line in the regions AA 10.The regions Demux 40 are provided with multiple selector, are used for
The data line drawn from the regions IC 60 is split, for the driving of multiple data lines.The regions WOA 50, i.e. Wire On
Array, the connection for cabling around panel.The regions IC 60 are used for the binding (Bonding) of IC, by IC driving panels
Circuit and TFT.The regions FPC 70 are used for the binding (Bonding) of FPC, cell phone mainboard are connected by FPC.
In the design of general liquid crystal display panel, data line is drawn from the regions IC 60, is inputted by the regions Fanout 30
Into the pixel charging circuit in the regions AA 10.The pixel charging circuit includes multiple selector and pixel circuit, wherein multichannel is selected
The effect for selecting device is that the charging of three row sub-pixel of a data line traffic control is used using the principle of time-shared switch.In existing multichannel
In selector and pixel circuit, can generally it use the transistor of same type as switching device, for example, making in multiple selector
The control of multiple selector is carried out with NMOS tft (PMOS thin film transistor (TFT)s), while the switch in pixel circuit uses
NMOS tft (PMOS thin film transistor (TFT)s).However, being carried out using this simple NMOS PMOS thin film transistor (TFT)s
When the control of door switch, due to the influence of the capacitance coupling effect of the parasitic capacitance of transistor inherently, the output of circuit is believed
Number certain deformation can occur so that the pixel of charging cannot keep ideal current potential, to influence the aobvious of entire driving panel
Show effect.
Specifically, in multiple selector, as the transistor of switch, there are parasitic capacitance Cgs and Cgd.Work as transistor
Grid when having switch change, parasitic capacitance can make the saltus step for the signal that the output end of transistor exports with grid line occur
It is corresponding to change.In pixel circuit, as the transistor of switch, there are parasitic capacitance Cgs and Cgd.When gate drive signal is sent out
When raw change, due to the coupling effect of capacitance, it can make the current potential of storage capacitance that corresponding change occur.
That is, during charging to pixel, pixel cannot keep ideal current potential in the last stage,
The current potential of pixel can be influenced by switching signal twice.The variation of first time pixel potential be due in multiple selector when
Clock signal CK is by the influence of high level to low transition, and it is slightly lower to be coupled (Couple) to one for pixel potential at this time
Current potential.The variation of second of pixel potential is the gate drive signal that is exported due to grid line from high level to low transition
It influences, pixel potential is coupled (Couple) to a lower current potential at this time.Therefore, simple NMOS or PMOS is constituted
Pixel charging circuit can influence the charging potential of pixel so that certain drift occurs for common electric potential, to influence the aobvious of panel
Show effect.
Main purpose of the embodiment of the present invention is to provide a kind of pixel charging circuit, which is ensureing normally to carry out pixel
Under the premise of charging, the influence of the capacitance coupling effect of the parasitic capacitance due to transistor inherently can be effectively reduced,
Pixel charging potential is set to keep ideal potential, to improve display effect.
Fig. 2 is the structural schematic diagram of the pixel charging circuit of first embodiment of the invention.It is described in detail below with reference to Fig. 2
The structure of the pixel charging circuit.
As shown in Fig. 2, pixel charging circuit includes multiple selector 110 and pixel circuit 120.Multiple selector 110 is wrapped
Include multiple (being usually at least three) selecting module such as 110A, 110B and 110C, one end of multiple selecting modules and same data
Signal output end DATA connections, the other end different from pixel circuit 120 sub-pixel connections respectively, each selecting module is in quilt
Data-signal is provided to corresponding sub-pixel carry out pixel charging, i.e., each selecting module 110A, 110B in this example after gating
And 110C provides data-signal after being strobed to corresponding sub-pixel.So-called " sub-pixel " can be red sub-pixel R, green
The sub-pixel of the different colours such as sub-pixel G or blue subpixels B.
Specifically, each sub-pixel includes mainly the first switch Mp being connect with gate lines G ate, storage in pixel circuit 120
Deposit capacitance Cst and liquid crystal capacitance Cls；The grid of first switch Mp is electrically coupled to the respective gates line in a plurality of grid line
Corresponding selecting module such as 110A, 110B that the drain electrode of Gate, first switch Mp are electrically coupled in multiple selector 110 and
110C, and the source electrode of first switch Mp is electrically coupled to common electric potential Vcom by storage capacitors Cst and liquid crystal capacitance Cls,
This, storage capacitors Cst is connected in parallel with liquid crystal capacitance Cls.In addition, Fig. 2 also shows the existing parasitisms of first switch Mp itself
Capacitance Cgd and Cgs.First switch Mp in this example is NMOS tft.
Each selecting module (110A, 110B or 110C) includes：Second switch；Clock signal control terminal is opened with second
The control terminal of pass connects, and output clock signal is to control the opening and closing of second switch.Such as selecting module 110A includes the
Two switch SW-A and clock signal control terminal CK1, selecting module 110B include second switch SW-B and clock signal control terminal
CK2, selecting module 110C include second switch SW-C and clock signal control terminal CK3.It is opened in addition, also showing second in Fig. 2
Close parasitic capacitance Cgd and Cgs existing for SW-A, SW-B, SW-C itself.
It should be noted that the second switch of each selecting module uses and pixel circuit 120 in this multiple selector 110
In the different types of switch of first switch, the two is complimentary to one another, i.e., second switch be PMOS thin film transistor (TFT)s.Due to pixel electricity
First switch in road 120 is NMOS tft, and the second switch in multiple selector 110 is PMOS thin film transistor (TFT)s,
Therefore it using the characteristic of transistor and the transistor complementary in pixel circuit 120 in multiple selector 110, is filled carrying out pixel
Caused pixel potential when can greatly eliminate the signal saltus step of gate lines G ate and the output of clock signal control terminal when electric
The error of (data-signal) improves the charging ability of pixel.Furthermore, it is contemplated that LTPS has higher carrier mobility, this
Therefore the NMOS tft or PMOS thin film transistor (TFT)s that switch in embodiment is preferably based on LTPS can reduce work(
Consumption, improves the current carrying capacity of device, meanwhile, improve the switch conversion speed of transistor.
It is readily appreciated that, when the first switch in pixel circuit 120 is NMOS tft, this multiple selector 110
In the second switch of each selecting module be PMOS thin film transistor (TFT)s, by using the mashed up design methods of N/PMOS, profit
With the characteristic of NMOS and PMOS complementations, the compensation to pixel charging potential can be realized so that pixel can keep ideal electricity
Position, promotes the display effect of panel.The advantages of in order to which the present embodiment is better described, illustrates that this pixel is filled referring to Fig. 3
The principle when work of circuit.
Fig. 3 is the waveform timing chart of the pixel charging circuit of the present embodiment and the waveform diagram of respective drive signal.
In figure 3, DATA indicates that the data-signal initially exported to sub-pixel R, G, B in different periods, Gate indicate grid input letter
Number, CK1, CK2, CK3 indicate the clock signal of clock signal control terminal CK1, CK2, CK3 input respectively, and R, G, B are indicated most respectively
It is input to the data-signal of different subpixel eventually.It is known that the week opened in gate lines G ate and (be in high level) from Fig. 3
In phase, the voltage of each selecting module 110A, 110B and the 110C data-signals to be transmitted is sequentially 3V, 1V and 4V.
Since the second switch of multiple selector 110 is PMOS transistor, in the CK outputs of clock signal control terminal
When signal is low level (this example is -7V), second switch SW-A, SW-B, SW-C are opened, and are high level (this example in output signal
For 9V) when, second switch SW-A, SW-B, SW-C are closed.
From the figure 3, it may be seen that during being charged to pixel using circuit shown in Fig. 2, although the current potential of pixel can also be sent out
Life changes twice, but final pixel can keep ideal current potential, realize the normal display of panel.Specifically, picture for the first time
The variation of plain current potential is the clock signal due to the clock signal control terminal CK outputs of multiple selector 110 by low level to high electricity
The influence of flat saltus step, at this time pixel potential be coupled to a slightly higher current potential.The variation of second of pixel potential is due to grid
Influence of the pole drive signal from high level to low transition, at this time pixel potential be coupled to a lower current potential, just return
To original current potential, the normal display of pixel is realized.
More specifically, being the low level stage in the CK1 outputs of clock signal control terminal, second switch SW-A is opened, in this phase
Between pre-transmission to sub-pixel R data-signal be 3V.But after saltus step occurs for clock signal CK1, i.e., high electricity is become from low level
Usually, second switch SW-A is closed, and due to the influence of parasitic capacitance Cgs, being transferred to the data-signal of sub-pixel R becomes 3V+ △,
The current potential is continued until that saltus step occurs for gate lines G ate, due to being influenced by the parasitic capacitance Cgs of first switch Mp, transmits
Become 3V+ △-△ to the data-signal of sub-pixel R, just return to original current potential 3V, realizes the normal display of sub-pixel R.
It it is the low level stage in the CK2 outputs of clock signal control terminal, second switch SW-B is opened, and pre-transmission is given during this period
The data-signal of sub-pixel G is 1V.But after saltus step occurs for clock signal CK2, i.e., when becoming high level from low level, second opens
It closes SW-B to close, due to the influence of parasitic capacitance Cgs, being transferred to the data-signal of sub-pixel G becomes 1V+ △, and the current potential is always
Continue to that gate lines G ate occurs saltus step and is transferred to sub-pixel G due to being influenced by the parasitic capacitance Cgs of first switch Mp
Data-signal become 1V+ △-△, just return to original current potential 1V, realize the normal display of sub-pixel G.
It it is the low level stage in the CK3 outputs of clock signal control terminal, second switch SW-C is opened, and pre-transmission is given during this period
The data-signal of sub-pixel B is 4V.But after saltus step occurs for clock signal CK3, i.e., when becoming high level from low level, second opens
It closes SW-C to close, due to the influence of parasitic capacitance Cgs, being transferred to the data-signal of sub-pixel B becomes 4V+ △, and the current potential is always
Continue to that gate lines G ate occurs saltus step and is transferred to sub-pixel B due to being influenced by the parasitic capacitance Cgs of first switch Mp
Data-signal become 4V+ △-△, just return to original current potential 4V, realize the normal display of sub-pixel B.
Pixel charging circuit in above-described embodiment mainly changes electricity for traditional pixel charging circuit
The circuit structure of multiple selector in road.In the present embodiment, second switch is PMOS thin film transistor (TFT)s, utilizes multi-path choice
The characteristic of transistor and pixel circuit transistor complementary in device, greatly improves the charging ability of pixel.In this circuit, lead to
It crosses using design method mashed up N/PMOS, using the characteristic of NMOS and PMOS complementations, realizes the compensation to pixel charging potential,
Enable pixel to keep ideal current potential, promotes the display effect of panel.
Second embodiment
Fig. 4 is the structural schematic diagram of the pixel charging circuit of second embodiment of the invention.Fig. 5 is that pixel shown in Fig. 4 is filled
The waveform timing chart of circuit.
In the present embodiment, the thin film transistor (TFT) of pixel charging circuit is PMOS thin film transistor (TFT)s, and in multiple selector
Switch is to use NMOS tft, utilizes the characteristic of transistor complementary in transistor in multiple selector and pixel circuit, drop
The influence of the capacitance coupling effect of the low parasitic capacitance due to transistor inherently, greatly improves the charging energy of pixel
Power.
As shown in figure 4, pixel charging circuit includes multiple selector 210 and pixel circuit 220.Multiple selector 210 is wrapped
Include multiple (being usually at least three) selecting module such as 210A, 210B and 210C, one end of multiple selecting modules and same data
Signal output end DATA connections, the other end different from pixel circuit 220 sub-pixel connections respectively, each selecting module is in quilt
Data-signal is provided to corresponding sub-pixel carry out pixel charging, i.e., each selecting module 210A, 210B in this example after gating
And 210C provides data-signal after being strobed to corresponding sub-pixel.
Each selecting module (210A, 210B and 210C) includes：Second switch；Clock signal control terminal is opened with second
The control terminal of pass connects, and output clock signal is to control the opening and closing of second switch.Such as selecting module 210A includes the
Two switch SW-A and clock signal control terminal CK1, selecting module 210B include second switch SW-B and clock signal control terminal
CK2, selecting module 210C include second switch SW-C and clock signal control terminal CK3.It is opened in addition, also showing second in Fig. 4
Close parasitic capacitance Cgd and Cgs existing for SW-A, SW-B, SW-C itself.Compared with first embodiment, in this multiple selector 210
Second switch SW-B, second switch SW-B, second switch SW-C be NMOS tft.
Specifically, each sub-pixel includes mainly first switch Mp, storage capacitors Cst and liquid crystal in pixel circuit 220
Capacitance Cls；The grid of first switch Mp is electrically coupled to the respective gates line Gate in a plurality of grid line, first switch Mp's
Drain corresponding selecting module such as 210A, 210B and the 210C being electrically coupled in multiple selector 210, and first switch Mp
Source electrode common electric potential Vcom is electrically coupled to by storage capacitors Cst and liquid crystal capacitance Cls, here, storage capacitors Cst and liquid
Brilliant capacitance Cls is connected in parallel.In addition, Fig. 4 also shows parasitic capacitance Cgd and Cgs existing for first switch Mp itself.In tradition
Pixel circuit in, first switch Mp is generally NMOS tft, and the first switch Mp in this example then selects thin with NMOS
The opposite transistor of film transistor type, such as first switch Mp in sub-pixel B (dotted line frame 220A) are PMOS film crystals
Pipe.
It should be noted that the first switch in this pixel circuit 220 uses and each selection in multiple selector 210
The different types of switch of second switch of module, i.e. first switch are PMOS thin film transistor (TFT)s.Due in pixel circuit 220
One switch is PMOS thin film transistor (TFT)s, and the second switch in multiple selector 210 is NMOS tft, therefore utilizes multichannel
The characteristic of transistor in selector 210 and the transistor complementary in pixel circuit 220, can when carrying out pixel charging
Caused pixel potential (believe by data when the signal saltus step that greatly elimination grid line and the clock signal control terminal export
Number) error, improve the charging ability of pixel.
Furthermore, it is contemplated that there is LTPS higher carrier mobility, the switch in the present embodiment to be preferably based on LTPS
NMOS tft or PMOS thin film transistor (TFT)s therefore can reduce power consumption, improve the current carrying capacity of device, together
When, improve the switch conversion speed of transistor.
Fig. 4 is the waveform timing chart of the pixel charging circuit of the present embodiment and the waveform diagram of respective drive signal.
In Fig. 4, DATA indicates that the data-signal initially exported to sub-pixel R, G, B in different periods, Gate indicate grid input letter
Number, CK1, CK2, CK3 indicate the clock signal of clock signal control terminal CK1, CK2, CK3 input respectively, and R, G, B are indicated most respectively
It is input to the data-signal of different subpixel eventually.It is known that the week opened in gate lines G ate and (be in low level) from Fig. 4
In phase, the voltage of each selecting module 210A, 210B and the 210C data-signals to be transmitted is sequentially 3V, 1V and 4V.
It is low in the signal of gate lines G ate outputs since the first switch of pixel circuit 210 is PMOS transistor
When level (this example is -7V), first switch Mp is opened, and when output signal is high level (this example 9V), first switch Mp is closed
It closes.
As shown in Figure 5, during being charged to pixel using circuit shown in Fig. 4, although the current potential of pixel can also be sent out
Life changes twice, but final pixel can keep ideal current potential, realize the normal display of panel.Specifically, picture for the first time
The variation of plain current potential is the clock signal due to the clock signal control terminal CK outputs of multiple selector 210 by high level to low electricity
The influence of flat saltus step, at this time pixel potential be coupled to a slightly lower current potential.The variation of second of pixel potential is due to grid
The gate drive signal of polar curve output from low level to the influence of high level saltus step, at this time pixel potential be coupled to one it is higher
Current potential just returns to original current potential, realizes the normal display of pixel.
More specifically, being the high level stage in the CK1 outputs of clock signal control terminal, second switch SW-A is opened, in this phase
Between pre-transmission to sub-pixel R data-signal be 3V.But after saltus step occurs for clock signal CK1, i.e., low electricity is become from high level
Usually, second switch SW-A is closed, and due to the influence of parasitic capacitance Cgs, being transferred to the data-signal of sub-pixel R becomes 3V- △,
The current potential is continued until that saltus step occurs for gate lines G ate, due to being influenced by the parasitic capacitance Cgs of first switch Mp, transmits
Become 3V- △+△ to the data-signal of sub-pixel R, just return to original current potential 3V, realizes the normal display of sub-pixel R.
It it is the high level stage in the CK2 outputs of clock signal control terminal, second switch SW-B is opened, and pre-transmission is given during this period
The data-signal of sub-pixel G is 1V.But after saltus step occurs for clock signal CK2, i.e., when becoming low level from high level, second opens
It closes SW-B to close, due to the influence of parasitic capacitance Cgs, being transferred to the data-signal of sub-pixel G becomes 1V- △, and the current potential is always
Continue to that gate lines G ate occurs saltus step and is transferred to sub-pixel G due to being influenced by the parasitic capacitance Cgs of first switch Mp
Data-signal become 1V- △+△, just return to original current potential 1V, realize the normal display of sub-pixel G.
It it is the high level stage in the CK3 outputs of clock signal control terminal, second switch SW-C is opened, and pre-transmission is given during this period
The data-signal of sub-pixel B is 4V.But after saltus step occurs for clock signal CK3, i.e., when becoming low level from high level, second opens
It closes SW-C to close, due to the influence of parasitic capacitance Cgs, being transferred to the data-signal of sub-pixel B becomes 4V- △, and the current potential is always
Continue to that gate lines G ate occurs saltus step and is transferred to sub-pixel B due to being influenced by the parasitic capacitance Cgs of first switch Mp
Data-signal become 4V- △+△, just return to original current potential 4V, realize the normal display of sub-pixel B.
In general circuit design, the circuit design of multiple selector often uses the crystalline substance with pixel circuit same type
Body pipe.In the present embodiment, the first switch in pixel circuit is PMOS thin film transistor (TFT)s, utilizes transistor in multiple selector
With the characteristic of transistor complementary in pixel circuit, the charging ability of pixel is greatly improved.In this circuit, and use N/
Design method mashed up PMOS realizes the compensation to pixel charging potential so that pixel using the characteristic of NMOS and PMOS complementations
Ideal current potential can be kept, the display effect of liquid crystal display panel is promoted.
In conclusion pixel charging circuit provided in an embodiment of the present invention utilizes NMOS using the mashed up designs of N/PMOS
Thin film transistor (TFT) and the characteristic of PMOS thin film transistor (TFT) complementations significantly reduce under the premise of ensureing that pixel charges normal
Due to the influence of the capacitance coupling effect of the parasitic capacitance of transistor inherently, the charging ability of pixel is improved so that as
Element can keep ideal current potential, promote the display effect of liquid crystal display panel.
Although disclosed herein embodiment it is as above, the content only technical solution of the present invention for ease of understanding
And the embodiment used, it is not limited to the present invention.Technical staff in any fields of the present invention is not departing from this
Under the premise of the disclosed spirit and scope of invention, any modification and variation can be carried out in the form and details of implementation,
But the scope of patent protection of the present invention, still should be subject to the scope of the claims as defined in the appended claims.
Claims (4)
1. a kind of pixel charging circuit, including：
Pixel circuit comprising multiple sub-pixels, each sub-pixel include first switch connected to the gate line；
Multiple selector comprising multiple selecting modules, one end of the multiple selecting module and same data signal output
Connection, the other end are connected from different sub-pixels respectively, and each selecting module provides number after being strobed to corresponding sub-pixel
It is believed that number progress pixel charging, each selecting module include：Second switch；Clock signal control terminal, output clock signal with
Control the opening and closing of the second switch；
Wherein, the first switch and the second switch are complimentary to one another, and the grid can be eliminated when carrying out pixel charging
The error of caused data-signal when the signal saltus step of line and clock signal control terminal output；
Wherein, the first switch is NMOS tft, and the second switch is PMOS thin film transistor (TFT)s or described the
One switch is PMOS thin film transistor (TFT)s, and the second switch is NMOS tft.
2. pixel charging circuit according to claim 1, which is characterized in that
The first switch and the second switch are NMOS tft or PMOS thin film transistor (TFT)s based on LTPS.
3. a kind of liquid crystal display panel comprising pixel charging circuit, the pixel charging circuit include：
Pixel circuit comprising multiple sub-pixels, each sub-pixel include first switch connected to the gate line；
Multiple selector comprising multiple selecting modules, one end of the multiple selecting module and same data signal output
Connection, the other end are connected from different sub-pixels respectively, and each selecting module provides number after being strobed to corresponding sub-pixel
It is believed that number progress pixel charging, each selecting module include：Second switch；Clock signal control terminal, output clock signal with
Control the opening and closing of the second switch；
Wherein, the first switch and the second switch are complimentary to one another, and the grid can be eliminated when carrying out pixel charging
The error of caused data-signal when the signal saltus step of line and clock signal control terminal output；
Wherein, the first switch is NMOS tft, and the second switch is PMOS thin film transistor (TFT)s or described the
One switch is PMOS thin film transistor (TFT)s, and the second switch is NMOS tft.
4. liquid crystal display panel according to claim 3, which is characterized in that
The first switch and the second switch are NMOS tft or PMOS thin film transistor (TFT)s based on LTPS.
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| CN106097955B (en) * | 2016-08-09 | 2019-08-27 | 厦门天马微电子有限公司 | A kind of driving method of display panel, multiple selector and display panel |
| CN108957814B (en) * | 2018-08-29 | 2021-08-13 | 南京京东方显示技术有限公司 | Liquid crystal display device and circuit compensation method |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100924143B1 (en) * | 2008-04-02 | 2009-10-28 | 삼성모바일디스플레이주식회사 | Flat Panel Display device and Driving method of the same |
| CN103366701A (en) * | 2012-08-06 | 2013-10-23 | 友达光电股份有限公司 | Display device with multiplexer feedthrough effect compensation framework and driving method thereof |
| CN103545343A (en) * | 2013-10-28 | 2014-01-29 | 深圳丹邦投资集团有限公司 | High-accuracy voltage programming pixel circuit and OLED displayer |
| CN103714784A (en) * | 2012-09-28 | 2014-04-09 | 乐金显示有限公司 | Liquid crystal display device including TFT compensation circuit |
| CN104167191A (en) * | 2014-07-04 | 2014-11-26 | 深圳市华星光电技术有限公司 | Complementary type GOA circuit used for flat display |
| CN104376814A (en) * | 2014-11-25 | 2015-02-25 | 上海天马微电子有限公司 | Drive circuit, drive method, display panel and display device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010061656A1 (en) * | 2008-11-28 | 2010-06-03 | シャープ株式会社 | Display device and method for driving the same |
-
2015
- 2015-07-30 CN CN201510458967.9A patent/CN104977768B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100924143B1 (en) * | 2008-04-02 | 2009-10-28 | 삼성모바일디스플레이주식회사 | Flat Panel Display device and Driving method of the same |
| CN103366701A (en) * | 2012-08-06 | 2013-10-23 | 友达光电股份有限公司 | Display device with multiplexer feedthrough effect compensation framework and driving method thereof |
| CN103714784A (en) * | 2012-09-28 | 2014-04-09 | 乐金显示有限公司 | Liquid crystal display device including TFT compensation circuit |
| CN103545343A (en) * | 2013-10-28 | 2014-01-29 | 深圳丹邦投资集团有限公司 | High-accuracy voltage programming pixel circuit and OLED displayer |
| CN104167191A (en) * | 2014-07-04 | 2014-11-26 | 深圳市华星光电技术有限公司 | Complementary type GOA circuit used for flat display |
| CN104376814A (en) * | 2014-11-25 | 2015-02-25 | 上海天马微电子有限公司 | Drive circuit, drive method, display panel and display device |
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