CN104952939A - Metal-insulator-metal capacitor structure - Google Patents
Metal-insulator-metal capacitor structure Download PDFInfo
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- CN104952939A CN104952939A CN201410114832.6A CN201410114832A CN104952939A CN 104952939 A CN104952939 A CN 104952939A CN 201410114832 A CN201410114832 A CN 201410114832A CN 104952939 A CN104952939 A CN 104952939A
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 24
- 239000002184 metal Substances 0.000 title claims abstract description 24
- 239000003990 capacitor Substances 0.000 title abstract description 10
- 239000004065 semiconductor Substances 0.000 claims description 10
- 241000276425 Xiphophorus maculatus Species 0.000 claims description 8
- 239000010410 layer Substances 0.000 abstract description 81
- 239000011229 interlayer Substances 0.000 abstract description 18
- 238000000034 method Methods 0.000 description 21
- 239000010949 copper Substances 0.000 description 19
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 17
- 229910052802 copper Inorganic materials 0.000 description 17
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 15
- 239000000463 material Substances 0.000 description 15
- 230000004888 barrier function Effects 0.000 description 13
- 238000009413 insulation Methods 0.000 description 13
- 238000009792 diffusion process Methods 0.000 description 10
- 238000009826 distribution Methods 0.000 description 9
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 7
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 6
- 239000006117 anti-reflective coating Substances 0.000 description 6
- 229910052799 carbon Inorganic materials 0.000 description 6
- 150000004767 nitrides Chemical class 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000009713 electroplating Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 239000011810 insulating material Substances 0.000 description 5
- 239000007769 metal material Substances 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 230000007547 defect Effects 0.000 description 4
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 229910052731 fluorine Inorganic materials 0.000 description 3
- 239000011737 fluorine Substances 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 239000000654 additive Substances 0.000 description 2
- 230000000996 additive effect Effects 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 238000009718 spray deposition Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
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- 230000004069 differentiation Effects 0.000 description 1
- 239000003792 electrolyte Substances 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000003112 inhibitor Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors having potential barriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention relates to a metal-insulator-metal capacitor structure. The metal-insulator-metal capacitor structure includes an upper pole plate, a lower pole plate and electric medium disposed between the upper pole plate and the lower pole plate. The upper pole plate and the lower pole plate are each of a non-planar plate structure having a plurality of parts arranged in a spaced manner. The capacitor structure adopts a metal-insulator-metal layer structure. In the metal-insulator-metal layer structure, the upper pole plate and the lower pole plate do not adopt large-area plate structures and are formed by mutual connection of the different parts, so that hill-shaped projection is avoided when a dielectric layer is formed above the capacitor structure. Besides, the parts are arranged in a spaced manner, so that no bosses are formed when the interlayer dielectric layer is formed above the capacitor structure and no pits are formed when a through hole or other patterns are formed. Therefore, device yield can be improved.
Description
Technical field
The present invention relates to semiconductor applications, particularly, the present invention relates to a kind of metal-insulator-metal type capacitance structure.
Background technology
Along with the increase day by day of the semiconductor storage demand for high power capacity, the integration density of semiconductor storage receives the concern of people, in order to increase the integration density of semiconductor storage, have employed many diverse ways in prior art, such as by reducing wafer size and/or changing inner structure unit and form multiple memory cell on single wafer, changing for passing through the method that cellular construction increases integration density, having carried out attempting ditch and having reduced cellar area by the floor plan or change cell layout changing active area.
Along with the development integrated circuit of semiconductor technology and large-scale integrated circuit are widely used, can be passive or active in the components and parts of composition integrated circuit, integrated passive devices (integrated passive device is become when described components and parts are passive device, IPD), IPD provides the integrated of the passive device such as high-accuracy capacitor and high-performance inductance, and the application at present on radio frequency becomes new focus.
Described passive device comprises metal-insulating layer-metal capacitor, metal-insulating layer-metal capacitor is due to its superior performance, in increasing application and IC, metal-insulating layer-metal capacitor structure described in the prior art as shown in Figure 1a, described structure comprises metal level 101-insulating barrier 102-metal level 103, wherein because described metal-insulator-metal electric capacity has larger metal pattern, mountain ridge (hill-shape) can be formed above described electric capacity form dielectric layer 104 planarization above electric capacity after, as shown in Figure 1 b, because described mountain ridge is difficult to form smooth photoetching agent pattern up, and then produce the defective through hole of a large amount of tool, as shown in Figure 2.
Therefore, the electric capacity of metal-insulator-metal described in prior art is larger area and flat distribution, cause and easily form projection in subsequent steps, affect through hole and other processing steps, the yield of device is caused to reduce, so need to be improved further, to eliminate the problems referred to above the structure of the electric capacity of metal-insulator-metal described in prior art.
Summary of the invention
In summary of the invention part, introduce the concept of a series of reduced form, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that the key feature and essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range attempting to determine technical scheme required for protection.
The present invention is in order to overcome current existing problems, provide a kind of metal-insulator-metal type capacitance structure, comprise top crown, bottom crown and the dielectric between described top crown and described bottom crown, wherein said top crown and described bottom crown are the on-plane surface platy structure with multiple intervals setting unit.
As preferably, described top crown and described bottom crown include some mutually nested circuluses, and wherein said some circulus intervals are arranged, and are connected as one by level connection joint end.
As preferably, described top crown and described bottom crown all select planar spiral structures.
As preferably, described top crown and described bottom crown are all in herring-bone form structure.
As preferably, described herring-bone form structure comprises axis and is positioned at some branches of described axis both sides.
As preferably, some branches correspondence of described axis both sides is arranged, and wherein described some branches interval of every side is arranged.
As preferably, described capacitance structure also comprises through hole and lower through-hole further, and wherein said upper through hole is connected with described top crown, and described lower through-hole is connected with described bottom crown.
As preferably, Ni metal selected by described top crown and described bottom crown;
Described dielectric selects SiN.
Present invention also offers a kind of semiconductor device, described semiconductor device comprises above-mentioned capacitance structure.
The present invention is in order to solve problems of the prior art, provide a kind of capacitance structure, comprise top crown, bottom crown and the dielectric between described top crown and described bottom crown, wherein said top crown and described bottom crown complete section figure are vertically some spaced square structures.
Wherein said capacitance structure selects the structure of metal-insulator-metal, described in described structure, large-area platy structure no longer selected by top crown and described bottom crown, but be interconnected by multiple part and form, thus avoid the problem forming mountain ridge projections (hill-shape) when to form dielectric layer above described electric capacity, and spaced setting between described multiple part, projection can not be formed when forming interlayer dielectric layer above described capacitance structure, defect can not be caused when forming through hole or other patterns, the yield of device can be improved.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining device of the present invention and principle.In the accompanying drawings,
Fig. 1 a-1b is the structural representation of capacitance structure described in prior art;
Fig. 2 is for producing the SEM figure of defect when forming through hole above capacitance structure described in prior art;
The perspective view that Fig. 3 a-3f is capacitance structure described in the specific embodiment of the present invention and cutaway view.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it is obvious to the skilled person that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
Should be understood that, the present invention can implement in different forms, and should not be interpreted as the embodiment that is confined to propose here.On the contrary, provide these embodiments will expose thoroughly with complete, and scope of the present invention is fully passed to those skilled in the art.In the accompanying drawings, in order to clear, the size in Ceng He district and relative size may be exaggerated.Same reference numerals represents identical element from start to finish.
Be understood that, when element or layer be called as " ... on ", " with ... adjacent ", " being connected to " or " being coupled to " other element or layer time, its can directly on other element or layer, with it adjacent, connect or be coupled to other element or layer, or the element that can exist between two parties or layer.On the contrary, when element be called as " directly exist ... on ", " with ... direct neighbor ", " being directly connected to " or " being directly coupled to " other element or layer time, then there is not element between two parties or layer.Although it should be understood that and term first, second, third, etc. can be used to describe various element, parts, district, floor and/or part, these elements, parts, district, floor and/or part should not limited by these terms.These terms be only used for differentiation element, parts, district, floor or part and another element, parts, district, floor or part.Therefore, do not departing under the present invention's instruction, the first element discussed below, parts, district, floor or part can be expressed as the second element, parts, district, floor or part.
Spatial relationship term such as " ... under ", " ... below ", " below ", " ... under ", " ... on ", " above " etc., here can be used thus the relation of the element of shown in description figure or feature and other element or feature for convenience of description.It should be understood that except the orientation shown in figure, spatial relationship term intention also comprises the different orientation of the device in using and operating.Such as, if the device upset in accompanying drawing, then, be described as " below other element " or " under it " or " under it " element or feature will be oriented to other element or feature " on ".Therefore, exemplary term " ... below " and " ... under " upper and lower two orientations can be comprised.Device can additionally orientation (90-degree rotation or other orientation) and as used herein spatial description language correspondingly explained.
The object of term is only to describe specific embodiment and not as restriction of the present invention as used herein.When this uses, " one ", " one " and " described/to be somebody's turn to do " of singulative is also intended to comprise plural form, unless context is known point out other mode.It is also to be understood that term " composition " and/or " comprising ", when using in this specification, determine the existence of described feature, integer, step, operation, element and/or parts, but do not get rid of one or more other feature, integer, step, operation, element, the existence of parts and/or group or interpolation.When this uses, term "and/or" comprises any of relevant Listed Items and all combinations.
Here with reference to the cross-sectional view as the schematic diagram of desirable embodiment of the present invention (and intermediate structure), inventive embodiment is described.Like this, it is expected to the change from shown shape because such as manufacturing technology and/or tolerance cause.Therefore, embodiments of the invention should not be confined to the given shape in district shown here, but comprise owing to such as manufacturing the form variations caused.Such as, the injection region being shown as rectangle has round or bending features and/or implantation concentration gradient usually at its edge, instead of the binary from injection region to non-injection regions changes.Equally, by inject formed disposal area this disposal area and injection can be caused to carry out time process surface between district some inject.Therefore, the district shown in figure is in fact schematic, and their shape is not intended the true form in the district of display device and is not intended to limit scope of the present invention.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, to explain the technical scheme of the present invention's proposition.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
The present invention is in order to solve problems of the prior art, provide a kind of capacitance structure, comprise top crown, bottom crown and the dielectric between described top crown and described bottom crown, wherein said top crown and described bottom crown are the on-plane surface platy structure with multiple intervals setting unit.
Wherein said capacitance structure selects the structure of metal-insulator-metal, described in described structure, large-area platy structure no longer selected by top crown and described bottom crown, but be interconnected by multiple part and form, thus avoid the problem forming mountain ridge projections (hill-shape) when to form dielectric layer above described electric capacity, and spaced setting between described multiple part, top crown and the bottom crown of capacitance structure described in the cutaway view therefore obtained after vertically carrying out cutting to described capacitance structure are discontinuous square structure.
In the present invention because the platy structure of continuous print, larger area no longer selected by the top crown in described capacitance structure and described bottom crown, but select the spaced part of tool each other, projection can not be formed when therefore forming interlayer dielectric layer above described capacitance structure, can not defect be caused when forming through hole or other patterns, the yield of device can be improved.
Wherein, described top crown and described bottom crown can select helical form, mutually nested circular or herring-bone form, described in cited structure, top crown and bottom crown include some mutually isolated parts, its profile is then the square structure of spaced setting, it should be noted that the structure that can meet above-mentioned requirements is not limited to cited shape.Respectively the structure of described helical form, mutually nested circular or herring-bone form is described further below in conjunction with accompanying drawing.
Embodiment 1
As shown in Figure 3 a-3b, wherein said Fig. 3 a for the generalized section of capacitance structure described in this embodiment, described section be the generalized section on vertical direction, wherein Fig. 3 b is the perspective view of described capacitance structure.
As shown in Figure 3 b, described top crown 204 and described bottom crown 205 all select metal material, and described metal material can select copper, gold, silver, tungsten and other similar materials, and preferable alloy copper is as described top crown 204 and described bottom crown 205.
Dielectric is formed between wherein said top crown and described bottom crown, wherein said dielectric selects insulating material, such as oxide skin(coating) or nitride layer, be preferably nitride layer in this embodiment, such as SiN layer, but be not limited to described material, other conventional insulating material of this area can also be selected.
Wherein, described capacitance structure is formed in described interlayer dielectric layer 201, and described interlayer dielectric layer 201 can use such as SiO
2, fluorocarbon (CF), carbon doped silicon oxide (SiOC) or carbonitride of silicium (SiCN) etc.Or, also can be used in the film etc. fluorocarbon (CF) defining SiCN film.Fluorocarbon with fluorine (F) and carbon (C) for main component.Fluorocarbon also can use the material having noncrystal (amorphism) and construct.
In this embodiment, described top crown 204 and described bottom crown 205 all select planar spiral structures, and as shown in Figure 3 b, as preferably, wherein said top crown 204 and described bottom crown 205 have identical structure, and upper and lower corresponding setting.
Wherein, described top crown 204 and described bottom crown 205 are plane and arrange, and described helical structure has two ends, are respectively the one end being positioned at described helical structure inside and the one end being positioned at outside, and one end of wherein said outside is used for time electrical connection.
As preferably, in this embodiment, be positioned at outside one end in wherein said top crown 204 and be connected with upper through hole 202, realized the electrical connection of described top crown 204 by described upper through hole.
Be positioned at outside one end in same described bottom crown 205 to be connected with lower through-hole 203, realized the electrical connection of described bottom crown 205 by described lower through-hole.
Further, the distance between described top crown and described bottom crown, and described top crown and the spiral-shaped size of bottom crown all can be arranged according to specific needs, do not limit to a certain number range or shape.
Wherein, Fig. 3 a is the generalized section of capacitance structure described in this embodiment, described section is the generalized section on vertical direction, the profile of wherein said top crown and described bottom crown is the square structure of spaced setting, to avoid the formation of described mountain ridge projections (hill-shape).
Embodiment 2
As shown in Fig. 3 c-3d, wherein said Fig. 3 c for the generalized section of capacitance structure described in this embodiment, described section be the generalized section on vertical direction, wherein Fig. 3 d is the perspective view of described capacitance structure.
As shown in Figure 3 d, described top crown 204 and described bottom crown 205 all select metal material, and described metal material can select copper, gold, silver, tungsten and other similar materials, and preferable alloy copper is as described top crown 204 and described bottom crown 205.
Dielectric is formed between wherein said top crown and described bottom crown, wherein said dielectric selects insulating material, such as oxide skin(coating) or nitride layer, be preferably nitride layer in this embodiment, such as SiN layer, but be not limited to described material, other conventional insulating material of this area can also be selected.
Wherein, described capacitance structure is formed in described interlayer dielectric layer 201, and described interlayer dielectric layer 201 can use such as SiO
2, fluorocarbon (CF), carbon doped silicon oxide (SiOC) or carbonitride of silicium (SiCN) etc.Or, also can be used in the film etc. fluorocarbon (CF) defining SiCN film.Fluorocarbon with fluorine (F) and carbon (C) for main component.Fluorocarbon also can use the material having noncrystal (amorphism) and construct.
In this embodiment, herring-bone form structure all selected by described top crown 204 and described bottom crown 205.
Wherein, include an axis 207 in described top crown 204 and described bottom crown 205, lay respectively at the middle part of described top crown 204 and described bottom crown 205, be preferably positioned at the centre of top crown 204 and described bottom crown 205.
Wherein said axis 207 is a bonding jumper or metallic plate, wherein the both sides of described axis 207 is provided with some branches 206, and described some branches 206 of both sides are mutually corresponding to be arranged.
The wherein spaced setting of described some branches of every side, to be evenly distributed on described axis on 207, wherein said branch non-perpendicular to described axis, but with described axis, there is certain angle, described angle is less than 90 °, be preferably 45-60 °, but be not limited to this number range, can arrange according to concrete needs.
In addition, the distance between described branch, and the length of described branch is all not limited to a certain number range, can arrange as required.
In addition, described top crown 204 is connected with upper through hole 202 by the axis being positioned at top, is realized the electrical connection of described top crown 204 by described upper through hole.
Axis by being positioned at below in same described bottom crown 205 is connected with lower through-hole 203, is realized the electrical connection of described bottom crown 205 by described lower through-hole.
Further, the distance between described top crown and described bottom crown, and described top crown and the spiral-shaped size of bottom crown all can be arranged according to specific needs, do not limit to a certain number range or shape.
Wherein, Fig. 3 c is the generalized section of capacitance structure described in this embodiment, described section is the generalized section on vertical direction, the profile of wherein said top crown and described bottom crown is the square structure of spaced setting, to avoid the formation of described mountain ridge projections (hill-shape).
Embodiment 3
Wherein said top crown 204 and described bottom crown 205, described electrolyte and the material selected by described interlayer dielectric layer 201 all can with reference to embodiment 1 or embodiments 2, do not repeat them here, carry out introduction emphatically below in conjunction with the structure of accompanying drawing 3e-3f to described top crown and described bottom crown.
As illustrated in figure 3f, described top crown 204 and described bottom crown 205 all select circulus, and it is mutually nested together that wherein said top crown 204 and described bottom crown 205 include some circuluses.
As preferably, wherein said circulus can be selected circular, or the mechanism of similar annulus, such as oval or other shapes, polygon can also be selected in an embodiment of the present invention mutually nested, the polygonal structure of such as square, rectangle or rule is mutually nested, is not limited to a certain.
Wherein said circulus has certain width, and the distance of the width of described circulus and inside and outside circulus centre, is not limited to a certain number range.
Wherein said inside and outside nested circulus is interconnected by level connection joint end 208, and to form described top crown 204 and described bottom crown 205, wherein said level connection joint end 208 is platy structure.
As preferably, described top crown is connected with upper through hole 202 by the level connection joint end being positioned at top, is realized the electrical connection of described top crown 204 by described upper through hole.
Level connection joint end by being positioned at below in same described bottom crown 205 is connected with lower through-hole 203, is realized the electrical connection of described bottom crown 205 by described lower through-hole.
Wherein, Fig. 3 e is the generalized section of capacitance structure described in this embodiment, described section is the generalized section on vertical direction, the profile of wherein said top crown and described bottom crown is the square structure of spaced setting, to avoid the formation of described mountain ridge projections (hill-shape).
Embodiment 4
Present invention also offers a kind of preparation method of described capacitance structure, comprise particularly:
Step 201 provides substrate, and described substrate forms interlayer dielectric layer.
Particularly, described substrate can be formed with active device or passive device, kind and the formation method of described active device and passive device do not repeat them here.
Be formed with interlayer dielectric layer on the substrate, described interlayer dielectric layer can use such as SiO
2, fluorocarbon (CF), carbon doped silicon oxide (SiOC) or carbonitride of silicium (SiCN) etc.Or, also can be used in the film etc. fluorocarbon (CF) defining SiCN film.Fluorocarbon with fluorine (F) and carbon (C) for main component.Fluorocarbon also can use the material having noncrystal (amorphism) and construct.
Perform step 202, described interlayer dielectric layer forms bottom through-hole.
Particularly, first on described interlayer dielectric layer, form photoresist layer or organic distribution layer (Organic distribution layer of patterning, ODL), siliceous bottom antireflective coating (Si-BARC) and be positioned at the photoresist layer (not shown) of patterning at top, the position of the described bottom through-hole opening of the pattern definition on wherein said photoresist and size, then with described photoresist layer for mask layer etching described organic distribution layer, bottom antireflective coating forms the pattern of groove, then with described organic distribution layer, bottom antireflective coating is mask, etch described interlayer dielectric layer, to form described bottom through-hole opening.
Further, described bottom through-hole opening can select common shape, the conventional trench that the critical size of such as upper and lower opening is the same, or can also select groove wide at the top and narrow at the bottom, is not limited to a certain shape, can arranges as required.
Particularly, select dry etching or wet etching in this step, preferably C-F etchant etches described Semiconductor substrate in the present invention, and described C-F etchant is CF
4, CHF
3, C
4f
8and C
5f
8in one or more.In this embodiment, described dry etching can select CF
4, CHF
3, add N in addition
2, CO
2in one as etching atmosphere, wherein gas flow is CF
410-200sccm, CHF
310-200sccm, N
2or CO
2or O
210-400sccm, described etching pressure is 30-150mTorr, and etching period is 5-120s, is preferably 5-60s, is more preferably 5-30s.
Then in described bottom through-hole opening filled conductive material planarization to form bottom through-hole.
Particularly, first diffusion impervious layer (barrier) (not shown) is formed in the trench in this step, be preferably formed copper diffusion barrier layer, the formation method of described copper diffusion barrier layer can for mainly to select physical vaporous deposition and chemical vapour deposition technique, particularly, can select evaporation, electron beam evaporation, plasma spray deposition and sputtering, preferably plasma spray deposition and sputtering method form described copper diffusion barrier layer in the present invention.The thickness of described copper diffusion barrier layer is not limited in a certain numerical value or scope, can adjust as required.
As preferably, described diffusion barrier material can one or more for being selected from TaN, Ta, TiN, Ti, reduce the RC delay time because dead resistance and parasitic capacitance cause.
Then in the first Seed Layer of plated metal copper on described diffusion impervious layer, the deposition process of described Seed Layer can select chemical vapor deposition (CVD) method, physical vapor deposition (PVD) method or ald (ALD) method etc.
Then select the method for Cu electroplating (ECP) to form described metallic copper, as preferably, can also use additive when electroplating, described additive is smooth dose (LEVELER), accelerator (ACCELERATORE) and inhibitor (SUPPRESSOR).
As preferably, forming the step that can also comprise annealing after described metallic copper is formed further, annealing can carry out 2-4 hour at 80-160 DEG C, to impel copper crystallization again, crystal grain of growing up, reduces resistance and improves stability.
Then metallic copper material described in planarization is to described interlayer dielectric layer, to form bottom through-hole, described interlayer dielectric layer as the stop-layer in planarisation step, to prevent from causing corrosion to metal material layer in this planarization process.
Perform step 203, above described interlayer dielectric layer and described bottom through-hole, form bottom insulation layer.
Wherein, described bottom insulation layer can select oxide skin(coating) or nitride layer, is preferably nitride layer, such as SiN layer in this embodiment, but is not limited to described material, can also select other conventional insulating material of this area.
Perform step 204, in described bottom insulation layer, form bottom crown.
Particularly, first in described bottom insulation layer, form photoresist layer or organic distribution layer (Organic distribution layer of patterning, ODL), siliceous bottom antireflective coating (Si-BARC) and be positioned at the photoresist layer (not shown) of patterning at top, pattern definition on the wherein said photoresist pattern of described bottom crown, then with described photoresist layer for mask layer etching described organic distribution layer, bottom antireflective coating forms the pattern of bottom crown, then with described organic distribution layer, bottom antireflective coating is mask, etch described bottom insulation layer, to form the pattern of described bottom crown.
Wherein, the one in embodiment 1-3 selected by described bottom crown pattern.
Then in the described bottom crown pattern of described bottom insulation layer, diffusion impervious layer (barrier) (not shown) is formed, be preferably formed copper diffusion barrier layer, then in the first Seed Layer of plated metal copper on described diffusion impervious layer, the deposition process of described Seed Layer can select chemical vapor deposition (CVD) method, physical vapor deposition (PVD) method or ald (ALD) method etc.
Then the method for Cu electroplating (ECP) is selected to form described metallic copper.As preferably, forming the step that can also comprise annealing after described metallic copper is formed further.
Perform step 205, deposition middle part insulating barrier in described bottom insulation layer and described bottom crown.
As preferably, described middle part insulating barrier selects the material identical with described bottom insulation layer, but is not limited to described material, and described middle part insulating barrier is used as the dielectric of described capacitance structure.
Perform step 206, in described middle part insulating barrier disposed thereon upper insulation layer, and form top crown in described upper insulation layer.
Described upper insulation layer selects the material identical with described bottom insulation layer, but is not limited to described material.
The method forming top crown in described upper insulation layer can with reference to the method forming bottom crown, do not repeat them here, but it should be noted that the formation method of described top crown is not limited to the method, those skilled in the art can also select other conventional methods.
Perform step 207, formed above described top crown described on through hole.
Concrete grammar with reference to the method forming lower through-hole, can not repeat them here, but it should be noted that the formation method of described upper through hole is not limited to the method, and those skilled in the art can also select other conventional methods.
Capacitance structure of the present invention, comprise top crown, bottom crown and the dielectric between described top crown and described bottom crown, large-area platy structure no longer selected by described top crown and described bottom crown, but be interconnected by multiple part and form, thus avoid the problem forming mountain ridge projections (hill-shape) when to form dielectric layer above described electric capacity, and spaced setting between described multiple part, projection can not be formed when forming interlayer dielectric layer above described capacitance structure, defect can not be caused when forming through hole or other patterns, the yield of device can be improved.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.
Claims (9)
1. a metal-insulator-metal type capacitance structure, comprises top crown, bottom crown and the dielectric between described top crown and described bottom crown, and wherein said top crown and described bottom crown are the on-plane surface platy structure with multiple intervals setting unit.
2. capacitance structure according to claim 1, is characterized in that, described top crown and described bottom crown include some mutually nested circuluses, and wherein said some circulus intervals are arranged, and are connected as one by level connection joint end.
3. capacitance structure according to claim 1, is characterized in that, described top crown and described bottom crown all select planar spiral structures.
4. capacitance structure according to claim 1, is characterized in that, described top crown and described bottom crown are all in herring-bone form structure.
5. capacitance structure according to claim 4, is characterized in that, described herring-bone form structure comprises axis and is positioned at some branches of described axis both sides.
6. capacitance structure according to claim 5, is characterized in that, some branches correspondence of described axis both sides is arranged, and wherein described some branches interval of every side is arranged.
7. capacitance structure according to claim 1, is characterized in that, described capacitance structure also comprises through hole and lower through-hole further, and wherein said upper through hole is connected with described top crown, and described lower through-hole is connected with described bottom crown.
8. capacitance structure according to claim 1, is characterized in that, Ni metal selected by described top crown and described bottom crown;
Described dielectric selects SiN.
9. a semiconductor device, described semiconductor device comprises the described capacitance structure of one of claim 1 to 8.
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| CN107275313A (en) * | 2016-03-31 | 2017-10-20 | 台湾积体电路制造股份有限公司 | The capacitor arrangement and its manufacture method of IC chip |
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| CN103311218A (en) * | 2012-03-02 | 2013-09-18 | 台湾积体电路制造股份有限公司 | Structure and method for a fishbone differential capacitor |
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| JP2007134482A (en) * | 2005-11-10 | 2007-05-31 | Toppan Printing Co Ltd | Thin film transistor device, its manufacturing method, thin film transistor array using the same and thin film transistor display |
| CN101916759A (en) * | 2008-12-03 | 2010-12-15 | 恩益禧电子股份有限公司 | Semiconductor device and method of manufacturing the same |
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