CN104952886B - Insulating barrier covers silicon structure and preparation method thereof - Google Patents

Insulating barrier covers silicon structure and preparation method thereof Download PDF

Info

Publication number
CN104952886B
CN104952886B CN201510325062.4A CN201510325062A CN104952886B CN 104952886 B CN104952886 B CN 104952886B CN 201510325062 A CN201510325062 A CN 201510325062A CN 104952886 B CN104952886 B CN 104952886B
Authority
CN
China
Prior art keywords
insulating barrier
basic unit
opening
insulation system
covers
Prior art date
Application number
CN201510325062.4A
Other languages
Chinese (zh)
Other versions
CN104952886A (en
Inventor
吴孝哲
Original Assignee
江苏时代全芯存储科技有限公司
江苏时代芯存半导体有限公司
英属维京群岛商时代全芯科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 江苏时代全芯存储科技有限公司, 江苏时代芯存半导体有限公司, 英属维京群岛商时代全芯科技有限公司 filed Critical 江苏时代全芯存储科技有限公司
Priority to CN201510325062.4A priority Critical patent/CN104952886B/en
Publication of CN104952886A publication Critical patent/CN104952886A/en
Application granted granted Critical
Publication of CN104952886B publication Critical patent/CN104952886B/en

Links

Abstract

The invention discloses a kind of insulating barrier to cover silicon structure and preparation method thereof.Insulating barrier covers silicon structure and includes a bottom, an insulating barrier, an active layers and a barrier layer.Insulating barrier is located on bottom, and active layers are embedded in insulating barrier.Barrier layer is then located in insulating barrier and around active layers.

Description

Insulating barrier covers silicon structure and preparation method thereof

Technical field

The present invention is that a kind of relevant insulating barrier covers silicon structure and preparation method thereof.

Background technology

Semiconductor industry undergoes the growth of high speed.The technological progress of the material and design aspect of integrated circuit has been created several The integrated circuit of generation, the integrated circuit per a generation all have circuit smaller than prior-generation and more complicated.Drilled in integrated circuit During entering, feature structure density (that is, the number for the element being connected with each other in every chip area) is generally with dimensioning The diminution of very little (that is, the producible minimal modules of used manufacture method or circuit) and increase.The system of this size reduction Journey will the advantages of be improve production efficiency and reduce relevant cost.

Also the complexity of integrated circuit is processed and manufactured in lifting simultaneously for the reduction of size, in order to realize these progress, is being collected Similar development is needed into circuit fabrication and manufacture view.Wherein insulating barrier, which covers silicon structure, has the transistor of preparation thereon The advantages of operating quick, low power consumption, low soft error, locking suppression (latch-up immunity), and it is widely used in half Conductor industry.Tradition, which prepares insulating barrier, to be covered the mode of silicon structure and includes oxonium ion implantation silicon wafer isolation method (separation by Implantation of oxygen, SIMOX) (bonding) mode is bonded with wafer.Oxonium ion implantation silicon wafer isolation method be by Oxonium ion is got in wafer in a manner of high-energy, oxonium ion is distributed in below silicon wafer surface, is then moved back via high temperature Fiery (anneal) in wafer to form oxide layer.Wafer fitting (bonding) mode then generally need to first prepare an element wafer (device wafer) and operation wafer (handle wafer), formation oxide layer is followed by element wafer or operation wafer Both are closed, and removes operation wafer by way of cutting off, grinding or etch again.However, above-mentioned two ways generally existing The problem of oxidated layer thickness is excessively thin, and processing procedure is complicated and Expenses Cost.Accordingly, industry needs a kind of novel mode badly to prepare absolutely Edge layer covers silicon structure.

The content of the invention

It is an aspect of the present invention to provide a kind of insulating barrier to cover silicon structure, comprising a bottom, an insulating barrier, an active layers with One barrier layer.Insulating barrier is located on bottom, and active layers are embedded in insulating barrier.Barrier layer is then located in insulating barrier and around actively Layer.

According to one or more embodiments of the invention, insulating barrier includes one first insulation system and one second insulation system. First insulation system contacts active layers, and a Part II position between bottom and active layers, and comprising a Part I Between bottom and Part I, and the width of Part II is less than the width of active layers.Second insulation system is then located at bottom On, and around active layers and the first insulation system.

According to one or more embodiments of the invention, the first insulation system is with different material institutes from the second insulation system Composition.

According to one or more of the invention embodiments, ratio between the width of Part II and the width of active layers between Between 0.2 to 0.5.

Another aspect of the present invention is to provide the preparation method that a kind of insulating barrier covers silicon structure, comprises the steps of.First cover The hard cover screen of lid one first removes the first hard cover screen and the basic unit of part in a basic unit, to form one first opening exposure base Layer.The side wall of the opening of barrier layer covering first is subsequently formed, more removes the part basic unit in the first opening, to form one second Opening.Tropism removes the basic unit in the second opening afterwards etc., to form basic unit's bridge part, and aoxidizes basic unit's bridge part To form one first insulation system.One second insulation system is eventually formed in the second opening.

According to one or more embodiments of the invention, the side wall for forming the opening of barrier layer covering first comprises the steps of. It is initially formed one second hard cover screen and conformally covers side wall and the bottom of the first hard cover screen and the first opening, and removes the first opening Second hard cover screen of bottom.

It is exhausted to form first with wet oxidation processing procedure oxidation basic unit's bridge part according to one or more embodiments of the invention Edge structure, and the temperature of wet oxidation processing procedure is more than 1000 DEG C.

It is to be removed with tropisms such as a wet etching processing procedures in the second opening according to one or more embodiments of the invention Basic unit.

According to one or more embodiments of the invention, after the second insulation system is formed in second opening, also include The following steps.Remove the first hard cover screen, and the second insulation system of grinding.

It is with spin coating, physical vapour deposition (PVD), chemical vapor deposition or atomic layer according to one or more embodiments of the invention Deposition forms second insulation system in second opening.

Brief description of the drawings

For allow the present invention above and other purpose, feature, advantage and embodiment can become apparent, appended accompanying drawing it is detailed Carefully it is described as follows:

Figure 1A, Fig. 2A, Fig. 3 A, Fig. 4 A, Fig. 5 A, Fig. 6 A, Fig. 7 A and Fig. 8 A illustrate insulating barrier, and to cover silicon structure each in processing procedure The top view in stage;

Figure 1B, Fig. 2 B, Fig. 3 B, Fig. 4 B, Fig. 5 B, Fig. 6 B, Fig. 7 B and Fig. 8 B are respectively Figure 1A, Fig. 2A, Fig. 3 A, Fig. 4 A, figure 5A, Fig. 6 A, Fig. 7 A and profiles of Fig. 8 A along AA hatching lines;And

Fig. 1 C, Fig. 2 C, Fig. 3 C, Fig. 4 C, Fig. 5 C, Fig. 6 C, Fig. 7 C and Fig. 8 C are respectively Figure 1A, Fig. 2A, Fig. 3 A, Fig. 4 A, figure 5A, Fig. 6 A, Fig. 7 A and profiles of Fig. 8 A along BB hatching lines.

Embodiment

Multiple embodiments of the present invention, as clearly stated, the details in many practices will be disclosed with accompanying drawing below It will be explained in the following description.It should be appreciated, however, that the details in these practices is not applied to limit the present invention.Also It is to say, in some embodiments of the present invention, the details in these practices is non-essential.In addition, for the sake of simplifying accompanying drawing, one A little known usual structures will be illustrated in a manner of simply illustrating in the accompanying drawings with element.

Figure 1A to Fig. 8 A, Figure 1B to Fig. 8 B are referred to Fig. 1 C to Fig. 8 C to understand that the insulating barrier of the present invention covers silicon structure Preparation method.Figure 1A, Fig. 2A, Fig. 3 A, Fig. 4 A, Fig. 5 A, Fig. 6 A, Fig. 7 A and Fig. 8 A illustrate insulating barrier, and to cover silicon structure each in processing procedure Top view, Figure 1B, Fig. 2 B, Fig. 3 B, Fig. 4 B, Fig. 5 B, Fig. 6 B, Fig. 7 B and Fig. 8 B in stage are respectively Figure 1A, Fig. 2A, Fig. 3 A, figure Profile along AA hatching lines of 4A, Fig. 5 A, Fig. 6 A, Fig. 7 A and Fig. 8 A and Fig. 1 C, Fig. 2 C, Fig. 3 C, Fig. 4 C, Fig. 5 C, Fig. 6 C, figure 7C and Fig. 8 C are respectively Figure 1A, Fig. 2A, Fig. 3 A, Fig. 4 A, Fig. 5 A, Fig. 6 A, Fig. 7 A and profiles of Fig. 8 A along BB hatching lines.Scheming In 1A to Fig. 8 A, AA hatching lines are substantially vertical with BB hatching lines.

As shown in Figure 1A to Fig. 1 C, one first hard cover screen 120 is initially formed in a basic unit 110.Form the first hard cover screen 120 Mode may be, for example, physical vapour deposition (PVD), chemical vapor deposition or ald.In the section Example of the present invention, base The material of layer 110 includes silicon or other semiconductor elements, such as germanium or iii-v element, but is not limited.In the portion of the present invention It is first to deposit an oxide layer to basic unit 110 in point embodiment, redeposited first hard cover screen 120 is in oxide layer, to form oxygen Change layer between the hard cover screen 120 of basic unit 110 and first.In the other parts embodiment of the present invention, the mode of oxide layer is formed May be, for example, physical vapour deposition (PVD), chemical vapor deposition or ald.In the other parts embodiment of the present invention, oxidation Layer is the native oxide of basic unit 110, it is not necessary to is formed with additional step.In the section Example of the present invention, the first hard cover screen 120 material includes silicon nitride, silicon oxynitride, carborundum, or other suitable materials.

With continued reference to Fig. 2A to Fig. 2 C, the first hard cover screen 120 and the basic unit 110 of part are removed, is open with forming one first 130 exposure basic units 110.In this step, it is that photoresist layer (is not first illustrated into) rotary coating to the first hard cover screen 120, then profit The pattern of one light shield (not illustrating) is transferred on photoresist layer with exposure imaging, with the first hard cover screen 120 of expose portion.Finally Using dry ecthing or wet etching processing procedure, to remove the first hard cover screen 120 and the basic unit 110 of part of part by photoresist layer, and Form the first opening 130.And side wall and bottom of the partial basic unit 110 exposed to this first opening 130.In the part of the present invention In embodiment, photoresist layer is removed after the first opening 130 is formed.

Referring next to Fig. 3 A to Fig. 3 C, one second hard cover screen 140 of formation conformally covers the first hard cover screen 120 and opened with first The side wall of mouth 130 and bottom.In this step, the second hard cover screen 140 is the upper surface for conformably covering the first hard cover screen 120, And first opening 130 side wall and bottom.And second hard cover screen 140 can be big in the thickness T2 of the side-walls of the first opening 130 In its thickness T1 on bottom of the upper surface of the first hard cover screen 120 with the first opening 130.It should be noted that this place The thickness stated is the thickness with basic unit 110 in vertical direction.In the section Example of the present invention, the second hard cover screen 140 is formed Mode may be, for example, physical vapour deposition (PVD), chemical vapor deposition or ald.In the section Example of the present invention, the The material of two hard cover screens 140 includes silicon nitride, silicon oxynitride, carborundum, or other suitable materials, and the first hard cover screen 120 Identical or different material can be selected with the second hard cover screen 140.

With continued reference to Fig. 4 A to Fig. 4 C, the bottom of the first opening 130 and the second hard cover screen on the first hard cover screen 120 are removed 140, so that basic unit 110 is exposed to the bottom of the first opening 130.In this step, be using an anisotropic etching processing procedure with The gradually hard cover screen 140 of abatement second and the thickness of basic unit 110 in vertical direction, with remove completely the bottom of the first opening 130 with The second hard cover screen 140 on first hard cover screen 120.However, positioned at first opening 130 side wall the second hard cover screen 140 because tool There is larger thickness without being completely removed, thus the side wall of the opening of covering first 130 can be formed from the second hard cover screen 140 Barrier layer 142.The present invention section Example in, be using a dry ecthing procedure with remove the bottom of the first opening 130 and The second hard cover screen 140 on first hard cover screen 120, the etching gas that dry ecthing procedure uses can include sulfur hexafluoride, helium, four Fluorocarbons, fluoroform, hydrogen bromide, chlorine, oxygen, nitrogen or its combination, but the present invention is not limited.

With continued reference to Fig. 5 A to Fig. 5 C, the part basic unit 110 in the first opening 140 is removed, to form one second opening 150, then etc. tropism remove the basic unit 110 in the second opening 150, to form basic unit's bridge part 160.Such as preceding institute State, basic unit 110 is exposed to the bottom of the first opening 140, and the side wall of the opening 140 of the covering of barrier layer 142 first is to protect part Basic unit 110 be not removed in follow-up processing procedure.First removed using dry ecthing or wet etching processing procedure exposed to the first opening 130 Bottom basic unit 110, with formed second opening 150 make basic unit 110 exposed to second opening 150 bottom and side-walls, it The basic unit 110 in the second opening 150 is removed with tropisms such as a wet etching processing procedures again afterwards.Etching solution can lateral etch exposure In the basic unit 110 of the side wall of the second opening 150, to form basic unit's bridge part 160, and in the same of the opening of lateral etch second 150 When etching solution can also etch the second opening 150 bottom basic unit 110.In the section Example of the present invention, wet etching processing procedure The etching solution used is potassium hydroxide, but is not limited.Other suitable etching solutions the tropism such as are used equally for remove being exposed to Basic unit 110 in second opening 150.

Fig. 5 C are referred to, when waiting tropism to remove exposed to the basic unit 110 of the side wall of the second opening 150, barrier layer 142 will Basic unit 110 on protecting grassroots level bridge part 160, is not removed it.Thereby, the width W1 of basic unit's bridge part 160 can be less than base The width W2 of basic unit 110 on layer bridge part 160.It should be specified herein, width W1 and W2 described herein is cutd open along BB The width in line direction.Enough bearing capacities can not be provided give basic unit thereon if the width W1 of basic unit's bridge part 160 is too small 110, but this width W2 is excessive and by the processing procedure after being unfavorable for, and it will be in subsequent detailed.In the section Example of the present invention, Ratio between the width W2 of basic unit 110 on the width W1 and basic unit's bridge part 160 of basic unit's bridge part 160 is between 0.2 to 0.5 Between, preferably 0.3.

Referring next to Fig. 6 A to Fig. 6 C, basic unit's bridge part 160 is aoxidized to form one first insulation system 172.In this step In, it is using wet oxidation processing procedure oxidation basic unit bridge part 160.Aqueous vapor is first passed through into the second opening 150, and improves temperature extremely More than 1000 DEG C so that hydrone resolves into hydrogen ion and hydroxide ion at high temperature.This little ion is from the second opening 150 Side-walls diffuse into basic unit's bridge part 160 and carry out oxidation reaction with basic unit bridge part 160, by the oxygen of basic unit's bridge part 160 It is melted into the first insulation system 172.The material of first insulation system 172 is the oxide of the material of basic unit 110, for example, when When the material of basic unit 110 is silicon (Si), it is silica that aqueous vapor can carry out oxidation reaction and form material with basic unit bridge part 160 First insulation system 172.

First hard cover screen 120 and barrier layer 142 can be on protecting grassroots level bridge part 160 basic unit 110 do not contacted with aqueous vapor and Oxidation.However, ion may proceed to diffuse in the basic unit 110 on basic unit's bridge part 160 and incites somebody to action after entrance basic unit bridge part 160 It is aoxidized.Similarly, in the basic unit 110 that ion also may proceed to diffuse under basic unit's bridge part 160 and it is oxidized.Such as Fig. 6 B and figure Shown in 6C, the basic unit 110 on basic unit's bridge part 160 is not fully oxidized, and a remaining active layers 112 are tied in into the first insulation On structure 172.Similarly, the basic unit 110 under basic unit's bridge part 160 is not also fully oxidized, and a remaining bottom 114 is in exhausted into first Under edge structure 172.On the other hand, because the width W1 of basic unit's bridge part 160 is less than the width of the basic unit 110 on basic unit's bridge part 160 W2 is spent, and the basic unit's bridge part 160 for making to expand after oxidation is not likely to produce stress extruding basic unit 110.

Referring next to Fig. 7 A to Fig. 7 C, one second insulation system 174 is formed in the second opening 150.In this step, it is Deposited in a manner of spin coating, physical vapour deposition (PVD), chemical vapor deposition or ald, such as:Spin-on glasses, silica, Silicon nitride, aluminum oxide and aluminium nitride are into the second opening 150, to form the around active layers 112 and first insulation systems 172 Two insulation systems 174.The present invention section Example in, be in a manner of ald deposition of aluminium oxide to second opening In 150, with the effective hole (void) for filling up the second opening 150, reducing in the second insulation system 174, and aluminum oxide has more There is preferable capacity of heat transmission.It is that spin-on glasses are filled in a manner of spin coating to extremely in the other parts embodiment of the present invention In second opening 150, spin-on glasses (spin-on glass) are liquid oxygen SiClxs, and it has mobility and flow to second and open Mouthfuls 150 to be fully filled with.The solvent in spin-on glasses is evaporated off at a temperature of 400~450 DEG C afterwards, to form second Insulation system 174.Hardly there is hole in the second insulation system 174 formed in a manner of spin coating, thus have and more preferably fill out Fill ability.

After the second insulation system 174 is formed, the first hard cover screen 120 in active layers 112, and partial barrier are more removed Layer 142 is also removed simultaneously.It is that the first hardcoat is removed with phosphoric acid or other suitable solution in the section Example of the present invention Curtain 120 and the barrier layer of part.Afterwards, the second insulation system 174 is more ground, a upper table of the second insulation system 174 is made with order Face and a upper surface of active layers 112 are copline.Wherein the first insulation system 172 collectively constitutes with the second insulation system 174 One insulating barrier 170 completes the preparation of silicon-on-insulator structure to isolate active layers 112 and basic unit 114.In the portion of the present invention Divide in embodiment, be with the insulation of chemical mechanical milling method (chemical mechanical polishing, CMP) grinding second Structure 174.

It can be learnt by above-mentioned step, the preparation method that insulating barrier provided by the invention covers silicon structure can be directly in single base Insulating barrier 170 is formed in layer 110 so that basic unit 110 is divided into active layers 112 and basic unit 114, and active layers 112 are embedded in insulating barrier In 170.Compared to prior art, the invention discloses processing procedure need to only use single base layer 110 to complete silicon-on-insulator The preparation of structure, therefore be not required to prepare extra basic unit, more avoid because cutting off, grinding or etch caused by this extra basic unit Active layers 112 in stress or high temperature failure silicon-on-insulator structure.On the other hand, the invention discloses processing procedure use in base The faster hydrogen ion of diffusion velocity and hydroxide ion are to carry out oxidation reaction in layer 110, and are not required to incite somebody to action in a manner of high energy Oxygen is implanted into basic unit 110, therefore further improves process efficiency.

Fig. 8 A to Fig. 8 C are finally referred to, are formed in a grid structure 180 to active layers 112.In this step, it is first heavy Product gate dielectric 182 covers active layers 112, and then redeposited gate electrode 184 is finally schemed again on gate dielectric 182 Case gate dielectric 182 and gate electrode 184 are to form grid structure 180 in active layers 112.Afterwards can doping grid again The active layers 112 of the both sides of electrode 180 are to form source region and drain region in active layers 112.It is real in the part of the present invention Apply in example, the mode for forming gate dielectric 182 and gate electrode 184 may be, for example, physical vapour deposition (PVD), chemical vapor deposition Or ald.In the other parts embodiment of the present invention, after being formed in grid structure 180 to active layers 112, more shape Into a clearance wall 190 in active layers 112, and grid structure 180 is located between two clearance walls 190.

Please continue to refer to Fig. 8 A to Fig. 8 C, Fig. 8 A illustrate a kind of insulating barrier in some embodiments of the present invention and cover silicon structure The insulating barrier that top view, Fig. 8 B illustrate Fig. 8 A covers profile of the silicon structure along AA hatching lines and Fig. 8 C illustrate Figure 1A insulating barrier Cover profile of the silicon structure along BB hatching lines.As shown in Fig. 8 A to Fig. 8 C, a kind of insulating barrier covers silicon structure 100 and includes a bottom 114th, an insulating barrier 170, an active layers 112 and a barrier layer 142.Insulating barrier 170 is located on bottom 114, and active layers 112 are embedding In insulating barrier 170, and barrier layer 142 is similarly positioned in insulating barrier 170 and surround active layers 112.Barrier layer 142 is from second Hard cover screen 140 is formed, and its material includes silicon nitride, silicon oxynitride, carborundum, or other suitable materials.In addition, around actively The barrier layer 142 of layer 112 more lifts the insulation effect of active layers 112.

As shown in Fig. 8 B and Fig. 8 C, insulating barrier 170 includes one first insulation system 172 and one second insulation system 174, the One insulation system 172 contacts active layers 112 between bottom 114 and active layers 112, and comprising a Part I 172a, with And one Part II 172b between bottom 114 and Part I 172a.Specifically, hydrogen ion and hydrogen in oxidizing process Oxygen radical ion diffuses into the Part I that the first insulation system 172 is oxidized in basic unit's bridge part 160 and by basic unit's bridge part 160 172a, and in the basic unit 110 that this little ion more continues to diffuse on basic unit's bridge part 160 and it is oxidized to the first insulation system 172 Part II 172b.In the section Example of the present invention, this little ion more continues to diffuse under basic unit's bridge part 160 In basic unit 110 and the Part III 172c of the first insulation system 172 is oxidized to, and Part II 172b is located at Part I Between 172a and Part III 172c.In addition, the second insulation system 174 is located on bottom 114, and around active layers 112 and the One insulation system 172.Part II 172b width W1 is less than the width W2 of active layers 112, should be specified herein, this place The width W1 stated and W2 is the width along BB hatching lines direction.If Part II 172b width W1 is too small can not to be provided enough Bearing capacity give active layers 112 thereon, but this width W1 is excessive and easily hydrogen ion is diffused into active layers with hydroxide ion 112 with bottom 114 by its complete oxidation, it is easier to produce excessive stress in oxidation.In the section Example of the present invention In, the ratio between Part II 172b width W1 and the width W2 of active layers 112 is between 0.2 to 0.5, preferably 0.3。

In the section Example of the present invention, the first insulation system 172 is with identical or different with the second insulation system 174 Material formed, when the first insulation system 172 from the second insulation system 174 is formed with different materials, between both There to be an interface.In the section Example of the present invention, the material of the first insulation system 172 is the material of active layers 110 Oxide, and the material of the second insulation system 174 includes painting formula glass, silica, silicon nitride, aluminum oxide and aluminium nitride, but not As limit.

Insulating barrier covers silicon structure 100 and is also located at comprising grid structure 180 in active layers 112.Specifically, grid structure Active layers 112 are separated into source region and a drain region by 180, and the contact between grid structure 180 and active layers 112 Region is effective passage (effective channel) region of transistor to transmit electric current.Insulating barrier, which covers silicon structure 100, to be made There is the transistor prepared thereon quick operation, low power consumption, low soft error, locking to suppress (latch-up Immunity) the advantages of, the doubt of leakage current is more greatly reduced.Grid structure 180 includes a gate dielectric 182 and a grid Electrode 184 is located on gate dielectric 182.In the section Example of the present invention, the material of gate dielectric 182 includes oxidation Silicon, hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, tantalum hafnium oxide, titanium oxide hafnium, tantalum hafnium oxide, or its combination, and gate electrode 184 material includes polysilicon, tungsten, aluminium, titanium, titanium nitride, tantalum, tantalum nitride, cobalt, copper, nickel or its combination.In the portion of the present invention In point embodiment, insulating barrier covers silicon structure 100 also comprising a clearance wall 190 in active layers 112, and the sandwiched of grid structure 180 Between two clearance walls 190.

Although the present invention is disclosed above with embodiment, so it is not limited to the present invention, any to be familiar with this skill Person, without departing from the spirit and scope of the present invention, when can be used for a variety of modifications and variations, therefore protection scope of the present invention is worked as It is defined depending on the scope of which is defined in the appended claims.

Claims (9)

1. a kind of insulating barrier covers silicon structure, it is characterised in that includes:
One bottom;
One insulating barrier is located on the bottom;
One active layers are embedded in the insulating barrier;And
One barrier layer is located in the insulating barrier and surround the active layers,
Wherein the insulating barrier includes:
One first insulation system, it is located between the bottom and the active layers;And
One second insulation system, it is located on the bottom, and surround the active layers and first insulation system,
Wherein first insulation system includes:
One Part I contacts the active layers;And
One Part II is located between the bottom and the Part I, and the width of the Part II is less than the width of the active layers Degree.
2. insulating barrier according to claim 1 covers silicon structure, it is characterised in that first insulation system and second insulation Structure is formed with different materials.
3. insulating barrier according to claim 1 covers silicon structure, it is characterised in that the width of the Part II and the active layers Width between ratio between 0.2 to 0.5.
4. a kind of insulating barrier covers the preparation method of silicon structure, it is characterised in that includes:
One first hard cover screen is covered in a basic unit;
First hard cover screen and basic unit of part are removed, to form one first opening exposure basic unit;
Form the side wall that a barrier layer covers first opening;
Part basic unit in first opening is removed, to form one second opening;
The basic unit in second opening is removed etc. tropism, to form basic unit's bridge part;
Basic unit's bridge part is aoxidized to form one first insulation system;And
One second insulation system is formed in second opening.
5. insulating barrier according to claim 4 covers the preparation method of silicon structure, it is characterised in that the formation barrier layer covers The side wall for covering first opening includes:
Form side wall and bottom that one second hard cover screen conformally covers first hard cover screen and first opening;And
Remove the bottom of first opening and second hard cover screen on first hard cover screen.
6. insulating barrier according to claim 4 covers the preparation method of silicon structure, it is characterised in that is with a wet oxidation processing procedure Basic unit's bridge part is aoxidized to form first insulation system, and the temperature of the wet oxidation processing procedure is more than 1000 DEG C.
7. insulating barrier according to claim 4 covers the preparation method of silicon structure, it is characterised in that is with a wet etching processing procedure The basic unit in second opening is removed etc. tropism.
8. insulating barrier according to claim 4 covers the preparation method of silicon structure, it is characterised in that is forming second insulation After structure is in second opening, also include:
Remove first hard cover screen;And
Grind second insulation system.
9. insulating barrier according to claim 4 covers the preparation method of silicon structure, it is characterised in that is with spin coating, physics gas Mutually deposition, chemical vapor deposition or ald form second insulation system in second opening.
CN201510325062.4A 2015-06-12 2015-06-12 Insulating barrier covers silicon structure and preparation method thereof CN104952886B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201510325062.4A CN104952886B (en) 2015-06-12 2015-06-12 Insulating barrier covers silicon structure and preparation method thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201711463663.7A CN107994037B (en) 2015-06-12 2015-06-12 Insulating layer covers silicon structure
CN201510325062.4A CN104952886B (en) 2015-06-12 2015-06-12 Insulating barrier covers silicon structure and preparation method thereof

Related Child Applications (1)

Application Number Title Priority Date Filing Date
CN201711463663.7A Division CN107994037B (en) 2015-06-12 2015-06-12 Insulating layer covers silicon structure

Publications (2)

Publication Number Publication Date
CN104952886A CN104952886A (en) 2015-09-30
CN104952886B true CN104952886B (en) 2018-04-06

Family

ID=54167430

Family Applications (2)

Application Number Title Priority Date Filing Date
CN201510325062.4A CN104952886B (en) 2015-06-12 2015-06-12 Insulating barrier covers silicon structure and preparation method thereof
CN201711463663.7A CN107994037B (en) 2015-06-12 2015-06-12 Insulating layer covers silicon structure

Family Applications After (1)

Application Number Title Priority Date Filing Date
CN201711463663.7A CN107994037B (en) 2015-06-12 2015-06-12 Insulating layer covers silicon structure

Country Status (1)

Country Link
CN (2) CN104952886B (en)

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5583368A (en) * 1994-08-11 1996-12-10 International Business Machines Corporation Stacked devices
US6864149B2 (en) * 2003-05-09 2005-03-08 Taiwan Semiconductor Manufacturing Company SOI chip with mesa isolation and recess resistant regions
TWI251342B (en) * 2003-07-24 2006-03-11 Samsung Electronics Co Ltd Vertical double-channel silicon-on-insulator transistor and method of manufacturing the same
US7119023B2 (en) * 2003-10-16 2006-10-10 Taiwan Semiconductor Manufacturing Company, Ltd. Process integration of SOI FETs with active layer spacer
US7157350B2 (en) * 2004-05-17 2007-01-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming SOI-like structure in a bulk semiconductor substrate using self-organized atomic migration
KR100585161B1 (en) * 2004-10-02 2006-05-30 삼성전자주식회사 Manufacturing method and device of multi-channel transistor
CN101459052A (en) * 2007-12-11 2009-06-17 茂德科技股份有限公司 Manufacturing method for silicon coating on insulation layer and construction for coating silicon on the insulation layer
US7939392B2 (en) * 2008-10-06 2011-05-10 Taiwan Semiconductor Manufacturing Company, Ltd. Method for gate height control in a gate last process
US20120049358A1 (en) * 2010-08-24 2012-03-01 Bin-Hong Cheng Semiconductor Device and Semiconductor Process for Making the Same
US9972524B2 (en) * 2013-03-11 2018-05-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method for fabricating a semiconductor device

Also Published As

Publication number Publication date
CN107994037B (en) 2019-07-26
CN107994037A (en) 2018-05-04
CN104952886A (en) 2015-09-30

Similar Documents

Publication Publication Date Title
TWI593103B (en) Methods of forming stressed layers on finfet semiconductor devices and the resulting devices
CN104795331B (en) The forming method of transistor
EP2725607B1 (en) Method of making a logic transistor and a non-volatile memory (nvm) cell
US8735270B2 (en) Method for making high-K metal gate electrode structures by separate removal of placeholder materials
DE112011102943B4 (en) A method of forming a replacement metal gate with rimless contact
US8716828B2 (en) Semiconductor device with isolation trench liner
TWI546896B (en) Method of integrating a charge-trapping gate stack into a cmos flow
DE102014219912A1 (en) Method for forming FinFET semiconductor devices using a Austauschgatetechnik and the resulting devices
CN101752317B (en) Method for manufacturing semiconductor device
US6906398B2 (en) Semiconductor chip with gate dielectrics for high-performance and low-leakage applications
DE112005000854B4 (en) A method of manufacturing a semiconductor element having a high-K-gate dielectric layer and a metal gate electrode
CN100565811C (en) Semiconductor device with the metal gate electrode that on the height-k gate dielectric layer of annealing, forms
TWI390729B (en) Semiconductor structures integrating damascene-body finfet's and planar devices on a common substrate and methods for forming such semiconductor structures
CN1531066B (en) Manufacture and structure of semiconductor on insulating layer with concave resistance
TWI390665B (en) Semiconductor device having dual-sti (shallow trench isolation) and manufacturing method thereof
JP3634320B2 (en) Semiconductor device and manufacturing method of semiconductor device
CN101515560B (en) A method for forming a shallow trench isolation region
CN101872742B (en) Semiconductor device and manufacturing method
TW201511283A (en) Methods of forming contact structures on finfet semiconductor devices and the resulting devices
TWI495106B (en) Fin field effect transistors and methods for fabricating the same
CN103972067B (en) Integrated circuit having replacement gate structure and method for fabricating the same
US8846513B2 (en) Semiconductor device comprising replacement gate electrode structures and self-aligned contact elements formed by a late contact fill
US20120252171A1 (en) Non-volatile memory and logic circuit process integration
US7754593B2 (en) Semiconductor device and manufacturing method therefor
TWI578446B (en) Non-volatile memory array with concurrently formed low and high voltage logic devices

Legal Events

Date Code Title Description
PB01 Publication
C06 Publication
SE01 Entry into force of request for substantive examination
C10 Entry into substantive examination
TA01 Transfer of patent application right

Effective date of registration: 20170628

Address after: No. 188 East Huaihe Road, Huaiyin District, Jiangsu, Huaian

Applicant after: Jiangsu times all core storage technology Co., Ltd.

Applicant after: Jiangsu times core semiconductor Co., Ltd.

Applicant after: The British Vigin Islands manufacturer epoch Quan Xin Science and Technology Ltd.

Address before: 315195 Zhejiang city of Ningbo province Yinzhou Industrial Park (New Yinzhou District Jiang Shan Zhen Zhang Yu Cun)

Applicant before: Ningbo epoch Quan Xin Science and Technology Ltd.

Applicant before: The British Vigin Islands manufacturer epoch Quan Xin Science and Technology Ltd.

TA01 Transfer of patent application right
GR01 Patent grant
GR01 Patent grant
CP03 Change of name, title or address

Address after: No. 601, Changjiang East Road, Huaiyin District, Huaian, Jiangsu

Co-patentee after: Jiangsu times core semiconductor Co., Ltd.

Patentee after: Jiangsu Times Full Core Storage Technology Co., Ltd.

Co-patentee after: The British Vigin Islands manufacturer epoch Quan Xin Science and Technology Ltd.

Address before: 223001 No. 188 Huaihe East Road, Huaiyin District, Huaian City, Jiangsu Province

Co-patentee before: Jiangsu times core semiconductor Co., Ltd.

Patentee before: Jiangsu times all core storage technology Co., Ltd.

Co-patentee before: The British Vigin Islands manufacturer epoch Quan Xin Science and Technology Ltd.

CP03 Change of name, title or address