CN104931930A

CN104931930A - Beam control information message caching method

Info

Publication number: CN104931930A
Application number: CN201510359213.8A
Authority: CN
Inventors: 周邦华; 于志伟; 刘剑; 吴卫
Original assignee: 724th Research Institute of CSIC
Current assignee: 724th Research Institute of CSIC
Priority date: 2015-06-25
Filing date: 2015-06-25
Publication date: 2015-09-23

Abstract

The invention relates to a beam control information message caching method. The beam control information message caching method is implemented in an FPGA processor, beam control information data from an RAPIDIO link is received, two levels of caches are adopted, the first level is to pass through an FIFO at first, and the second level is to store the beam control information data in a BRAM. The write-in of the FIFO is controlled by the RAPIDIO link, and the FIFO starts read-out after caching 5000 pieces of data. The write-in of the BRAM is effectively controlled by a beam-control controller or by reset enabled control, thus the beam control information message can be read out by taking a counter as an address, and the BRAM can be reset, thereby reducing difficulty of external control. In order to shorten reset time of the BRAM, all-zero data is only written into the first 32 addresses, and the whole beam control information message stored in the BRAM is invalid through invalidating the head part of the beam control information message, thereby achieving the reset purpose.

Description

A kind of ripple control infomational message caching method

Technical field

The present invention relates to a kind of ripple control infomational message caching method, belong to Transmission System of Radar Data technology, mainly for phased-array radar real time beam control technology.

Background technology

Phased-array radar generally adopts CPU application embedded system to do ripple control resource scheduling algorithm, obtains multitask ripple control infomational message under calculating cycle a period of time.General use two storeies realize ping-pong operation, carry out circulation read-write.Do like this and cause controlling the more difficult storage resources with taking twice.In order to improve FPGA internal storage resources service efficiency, reducing and controlling difficulty, proposing a kind of new caching technology to reduce ripple control Software for Design difficulty.

Summary of the invention

The object of the invention is to design a kind of caching method, is satisfied different phased-array radar real time beam control technology, reduces ripple control infomational message Read-write Catrol difficulty.

The technical solution realizing the object of the invention is: in phased-array radar, and mode module and scheduling of resource software are in different hardware processors, and mode module uses FPGA processor, scheduling of resource software application POWERPC processor.Ripple control module is to scheduling of resource software application task, and scheduling of resource software calculates one group of ripple control infomational message, issues ripple control module by RAPIDIO link.In ripple control inside modules, the ripple control infomational message sent by RAPIDIO link first carries out buffer memory through a FIFO, realize the conversion of data transfer rate and bit wide, reach after 5000 according to the data volume of buffer memory in FIFO, write counter with one to be written in BRAM as the data of address accumulator by FIFO, until FIFO is sky.Ripple control program is according to radar requirements of one's work, from BRAM, the data of one section of fixed size are read as a frame ripple control information task message every one period of work period, along with work schedule need to read each ripple control infomational message one by one time, read counter can be used as address easily to read message in BRAM like clockwork.At present, when the reset signal RST of BRAM puts 1, make output be null value, can not remove the data of storage inside, when reset signal RST sets to 0, the value of reading remains original storage data.Simple and easy to operate for making BRAM reset, because front 32 addresses of BRAM are ripple control infomational message heads, these 32 addresses can be write full zero data, the ripple control infomational message that whole BRAM is stored is invalid, completes BRAM reset with this.After having read last ripple control infomational message, control program has completed BRAM and has reset, then to scheduling of resource software application task, just can before the arrival of next group task cycle more new task message.Issue even without new task message, also can not read original message with making the mistake.Concerning BRAM, reset and two work of write ripple control infomational message, ripple control control program separates completely from the time, so can guarantee that BRAM read-write is errorless.

Accompanying drawing explanation

Fig. 1 is ripple control method for caching information schematic diagram.

Fig. 2 is that ripple control information produces and buffer memory sequential chart.

Embodiment

Ripple control infomational message caching method of the present invention, as shown in Figure 2, is divided into following 5 steps:

1. ripple control controller produces task message application pulse, carries out FIFO, BRAM reset as benchmark.FIFO is set to 64 inputs, 16 way of outputs, and the input and output of BRAM are 16.When FIFO resets, be directly 1 by the RST signal assignment of FIFO, after keeping 3 clock period, then assignment is 0.When BRAM resets, write full zero data to address, address 0 to 32, because this sector address is ripple control infomational message head, after effective message of head is written into full zero data, the ripple control infomational message in whole BRAM is all judged as invalid packet by ripple control controller.

2., after completing the 1st step, ripple control controller generates task application message and doorbell information, is dealt into scheduling of resource software end by RAPIDIO transmission program.Scheduling of resource software can calculate the ripple control parameter of future time sheet, forms ripple control infomational message.Ripple control module FIFO receives the ripple control infomational message from RAPIDIO interface, realizes the conversion being transformed into 100MHz, 16 bit data by 156.25MHz, 64 bit data.During write FIFO, by high 14 trigger pips as write process of RAPIDIO receiver address signal, when this address signal is the value of setting each time, write 64 bit data to FIFO.

3. judge that FIFO is data cached whether more than 5000, if more than 5000, then start immediately and write BRAM control program.From address 0, the ripple control infomational message head read by FIFO one by one, each subtask message of ripple control infomational message are written in BRAM, until FIFO is empty.

4. when entering next timeslice from a work slice circulation, first more senior task order is judged whether by ripple control controller, if have, enter the mode of operation of high priority, if without, carry out from BRAM, read ripple control infomational message and produce ripple control control signal and message.

5. read the data of front 32 addresses, address 0 to 31 of BRAM, judge that whether the ripple control infomational message in current BRAM is effective, if invalid, stop.If effectively, then extract the initial time of each subtask in this timeslice from ripple control infomational message head, timeslice can be divided into multiple continuous print work period.At each work period initial time, from BRAM, read ripple control subtask message, and produce every gating pulse and optical fiber control message according to ripple control subtask message.After in the end a task message reads, produce task application pulse by ripple control controller, enter the 1st step and do FIFO, BRAM clearing work.

Claims

1. a ripple control infomational message caching method, is characterized in that: the buffer memory link forming RAPIDIO interface data with FIFO+BRAM; The clearing of FIFO and BRAM is staggered with reading and writing data from the time by ripple control Control timing sequence; FIFO write end carries out control by the control signal of RAPIDIO interface and writes; When the buffer data size of FIFO is more than 5000, runs through continuously with regard to disposable and be written in BRAM, using as ripple control infomational message; After ripple control infomational message reads under the control of ripple control program from BRAM, ripple control program is by front for BRAM 32 addresses write complete zero, and it is invalid to be set to by BRAM internal wave control infomational message; Such design, avoiding when not having new ripple control infomational message write, again can read the mistake of original message as current time message again.

2. ripple control infomational message caching method according to claim 1, is characterized in that: described FIFO converts RAPIDIO link data to 16 by 64, and is transformed into real work clock frequency by data transfer rate by 156.25MHz.

3. ripple control infomational message caching method according to claim 1 and 2, it is characterized in that: described BRAM is the ripple control information data in buffer memory maximum 10 cycles, after according to radar work schedule, in the end a ripple control infomational message reads, 32 addresses before BRAM are write full zero data, and it is invalid the data in whole BRAM to be set to; Clearing work is replaced with this, then to the new ripple control infomational message of ripple control scheduling of resource software application.