CN104882372A - Semiconductor device manufacturing method - Google Patents
Semiconductor device manufacturing method Download PDFInfo
- Publication number
- CN104882372A CN104882372A CN201410073319.7A CN201410073319A CN104882372A CN 104882372 A CN104882372 A CN 104882372A CN 201410073319 A CN201410073319 A CN 201410073319A CN 104882372 A CN104882372 A CN 104882372A
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- CN
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- Prior art keywords
- semiconductor device
- polysilicon layer
- manufacture method
- type doped
- doped ions
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 51
- 229920005591 polysilicon Polymers 0.000 claims abstract description 50
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 18
- 238000000137 annealing Methods 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 238000002347 injection Methods 0.000 claims abstract description 13
- 239000007924 injection Substances 0.000 claims abstract description 13
- 238000000059 patterning Methods 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 49
- 150000002500 ions Chemical class 0.000 claims description 37
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 13
- 238000005516 engineering process Methods 0.000 claims description 9
- 229910052757 nitrogen Inorganic materials 0.000 claims description 7
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 5
- 229910052732 germanium Inorganic materials 0.000 claims description 5
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 5
- 229910052698 phosphorus Inorganic materials 0.000 claims description 5
- 239000011574 phosphorus Substances 0.000 claims description 5
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 4
- 229910052785 arsenic Inorganic materials 0.000 claims description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 claims description 4
- -1 boron ion Chemical class 0.000 claims description 4
- 229910052799 carbon Inorganic materials 0.000 claims description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 claims description 3
- 239000002019 doping agent Substances 0.000 claims description 3
- 239000007943 implant Substances 0.000 claims description 3
- 238000004151 rapid thermal annealing Methods 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000005530 etching Methods 0.000 description 5
- 239000007789 gas Substances 0.000 description 5
- 239000012212 insulator Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- RWRIWBAIICGTTQ-UHFFFAOYSA-N difluoromethane Chemical compound FCF RWRIWBAIICGTTQ-UHFFFAOYSA-N 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000001307 helium Substances 0.000 description 2
- 229910052734 helium Inorganic materials 0.000 description 2
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 229910003481 amorphous carbon Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000003698 laser cutting Methods 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 description 1
- 229910052753 mercury Inorganic materials 0.000 description 1
- 238000003801 milling Methods 0.000 description 1
- 239000003595 mist Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- NHDHVHZZCFYRSB-UHFFFAOYSA-N pyriproxyfen Chemical compound C=1C=CC=NC=1OC(C)COC(C=C1)=CC=C1OC1=CC=CC=C1 NHDHVHZZCFYRSB-UHFFFAOYSA-N 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 description 1
- 229960000909 sulfur hexafluoride Drugs 0.000 description 1
- 238000009281 ultraviolet germicidal irradiation Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
Abstract
The invention provides a semiconductor device manufacturing method, comprising the steps of: providing a semiconductor substrate; forming a polysilicon layer on the semiconductor substrate; covering the surface of the polysilicon layer to form a patterned first photoresist layer, and performing N type doping ion common injection on the polysilicon layer; performing annealing treatment; and patterning the polysilicon layer in order to form a polysilicon grid. The semiconductor device manufacturing method can effectively reduce line width roughness (LWR) of the polysilicon grid, and furthermore improve device performance.
Description
Technical field
The present invention relates to semiconductor fabrication process, particularly relate to a kind of manufacture method of semiconductor device.
Background technology
Increase gradually along with to very lagre scale integrated circuit (VLSIC) high integration and high performance demand, the critical size of semiconductor device is more and more less, the live width of polysilicon gate is also more and more thinner, also has higher requirement to line width roughness (Line Width Roughness, LWR) simultaneously.The line width roughness (LWR) of ITRS (ITRS) versions in 2009 to polysilicon gate gives new guide route, ITRS2009 points out, when semiconductor device adopts process node to be the processing procedure of 45nm, line width roughness will be reduced to 3.2nm.And more and more less along with process node, the importance of line roughness is also more and more significant.
Illustrate in Fig. 1 that prior art makes the process chart of polysilicon gate, the manufacture method of prior art has been described below in conjunction with Fig. 1.
Perform step 101, Semiconductor substrate is provided, form polysilicon layer and screen successively on a semiconductor substrate.Perform step 102, form the photoresist layer with the patterns of openings exposing pre-formed P type ion implanted region on the surface of screen, and the injection of P type Doped ions is carried out to polysilicon layer.Described P type Doped ions implantation step is the process of boron ion implantation.After P type Doped ions injects, remove the photoresist layer of surface coverage.Perform step 103, form the photoresist layer with the patterns of openings exposing pre-formed N-type ion implanted region on the surface of screen, the injection of N-type Doped ions is carried out to polysilicon layer.Doped N-type Doped ions in this polycrystal layer, such as arsenic (As) and/or phosphorus (P), to form N-type polycrystalline silicon grid.Ion injection method can be used to complete N-type grid doping technique.After N-type Doped ions injects, remove the photoresist layer of surface coverage.Perform step 104, patterning screen, etches polysilicon layer and gate oxide layers, to form polysilicon gate.Photoetching technique is utilized to define gate patterns on the shielding layer.
Adopting prior art to make the line width roughness of polysilicon gate is 3.3nm, and reduces line width roughness and improve for the performance of device and have very large effect.
Therefore, be badly in need of a kind of new manufacture method, to overcome deficiency of the prior art.
Summary of the invention
In summary of the invention part, introduce the concept of a series of reduced form, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that the key feature and essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range attempting to determine technical scheme required for protection.
In order to solve problems of the prior art, the present invention proposes a kind of manufacture method of semiconductor device, comprising the following steps, Semiconductor substrate is provided; Form polysilicon layer on the semiconductor substrate; Form the first photoresist layer of patterning in the surface coverage of described polysilicon layer, described polysilicon layer is carried out to the common injection technology of N-type Doped ions; Carry out annealing in process; Polysilicon layer described in patterning, to form polysilicon gate.
Preferably, described N-type Doped ions is arsenic or phosphorus.
Preferably, in the common injection technology of described N-type Doped ions, dopant dose is 5E14 ~ 1.5E15/square centimeter, and implant energy is 6 ~ 18KeV.
Preferably, the technological parameter of described annealing in process is: annealing temperature is 600 ~ 1000 DEG C, and the time is 10 ~ 30 minutes.
Preferably, the ion jointly injected with described N-type Doped ions is nitrogen, carbon, germanium or fluorine ion.
Preferably, between described Semiconductor substrate and described polysilicon layer, also gate oxide layers is formed with.
Preferably, screen is formed with on described polysilicon layer.
Preferably, before described first photoresist layer of formation, the surface being also included in described polysilicon layer forms second photoresist layer with the patterns of openings exposing pre-formed P type ion implanted region, and carries out the step of P type Doped ions injection to described polysilicon layer.
Preferably, described P type Doped ions is boron ion.
Preferably, described annealing method is that pipe furnace annealing or peak value are annealed or rapid thermal annealing.
To sum up, according to manufacturing process of the present invention, the line width roughness of polysilicon gate can be effectively reduced, and then improve the performance of device.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.
In accompanying drawing:
Fig. 1 is the flow chart of the step that the method for prior art exemplary embodiment is implemented successively;
Fig. 2 is the flow chart of step implemented successively of method according to an exemplary embodiment of the present invention.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it is obvious to the skilled person that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
In order to thoroughly understand the present invention, by following description, detailed step is proposed, to explain the manufacturing process of the present invention's proposition.Obviously, the specific details that the technical staff that execution of the present invention is not limited to semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
Should be understood that, " comprise " when using term in this manual and/or " comprising " time, it indicates exists described feature, entirety, step, operation, element and/or assembly, but does not get rid of existence or additional other features one or more, entirety, step, operation, element, assembly and/or their combination.
[exemplary embodiment]
Below in conjunction with accompanying drawing, the present invention is described in more detail, wherein denotes the preferred embodiments of the present invention, should be appreciated that those skilled in the art can modify the present invention described here, and still realize advantageous effects of the present invention.
Fig. 2 shows and makes polysilicon gate process flow chart according to one embodiment of the present invention.Manufacture method of the present invention is described in detail below in conjunction with Fig. 2.
Perform step 201, Semiconductor substrate is provided, form polysilicon layer and screen successively on a semiconductor substrate.Described Semiconductor substrate can be at least one in following mentioned material: stacked SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc. on stacked silicon (SSOI), insulator on silicon, silicon-on-insulator (SOI), insulator.
Described polysilicon layer can be formed by methods such as chemical vapour deposition (CVD), magnetron sputtering, physical vapour deposition (PVD) or alds.As an example, select low-pressure chemical vapor phase deposition (LPCVD) technique.The process conditions forming described polysilicon layer comprise: reacting gas is silane (SiH
4), the range of flow of described silane can be 100 ~ 200 cc/min (sccm), as 150sccm; In reaction chamber, temperature range can be 700 ~ 750 degrees Celsius; Reaction chamber internal pressure can be 250 ~ 350 millis millimetres of mercury (mTorr), as 300mTorr; Also can comprise buffer gas in described reacting gas, described buffer gas can be helium (He) or nitrogen, and the range of flow of described helium and nitrogen can be 5 ~ 20 liters/min (slm), as 8slm, 10slm or 15slm.
Can also form gate oxide layers between this external Semiconductor substrate and polysilicon layer, this gate oxide layers can be the silicon dioxide layer formed at the temperature of about 800 ~ 1000 degrees Celsius in oxygen steam ambient by oxidation technology.
The material of described screen can be amorphous carbon or silica.The method forming screen can be chemical vapour deposition (CVD) or physical vapour deposition (PVD).Thickness can be 50nm ~ 150nm.The material of screen adopts agraphitic carbon, can reduce the degree of roughness of sidewall, thus when subsequent etching polysilicon layer, can improve the homogeneity of the grid structure width etched.
Perform step 202, form the photoresist layer with the patterns of openings exposing pre-formed P type ion implanted region on the surface of screen, and the injection of P type Doped ions is carried out to polysilicon layer.Described P type Doped ions implantation step is the process of boron ion implantation.The method carrying out injecting can be the common utilization ion implantation device of field of semiconductor manufacture by high energy foreign ion implanted polysilicon layer, thus change the conductivity of gate polysilicon layer.After P type Doped ions injects, remove the photoresistance of surface coverage.
Perform step 203, form the photoresist layer with the patterns of openings exposing pre-formed N-type ion implanted region on the surface of screen, and polysilicon layer is carried out to the common injection technology of N-type Doped ions.Described N-type Doped ions is arsenic or phosphorus, is preferably phosphorus.The ion jointly injected with described N-type Doped ions is nitrogen, carbon, germanium or fluorine ion, is preferably Nitrogen ion.The method carrying out injecting can be that the common utilization ion implantation device of field of semiconductor manufacture is by high energy foreign ion implanted polysilicon layer, as an example, in described nitrogen and the common injection technology of phosphonium ion, implant energy is 6 ~ 18KeV, and dopant dose is 5E14 ~ 1.5E15/square centimeter.After N-type Doped ions injects, remove the photoresistance covering surface.
Perform step 204, carry out annealing in process.Described annealing method is pipe furnace annealing (FurnaceAnneal) or peak value annealing (Spike Anneal) or rapid thermal annealing (Rapid Thermal Anneal).As an example, select pipe furnace to anneal, annealing temperature is 600 ~ 1000 DEG C, and the time is 10 ~ 30 minutes.In other embodiments, also can adopt other annealing way, similar effect should be able to be reached.
Perform step 205, patterning screen, etches polysilicon layer and gate oxide layers, to form polysilicon gate.Photoetching method is utilized to define gate patterns on the shielding layer.Described photoetching method first forms photoresist layer at screen surface spin-coating method; Again there is the photomask blank of target gate figure for mask, use UV-irradiation photoresist layer; Then with the photoresist layer that developer solution process is exposed, photoresist layer forms target gate figure; Again there is the photoresist layer of target gate figure for mask, wet etching screen.Then, take screen as mask, etching grid polysilicon layer and gate oxide layers.Described etching can be dry etching or wet etching.Dry method etch technology includes but not limited to: reactive ion etching (RIE), ion beam milling, plasma etching or laser cutting.Described etching can be the plasma etching using the mist of difluoromethane and sulphur hexafluoride as etching gas, and the RF power wherein adopted is 100 ~ 1000W, and the flow of difluoromethane is 20 ~ 200sccm.
By the polysilicon gate that the method is formed, line width roughness is 3.0nm, and compare compared with the line width roughness of prior art 3.3nm, line width roughness diminishes.Therefore, according to manufacturing process of the present invention, the line width roughness of polysilicon gate can be effectively reduced, and then improve the performance of device.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.
Claims (10)
1. a manufacture method for semiconductor device, comprising:
Semiconductor substrate is provided;
Form polysilicon layer on the semiconductor substrate;
Form the first photoresist layer of patterning in the surface coverage of described polysilicon layer, described polysilicon layer is carried out to the common injection technology of N-type Doped ions;
Carry out annealing in process;
Polysilicon layer described in patterning, to form polysilicon gate.
2. the manufacture method of semiconductor device as claimed in claim 1, it is characterized in that, described N-type Doped ions is arsenic or phosphorus.
3. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that, in the common injection technology of described N-type Doped ions, dopant dose is 5E14 ~ 1.5E15/square centimeter, and implant energy is 6 ~ 18KeV.
4. the manufacture method of semiconductor device as claimed in claim 1, it is characterized in that, the technological parameter of described annealing in process is: annealing temperature is 600 ~ 1000 DEG C, and the time is 10 ~ 30 minutes.
5. the manufacture method of semiconductor device as claimed in claim 1, it is characterized in that, the ion jointly injected with described N-type Doped ions is nitrogen, carbon, germanium or fluorine ion.
6. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that, between described Semiconductor substrate and described polysilicon layer, be also formed with gate oxide layers.
7. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that, be formed with screen on described polysilicon layer.
8. the manufacture method of semiconductor device as claimed in claim 1, it is characterized in that, before described first photoresist layer of formation, the surface being also included in described polysilicon layer forms second photoresist layer with the patterns of openings exposing pre-formed P type ion implanted region, and carries out the step of P type Doped ions injection to described polysilicon layer.
9. the manufacture method of semiconductor device as claimed in claim 8, it is characterized in that, described P type Doped ions is boron ion.
10. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that, described annealing method is that pipe furnace annealing or peak value are annealed or rapid thermal annealing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410073319.7A CN104882372A (en) | 2014-02-28 | 2014-02-28 | Semiconductor device manufacturing method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410073319.7A CN104882372A (en) | 2014-02-28 | 2014-02-28 | Semiconductor device manufacturing method |
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| CN104882372A true CN104882372A (en) | 2015-09-02 |
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| CN201410073319.7A Pending CN104882372A (en) | 2014-02-28 | 2014-02-28 | Semiconductor device manufacturing method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110875171A (en) * | 2018-08-31 | 2020-03-10 | 北京北方华创微电子装备有限公司 | Preparation method of polycrystalline silicon functional layer |
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| CN103066005A (en) * | 2011-10-20 | 2013-04-24 | 台湾积体电路制造股份有限公司 | Method of forming integrated circuit |
| CN103094102A (en) * | 2011-11-04 | 2013-05-08 | 上海华虹Nec电子有限公司 | Method of eliminating etching residue of emitting electrode polycrystalline silicon in duotriode type transistor technology |
| CN103346124A (en) * | 2013-06-04 | 2013-10-09 | 上海华力微电子有限公司 | Method for improving qualified rate of semiconductor devices |
-
2014
- 2014-02-28 CN CN201410073319.7A patent/CN104882372A/en active Pending
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|---|---|---|---|---|
| US5633523A (en) * | 1994-04-28 | 1997-05-27 | Ricoh Company, Ltd. | Complementary mis semiconductor device of dual gate structure having a silicide layer including a thinned portion |
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| CN110875171A (en) * | 2018-08-31 | 2020-03-10 | 北京北方华创微电子装备有限公司 | Preparation method of polycrystalline silicon functional layer |
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