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CN104851908A - High-voltage super-junction MOSFET device terminal structure and manufacturing method thereof - Google Patents

High-voltage super-junction MOSFET device terminal structure and manufacturing method thereof Download PDF

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CN104851908A
CN104851908A CN 201510264631 CN201510264631A CN104851908A CN 104851908 A CN104851908 A CN 104851908A CN 201510264631 CN201510264631 CN 201510264631 CN 201510264631 A CN201510264631 A CN 201510264631A CN 104851908 A CN104851908 A CN 104851908A
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epitaxial
layer
terminal
region
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CN 201510264631
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白玉明
薛璐
张海涛
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无锡同方微电子有限公司
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET

Abstract

The invention relates to a high-voltage super-junction MOSFET device terminal structure and a manufacturing method thereof. The high-voltage super-junction MOSFET device terminal structure comprises a cellular region and a terminal region, and is characterized in that the terminal region comprises an N-type heavily-doped substrate and an N-type epitaxial layer arranged at the upper surface of the N-type heavily-doped substrate, the N-type epitaxial layer is provided with a wide SiO2 column area, and the wide SiO2 column area extends from the upper surface of the N-type epitaxial layer to the lower surface of the N-type epitaxial layer. A transition region is arranged between the cellular region and the terminal region. The transition region comprises the N-type heavily-doped substrate, the N-type epitaxial layer and two narrow P column areas formed in the N-type epitaxial layer, the narrow P column areas extend from the upper surface of the N-type epitaxial layer towards the lower surface of the N-type epitaxial layer, and a preset interval exists between the lower ends of the narrow P column areas and the lower surface of the N-type epitaxial layer. The cellular region comprises the N-type heavily-doped substrate, the N-type epitaxial layer, and a narrow P column area and an N<-> type area which are formed in the N-type epitaxial layer. According to the invention, the area of a terminal is greatly reduced while the voltage withstanding capability of the terminal is reached.

Description

高压超结MOSFET器件终端结构及其制作方法 High-voltage terminal super junction MOSFET device structure and manufacturing method

技术领域 FIELD

[0001] 本发明涉及一种高压超结MOSFET器件终端结构及其制作方法,属于半导体功率器件技术领域。 [0001] The present invention relates to a high end super junction MOSFET device structure and manufacturing method, devices belonging to the technical field of power semiconductors.

背景技术 Background technique

[0002] 超结MOSFET器件是近年来出现的一种重要的功率器件,它的基本原理是电荷平衡平理,超结MOSFET器件的基本超结结构采用交替排列的P柱和N柱。 [0002] The super junction MOSFET device is an important power devices in recent years, and its basic principle is flat charge balance processing, the super junction MOSFET device is basically a super junction structure and a P N columns columns are alternately arranged.

[0003] 超结MOSFET器件设计要考虑的一个重要问题是结终端结构的设计,好的结终端能有效提高器件耐压、降低漏电和提高器件可靠性。 An important problem [0003] The super junction MOSFET device design considerations is the design of the junction termination structure, a good junction termination can improve the breakdown voltage, reduced leakage, and improved device reliability. 目前应用最广泛的超结结构的终端结构采用与元胞部分相同的超结结构,即通过多组相同的沟槽结构组成。 The most widely used configuration of a terminal using the same super-junction structure of the cellular portion of the super junction structure, i.e., through the same groove structure consisting of a plurality of groups. 具体如附图1所示,包括N型重掺杂衬底100,在N型重掺杂衬底100上具有N型外延层101,N型外延层101中具有元胞区102和终端区103,元胞区102的N型外延层101中具有P柱区104和N型体区105,终端区103的N型外延层101中具有多组相同宽度均匀分布的P柱区104 ;所述P柱区104与N型外延层101的下表面之间存在一定间距,如N型外延层101的厚度为50 μπι时,P柱区104的高度一般为35〜45 μπι。 As specifically shown in Figure 1, comprises a heavily doped N-type substrate 100, a heavily doped N-type epitaxial layer 101 having N-type substrate 100, an N-type epitaxial layer 101 having a cell region and a terminal region 103 102 the P;, N type epitaxial layer 101 in the cell region 102 having the P column region 104 and the N-type body region 105, N-type epitaxial layer 101 in the terminal region 103 having the same width P column region 104 uniformly distributed plurality of sets there is a certain distance between the lower surface of the column area 104 and the N-type epitaxial layer 101, such as when the thickness of the N type epitaxial layer 101 is 50 μπι, the height of the P column region 104 is generally 35~45 μπι. 现有该种结构的高压超结MOSFET器件的P柱区104宽度较窄,一般为5 μ m左右,为了得到足够高的终端区域的耐压,终端区103必须占用很大的面积,如耐压为600V的高压超结MOSFET器件,其终端宽度至少大于130 μ m。 104 high-pressure column area width P of the kind of structure of the conventional super junction MOSFET device is narrow, generally about 5 μ m, in order to obtain a sufficiently high voltage terminal region, the terminal region 103 must occupy a large area, such as resistance to pressure of the high pressure super junction MOSFET device 600V, which is greater than the terminal width of at least 130 μ m.

发明内容 SUMMARY

[0004] 本发明的目的是克服现有技术中存在的不足,提供一种高压超结MOSFET器件终端结构及其制作方法,达到现有终端耐压能力的同时大大减小了终端的面积。 [0004] The object of the present invention is to overcome the disadvantages present in the prior art, while providing a high-pressure super junction MOSFET structure and a manufacturing method for a terminal device, the terminal voltage reaches the conventional capability of greatly reducing the area of ​​the terminal.

[0005] 按照本发明提供的技术方案,所述高压超结MOSFET器件终端结构,包括元胞区和终端区,其特征是:所述终端区包括N型重掺杂衬底和设置于N型重掺杂衬底上表面的N型外延层,在N型外延层上设置宽形S12柱区,宽形S1 2柱区由N型外延层的上表面延绅至N型外延层的下表面。 [0005] according to the aspect of the present invention provides a high-voltage terminal super junction MOSFET device structure, including cell region and a terminal region, wherein: the terminal region comprises an N type heavily doped N-type substrate and provided N-type epitaxial layer on the surface of the heavily doped substrate, disposed S12 column-shaped wide region on the N-type epitaxial layer, width S1 2 column area shaped lower surface of the N-type epitaxial layer extending from the upper surface of the N type epitaxial layer gentry to .

[0006] 在一个具体实施方式中,所述元胞区和终端区之间具有过渡区,所述过渡区包括N型重掺杂衬底、N型外延层以及形成于该N型外延层中的两个窄形P柱区,窄形P柱区由N型外延层的上表面朝下表面延伸,并且窄形P柱区的下端与N型外延层的下表面之间存在预设间距。 [0006] In one embodiment, a transition region between the cell region and a terminal region, the transition region comprises a heavily doped N-type substrate, and the N-type epitaxial layer formed on the N-type epitaxial layer narrow two column regions P, P column region narrow surface extending downwardly from the upper surface of the N-type epitaxial layer, and there is a predetermined spacing between the lower surface of the lower narrow region and the P column-shaped N-type epitaxial layer.

[0007] 在一个具体实施方式中,所述元胞区包括N型重掺杂衬底、N型外延层及形成于所述N型外延层中的窄形P柱区和N_体区,N—体区形成于窄形P柱区的上部;所述元胞区的窄形P柱区由N型外延层的上表面朝下表面延伸,并且窄形P柱区的下端与N型外延层的下表面之间存在预设间距。 [0007] In one specific embodiment, the cell region comprising a heavily doped N-type substrate, and N type epitaxial layer is formed on the N type epitaxial layer formed in the narrow region and the P column N_ body region, N- body region is formed in an upper portion of the column area narrow P; P narrow column area of ​​the cell region extending from the surface of the upper surface of the N-type epitaxial layer downward, and the lower end of the narrow region and the P column-shaped N-type epitaxial the preset spacing is present between the lower surface layer.

[0008] 在一个具体实施方式中,所述『体区朝终端区方向延伸,并与终端区接触。 [0008] In one embodiment, the "body region toward the terminal region extending in a direction, and in contact with the terminal zone.

[0009] 在一个具体实施方式中,所述『体区朝过渡区方向延伸,并与过渡区的一个窄形P柱区接触。 [0009] In one embodiment, the "direction toward the transition region extending in the body region, and formed in contact with a narrow transition zone P column region.

[0010] 在一个具体实施方式中,所述宽形S12柱区的宽度为40〜100 μπι。 [0010] In a specific embodiment, the width of the wide region of the column-shaped S12 40~100 μπι.

[0011] 在一个具体实施方式中,所述窄形P柱区的宽度约为5 μ m。 [0011] In one specific embodiment, the P column region narrower shaped approximately 5 μ m.

[0012] 所述高压超结MOSFET器件终端结构的制作方法,其特征是,采用如下步骤: [0012] The high-pressure super-junction MOSFET manufacturing method of a terminal structure of the device, characterized in that the following steps are taken:

(1)提供具有N型重掺杂衬底和N型外延层的半导体基片; (1) providing a substrate having a heavily doped N-type and N-type epitaxial layer of the semiconductor substrate;

(2)在N型外延层的终端区进行刻蚀,得到一个由N型外延层上表面贯穿至N型外延层下表面的第一槽体,第一槽体的宽度为40〜10ym; (2) etching in the terminal area N-type epitaxial layer, obtained through a N type epitaxial layer on a surface of the first tank to the lower surface of the N type epitaxial layer, the groove width of the first body is 40~10ym;

(3)在第一槽体中淀积氧化层,形成宽形S12柱区; (3) depositing a first oxide layer on the tank, with a width of column-shaped regions S12;

(4)采用CMP工艺将宽形S12柱区上表面进行磨平; (4) a CMP process to form a wide polished surface of the S12 column area;

(5)制作元胞区或者元胞区和过渡区。 (5) Preparation of cell region and a cell region or transition region.

[0013] 进一步的,制作元胞区和过渡区时,具体包括: [0013] Further, when creating cell region and a transition region comprises:

在元胞区和过渡区的N型外延层上刻蚀形成第二槽体,第二槽体由N型外延层的上表面朝下表面方向延伸,并且第二槽体的底部与N型外延层的下表面之间存在预设的距离,第二槽体的宽度约为5 μΐΉ ; On the N type epitaxial layer cell region and a transition region forming a second etching tank, the second tank body extending from the upper surface of the N-type epitaxial layer downward surface direction, and a second tank bottom and the N-type epitaxial predetermined distance exists between the lower surface layer, the width of the second tank is about 5 μΐΉ;

在第二槽体中填充P型半导体层,形成窄形P柱区; P-type semiconductor layer filling the second tank, the P column regions formed in a narrow shape;

在元胞区的窄形P柱区的顶部进行注入和扩散,形成N—体区。 Implanting and diffusing at the top of a narrow shaped cell region P column region, N- body region is formed.

[0014] 所述高压超结MOSFET器件终端结构的制作方法,其特征是,采用如下步骤: [0014] The high-pressure super-junction MOSFET manufacturing method of a terminal structure of the device, characterized in that the following steps are taken:

(1)提供具有N型重掺杂衬底和N型外延层的半导体基片; (1) providing a substrate having a heavily doped N-type and N-type epitaxial layer of the semiconductor substrate;

(2)在N型外延层的终端区进行刻蚀,得到多个由N型外延层上表面贯穿至N型外延层下表面的第三槽体,第三槽体的宽度为2〜5 μπι,第三槽体的宽度与第三槽体间距的比值为10:4 ; (2) etching in the terminal area N-type epitaxial layer, obtained through a plurality of N type epitaxial layer on the surface of the third tank to the lower surface of the N type epitaxial layer, the groove width of the third body is 2~5 μπι , the width of the third tank pitch ratio of the third tank is 10: 4;

(3)在第三槽体中湿氧化生长氧化层,形成宽形S12柱区; (3) in the third tank in a wet oxide grown oxide layer, forming a wide-shaped S12 column area;

(4)采用CMP工艺将宽形S12柱区上表面进行磨平; (4) a CMP process to form a wide polished surface of the S12 column area;

(5)制作元胞区或者元胞区和过渡区。 (5) Preparation of cell region and a cell region or transition region.

[0015] 本发明所述高压超结MOSFET器件终端结构及其制作方法,采用宽形S12柱区,该宽形S12柱区由N形外延层的上表面延伸至N形外延层的下表面,并且宽度较宽,为40〜100 μπι,从而达到现有终端耐压能力的同时大大减小了终端的面积。 [0015] The present invention is the super junction MOSFET high voltage termination structure and a manufacturing method for devices with wide column-shaped regions S12, S12 of the column-shaped wide region on the surface of the N epitaxial layer extends to the lower surface of the N type epitaxial layer is formed, and the wide width of 40~100 μπι, existing terminals so as to achieve pressure resistance while greatly reducing the area of ​​the terminal.

附图说明 BRIEF DESCRIPTION

[0016] 图1为现有技术中高压超结MOSFET器件终端的结构示意图。 [0016] FIG. 1 is a schematic structural diagram of the prior art high-voltage terminal of the super junction MOSFET device.

[0017] 图2-1为本发明实施例一的结构示意图。 [0017] FIG. 2-1 a schematic structural diagram of the embodiment of the present invention.

[0018] 图2-2为实施例一在N型外延层的终端区制作深沟槽后的结构示意图。 [0018] FIG. 2-2 a schematic structure after making a deep trench in the termination region of the N-type epitaxial layer embodiment.

[0019] 图2-3为实施例一在N型外延层的元胞区制作槽体后的结构示意图。 [0019] Figure 2-3 is a schematic view of the tank is produced in the cell region embodiment of the N-type epitaxial layer.

[0020] 图3-1为本发明实施例二的结构示意图。 [0020] FIG. 3-1 a schematic structural diagram of a second embodiment of the present invention.

[0021] 图3-2为实施例二在N型外延层的终端区制作多组深沟槽后的结构示意图。 [0021] Figure 3-2 two schematic structure after making a deep trench in the termination region plurality of sets of the N-type epitaxial layer embodiment.

[0022] 图3-3为实施例二在N型外延层的过渡区和元胞区制作槽体后的结构示意图。 [0022] Figure 3-3 is a schematic view of two embodiments of the tank after the production of the transition region and the N-type epitaxial layer of the cell region.

[0023] 图中标号为:100、200-Ν型重掺杂衬底,10U201-N型外延层,102,202-元胞区,103,203-终端区,104-Ρ柱区,105-Ν型体区,204-窄形P柱区,205_Ν_体区,206-宽形S12柱区,207-过渡区,208-第一槽体,209-第二槽体,210-第三槽体。 [0023] FIG designated: 100,200-Ν-type heavily doped substrate, 10U201-N-type epitaxial layer, 102,202- cell region, the terminal region 103,203-, 104-Ρ column region, 105-Ν-type body region , 204- narrow P column region, 205_Ν_ body region, 206- S12 column-shaped wide region, transition region 207-, 208- first tank, the second tank 209-, 210- third tank.

具体实施方式 detailed description

[0024] 下面结合具体附图对本发明作进一步说明。 [0024] below with specific reference to the present invention will be further described.

[0025] 实施例一: [0025] Example a:

如图2-1所示,本发明所述高压超结MOSFET器件终端结构包括元胞区202和终端区203,元胞区202包括N型重掺杂衬底200、N型外延层201及形成于所述N型外延层201中的窄形P柱区204和N—体区205,N—体区205形成于窄形P柱区204的上部,且所述N—体区205朝终端区203方向延伸,并与终端区203接触;所述窄形P柱区204由N型外延层201的上表面朝下表面延伸,并且窄形P柱区204的下端与N型外延层201的下表面之间存在预设间距,窄形P柱区204的宽度一般为5 μ m左右。 Shown in Figure 2-1, the present invention is the high-pressure super-junction MOSFET device termination structure 202 includes a cell region and a terminal region 203, cell region 202 includes an N type substrate 200 is heavily doped, N-type epitaxial layer 201 is formed and narrow P column regions in the N-type epitaxial layer 201 of body region 204 and N- 205, N- body region 205 is formed in an upper narrow P column region 204, body region 205 and the N- terminal region towards 203 extending direction and in contact with the terminal region 203; P column-shaped region of the narrow surface 204 extending from the upper surface of the N-type epitaxial layer 201 down, narrow shape and the lower end of the P column region 204 of the N type epitaxial layer 201 predetermined spacing exists between the surface of the narrow width P column-shaped region 204 is generally about 5 μ m.

[0026] 所述终端区203包括N型重掺杂衬底200和设置于N型重掺杂衬底200上表面的N型外延层201,在N型外延层201上设置宽形S12柱区206,宽形S1 2柱区206由N型外延层201的上表面延绅至N型外延层201的下表面,宽形S12柱区206的宽度为40〜100 μ m0 [0026] The termination region 203 includes a heavily doped N-type substrate 200 and disposed on a heavily doped N-type substrate 200. N-type epitaxial layer 201 surface, disposed S12 column-shaped wide region on the N-type epitaxial layer 201 206, column width S1 2 shaped region 206 extending from the upper surface of the N type epitaxial layer 201 gentry to the lower surface of the N-type epitaxial layer 201, wider S12 column-shaped zone 206 is 40~100 μ m0

[0027] 本实施例所述的高压超结MOSFET器件终端结构的制作工艺如下: [0027] Example embodiments of the present high-pressure super junction MOSFET fabrication process termination structure of the device is as follows:

(1)在N型重掺杂衬底200上形成N型外延层201 ; (1) is formed in the N type heavily doped N-type epitaxial layer 201 on the substrate 200;

(2)在N型外延层201上终端区203刻蚀一个深度大于或等于N型外延层201厚度的第一槽体208,第一槽体208的宽度为40〜100 μ m,如图2_2所示; (2) on the N-type epitaxial layer 201, a termination region 203 is etched depth is greater than or equal to the thickness of the N-type epitaxial layer 201 of the first groove 208, the groove width of the first body 208 is 40~100 μ m, 2_2 in FIG. shown;

(3)采用淀积氧化层的方式,在第一槽体208内填满S12,形成宽形S12柱区206 ; (3) by way of deposited oxide layer, in the first tank 208 filled S12, S12 column-shaped wide region 206 is formed;

(4)采用CMP (减薄/抛光)工艺磨平宽形S12柱区206的上表面; (4) using CMP (thinning / Polishing) process on the polished surface of the shaped wide region 206 S12 column;

(5)后续按现有常规工艺制作元胞区202,具体包括在元胞区202的N型外延层201上刻蚀形成第二槽体209,如图2-3所示,第二槽体209与N型外延层201的下表面之间具有预设的距离,在第二槽体209中外延生长窄形P柱区204 ;以及在窄形P柱区204的顶部形成N—型体区205 ;最终得到如图2-1所示的高压超结MOSFET器件终端结构。 (5) subsequent production process according to the prior conventional cell region 202, comprises a second groove 209 is formed on the etched N-type epitaxial layer 201 of the cell region 202, shown in Figure 2-3, the second tank 209 between the lower surface of the N-type epitaxial layer 201 having a predetermined distance, 204 is epitaxially grown in the (narrow) 209 P column region of the second tank; N- type and forming a body region at the top of a narrow shaped P column region 204 205; finally obtained as shown in FIG high voltage MOSFET device terminals 2-1 superjunction structure.

[0028] 对于现有的高压超结MOSFET器件,由于P柱区的宽度较窄,一般为5 μ m左右,为了得到足够高的终端区域的耐压,终端区必须占用很大的面积,如耐压为600V的高压超结MOSFET器件,其终端宽度至少大于130 μπι。 [0028] For the conventional high-pressure super-junction MOSFET device, since the width of the P column region is narrow, generally about 5 μ m, in order to obtain a sufficiently high voltage terminal region, the terminal region must occupy a large area, such as a withstand voltage of 600V high pressure super junction MOSFET device, which is at least larger than a width of the terminal 130 μπι. 而本实施例中,所述宽形S12柱区由N形外延层的上表面延伸至N形外延层的下表面,并且宽度较宽,为40〜100 μ m,从而达到现有终端耐压能力的同时大大减小了终端的面积。 In the present embodiment, the width of a column-shaped region extending S12 from the upper surface of the N type epitaxial layer to a lower surface of the N type epitaxial layer, and the wide width of 40~100 μ m, so as to achieve the existing terminal voltage the ability to simultaneously greatly reducing the area of ​​the terminal.

[0029] 实施例二: [0029] Example II:

如图3-1所示,本发明所述高压超结MOSFET器件终端结构包括元胞区202、终端区203以及位于元胞区202和终端区203之间的过渡区207,元胞区202包括N型重掺杂衬底200、N型外延层201及形成于所述N型外延层201中的窄形P柱区204和N—体区205,N'体区205形成于窄形P柱区204的上部,且所述N_体区205朝终端区203方向延伸,并与过渡区207接触;所述窄形P柱区204由N型外延层201的上表面朝下表面延伸,并且窄形P柱区204的下端与N型外延层201的下表面之间存在预设间距,窄形P柱区204的宽度一般为5 μ m左右。 As shown, the present invention is the high-voltage terminal super junction MOSFET device structure 202 includes a cell region, the terminal region 203 and transition region 203 located between the cell region and a terminal region 202 2073-1, cell region 202 includes heavily doped N-type substrate 200, N-type epitaxial layer 201 and formed in the N-type column regions narrow P epitaxial layer 201 N- body region 204 and 205, N 'narrow body region 205 is formed on the column-shaped P the upper region 204, and the direction 205 N_ 203 toward the body region extends terminal region, and in contact with the transition zone 207; P column-shaped region of the narrow surface 204 extending from the upper surface of the N-type epitaxial layer 201 down, and the preset spacing is present between the lower surface of the narrow-shaped lower end of the P column region 204 of the N type epitaxial layer 201, a narrow shaped P column region 204 is generally about 5 μ m.

[0030] 所述过渡区207包括N型重掺杂衬底200、N型外延层201以及形成于该N型外延层201中的两个窄形P柱区204,过渡区207的一个窄形P柱区204的上部与元胞区202的N_体区205接触。 [0030] The transition region 207 includes an N type substrate 200 is heavily doped, N-type epitaxial layer 201 and two narrow-P column-shaped region is formed in the N type epitaxial layer 201 204, a narrow transition region shape 207 an upper portion of the contact region 205 and the P column cell region 204 of the body region 202 N_. 所述窄形P柱区204由N型外延层201的上表面朝下表面延伸,并且窄形P柱区204的下端与N型外延层201的下表面之间存在预设间距,窄形P柱区204的宽度一般为5 μπι左右。 Narrow regions of the P column 204 extending downwardly from the surface of the upper surface of the N type epitaxial layer 201, and there is a predetermined spacing between the lower surface of the narrow-shaped lower end of the P column region 204 of the N type epitaxial layer 201, P Narrow the width of the column region 204 is generally about 5 μπι.

[0031] 所述终端区203包括N型重掺杂衬底200和设置于N型重掺杂衬底200上表面的N型外延层201,在N型外延层201上设置宽形S12柱区206,宽形S1 2柱区206由N型外延层201的上表面延绅至N型外延层201的下表面,宽形S12柱区206的宽度为40〜100 μ m0 [0031] The termination region 203 includes a heavily doped N-type substrate 200 and disposed on a heavily doped N-type substrate 200. N-type epitaxial layer 201 surface, disposed S12 column-shaped wide region on the N-type epitaxial layer 201 206, column width S1 2 shaped region 206 extending from the upper surface of the N type epitaxial layer 201 gentry to the lower surface of the N-type epitaxial layer 201, wider S12 column-shaped zone 206 is 40~100 μ m0

[0032] 本实施例所述的高压超结MOSFET器件终端结构的制作工艺如下: [0032] Example of the present embodiment the high pressure super junction MOSFET fabrication process termination structure of the device is as follows:

(1)在N型重掺杂衬底200上形成N型外延层201 ; (1) is formed in the N type heavily doped N-type epitaxial layer 201 on the substrate 200;

(2)在N型外延层201上终端区203刻蚀多个深度大于或等于N型外延层201厚度的第三槽体210,第三槽体210的宽度为2〜5 μ m,第三槽体210的宽度与第三槽体210间距的比值为10:4,如图3-2所示; (2) on the N-type epitaxial layer, a plurality of etching depths 201,203 terminal area equal to or greater than the thickness of the N type epitaxial layer 201 of the third groove 210, the groove width of the third body 210 is 2~5 μ m, the third width 210 ratio of groove pitch of the third tank 210 is 10: 4, shown in Figure 3-2;

(3)采用湿氧生长氧化层的方式,在第三槽体210间生长S12,形成由氧化层填充的宽形S12柱区206 ; (3) an oxygen-wet grown oxide layer, a third groove 210 in body growth S12, S12 column-shaped region with a width of 206 filled with the oxide layer;

(4)采用CMP (减薄/抛光)工艺磨平宽形S12柱区206的上表面; (4) using CMP (thinning / Polishing) process on the polished surface of the shaped wide region 206 S12 column;

(5)后续按现有常规工艺制作元胞区202和过渡区207,具体包括在元胞区202和过渡区207的N型外延层201上刻蚀形成第二槽体209,如图3_3所示,第二槽体209与N型外延层201的下表面之间具有预设的距离,在第二槽体209中外延生长窄形P柱区204 ;以及在元胞区202的窄形P柱区204的顶部形成N—型体区205 ;最终得到如图3_1所示的高压超结MOSFET器件终端结构。 (5) subsequent production process according to the prior conventional cell region 202 and transition region 207 comprises a second etched groove 209 is formed on the N type epitaxial layer 201 cell region 202 and transition region 207, as shown in FIG 3_3 shown, the second groove 209 between the lower surface of the N-type epitaxial layer 201 having a predetermined distance, 209 is epitaxially grown in a narrow region of the second pillar-shaped groove P 204; P and a narrow shape in the cell region 202 N- type body region 205 at the top 204 of the column region is formed; high pressure finally obtained as shown in FIG terminal device 3_1 super junction MOSFET structure.

Claims (10)

1.一种高压超结MOSFET器件终端结构,包括元胞区(202)和终端区(203),其特征是:所述终端区(203)包括N型重掺杂衬底(200)和设置于N型重掺杂衬底(200)上表面的N型外延层(201),在N型外延层(201)上设置宽形S12柱区(206),宽形S12柱区(206)由N型外延层(201)的上表面延绅至N型外延层(201)的下表面。 1. A high-pressure super-junction MOSFET device termination structure, comprising a cell region (202) and a terminal area (203), characterized in that: said terminal zone (203) comprises a heavily doped N-type substrate (200) and disposed N-type heavily doped N-type epitaxial layer on a surface (200) of the substrate (201), disposed S12 column-shaped wide region (206) on the N-type epitaxial layer (201), S12-shaped wide column area (206) by a gentry upper surface of N type epitaxial layer extension (201) to the lower surface of the N-type epitaxial layer (201).
2.如权利要求1所述的高压超结MOSFET器件终端结构,其特征是:所述元胞区(202)和终端区(203)之间具有过渡区(207),所述过渡区(207)包括N型重掺杂衬底(200)、N型外延层(201)以及形成于该N型外延层(201)中的两个窄形P柱区(204),窄形P柱区(204)由N型外延层(201)的上表面朝下表面延伸,并且窄形P柱区(204)的下端与N型外延层(201)的下表面之间存在预设间距。 The transition zone (207 a transition region (207) between the cell region (202) and a terminal zone (203): as claimed in claim 1, said high voltage super junction MOSFET device termination structure, wherein ) comprises a heavily doped N-type substrate (200 is), the N-type epitaxial layer (201) and formed in the N type epitaxial layer (P column-shaped two narrow region (204) 201), narrow P column region ( 204) surface extending downward from the upper surface of the N-type epitaxial layer (201), and there is a predetermined spacing between the lower surface of the narrow P column-shaped region (204) and the lower end of the N-type epitaxial layer (201).
3.如权利要求1或2所述的高压超结MOSFET器件终端结构,其特征是:所述元胞区(202)包括N型重掺杂衬底(200)、N型外延层(201)及形成于所述N型外延层(201)中的窄形P柱区(204 )和『体区(205 ),『体区(205 )形成于窄形P柱区(204 )的上部;所述元胞区(202)的窄形P柱区(204)由N型外延层(201)的上表面朝下表面延伸,并且窄形P柱区(204)的下端与N型外延层(201)的下表面之间存在预设间距。 The high-pressure of claim 1 or claim 2 super junction MOSFET device termination structure, wherein: the cell region (202) comprises a heavily doped N-type substrate (200 is), the N-type epitaxial layer (201) and formed in the N type epitaxial layer (201) formed in the narrow region P column (204) and a "body region (205)," body region (205) formed in an upper portion of the P column region (narrow) (204); the N-type epitaxial layer (201) surface extending downward of the upper surface of the P column region (narrow) (204) of said cell region (202), and a narrow P column region (204) and the lower end of the N-type epitaxial layer (201 ) preset spacing is present between the lower surface.
4.如权利要求3所述的高压超结MOSFET器件终端结构,其特征是:所述N —体区(205)朝终端区(203)方向延伸,并与终端区(203)接触。 4. The high-pressure according to claim 3 super junction MOSFET device termination structure, wherein: the N - body region (205) extending in a direction toward the terminal area (203), and in contact with the terminal zone (203).
5.如权利要求3所述的高压超结MOSFET器件终端结构,其特征是:所述N —体区(205)朝过渡区(207 )方向延伸,并与过渡区(207 )的一个窄形P柱区(204 )接触。 A high voltage according to claim 3 super junction MOSFET device termination structure, wherein: the N - body region (205) extending in a direction towards the transition region (207), and the transition zone (207) to a Narrow P column region (204) in contact.
6.如权利要求1或2所述的高压超结MOSFET器件终端结构,其特征是:所述宽形S1 2柱区(206)的宽度为40〜100 μ m。 The high pressure or according to claim 12 super junction MOSFET device termination structure, wherein: the width of said wide column-shaped region S1 2 (206) is 40~100 μ m.
7.如权利要求3所述的高压超结MOSFET器件终端结构,其特征是:所述窄形P柱区(204)的宽度约为5 μ m。 7. The high-pressure according to claim 3 super junction MOSFET device termination structure, wherein: the width of said narrow shaped P column region (204) is about 5 μ m.
8.一种高压超结MOSFET器件终端结构的制作方法,其特征是,采用如下步骤: (1)提供具有N型重掺杂衬底和N型外延层的半导体基片; (2)在N型外延层的终端区进行刻蚀,得到一个由N型外延层上表面贯穿至N型外延层下表面的第一槽体,第一槽体的宽度为40〜10ym; (3)在第一槽体中淀积氧化层,形成宽形S12柱区; (4)采用CMP工艺将宽形S12柱区上表面进行磨平; (5)制作元胞区或者元胞区和过渡区。 A method of manufacturing a high pressure super junction termination structure MOSFET device, wherein, the following steps: (1) providing a substrate having a heavily doped N-type and N-type epitaxial layer of a semiconductor substrate; (2) N termination region type epitaxial layer is etched to obtain a penetrated by the N type epitaxial layer to a first surface of the tank at the surface of the N type epitaxial layer, the groove width of the first body is 40~10ym; (3) in a first depositing tank in the oxide layer, with a width of column-shaped regions S12; (4) a CMP process to form a wide polished surface S12 column area; (5) Preparation of cell region and a cell region or transition region.
9.如权利要求8所述的高压超结MOSFET器件终端结构的制作方法,其特征是:制作元胞区和过渡区时,具体包括: 在元胞区和过渡区的N型外延层上刻蚀形成第二槽体,第二槽体由N型外延层的上表面朝下表面方向延伸,并且第二槽体的底部与N型外延层的下表面之间存在预设的距离,第二槽体的宽度约为5 μΐΉ ; 在第二槽体中填充P型半导体层,形成窄形P柱区; 在元胞区的窄形P柱区的顶部进行注入和扩散,形成N—体区。 9. The high-pressure according to claim 8, wherein the super junction MOSFET manufacturing method of the structure of a terminal device, wherein: when making a transition region and a cell region, comprises: carved in the N type epitaxial layer cell region and a transition region forming a second etching tank, the second tank body extending from the upper surface of the N-type epitaxial layer surface downward direction, and there is a predetermined distance between the lower surface of the bottom and the N type epitaxial layer of the second tank, the second the width of the tank is about 5 μΐΉ; in the second tank is filled with a P-type semiconductor layer formed of the P column region narrow; implanting and diffusing P-shaped narrow at the top of column area of ​​the cell region, the body region forming N- .
10.一种高压超结MOSFET器件终端结构的制作方法,其特征是,采用如下步骤: (1)提供具有N型重掺杂衬底和N型外延层的半导体基片; (2)在N型外延层的终端区进行刻蚀,得到多个由N型外延层上表面贯穿至N型外延层下表面的第三槽体,第三槽体的宽度为2〜5 μΐϋ,第三槽体的宽度与第三槽体间距的比值为10:4 ; (3)在第三槽体中湿氧化生长氧化层,形成宽形S12柱区; (4)采用CMP工艺将宽形S12柱区上表面进行磨平; (5)制作元胞区或者元胞区和过渡区。 10. A high-pressure super-junction MOSFET manufacturing method of a terminal structure of the device, characterized in that the following steps are taken: (1) providing a substrate having a heavily doped N-type and N-type epitaxial layer of a semiconductor substrate; (2) N termination region type epitaxial layer is etched to obtain a plurality of through the N type epitaxial layer to the surface of the third tank at the surface of the N type epitaxial layer, the groove width of the third body is 2~5 μΐϋ, a third tank the width of the third tank pitch ratio of 10: 4; (3) a wet oxide grown oxide layer in the third tank, with a width of column-shaped regions S12; S12 column-shaped wide upper region (4) a CMP process polished surface; (5) Preparation of cell region and a cell region or transition region.
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US20050145933A1 (en) * 2003-10-29 2005-07-07 Yasuhiko Onishi Semiconductor device
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