CN104836461A - Intermittent boost converter controlled by switching period optimum utilization rate - Google Patents

Abstract

The present invention discloses an intermittent boost converter controlled by a switching period optimum utilization rate. The intermittent boost converter controlled by the switching period optimum utilization rate comprises a main power circuit and a control circuit, the structure of the control circuit is that the input end of a first bleeder circuit is connected with an input voltage sampling point, and the output end is connected with the inverting input end of a subtraction circuit; the input end of a second bleeder circuit is connected with the output voltage anode of the main power circuit, and the output end is connected with the non inverting input end of the subtraction circuit and the second input end of a multiplier separately; the output end of the subtraction circuit is connected with the first input end vx of the multiplier, the inverting input end of an error adjusting circuit is connected with the anode of an output voltage, and the non inverting input end of the error adjusting circuit is connected with a voltage reference signal; the output end of the error adjusting circuit is connected with the third input end of the multiplier, and the output end of the multiplier is connected with the input end of a chip UC3525A. According to the present invention, a critical inductance value is increased, the conversion efficiency is improved, at the same time, the output voltage ripple or output energy storage capacitance is also reduced.

Description

Adopt the interrupted booster converter that switch periods optimal utilization rate controls

Technical field

The present invention relates to the A.C.-D.C. converter technical field of electrical energy changer, particularly a kind of interrupted booster converter adopting switch periods optimal utilization rate to control.

Background technology

Power factor correction (Power Factor Correction, PFC) converter can reduce Harmonics of Input, improves input power factor, is used widely.Pfc converter is divided into active and passive two kinds of modes, and relative to passive mode, active mode has that input power factor is high, volume is little, low cost and other advantages.

Active PFC converter can adopt multiple circuit to open up and control method, wherein Boost pfc converter is one of conventional several pfc converters, according to continuous current mode whether, three kinds of mode of operations can be divided into, i.e. continuous current mode pattern (Continuous Current Mode, CCM), critical current mode continuous mode (Critical Continuous Current Mode, CRM), discontinous mode (Discontinuous Current Mode, DCM).

Wherein discontinuous conduct mode boosting power factor correcting converter has switching tube zero current turning-on, diode without Reverse recovery and the advantage such as switching frequency is constant, but owing to being operated in discontinuous mode, the transmission of energy does not take whole switch periods, its inductive current peak and effective value larger, switching tube and diode as the same, while exacerbates power device current stress, also bring the increase of conduction loss and switching tube turn-off power loss, affect the raising of efficiency.

Summary of the invention

The object of the present invention is to provide a kind of interrupted booster converter adopting switch periods optimal utilization rate to control, controlled by a kind of new switch periods optimal utilization rate, substantially increase threshold inductance value, reduce inductive current peak and effective value.

The technical solution realizing the object of the invention is: a kind of interrupted booster converter adopting switch periods optimal utilization rate to control, comprises converter main power circuit and control circuit: described converter main power circuit comprises input voltage source v _in, electromagnetic interface filter, diode rectifier circuit RB, Boost inductance L _b, switching tube Q _b, diode D _b, storage capacitor C _o, load R _ld; Wherein input voltage source v _inbe connected with the input port of electromagnetic interface filter, the output port of electromagnetic interface filter is connected with the input port of diode rectifier circuit RB, and the output negative pole of diode rectifier circuit RB is reference potential zero point, the output cathode of diode rectifier circuit RB and Boost inductance L _bone end connect, Boost inductance L _bthe other end respectively with switching tube Q _bdrain electrode and diode D _banode connect, switching tube Q _bsource electrode be connected zero point with reference potential, diode D _bnegative electrode respectively with storage capacitor C _oanode and load R _ldone end connect, storage capacitor C _onegative electrode and load R _ldthe other end be all connected zero point with reference potential;

Described control circuit comprises the first bleeder circuit, subtraction circuit, the second bleeder circuit, multiplier, regulating error circuit, chip UC3525A; The wherein input of the first bleeder circuit and input voltage sampled point V _gnamely the output cathode of diode rectifier circuit RB connects, and the output terminals A of the first bleeder circuit is connected with the inverting input of subtraction circuit, and the input of the second bleeder circuit connects the output voltage V of main power circuit _opositive pole, the output B of the second bleeder circuit respectively with the normal phase input end of subtraction circuit and the second input v of multiplier _zconnect, the output C of subtraction circuit and the first input end v of multiplier _xbe connected, the inverting input of regulating error circuit connects output voltage V _opositive pole, the normal phase input end of regulating error circuit connects voltage reference signal V _og, the output of regulating error circuit and the 3rd input v of multiplier _yconnect, the output P of multiplier is connected with the input of chip UC3525A.

Compared with prior art, its remarkable advantage is in the present invention: (1) threshold inductance value significantly increases, and inductive current peak and effective value reduce, and main power device current stress reduces, and the efficiency of converter improves; (2) Harmonics of Input meets IEC 61000-3-2Class D standard-required; (3) output voltage ripple reduces, especially when input voltage is higher.If keep the maximum ripple of output voltage constant, then storage capacitor value can be reduced to original 48.6% respectively.

Accompanying drawing explanation

Fig. 1 is Boost pfc converter main circuit.

Fig. 2 is DCM Boost pfc converter switch periods internal inductance current waveform.

Fig. 3 is DCM Boost pfc converter inductive current and mean value thereof and peak value waveform in half power frequency period.

Fig. 4 is the input current waveform in half power frequency period after standardization.

Fig. 5 is the PF curve chart under different situations.

Fig. 6 is the threshold inductance value under different input voltage.

Fig. 7 is the switch periods utilance curve in half power frequency period.

Fig. 8 is the inductive current waveform in pi/2 and 0 approximate angle switch periods, and wherein (a) is the inductive current oscillogram in pi/2 approximate angle switch periods, and (b) is the inductive current oscillogram in 0 approximate angle switch periods.

Fig. 9 is the graph of a relation of threshold inductance value and M and α, and wherein (a) is surface chart, and (b) is curve chart.

Figure 10 is the circuit structure diagram of the interrupted booster converter that the present invention adopts switch periods optimal utilization rate to control.

Figure 11 is switching tube drive singal and inductive current oscillogram, and wherein (a) determines Duty ratio control, and (b) is that switch periods optimal utilization rate controls (L _b2=92 μ H), (c) is that switch periods optimal utilization rate controls (L _b2=599 μ H).

Figure 12 is the input current waveform in half power frequency period.

Figure 13 is 3,5,7 subharmonic and the ratio of first-harmonic.

Figure 14 is 3,5,7 subharmonic and the ratio of power.

Figure 15 is the inductive current effective value under different input voltage.

Figure 16 is the inductive current peak in half power frequency period.

Figure 17 is Instantaneous input power perunit value in half power frequency period and output voltage waveforms.

Figure 18 is the ratio of the output voltage ripple under two kinds of control modes.

Embodiment

The operation principle of 1 DCM Boost pfc converter

Fig. 1 is main circuit.Fig. 2 gives the waveform of inductive current when working in DCM.Fig. 3 is in half power frequency period, inductive current and mean value thereof and peak value waveform.

The expression formula of input ac voltage is:

v _in＝V _msinωt (1)

In power frequency period, as duty ratio D _ytime fixing, suppose that the efficiency of converter is 100% (same afterwards), in [0-π], inductive current peak i in a switch periods _{lb_pk}, inductive current mean value i _{lb_ave}i.e. input current i _in, duty ratio D _y, inductive current D fall time _rbe respectively with power factor PF

$i_{\mathrm{Lb}\_\mathrm{pk}}=\frac{V_m\sin \mathrm{\ωt}\·D_y}{L_b{f}_s}---\left(2\right)$

$i_{\mathrm{in}}=i_{\mathrm{Lb}\_\mathrm{ave}}=\frac{V_m{D}_y^2}{2L_b{f}_s}\frac{\sin \mathrm{\ωt}}{1-\mathrm{\α}\left|\sin \mathrm{\ωt}\right|}---\left(3\right)$

$D_y=\frac{1}{V_m}\sqrt{\frac{2\mathrm{\π}{L}_b{f}_s{P}_o}{{\∫}_0^{\mathrm{\π}}\frac{{\sin }^2\mathrm{\ωt}}{1-\mathrm{\α}\left|\sin \mathrm{\ωt}\right|}\mathrm{d\ωt}}}---\left(4\right)$

$D_R=\frac{v_g}{V_o-v_g}{D}_y=\frac{\mathrm{\α}\left|\sin \mathrm{\ωt}\right|}{1-\mathrm{\α}\left|\sin \mathrm{\ωt}\right|}{D}_y---\left(5\right)$

$\mathrm{PF}=\frac{\sqrt{\frac{2}{\mathrm{\π}}}{\∫}_0^{\mathrm{\π}}\frac{{\sin }^2\mathrm{\ωt}}{1-\mathrm{\α}\left|\sin \mathrm{\ωt}\right|}\mathrm{d\ωt}}{\sqrt{{\∫}_0^{\mathrm{\π}}{\left(\frac{\sin \mathrm{\ωt}}{1-\mathrm{\α}\left|\sin \mathrm{\ωt}\right|}\right)}^2\mathrm{d\ωt}}}---\left(6\right)$

Wherein α=V _m/ V _o, V _mamplitude and the angular frequency of input voltage is respectively, V with ω _ofor output voltage, P _ofor power output, f _sfor switching frequency.

In order to easy analysis, with for fiducial value, by formula (3) standardization be under can being made in different α situation, in half power frequency period waveform, as shown in Figure 4.Can find out, the shape of input current is only relevant with α, and α is less, and input current is more close to sine.This is because inductive current ascent stage, its mean value is sinusoidal form; And in the inductive current decline stage, descending slope is relevant with α, α is less, and inductive current declines faster, and the mean value of this stage inductive current is more close to 0, thus the mean value of electric current is close to sine in whole switch periods, and PF value is more close to 1.

Within the scope of 175V ~ 265V ac input voltage, when output voltage is 400V, 0.62≤α≤0.94, can make the curve of PF, as shown in Figure 5 according to formula (6).As can be seen from the figure, α is larger, and PF value is lower.

Formula (4) is substituted into formula (3) carry out Fourier decomposition to it, can obtain the first-harmonic and 3 under each input voltage, 5,7 subharmonic current values, thus the ratio of harmonic wave and first-harmonic and input power can be obtained, respectively as shown in Figure 13 and Figure 14.As can be seen from Figure 13, main containing being 3 subharmonic of π with fundamental phase difference in input current, input voltage is higher, and this 3 subharmonic content is larger.

The proposition that 2 switch periods optimal utilization rates control

For the ease of analyzing, proposing the concept of switch periods utilance, being defined as β,

β＝D _y+D _R(7)

Formula (5) is substituted into formula (7) obtain

β＝D _yV _o/(V _o-V _m|sinωt|) (8)

For making discontinuous current mode, β≤1 must be met.

Formula (4) is substituted into formula (8), can obtain

$L_b\≤\frac{V_m^2{(1-\mathrm{\α}|\sin \mathrm{\ωt}\left|\right)}^2}{2\mathrm{\π}{f}_s{P}_o}{\∫}_0^{\mathrm{\π}}\frac{{\sin }^2\mathrm{\ωt}}{1-\mathrm{\α}\left|\sin \mathrm{\ωt}\right|}\mathrm{d\ωt}---\left(9\right)$

As can be seen from the above equation, transducer parameters one timing, in half power frequency period, threshold inductance value that all angles place requires is different, and wherein, threshold inductance value corresponding to pi/2 place is minimum, and the threshold inductance value of namely determining under Duty ratio control is

$L_{b1}=\frac{V_m^2{(1-\mathrm{\α})}^2}{2\mathrm{\π}{f}_s{P}_o}{\∫}_0^{\mathrm{\π}}\frac{{\sin }^2\mathrm{\ωt}}{1-\mathrm{\α}\left|\sin \mathrm{\ωt}\right|}\mathrm{d\ωt}---\left(10\right)$

The design parameter (Section six provides) of associative transformation device, can obtain Fig. 6 by formula (10), can find out, when determining Duty ratio control, threshold inductance value is 92 μ H.By L _b1=92 μ H and formula (4) substitute into formula (10), when can to make input voltage be 175V, 220V and 265V, and β ₁curve in half power frequency period [0, π] scope, as Fig. 7.As can be seen from Figure 7, under each input voltage, β ₁in [0, pi/2], become increasing trend, minimum near angle 0, namely switch periods utilance is low, and discontinuous current mode degree is the highest, maximum near angle pi/2, and namely switch periods utilance is high, and discontinuous current mode degree is minimum.

Fig. 8 gives the waveform of the inductive current in half power frequency period near pi/2 and 0 in switch periods, make following imagination, the threshold inductance value that maintenance is determined under Duty ratio control is constant, slightly duty ratio is reduced at pi/2 approximate angle, then switch periods utilance also corresponding reduction, discontinuous current mode degree increases; And in order to keep power output constant, near angle 0, needing the corresponding duty ratio that slightly increases, the also corresponding increase of switch periods utilance, discontinuous current mode degree reduces.Reduce further near pi/2 and 0 and increase duty ratio, the switch periods utilance so near respective angles will reduce further and increase, and discontinuous current degree also will increase further and reduce.In other words, along with the difference of the duty ratio near pi/2 and 0 progressively expands, β ₁close to 1 that is inductive current close to critical continuous mode switch periods residing for power frequency angle transit near 0 near pi/2 gradually.Can predict, in the process, there is the duty ratio by the change of certain rule, make [0, pi/2] in all lower i.e. discontinuous current mode degree of the switch periods utilance at arbitrarily angled place comparatively large, thus can increase threshold inductance value on the basis of original Duty ratio control, to improve switch periods utilance and to reduce discontinuous current mode degree, thus reduce inductive current peak and effective value, improve conversion efficiency.Below will to this labor.

According to above imagination, need to reduce and increase duty ratio near pi/2 and 0, and the input voltage of converter is sinusoidal form, studies SIN function to be introduced in change in duty cycle rule herein, to realize switch periods optimal utilization rate.The duty ratio expression formula that definition switch periods optimal utilization rate controls

D _y＝D ₀(1-M|sinωt|) (11)

Wherein M is undetermined coefficient, D ₀with relating to parameters such as M and converter input and output voltage, power output, switching frequency and inductance value.

The calculating of 3 maximum threshold inductance values

Formula (11) is substituted into formula (3), and can obtain input current expression formula is

$i_{\mathrm{in}}=\frac{V_m{D}_0^2{(1-M|\sin \mathrm{\ωt}\left|\right)}^2}{2L_b{f}_s}\frac{\sin \mathrm{\ωt}}{1-\mathrm{\α}\left|\sin \mathrm{\ωt}\right|}---\left(12\right)$

The power output that can be obtained converter by formula (1) and formula (12) is

$\begin{array}{c}{P}_o=P_{\mathrm{in}}=\frac{1}{\mathrm{\π}}{\∫}_0^{\mathrm{\π}}{v}_{\mathrm{in}}{i}_{\mathrm{in}}\mathrm{d\ωt}\\ =\frac{V_m^2{D}_0^2}{2\mathrm{\π}{L}_b{f}_s}{\∫}_0^{\mathrm{\π}}\frac{{\sin }^2\mathrm{\ωt}{(1-M|\sin \mathrm{\ωt}\left|\right)}^2}{1-\mathrm{\α}\left|\sin \mathrm{\ωt}\right|}\mathrm{d\ωt}\end{array}---\left(13\right)$

Can be obtained by formula (13)

$D_0=\frac{1}{V_m}\sqrt{\frac{2\mathrm{\π}{L}_b{f}_s{P}_o}{{\∫}_0^{\mathrm{\π}}\frac{{\sin }^2\mathrm{\ωt}{(1-M|\sin \mathrm{\ωt}\left|\right)}^2}{1-\mathrm{\α}\left|\sin \mathrm{\ωt}\right|}\mathrm{d\ωt}}}---\left(14\right)$

Formula (14) is under a certain M value, during converter steady operation, and the D in duty ratio expression formula (11) ₀with the relation of other parameters of circuit.

Formula (15) is substituted into formula (11), can obtain

$D_y=\frac{\frac{1}{V_m}\sqrt{2\mathrm{\π}{L}_b{f}_s{P}_o}(1-M|\sin \mathrm{\ωt}\left|\right)}{\sqrt{{\∫}_0^{\mathrm{\π}}\frac{{\sin }^2\mathrm{\ωt}{(1-M|\sin \mathrm{\ωt}\left|\right)}^2}{1-\mathrm{\α}\left|\sin \mathrm{\ωt}\right|}\mathrm{d\ωt}}}---\left(15\right)$

Formula (15) is substituted into formula (8), can obtain

$L_b\≤\frac{\frac{V_m^2}{2\mathrm{\π}{P}_o{f}_s}{\∫}_0^{\mathrm{\π}}\frac{{\sin }^2\mathrm{\ωt}{(1-M|\sin \mathrm{\ωt}\left|\right)}^2}{1-\mathrm{\α}\left|\sin \mathrm{\ωt}\right|}\mathrm{d\ωt}}{{\left(\frac{1-M\left|\sin \mathrm{\ωt}\right|}{1-\mathrm{\α}\left|\sin \mathrm{\ωt}\right|}\right)}^2}---\left(16\right)$

Carry out analysis to above formula known, as M >=α, obtain minimum value at ω t=0 place, as M< α, it obtains minimum value at ω t=pi/2 place, and so threshold inductance value is

$L_{b2}(M,\mathrm{\&alpha;})=\left\{\begin{array}{cc}\frac{V_m^2}{2\mathrm{\&pi;}{P}_o{f}_s}{\&Integral;}_0^{\mathrm{\&pi;}}\frac{{\sin }^2\mathrm{\&omega;t}{(1-M|\sin \mathrm{\&omega;t}\left|\right)}^2}{1-\mathrm{\&alpha;}\left|\sin \mathrm{\&omega;t}\right|}\mathrm{d\&omega;t}& M\&GreaterEqual;\mathrm{\&alpha;}\\ \frac{\frac{V_m^2}{2\mathrm{\&pi;}{P}_o{f}_s}{\&Integral;}_0^{\mathrm{\&pi;}}\frac{{\sin }^2\mathrm{\&omega;t}{(1-M|\sin \mathrm{\&omega;t}\left|\right)}^2}{1-\mathrm{\&alpha;}\left|\sin \mathrm{\&omega;t}\right|}\mathrm{d\&omega;t}}{{\left(\frac{1-M}{1-\mathrm{\&alpha;}}\right)}^2}& M<\mathrm{\&alpha;}\end{array}\right.---\left(17\right)$

Can be made the graph of a relation of threshold inductance value and M and α by formula (17), as Fig. 9, convolution (17) is known with Fig. 9, as M> α, and L _b2for subtraction function, as M≤α, L _b2for increasing function, therefore L during M=α _b2obtain maximum.M=α is substituted into formula (15) and formula (17), and duty ratio and the threshold inductance value that can obtain the control of switch periods optimal utilization rate are respectively

$D_y=\frac{1}{V_m}\sqrt{\frac{2\mathrm{\&pi;}{L}_b{f}_s{P}_o}{{\&Integral;}_0^{\mathrm{\&pi;}}{\sin }^2\mathrm{\&omega;t}(1-\mathrm{\&alpha;}|\sin \mathrm{\&omega;t}\left|\right)\mathrm{d\&omega;t}}}(1-\mathrm{\&alpha;}|\sin \mathrm{\&omega;t}\left|\right)---\left(18\right)$

$L_{b2}=\frac{V_m^2}{2\mathrm{\&pi;}{P}_o{f}_s}{\&Integral;}_0^{\mathrm{\&pi;}}{\sin }^2\mathrm{\&omega;t}(1-\mathrm{\&alpha;}|\sin \mathrm{\&omega;t}\left|\right)\mathrm{d\&omega;t}---\left(19\right)$

The design parameter of associative transformation device, can obtain Fig. 6 by formula (19).Can find out, the threshold inductance value under switch periods optimal utilization rate controls is 599 μ H, and determines compared with duty ratio, and threshold inductance value significantly increases.

4 performance comparison

4.1 switch periods utilances

The design parameter of associative transformation device, can be made respectively by formula (8) and formula (18) adopts switch periods optimal utilization rate to control, inductance value is 92 μ H and 599 μ H, and switch periods utilance when input voltage is 175V, 220V and 265V, as the β in Fig. 7 ₃and β ₂shown in.

Figure 11 sets forth and determines Duty ratio control, in three kinds of situations that switch periods optimal utilization rate controls (maintaining the constant and inductance value of former inductance value to increase), and switching tube drive singal and inductive current waveform schematic diagram.

As can be seen from Fig. 7 and Figure 11 (a), when Duty ratio control is determined in employing, when input voltage angle changes from 0 to pi/2, switch periods utilance raises gradually, discontinuous current mode degree reduces gradually, variation tendency in [pi/2, π] interval is symmetrical consistent with [0, pi/2].The switch periods utilance at pi/2 place is the highest, and 0 and π place minimum.Input voltage effective value is higher, and the difference of utilance maximal and minmal value is larger.When input voltage is 265V, the utilance at pi/2 place is 1.

As can be seen from Fig. 7 and Figure 11 (b), when adopting switch periods optimal utilization rate to control, if keep the threshold inductance value under original Duty ratio control constant, the switch periods utilance of pi/2 approximate angle reduces, discontinuous current mode degree increases, and the change of 0 angle accessory is contrary.In [0, π], the switch periods utilance at arbitrarily angled place is equal and be less than 1, and therefore, switch periods utilance has the space of improving further.

As can be seen from Fig. 7 and Figure 11 (c), switch periods optimal utilization rate is adopted to control and under corresponding inductance value, [0, π] in, the switch periods utilance at arbitrarily angled place is equal, and when input voltage is 265V, utilance is 1, when input voltage is 175V and 220V, utilance is close to 1.

4.2 input power factors and current harmonics

Can be obtained by formula (1), formula (3) and formula (18)

$\begin{array}{c}\mathrm{PF}=\frac{P_{\mathrm{in}}}{V_{\mathrm{in}\_\mathrm{rms}}{I}_{\mathrm{in}\_\mathrm{rms}}}=\frac{\frac{1}{\mathrm{\&pi;}}{\&Integral;}_0^{\mathrm{\&pi;}}{v}_{\mathrm{in}}{i}_{\mathrm{in}}\mathrm{d\&omega;t}}{\frac{V_m}{\sqrt{2}}\sqrt{\frac{1}{\mathrm{\&pi;}}{\&Integral;}_0^{\mathrm{\&pi;}}{i}_{\mathrm{in}}^2\mathrm{d\&omega;t}}}\\ =\frac{\sqrt{\frac{2}{\mathrm{\&pi;}}}{\&Integral;}_0^{\mathrm{\&pi;}}{\sin }^2\mathrm{\&omega;t}(1-\mathrm{\&alpha;}|\sin \mathrm{\&omega;t}\left|\right)\mathrm{d\&omega;t}}{\sqrt{{\&Integral;}_0^{\mathrm{\&pi;}}{\sin }^2\mathrm{\&omega;t}{(1-\mathrm{\&alpha;}|\sin \mathrm{\&omega;t}\left|\right)}^2\mathrm{d\&omega;t}}}\end{array}---\left(20\right)$

Corresponding PF curve can be made, as shown in Figure 5 by formula (20).As can be seen from the figure, and determine compared with Duty ratio control, switch periods optimal utilization rate controls lower PF value reduction.

Formula (4) and formula (18) are substituted into formula (3) respectively, obtain determine Duty ratio control and switch periods optimal utilization rate control under input current be

$i_{\mathrm{in}}=\frac{\mathrm{\&pi;}{P}_o}{V_m}\frac{\frac{\sin \mathrm{\&omega;t}}{1-\mathrm{\&alpha;}\left|\sin \mathrm{\&omega;t}\right|}}{{\&Integral;}_0^{\mathrm{\&pi;}}\frac{{\sin }^2\mathrm{\&omega;t}}{1-\mathrm{\&alpha;}\left|\sin \mathrm{\&omega;t}\right|}\mathrm{d\&omega;t}}---\left(21\right)$

$i_{\mathrm{in}}=\frac{\mathrm{\&pi;}{P}_o\sin \mathrm{\&omega;t}[1-\mathrm{\&alpha;}|\sin \mathrm{\&omega;t}\left|\right]}{V_m{\&Integral;}_0^{\mathrm{\&pi;}}{\sin }^2\mathrm{\&omega;t}[1-\mathrm{\&alpha;}|\sin \mathrm{\&omega;t}\left|\right]\mathrm{d\&omega;t}}---\left(22\right)$

By α=V _m/ V _osubstitute into above formula, the input current waveform under two kinds of control can be made by formula (21), (22), as shown in figure 12.

Fourier decomposition is carried out to formula (22), can obtain switch periods optimal utilization rate control lower first-harmonic and 3,5,7 subharmonic current values, thus the ratio of harmonic wave and first-harmonic and input power can be obtained, distinguish as shown in Figure 13 and Figure 14.

As can be seen from Figure 13, and determine compared with Duty ratio control, after adopting switch periods optimal utilization rate to control, in whole input voltage range, input voltage one timing, 3 subharmonic amplitudes become large, and phase place is contrary, 5 times and the reduction of 7 subharmonic amplitudes.IEC 61000-3-2, Class C specifies, input current 3,5,7 subharmonic should be less than 0.3 λ, 0.1,0.07 and 0.05 with the ratio of first-harmonic, and wherein λ is input power factor.Convolution (22) can obtain 3 subharmonic limit values, as shown in figure 13.Can find out, in 175-265V input voltage range, 7 subharmonic meet standard-required, and input voltage higher than 196V and 259V time, 3 times and 5 subharmonic exceed standard limited value respectively.Therefore, if converter occasion used will meet IEC 61000-3-2Class C standard, must compromise between 3,5 subharmonic limit values and switch periods optimal utilization, the duty cycle functions of converter of namely again deriving according to harmonic limits, and do correlated performance analysis.

According to IEC 61000-3-2, Class D to the regulation of pfc converter input current, 3,5,7 subharmonic effective values and the ratio of input power should be less than 3.4 respectively, 1.9,1.0mA/W.As can be seen from Figure 14, the Harmonics of Input under two kinds of control modes all meets standard-required.In general, DCM Boost pfc converter is mainly used in middle low power applications, is generally tens of to hundreds of watts, and therefore, converter must meet Class A, Class D and Class B to the requirement of the maximum effective value of harmonic current.

The design of 4.3 inductance and the change of inductive current effective value and peak value

Power frequency period internal inductance current effective value I _{lb_rms}for

$I_{\mathrm{Lb}\_\mathrm{rms}}=\frac{V_m{T}_s}{L_b}\sqrt{\frac{1}{\mathrm{\&pi;}}{\&Integral;}_0^{\mathrm{\&pi;}}\frac{V_o{D}_y^3{\left(\sin \mathrm{\&omega;t}\right)}^2}{3(V_o-V_m|\sin \mathrm{\&omega;t}\left|\right)}\mathrm{d\&omega;t}}---\left(23\right)$

By formula (4), L _b1=92 μ H and formula (20), L _b2=599 μ H, substitute into formula (23) respectively, can obtain the inductive current effective value I under two kinds of control modes _{lb1_rms}and I _{lb2_rms}, as shown in figure 15.Can find out, and determine compared with Duty ratio control, after adopting switch periods optimal utilization rate to control, inductive current effective value reduces, and the current effective value of the main power devices such as switching tube is also corresponding to diminish, and is conducive to the conduction loss reducing converter, improves conversion efficiency.

By formula (4), L _b1=92 μ H and formula (18), L _b2=599 μ H substitute into formula (2) respectively, and when can to obtain input voltage be 175V, 220V and 265V, the inductive current peak curve under two kinds of control modes, as Figure 16.As can be seen from the figure, with determine compared with Duty ratio control, after adopting switch periods optimal utilization rate to control, inductive current peak under each input voltage all reduces, when input voltage is 175V, inductive current peak (i.e. the peak current of switching tube and diode) is reduced to 1.66A from 4.88A, and current stress significantly reduces.

By L _b1=92 μ H, I _{lb_pk_max}=4.88A, I _{lb_rms_max}=1.30A and L _b2=599 μ H, I _{lb_pk_max}=1.66A, I _{lb_rms_max}=0.81A substitutes into the Packing coefficient K of formula magnetic core respectively _ucan obtain with the computing formula of air gap delta, after adopting switch periods optimal utilization rate to control, K _usubstantially constant with δ, the magnetic core identical with determining Duty ratio control can be used.Its reason is, although inductance value increases, its current peak and effective value significantly reduce.

The reduction of 4.4 output voltage ripples

By formula (1), formula (21) and formula (22) can obtain converter determine duty ratio and switch periods optimal utilization rate control under Instantaneous input power be respectively

$p_{\mathrm{in}1}=v_{\mathrm{in}}{i}_{\mathrm{in}}=\frac{\mathrm{\&pi;}{P}_o{\sin }^2\mathrm{\&omega;t}}{1-\mathrm{\&alpha;}\left|\sin \mathrm{\&omega;t}\right|}/{\&Integral;}_0^{\mathrm{\&pi;}}\frac{{\sin }^2\mathrm{\&omega;t}}{1-\mathrm{\&alpha;}\left|\sin \mathrm{\&omega;t}\right|}\mathrm{d\&omega;t}---\left(24\left(a\right)\right)$

$p_{\mathrm{in}2}=v_{\mathrm{in}}{i}_{\mathrm{in}}=\frac{\mathrm{\&pi;}{P}_o{\sin }^2\mathrm{\&omega;t}(1-\mathrm{\&alpha;}|\sin \mathrm{\&omega;t}\left|\right)}{{\&Integral;}_0^{\mathrm{\&pi;}}{\sin }^2\mathrm{\&omega;t}(1-\mathrm{\&alpha;}|\sin \mathrm{\&omega;t}\left|\right)\mathrm{d\&omega;t}}---\left(24\left(b\right)\right)$

Thus Instantaneous input power perunit value is respectively

$p_{\mathrm{in}1}^{*}=\frac{p_{\mathrm{in}1}}{P_o}=\frac{\mathrm{\&pi;}{\sin }^2\mathrm{\&omega;t}}{1-\mathrm{\&alpha;}\left|\sin \mathrm{\&omega;t}\right|}/{\&Integral;}_0^{\mathrm{\&pi;}}\frac{{\sin }^2\mathrm{\&omega;t}}{1-\mathrm{\&alpha;}\left|\sin \mathrm{\&omega;t}\right|}\mathrm{d\&omega;t}---\left(25\left(a\right)\right)$

$p_{\mathrm{in}2}^{*}=\frac{p_{\mathrm{in}2}}{P_o}=\frac{\mathrm{\&pi;}{\sin }^2\mathrm{\&omega;t}(1-\mathrm{\&alpha;}|\sin \mathrm{\&omega;t}\left|\right)}{{\&Integral;}_0^{\mathrm{\&pi;}}{\sin }^2\mathrm{\&omega;t}(1-\mathrm{\&alpha;}|\sin \mathrm{\&omega;t}\left|\right)\mathrm{d\&omega;t}}---\left(25\left(b\right)\right)$

Can make input voltage by formula (25) is 220V, the change curve of Instantaneous input power perunit value in half power frequency period under two kinds of control modes, as shown in figure 17.When time, storage capacitor C _ocharging; When time, C _oelectric discharge.From ω t=0, with the time shaft coordinate corresponding with first intersection point of 1 is respectively t ₁and t ₂and t ₁' and t' ₂.

Order at half power frequency period [0, π] in analysis is carried out to equation root can obtain, when α≤-1 or α>=1, equation without solution, during-1< α <1, equation has 2 real solutions, from the analysis of Section 2, α scope is 0.62≤α≤0.94, therefore, equation has two real solutions, is respectively

$\mathrm{\&omega;}{t}_1=\arcsin [(\sqrt{{\mathrm{\&alpha;}}^2{m}^2+4m}-\mathrm{\&alpha;m})/2]---\left(26\left(a\right)\right)$

$\mathrm{\&omega;}{t}_2=\mathrm{\&pi;}-\arcsin [(\sqrt{{\mathrm{\&alpha;}}^2{m}^2+4m}-\mathrm{\&alpha;m})/2]---\left(26\left(b\right)\right)$

Wherein $m=\frac{1}{\mathrm{\&pi;}}\{-\frac{2}{\mathrm{\&alpha;}}-\frac{\mathrm{\&pi;}}{{\mathrm{\&alpha;}}^2}+\frac{2}{{\mathrm{\&alpha;}}^2\sqrt{1-{\mathrm{\&alpha;}}^2}}[\frac{\mathrm{\&pi;}}{2}+\arctan \left(\frac{\mathrm{\&alpha;}}{\sqrt{1-{\mathrm{\&alpha;}}^2}}\right)\left]\right\}.$

Order in half power frequency period, equattion root is analyzed,

As 0.62≤α <0.87, equation has two real roots, is respectively

${\mathrm{\&omega;t}}_1^{\&prime;}=\arcsin \left\{\right[1+2\sin (\frac{\mathrm{\&pi;}}{6}-\frac{\mathrm{\&theta;}}{3})]/2\}---\left(27\left(a\right)\right)$

${\mathrm{\&omega;t}}_2^{\&prime;}=\mathrm{\&pi;}-\arcsin \left\{\right[1+2\sin (\frac{\mathrm{\&pi;}}{6}-\frac{\mathrm{\&theta;}}{3})]/2\}---\left(27\left(b\right)\right)$

When α=0.87, equation has three real roots, is respectively

${\mathrm{\&omega;t}}_1^{\&prime;}=\arcsin \left\{\right[1+2\sin (\frac{\mathrm{\&pi;}}{6}-\frac{\mathrm{\&theta;}}{3})]/2\}---\left(28\left(a\right)\right)$

ωt' ₂＝π/2 (28(b))

${\mathrm{\&omega;t}}_3^{\&prime;}=\mathrm{\&pi;}-\arcsin \left\{\right[1+2\sin (\frac{\mathrm{\&pi;}}{6}-\frac{\mathrm{\&theta;}}{3})]/2\}---\left(28\left(c\right)\right)$

When 0.87< α≤0.94, equation has four real roots, is respectively

${\mathrm{\&omega;t}}_1^{\&prime;}=\arcsin \left\{\right[1+2\sin (\frac{\mathrm{\&pi;}}{6}-\frac{\mathrm{\&theta;}}{3})]/2\}---\left(29\left(a\right)\right)$

${\mathrm{\&omega;t}}_2^{\&prime;}=\arcsin \left\{\right[1+2\sin (\frac{\mathrm{\&pi;}}{6}+\frac{\mathrm{\&theta;}}{3})]/2\}---\left(29\left(b\right)\right)$

${\mathrm{\&omega;t}}_3^{\&prime;}=\mathrm{\&pi;}-\arcsin \left\{\right[1+2\sin (\frac{\mathrm{\&pi;}}{6}+\frac{\mathrm{\&theta;}}{3})]/2\}---\left(29\left(c\right)\right)$

${\mathrm{\&omega;t}}_4^{\&prime;}=\mathrm{\&pi;}-\arcsin \left\{\right[1+2\sin (\frac{\mathrm{\&pi;}}{6}-\frac{\mathrm{\&theta;}}{3})]/2\}---\left(29\left(d\right)\right)$

Wherein $\mathrm{\&theta;}=\arccos [(\frac{27}{4}-\frac{2}{3\mathrm{\&pi;}})\mathrm{\&alpha;}-1].$

Can be obtained by formula (24), the instantaneous power in output capacitance is respectively

$p_{c1}=P_o(\frac{\mathrm{\&pi;}{\sin }^2\mathrm{\&omega;t}}{1-\mathrm{\&alpha;}\left|\sin \mathrm{\&omega;t}\right|}/{\&Integral;}_0^{\mathrm{\&pi;}}\frac{{\sin }^2\mathrm{\&omega;t}}{1-\mathrm{\&alpha;}\left|\sin \mathrm{\&omega;t}\right|}\mathrm{d\&omega;t}-1)---\left(30\left(a\right)\right)$

$p_{c2}=P_o(\frac{\mathrm{\&pi;}{\sin }^2\mathrm{\&omega;t}(1-\mathrm{\&alpha;}|\sin \mathrm{\&omega;t}\left|\right)}{{\&Integral;}_0^{\mathrm{\&pi;}}{\sin }^2\mathrm{\&omega;t}(1-\mathrm{\&alpha;}|\sin \mathrm{\&omega;t}\left|\right)\mathrm{d\&omega;t}}-1)---\left(30\left(b\right)\right)$

Convolution (30) can obtain the energy that electric capacity stores and be respectively

$E_{c1}=\frac{1}{2}{\mathrm{Cv}}_{c1}^2=\frac{1}{2}{\mathrm{CV}}_o^2+\frac{1}{\mathrm{\&omega;}}{\&Integral;}_0^{\mathrm{\&omega;t}}{p}_{c1}\mathrm{d\&omega;t}---\left(31\left(a\right)\right)$

$E_{c2}=\frac{1}{2}{\mathrm{Cv}}_{c2}^2=\frac{1}{2}{\mathrm{CV}}_o^2+\frac{1}{\mathrm{\&omega;}}{\&Integral;}_0^{\mathrm{\&omega;t}}{p}_{c2}\mathrm{d\&omega;t}---\left(31\left(b\right)\right)$

The instantaneous output voltage that can be obtained under two kinds of control by formula (30-31) is

$v_{c1}=\sqrt{V_o^2+\frac{2P_o}{\mathrm{\&omega;C}}{\&Integral;}_0^{\mathrm{\&omega;t}}(\frac{\frac{\mathrm{\&pi;}{\sin }^2\mathrm{\&omega;t}}{1-\mathrm{\&alpha;}\left|\sin \mathrm{\&omega;t}\right|}}{{\&Integral;}_0^{\mathrm{\&pi;}}\frac{{\sin }^2\mathrm{\&omega;t}}{1-\mathrm{\&alpha;}\left|\sin \mathrm{\&omega;t}\right|}\mathrm{d\&omega;t}}-1)\mathrm{d\&omega;t}}---\left(32\left(a\right)\right)$

$v_{c2}=\sqrt{V_o^2+\frac{2P_o}{\mathrm{\&omega;C}}{\&Integral;}_0^{\mathrm{\&omega;t}}[\frac{\mathrm{\&pi;}{\sin }^2\mathrm{\&omega;t}(1-\mathrm{\&alpha;}|\sin \mathrm{\&omega;t}\left|\right)}{{\&Integral;}_0^{\mathrm{\&pi;}}{\sin }^2\mathrm{\&omega;t}(1-\mathrm{\&alpha;}|\sin \mathrm{\&omega;t}\left|\right)\mathrm{d\&omega;t}}-1]\mathrm{d\&omega;t}}---\left(32\left(b\right)\right)$

The design parameter of associative transformation device, can obtain the output voltage waveforms under two kinds of control by formula (32), as shown in figure 17.Can find out, in half power frequency period [0, π], when Duty ratio control is determined in employing, input power perunit value and 1 has and only has 2 intersection points, and input voltage is higher, first intersection point ω t ₁more away from 0, the area surrounded with 1 is larger, and corresponding output voltage ripple is larger.When adopting switch periods optimal utilization rate to control, input power perunit value and 1 intersection point number have 2,3 ( tangent at pi/2 place with 1), 4 three kinds of situations, corresponding input voltage range is respectively 0.62≤α <0.87 and 175V≤V _rms<246V, α=0.87 i.e. V _rms=246V, 0.87< α≤0.94 i.e. 246V<V _rms≤ 265V, input voltage is higher, first intersection point ω t ₁' the closer to 0, the area surrounded with 1 is less, and corresponding output voltage ripple is less.

Storage capacitor C _othe ceiling capacity perunit value (fiducial value is the output energy in half power frequency period) stored in half power frequency period is respectively

${\mathrm{\&Delta;E}}_1^{*}=2{\&Integral;}_0^{{\mathrm{\&omega;t}}_1}(1-p_{\mathrm{in}1}^{*})\mathrm{d\&omega;t}/\mathrm{\&pi;}---\left(33\left(a\right)\right)$

${\mathrm{\&Delta;E}}_2^{*}=2{\&Integral;}_0^{{\mathrm{\&omega;t}}_1^{\&prime;}}(1-p_{\mathrm{in}2}^{*})\mathrm{d\&omega;t}/\mathrm{\&pi;}---\left(33\left(b\right)\right)$

According to the computing formula of capacitance energy storage, this ceiling capacity perunit value can be expressed as again

${\mathrm{\&Delta;E}}_1^{*}=\frac{\frac{1}{2}{C}_o{(V_o+\frac{\mathrm{\&Delta;}{V}_{o1}}{2})}^2-\frac{1}{2}{C}_o{(V_o-\frac{\mathrm{\&Delta;}{V}_{o1}}{2})}^2}{P_o{T}_{\mathrm{line}}/2}=\frac{2C_o{V}_o\mathrm{\&Delta;}{V}_{o1}}{P_o{T}_{\mathrm{line}}}---\left(34\left(a\right)\right)$

${\mathrm{\&Delta;E}}_2^{*}=\frac{\frac{1}{2}{C}_o{(V_o+\frac{\mathrm{\&Delta;}{V}_{o2}}{2})}^2-\frac{1}{2}{C}_o{(V_o-\frac{\mathrm{\&Delta;}{V}_{o2}}{2})}^2}{P_o{T}_{\mathrm{line}}/2}=\frac{2C_o{V}_o\mathrm{\&Delta;}{V}_{o2}}{P_o{T}_{\mathrm{line}}}---\left(34\left(b\right)\right)$

Wherein Δ V _o1with Δ V _o2be respectively the output voltage ripple value under two kinds of control.

Can be obtained by formula (33-34)

$\mathrm{\&Delta;}{V}_{o1}=2P_o{\&Integral;}_0^{{\mathrm{\&omega;t}}_1}(1-p_{\mathrm{in}1}^{*})\mathrm{d\&omega;t}/\mathrm{\&omega;}{C}_o{V}_o---\left(35\left(a\right)\right)$

$\mathrm{\&Delta;}{V}_{o2}=2P_o{\&Integral;}_0^{{\mathrm{\&omega;t}}_2}(1-p_{\mathrm{in}2}^{*})\mathrm{d\&omega;t}/\mathrm{\&omega;}{C}_o{V}_o---\left(35\left(b\right)\right)$

Simultaneous formula (26-29) and (35), and by α=V _m/ V _osubstitute into, the design parameter of associative transformation device, can obtain Figure 18.Can find out, when input voltage changes between 175-265VAC, the output voltage ripple determined under Duty ratio control increases to 7.0V gradually from 5.1V, and the output voltage ripple under switch periods optimal utilization rate controls is reduced to 2.2V gradually from 3.4V.With determine compared with Duty ratio control, the output voltage ripple under switch periods optimal utilization rate controls significantly reduces.In other words, if keep the maximum ripple of output voltage constant, storage capacitor value can be reduced to original 48.6%.

The interrupted booster converter that 5 the present invention adopt switch periods optimal utilization rate to control

In conjunction with Figure 10, input voltage v _gthrough the first resistance R ₁with the second resistance R ₂dividing potential drop obtains v _a=k _vgv _m| sin ω t|, k _vgdividing potential drop coefficient, k _vg=R ₁/ (R ₁+ R ₂).Output voltage V _othrough the 7th resistance R ₇with the 8th resistance R ₈dividing potential drop obtains v _b=k _vgv _o, v _awith v _baccess subtraction circuit, R ₃=R ₄=R ₅=R ₆, then export as v _c=k _vg(V _o-V _m| sin ω t|).V _oby the 9th resistance R ₉with the tenth resistance R ₁₀dividing potential drop, and given voltage reference V _ogcompare, here V _og=5.1V, R ₈=77.43R ₉, via the 11 resistance R ₁₁with the first electric capacity C ₁the adjuster of composition obtains error signal v _eA, v _b, v _cwith v _eAaccess multiplier, it exports as v _p=v _eAv _c/ v _b=v _eA[1-V _m/ V _o| sin ω t|], by v _p(amplitude is V with sawtooth waveforms _ramp) hand over and cut the duty ratio that can obtain such as formula Changing Pattern (18) Suo Shi, main power circuit parameter necessarily and steady operation time, v _eA/ V _ramp=D ₀.Physical circuit is as follows:

The interrupted booster converter that employing switch periods optimal utilization rate of the present invention controls, comprises converter main power circuit 1 and control circuit: described converter main power circuit 1 comprises input voltage source v _in, electromagnetic interface filter, diode rectifier circuit RB, Boost inductance L _b, switching tube Q _b, diode D _b, storage capacitor C _o, load R _ld; Wherein input voltage source v _inbe connected with the input port of electromagnetic interface filter, the output port of electromagnetic interface filter is connected with the input port of diode rectifier circuit RB, and the output negative pole of diode rectifier circuit RB is reference potential zero point, the output cathode of diode rectifier circuit RB and Boost inductance L _bone end connect, Boost inductance L _bthe other end respectively with switching tube Q _bdrain electrode and diode D _banode connect, switching tube Q _bsource electrode be connected zero point with reference potential, diode D _bnegative electrode respectively with storage capacitor C _oanode and load R _ldone end connect, storage capacitor C _onegative electrode and load R _ldthe other end be all connected zero point with reference potential;

Described control circuit comprises the first bleeder circuit 2, subtraction circuit 3, second bleeder circuit 4, multiplier 5, regulating error circuit 6, chip UC3525A 7; The wherein input of the first bleeder circuit 2 and input voltage sampled point V _gnamely the output cathode of diode rectifier circuit RB connects, and the output terminals A of the first bleeder circuit 2 is connected with the inverting input of subtraction circuit 3, and the input of the second bleeder circuit 4 connects the output voltage V of main power circuit 1 _opositive pole, the output B of the second bleeder circuit 4 respectively with the normal phase input end of subtraction circuit 3 and the second input v of multiplier 5 _zconnect, the output C of the subtraction circuit 3 and first input end v of multiplier 5 _xbe connected, the inverting input of regulating error circuit 6 connects output voltage V _opositive pole, the normal phase input end of regulating error circuit 6 connects voltage reference signal V _og, the output of regulating error circuit 6 and the 3rd input v of multiplier 5 _yconnect, the output P of multiplier 5 is connected with the input of chip UC3525A 7.

The first described bleeder circuit 2 comprises the first operational amplifier A ₁, the first resistance R ₁, the second resistance R ₂; Input voltage sampled point v _gwith the first resistance R ₁one end connect, the first resistance R ₁the other end respectively with the first operational amplifier A ₁normal phase input end and the second resistance R ₂one end connect, the second resistance R ₂the other end be connected zero point with reference potential, the first operational amplifier A ₁reverse input end be directly connected with output terminals A, form in-phase voltage follower.

Described subtraction circuit 3 comprises the 3rd resistance R ₃, the 4th resistance R ₄, the 5th resistance R ₅, the 6th resistance R ₆, the second operational amplifier A ₂, wherein the 3rd resistance R ₃one end is connected with the output terminals A of the first bleeder circuit 2, and the other end is connected to the second operational amplifier A ₂inverting input, the 6th resistance R ₆be serially connected with the second operational amplifier A ₂inverting input and output between, the 4th resistance R ₄one end is connected to the output B of the second bleeder circuit 4, the 4th resistance R ₄the other end respectively with the first operational amplifier A ₂normal phase input end and the 5th resistance R ₅one end connect, the 5th resistance R ₅the other end be connected zero point with reference potential.

The second described bleeder circuit 4 comprises the 3rd operational amplifier A ₃, the 7th resistance R ₇, the 8th resistance R ₈; Output voltage V _opositive pole and the 7th resistance R ₇one end connect, the 7th resistance R ₇the other end respectively with the 3rd operational amplifier A ₃normal phase input end and the 8th resistance R ₈one end connect, the 8th resistance R ₈the other end be connected zero point with reference potential, the 3rd operational amplifier A ₃reverse input end be directly connected with output terminals A, form in-phase voltage follower.

Described regulating error circuit 6 comprises the 9th resistance R ₉, the tenth resistance R ₁₀, the 11 resistance R ₁₁, the first electric capacity C ₁, four-operational amplifier A ₄; Wherein the 9th resistance R ₉one end is connected with the output B of the second bleeder circuit 4, the other end respectively with four-operational amplifier A ₄inverting input, the tenth resistance R ₁₀one end, the 11 resistance R ₁₁one end connect, the tenth resistance R ₁₀the other end be connected zero point with reference point position, the 11 resistance R ₁₁the other end and the first electric capacity C ₁one end connects, the first electric capacity C ₁the other end and four-operational amplifier A ₄output connect, four-operational amplifier A ₄normal phase input end connect voltage reference signal V _og.

Described chip UC3525A 7 is produced by TI company, comprises the 5th operational amplifier A ₅, the 6th amplifier A ₆, PWM Latch circuit and frequency divider, this chip is a kind of voltage type PWM integrated manipulator, is integrated with all functions of carrying out needed for pulse-width modulation.

In sum, the interrupted booster converter that employing switch periods optimal utilization rate of the present invention controls, switch periods optimal utilization rate is adopted to control, increase threshold inductance value, reduce main power device current peak and effective value, improve conversion efficiency, also reduce output voltage ripple simultaneously or export storage capacitor.With determine compared with Duty ratio control, under the prerequisite meeting IEC61000-3-2Class D standard, both to have reduced conduction loss and switching tube turn-off power loss, improve conversion efficiency, turn reduce output voltage ripple or export storage capacitor.

Claims (6)

1. the interrupted booster converter adopting switch periods optimal utilization rate to control, is characterized in that, comprises converter main power circuit (1) and control circuit: described converter main power circuit (1) comprises input voltage source v _in, electromagnetic interface filter, diode rectifier circuit RB, Boost inductance L _b, switching tube Q _b, diode D _b, storage capacitor C _o, load R _ld; Wherein input voltage source v _inbe connected with the input port of electromagnetic interface filter, the output port of electromagnetic interface filter is connected with the input port of diode rectifier circuit RB, and the output negative pole of diode rectifier circuit RB is reference potential zero point, the output cathode of diode rectifier circuit RB and Boost inductance L _bone end connect, Boost inductance L _bthe other end respectively with switching tube Q _bdrain electrode and diode D _banode connect, switching tube Q _bsource electrode be connected zero point with reference potential, diode D _bnegative electrode respectively with storage capacitor C _oanode and load R _ldone end connect, storage capacitor C _onegative electrode and load R _ldthe other end be all connected zero point with reference potential;

Described control circuit comprises the first bleeder circuit (2), subtraction circuit (3), the second bleeder circuit (4), multiplier (5), regulating error circuit (6), chip UC3525A (7); The wherein input of the first bleeder circuit (2) and input voltage sampled point v _gnamely the output cathode of diode rectifier circuit RB connects, the output terminals A of the first bleeder circuit (2) is connected with the inverting input of subtraction circuit (3), and the input of the second bleeder circuit (4) connects the output voltage V of main power circuit (1) _opositive pole, the output B of the second bleeder circuit (4) respectively with the normal phase input end of subtraction circuit (3) and the second input v of multiplier (5) _zconnect, the output C of subtraction circuit (3) and the first input end v of multiplier (5) _xbe connected, the inverting input of regulating error circuit (6) connects output voltage V _opositive pole, the normal phase input end of regulating error circuit (6) connects voltage reference signal V _og, the output of regulating error circuit (6) and the 3rd input v of multiplier (5) _yconnect, the output P of multiplier (5) is connected with the input of chip UC3525A (7).

2. the interrupted booster converter of employing switch periods optimal utilization rate control according to claim 1, it is characterized in that, described the first bleeder circuit (2) comprises the first operational amplifier A ₁, the first resistance R ₁, the second resistance R ₂; Input voltage sampled point v _gwith the first resistance R ₁one end connect, the first resistance R ₁the other end respectively with the first operational amplifier A ₁normal phase input end and the second resistance R ₂one end connect, the second resistance R ₂the other end be connected zero point with reference potential, the first operational amplifier A ₁reverse input end be directly connected with output terminals A, form in-phase voltage follower.

3. the interrupted booster converter of employing switch periods optimal utilization rate control according to claim 1, it is characterized in that, described subtraction circuit (3) comprises the 3rd resistance R ₃, the 4th resistance R ₄, the 5th resistance R ₅, the 6th resistance R ₆, the second operational amplifier A ₂, wherein the 3rd resistance R ₃one end is connected with the output terminals A of the first bleeder circuit (2), and the other end is connected to the second operational amplifier A ₂inverting input, the 6th resistance R ₆be serially connected with the second operational amplifier A ₂inverting input and output between, the 4th resistance R ₄one end is connected to the output B of the second bleeder circuit (4), the 4th resistance R ₄the other end respectively with the first operational amplifier A ₂normal phase input end and the 5th resistance R ₅one end connect, the 5th resistance R ₅the other end be connected zero point with reference potential.

4. the interrupted booster converter of employing switch periods optimal utilization rate control according to claim 1, it is characterized in that, described the second bleeder circuit (4) comprises the 3rd operational amplifier A ₃, the 7th resistance R ₇, the 8th resistance R ₈; Output voltage V _opositive pole and the 7th resistance R ₇one end connect, the 7th resistance R ₇the other end respectively with the 3rd operational amplifier A ₃normal phase input end and the 8th resistance R ₈one end connect, the 8th resistance R ₈the other end be connected zero point with reference potential, the 3rd operational amplifier A ₃reverse input end be directly connected with output terminals A, form in-phase voltage follower.

5. the interrupted booster converter of employing switch periods optimal utilization rate control according to claim 1, it is characterized in that, described regulating error circuit (6) comprises the 9th resistance R ₉, the tenth resistance R ₁₀, the 11 resistance R ₁₁, the first electric capacity C ₁, four-operational amplifier A ₄; Wherein the 9th resistance R ₉one end is connected with the output B of the second bleeder circuit (4), the other end respectively with four-operational amplifier A ₄inverting input, the tenth resistance R ₁₀one end, the 11 resistance R ₁₁one end connect, the tenth resistance R ₁₀the other end be connected zero point with reference point position, the 11 resistance R ₁₁the other end and the first electric capacity C ₁one end connects, the first electric capacity C ₁the other end and four-operational amplifier A ₄output connect, four-operational amplifier A ₄normal phase input end connect voltage reference signal V _og.

6. the interrupted booster converter of employing switch periods optimal utilization rate control according to claim 2, it is characterized in that, described chip UC3525A (7) is produced by TI company, comprises the 5th operational amplifier A ₅, the 6th amplifier A ₆, PWM Latch circuit and frequency divider, this chip is a kind of voltage type PWM integrated manipulator, is integrated with the function of carrying out needed for pulse-width modulation.