CN104821821A - Method for determining loop parameters of phase-locked receiver, and parameter calculator - Google Patents

Method for determining loop parameters of phase-locked receiver, and parameter calculator Download PDF

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CN104821821A
CN104821821A CN201510158717.3A CN201510158717A CN104821821A CN 104821821 A CN104821821 A CN 104821821A CN 201510158717 A CN201510158717 A CN 201510158717A CN 104821821 A CN104821821 A CN 104821821A
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loop
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phase
parameters
step
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CN104821821B (en
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王文伟
戴琳
舒丽霞
王文婧
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上海航天测控通信研究所
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Abstract

The invention provides a method for determining loop parameters of a phase-locked receiver, and a parameter calculator. The method comprises a first step of initializing condition parameters, and testing a loop part, so as to obtain loop part index data; a second step of setting resistance and capacitance parameters of a first-order active power filter; a third step of according to the condition parameters, the loop part index data, the resistance and capacitance parameters of the first-order active power filter, and a preset rule, acquiring the loop parameters of the phase-locked receiver, wherein the loop parameters of the phase-locked receiver comprise single side band loop band width, natural resonance frequency, damping coefficient, loop input signal to noise ratio, loop signal to noise ratio, stable phase error, and fast capture range; and a fourth step of judging whether the parameters meet all the following requirements, wherein the loop signal to noise ratio is greater than 6dB, the damping coefficient is in the range of 0.65-0.75, and the stable phase error is less than 20 degree; if the parameters meet all the requirements, outputting and/or storing the loop parameters of the phase-locked receiver.

Description

锁相接收机环路参数确定方法及参数计算器 The receiver phase locked loop parameter determination method and the parameter calculator

技术领域 FIELD

[0001] 本发明设及锁相接收机领域,具体地,设及一种锁相接收机环路参数确定方法及参数计算器。 [0001] The receiver set and lock the art of the present invention, specifically, the receiver phase locked loop is provided, and one method of determining parameters and parameter calculator.

背景技术 Background technique

[0002] 锁相技术起源于上世纪=十年代,五十年代初开始应用,发展至今技术已十分成熟。 [0002] lock-in technique originated in the last century = 1980s, began to use the early fifties, the development has been very mature technology. 由于航天技术的需要,在空间电子系统中,不论是星船还是地面电子设备,都广泛采用锁相技术。 Due to the need of space technology, space in the electronic system, whether the star ship or ground electronic equipment, are widely used lock-in technique. 特别是锁相接收机被成功应用W后,使空间电子系统的性能得到了很大的改善。 Especially after the lock-in receiver has been successfully applied W, the performance space of the electronic system has been greatly improved. 我国卫星测控领域中的USB(S波段统一测控体制)应答机均采用锁相接收机结构,X频段锁相接收机工作原理与USB锁相接收机相同,区别在于工作频段高、频率流程较复杂。 Field of satellite monitoring of USB (S-band unified monitoring and control system) answering machines are phase-locked receiver structure, X-band PLL receiver works with USB receiver lock the same, except that the high operating frequency, the frequency of the process is more complex .

[0003] 环路参数是锁相接收机设计关键,参数的选取直接影响到接收机灵敏度、环路稳定性、环路跟踪范围、捕获时间等重要指标。 [0003] The key parameter is the phase locked loop receiver design, select parameters directly affects the sensitivity of the receiver, an important indicator of stability of the loop, the loop tracking range, the capture time. 锁相接收机的环路工作过程与教科书上经典锁相环一样,唯一的区别在于前者的压控晶振有分频、倍频,设及倍频次数,后者是直接在压控晶振频率上锁定,另外前者内部鉴相灵敏度与上行功率有关,需进行测量得到。 Phase-locked loop receiver working process and textbooks as a classic phase-locked loop, the only difference is that the former voltage-controlled crystal oscillator frequency dividing, multiplying, and set the number of frequency, which is directly on the voltage-controlled crystal oscillator frequencies lock, the former additional internal phase sensitivity related to uplink power, need to be measured.

[0004] 由于计算环路参数方法比较复杂,对于模拟方法实现的锁相接收机需要对环路参数进行多次调试才能得到较优的设计结果,调试工作量很大。 [0004] Since the calculation method is more complex loop parameters for the simulation method to achieve the phase-locked loop receivers need to debug multiple parameters to get superior design results, a large debugging effort.

发明内容 SUMMARY

[0005] 针对现有技术中的缺陷,本发明的目的是提供一种锁相接收机环路参数确定方法及参数计算器。 [0005] For the prior art drawbacks, an object of the present invention is to provide a phase locked loop receiver parameter determination method and parameter calculator.

[0006] 根据本发明提供的一种锁相接收机环路参数确定方法,包括: [0006] According to one method of determining the phase locked loop parameters according to the present invention provides a receiver, comprising:

[0007] 步骤1,初始化条件参数,和对环路部件测试获得环路部件指标数据; [0007] Step 1, initialization condition parameters, and a loop member of the loop index data obtained test member;

[000引步骤2,设置一阶有源滤波器的电阻和电容参数; [000 cited Step 2, provided the first-order active filter parameters of resistance and capacitance;

[0009] 步骤3,根据所述条件参数、环路部件指标数据、一阶有源滤波器的电阻和电容参数W及预设规则获得锁相接收机环路参数,所述锁相接收机环路参数包含单边带环路带宽、自然谐振频率、阻巧系数、环路输入信噪比、环路信噪比、稳态相位误差、快捕带; [0009] Step 3, to obtain the receiver phase locked loop parameters according to the condition parameter, index data loop member, the resistance and capacitance parameters W and a preset rule order active filter, said phase locked loop receiver SSB path parameter contains the loop bandwidth, natural resonant frequency, Qiao resistance coefficient, a loop input SNR, SNR loop, steady state phase error, with fast acquisition;

[0010] 步骤4,判断是否同时满足: [0010] Step 4, it is determined whether or not conditions are satisfied:

[0011] 所述环路信噪比大于6地, [0011] The loop 6 is greater than the signal to noise ratio,

[0012] 所述阻巧系数自0.65-0. 75范围内, [0012] The resistance coefficient of coincidence in the range of from 0.65-0. 75,

[0013] 所述稳态相位误差小于20°, [0013] The steady state phase error is less than 20 °,

[0014] 若不同时满足,则返回步骤2, [0014] If not satisfied, return to step 2,

[0015] 若同时满足,则输出和/或保存所述单边带环路带宽、自然谐振频率、阻巧系数、 环路输入信噪比、环路信噪比、稳态相位误差、快捕带的数值。 [0015] When satisfied, the output and / or saving the loop bandwidth of the single sideband, natural resonant frequency, Qiao resistance coefficient, a loop input SNR, SNR loop, steady state phase error, rapid acquisition with value.

[0016] 进一步地,所述条件参数包括噪声系数、中频带宽、最小输入信号、晶振倍频次数、 输入信号频率变化范围和频率变化率; [0016] Further, the condition parameter comprises a noise factor, IF bandwidth, minimum input signal, the number of the crystal frequency, the input signal frequency range and the frequency change rate;

[0017] 所述指标数据包括压控晶振的压控灵敏度和鉴相器的鉴相灵敏度。 The [0017] indicator data includes a voltage controlled oscillator of the phase voltage control sensitivity and the sensitivity of the phase detector.

[0018] 进一步地,所述对环路部件测试并获得鉴相器的鉴相灵敏度的过程为: [0018] Further, the components of the process loop discriminator tested and the sensitivity of the phase detector is a phase:

[0019] 步骤1. 1,测量获得所述鉴相器的输入端信号幅度, [0019] Step 1.1, obtained by the measurement of the amplitude signal at the input of the phase detector,

[0020] 步骤1. 2,其他条件不变仅断开所述频谱分析仪与所述鉴相器输入端的连接,外接信号源输出信号至向所述鉴相器输入端, [0020] Step 1.2, ceteris paribus disconnect only the spectral analyzer connected to the input of the phase detector, to the external signal source output signal to the phase detector input,

[0021] 步骤1. 3,设置所述信号源输出信号幅度为步骤1. 1中测量获得的输入端信号幅度, [0021] Step 1.3, provided the signal source output signal amplitude of input signal amplitude measurement obtained in step 1.1, and

[0022] 步骤1. 4,通过示波器测量获取差拍波形,示波器测量差拍波峰的峰峰值/ 31为所述鉴相器的鉴相灵敏度。 [0022] Step 1.4, the beat waveform acquired by an oscilloscope measurements, an oscilloscope to measure peak beat peaks / 31 is the phase sensitivity of the phase detector.

[0023] 进一步地,所述预设规则为: [0023] Further, the preset rule is:

[0024]Kv=Kv.Text*1000*2*3. 14/m, [0024] Kv = Kv.Text * 1000 * 2 * 3. 14 / m,

[002引K= (FreqmultipleTime.Text+1)体d*Kv,其中,(FreqmultipleTime)+1 为晶振总的倍频次数 [002 Primer K = (FreqmultipleTime.Text + 1) body d * Kv, wherein, (FreqmultipleTime) +1 is the total number of frequency doubling crystal

[0026]T1 = (C.Text)*(Rl.Text)*(l+巧2.Text)/巧3.Text))/1000 [0026] T1 = (C.Text) * (Rl.Text) * (l + clever 2.Text) / Qiao 3.Text)) / 1000

[0027]T2 = (C.Text) * (R2.Text)/lOOO [0027] T2 = (C.Text) * (R2.Text) / lOOO

[002引A=巧3.Text:)/巧1.Text), [002 primer A = Qiao 3.Text:) / Qiao 1.Text),

[0029] 其中,时间常数 [0029] wherein the time constant

Figure CN104821821AD00061

时间常数T2 =R2XC,滤波器直流增益A= R3/R1 Time constant T2 = R2XC, filter DC gain A = R3 / R1

[0030] Wn = SqHK/Tl) [0030] Wn = SqHK / Tl)

[0031] E = (Wn/2)*(T化1/(A*K)) [0031] E = (Wn / 2) * (T of 1 / (A * K))

[0032]化=Wn* (E/化1/巧巧)) [0032] of = Wn * (E / of 1 / Qiaoqiao))

[0033]CN= 174-NF+I吨utMinPower-10*Log炬L)/Log(10)-3 [0033] CN = 174-NF + I t utMinPower-10 * Log torch L) / Log (10) -3

[0034]PhaseError= (FreqSweepRange.Text) *1000*360/K/A+巧reqSweepRate. Text)*1000*360/(Wn*Wn) [0034] PhaseError = (FreqSweepRange.Text) * 1000 * 360 / K / A + clever reqSweepRate. Text) * 1000 * 360 / (Wn * Wn)

[0035] FastCap化reBW = 2巧*Wn/6. 18 [0035] FastCap coincidence of reBW = 2 * Wn / 6. 18

[0036] 其中,Kv为压控晶振的压控灵敏度,Kv.Text为测量得到的压控灵敏度结果, Kd为鉴相器的鉴相灵敏度,K为压控晶振输出频率总的倍频次数,Wn为环路自然谐振频率,E为阻巧系数,化为单边带环路带宽,化eqSweepRange为设置的输入频率扫描范围, 化eqSweepRate为设置的输入频率扫描速率,CN为环路信噪比,NF为锁相接收机噪声系数, InputMinPower为最小输入信号,PhaseElrror为环路稳态相位误差,FastCap1:ureBW为快捕-W- J巿'〇 [0036] wherein the voltage control sensitivity Kv of the voltage controlled oscillator, Kv.Text voltage control sensitivity of the measured result, for the Kd of the phase detector sensitivity of the phase detector, K is the total number of times the frequency of the voltage controlled oscillator output frequency, Wn is the natural resonant frequency of the loop, E is the coefficient of resistance Qiao, SSB into the loop bandwidth of the frequency sweep range eqSweepRange input set of input frequency sweep rate eqSweepRate set, CN is the loop SNR , NF is the noise figure of the receiver phase lock, InputMinPower for the minimum input signal, PhaseElrror the loop steady state phase error, FastCap1: ureBW faster capture market -W- J 'square

[0037] 基于相同的发明构思,本发明还包括一种参数计算器,其特征在于,包括输入模块和计算模块; [0037] Based on the same inventive concept, the present invention also includes a parameter calculator, characterized by comprising an input module and a calculation module;

[0038] 所述输入模块用于: [0038] The input module configured to:

[0039] 初始化条件参数, [0039] initialization condition parameters,

[0040] 对环路部件测试获得环路部件指标数据, [0040] The obtained data indicator member loop test loop member,

[0041]W及设置一阶有源滤波器的电阻和电容参数; [0041] W and provided with a first order active filter parameters of resistance and capacitance;

[0042] 所述计算模块用于: [0042] The calculation module is configured to:

[0043] 根据所述条件参数、环路部件指标数据、一阶有源滤波器的电阻和电容参数W及预设规则获得锁相接收机环路参数,所述锁相接收机环路参数包含单边带环路带宽、自然谐振频率、阻巧系数、环路输入信噪比、环路信噪比、稳态相位误差、快捕带。 [0043] The receiver phase locked loop parameters obtained according to the condition parameter, index data loop member, the resistance and capacitance parameters W and a preset rule order active filter, the receiver phase locked loop parameters comprising SSB loop bandwidth, natural resonant frequency, Qiao resistance coefficient, a loop input SNR, SNR loop, steady state phase error, with fast acquisition.

[0044] 进一步地,所述预设规则为: [0044] Further, the preset rule is:

[0045] Kv=Kv.Text*1000*2*3. 14/m, [0045] Kv = Kv.Text * 1000 * 2 * 3. 14 / m,

[0046] K= (FreqmultipleTime.Text+1)体d*Kv,其中,(FreqmultipleTime)+1 为晶振总的倍频次数 [0046] K = (FreqmultipleTime.Text + 1) body d * Kv, wherein, (FreqmultipleTime) +1 is the total number of frequency doubling crystal

[0047] T1 = (C.Text)*(Rl.Text)*(l+巧2.Text)/巧3.Text))/1000 [0047] T1 = (C.Text) * (Rl.Text) * (l + clever 2.Text) / Qiao 3.Text)) / 1000

[0048] T2 = (C.Text) * (R2.Text)/lOOO [0048] T2 = (C.Text) * (R2.Text) / lOOO

[0049] A=巧3.Text:)/巧1.Text), [0049] A = Qiao 3.Text:) / Qiao 1.Text),

[0050] 其中,时间常数 [0050] wherein the time constant

Figure CN104821821AD00071

时间常数T2 =R2XC,滤波器直流增益A= R3/R1 Time constant T2 = R2XC, filter DC gain A = R3 / R1

[CK)5UWn=SqHK/Tl) [CK) 5UWn = SqHK / Tl)

[0052] E= (Wn/2)*(T化1/(A*K)) [0052] E = (Wn / 2) * (T of 1 / (A * K))

[0053] 化=Wn* (E/化1/巧巧)) [0053] of = Wn * (E / of 1 / Qiaoqiao))

[0054] CN= 174-NF+I吨utMinPower-10*Log炬L)/Log(10)-3 [0054] CN = 174-NF + I t utMinPower-10 * Log torch L) / Log (10) -3

[005引PhaseError= (FreqSweepRange.Text)*1000*360/K/A+巧reqSweepRate. Text)*1000*360/(Wn*Wn) [005 cited PhaseError = (FreqSweepRange.Text) * 1000 * 360 / K / A + clever reqSweepRate. Text) * 1000 * 360 / (Wn * Wn)

[0056] FastCap化reBW= 2 巧*Wn/6. 18 [0056] FastCap coincidence of reBW = 2 * Wn / 6. 18

[0化7] 其中,Kv为压控晶振的压控灵敏度,Kv.Text为测量得到的压控灵敏度结果,Kd为鉴相器的鉴相灵敏度,K为压控晶振输出频率总的倍频次数,Wn为环路自然谐振频率,E为阻巧系数,化为单边带环路带宽,化eqSweepRange为设置的输入频率扫描范围, 化eqSweepRate为设置的输入频率扫描速率,CN为环路信噪比,NF为锁相接收机噪声系数, InputMinPower为最小输入信号,PhaseElrror为环路稳态相位误差,FastCap1:ureBW为快捕-W- J巿'〇 [0 of 7] where, Kv is a voltage-controlled oscillator of a voltage control sensitivity, Kv.Text voltage control sensitivity of the measured result, Kd is the phase sensitivity of the phase detector, K is the total frequency of the voltage controlled oscillator output frequency times, natural resonant frequency Wn of the loop, E is the coefficient of resistance Qiao, SSB into the loop bandwidth of the frequency sweep range eqSweepRange input set of input frequency sweep rate eqSweepRate set, CN the loop channel noise ratio, NF is the noise figure of the receiver phase lock, InputMinPower for the minimum input signal, PhaseElrror the loop steady state phase error, FastCap1: ureBW faster capture market -W- J 'square

[0化引进一步地,还包括一比较模块,判断是否同时满足: [0 of further primers, further comprising a comparison module determines whether simultaneously satisfied:

[0化9] 所述比较模块用于判断是否同时满足: [0 of 9] The comparison module for determining whether simultaneously satisfied:

[0060] 所述环路信噪比大于6地, [0060] The loop 6 is greater than the signal to noise ratio,

[0061] 所述阻巧系数自0.65-0. 75范围内, [0061] The resistance coefficient of coincidence in the range of from 0.65-0. 75,

[0062] 所述稳态相位误差小于20°, [0062] The steady state phase error is less than 20 °,

[0063] 若不同时满足,则输出"设置有误"并返回步骤2, [0063] If not satisfied, then the "setting error" and returns to step 2,

[0064] 若同时满足,则输出和/或保存所述单边带环路带宽、自然谐振频率、阻巧系数、 环路输入信噪比、环路信噪比、稳态相位误差、快捕带的数值。 [0064] When satisfied, the output and / or saving the loop bandwidth of the single sideband, natural resonant frequency, Qiao resistance coefficient, a loop input SNR, SNR loop, steady state phase error, rapid acquisition with value.

[0065] 利用本发明可极大减少环路参数的调试时间。 [0065] With the present invention greatly reduces the time to debug the loop parameters. 本发明可W应用到所有频段统一测控体制锁相接收机中。 The present invention may be applied to all frequency bands W Unified Control System lock receiver.

附图说明 BRIEF DESCRIPTION

[0066] 为了更清楚地说明本发明实施例的技术方案,下面将对实施例描述中所需要使用的附图作简单的介绍,显而易见,下面描述中的附图仅仅是本发明的一些实施例,对于本领域技术人员来讲,在不付出创造性劳动的前提下,还可w根据该些附图获得其他的附图。 [0066] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings for describing the need to use a simple embodiment will be described, it is apparent in the following description are only some embodiments of the drawings of the present invention. for those skilled in the art is concerned, without any creative effort, and other drawings may be obtained according to w the plurality of reference. 附图中: In the drawings:

[0067] 图1是锁相接收机环路参数确定方法流程图。 [0067] FIG. 1 is a phase locked loop receiver parameter determination method of a flow chart.

具体实施方式 Detailed ways

[0068] 下文结合附图W具体实施例的方式对本发明进行详细说明。 [0068] The present invention is hereinafter described in detail in conjunction with accompanying drawings of particular embodiments W. W下实施例将有助于本领域的技术人员进一步理解本发明,但不W任何形式限制本发明。 W contribute to the embodiment of the present art will be further understood in the art of the present invention, but not to limit the invention in any form W. 应当指出的是,还可W 使用其他的实施例,或者对本文列举的实施例进行结构和功能上的修改,而不会脱离本发明的范围和实质。 It should be noted that W may also be used in other embodiments, or the embodiments recited herein may be modified and the structural features, without departing from the scope and spirit of the invention.

[0069] 在本发明提供的一种锁相接收机环路参数确定方法的实施例中,步骤流程图如图1所示,包括: [0069] In an embodiment of a receiver phase locked loop parameters according to the present invention provides a method for determining the steps of the flowcharts shown in Figure 1, comprising:

[0070] 步骤1,初始化条件参数,和对环路部件测试获得环路部件指标数据; [0070] Step 1, initialization condition parameters, and a loop member of the loop index data obtained test member;

[0071] 步骤2,设置一阶有源滤波器的电阻和电容参数; [0071] Step 2, provided the first-order active filter resistance and capacitance parameters;

[0072] 步骤3,根据所述条件参数、环路部件指标数据、一阶有源滤波器的电阻和电容参数W及预设规则获得锁相接收机环路参数,所述锁相接收机环路参数包含单边带环路带宽、自然谐振频率、阻巧系数、环路输入信噪比、环路信噪比、稳态相位误差、快捕带; [0072] Step 3, to obtain the receiver phase locked loop parameters according to the condition parameter, index data loop member, the resistance and capacitance parameters W and a preset rule order active filter, said phase locked loop receiver SSB path parameter contains the loop bandwidth, natural resonant frequency, Qiao resistance coefficient, a loop input SNR, SNR loop, steady state phase error, with fast acquisition;

[0073] 步骤4,判断是否同时满足; [0073] Step 4, whether or not simultaneously satisfied;

[0074] 所述环路信噪比大于6地, [0074] The loop 6 is greater than the signal to noise ratio,

[0075] 所述阻巧系数自0.65-0. 75范围内, [0075] The resistance coefficient of coincidence in the range of from 0.65-0. 75,

[0076] 所述稳态相位误差小于20°, The [0076] steady state phase error is less than 20 °,

[0077] 若不同时满足,则返回步骤2, [0077] If not satisfied, return to step 2,

[007引若同时满足,则输出和/或保存所述单边带环路带宽、自然谐振频率、阻巧系数、 环路输入信噪比、环路信噪比、稳态相位误差、快捕带的数值。 [007 primer if satisfied, the output and / or saving the loop bandwidth of the single sideband, natural resonant frequency, Qiao resistance coefficient, a loop input SNR, SNR loop, steady state phase error, rapid acquisition with value.

[0079] 参数采集器根据参数库中的条件参数采集并向参数计算器发送初始预设的条件参数,或用户手动向输入设置所述条件参数进行所述初始化条件参数步骤。 [0079] Parameter acquisition and transmission acquisition parameter calculator initial preset condition parameter or condition parameter of the user to manually set the initialization condition parameter input step according to the conditions Parameter library. 所述条件参数包括噪声系数、中频带宽、最小输入信号、晶振倍频次数、输入信号频率变化范围和变化率. The condition parameters include noise figure, IF bandwidth, minimum input signal, the number of the crystal frequency, the input signal frequency range and rate of change.

[0080] 对环路部件测试获得并向所述参数计算器发送环路部件指标数据,所述指标数据包括压控晶振的压控灵敏度和鉴相器的鉴相灵敏度。 [0080] provided to the parameter calculator index data transmission loop section of the loop component testing, the index data comprises a phase sensitive phase detector and a voltage control sensitivity of the voltage controlled crystal oscillator.

[0081] 作为一种实施例,步骤1. 1,测量获得所述鉴相器的输入端信号幅度, [0081] As an embodiment, step 1.1, obtained by the measurement of the amplitude signal at the input of the phase detector,

[0082] 步骤1. 2,其他条件不变仅断开所述频谱分析仪与所述鉴相器输入端的连接,外接信号源输出信号至向所述鉴相器输入端, [0082] Step 1.2, ceteris paribus disconnect only the spectral analyzer connected to the input of the phase detector, to the external signal source output signal to the phase detector input,

[0083] 步骤1. 3,设置所述信号源输出信号幅度为步骤1. 1中测量获得的输入端信号幅度, [0083] Step 1.3, provided the signal source output signal amplitude of input signal amplitude measurement obtained in step 1.1, and

[0084] 步骤1. 4,通过示波器测量获取差拍波形,示波器测量差拍波峰的峰峰值/ 31为所述鉴相器的鉴相灵敏度。 [0084] Step 1.4, the beat waveform acquired by an oscilloscope measurements, an oscilloscope to measure peak beat peaks / 31 is the phase sensitivity of the phase detector.

[0085] 作为一种实施例,所述预设规则为: [0085] As an embodiment, the preset rule is:

[0086] Kv=Kv.Text*1000*2*3. 14/m, [0086] Kv = Kv.Text * 1000 * 2 * 3. 14 / m,

[0087]K= (FreqmultipleTime.Text+1)体d*Kv,其中,(FreqmultipleTime)+1 为晶振总的倍频次数 [0087] K = (FreqmultipleTime.Text + 1) body d * Kv, wherein, (FreqmultipleTime) +1 is the total number of frequency doubling crystal

[008引T1 =杞Text) * (R1.Text) * (1+ 巧2.Text) / 巧3.Text)) /1000 [008 primer T1 = Qi Text) * (R1.Text) * (1+ clever 2.Text) / Qiao 3.Text)) / 1000

[0089] T2 = (C.Text) * (R2.Text)/lOOO [0089] T2 = (C.Text) * (R2.Text) / lOOO

[0090] A=巧3.Texd/ 巧1.Text), [0090] A = clever 3.Texd / Qiao 1.Text),

[0091] 其中,时间常数 [0091] wherein the time constant

Figure CN104821821AD00091

,时间常数T2 =R2XC,滤波器直流增益A= R3/R1 , The time constant T2 = R2XC, filter DC gain A = R3 / R1

[009引Wn=SqHK/Tl) [009 cited Wn = SqHK / Tl)

[0093] E= (Wn/2)*(T化1/(A*K)) [0093] E = (Wn / 2) * (T of 1 / (A * K))

[0094] 化=Wn* (E/化1/巧巧)) [0094] of = Wn * (E / of 1 / Qiaoqiao))

[0095] CN= 174-NF+I吨utMinPower-10*Log炬L)/Log(10)-3 [0095] CN = 174-NF + I t utMinPower-10 * Log torch L) / Log (10) -3

[0096] PhaseError= (FreqSweepRange.Text)*1000*36〇/K/A+巧reqSweepRate. Text)*1000*360/(Wn*Wn) [0096] PhaseError = (FreqSweepRange.Text) * 1000 * 36〇 / K / A + clever reqSweepRate. Text) * 1000 * 360 / (Wn * Wn)

[0097] FastCap1:ureBW= 2 巧*Wn/6. 18 [0097] FastCap1:. UreBW = 2 Qiao * Wn / 6 18

[009引其中,Kv为压控晶振的压控灵敏度,Kv.Text为测量得到的压控灵敏度结果,Kd为鉴相器的鉴相灵敏度,K为压控晶振输出频率总的倍频次数,Wn为环路自然谐振频率,E为阻巧系数,化为单边带环路带宽,化eqSweepRange为设置的输入频率扫描范围, 化eqSweepRate为设置的输入频率扫描速率,CN为环路信噪比,NF为锁相接收机噪声系数, InputMinPower为最小输入信号,PhaseElrror为环路稳态相位误差,FastCap1:ureBW为快捕带。 [Wherein lead 009, Kv is a voltage control sensitivity of the voltage controlled oscillator, Kv.Text voltage control sensitivity of the measured result, for the Kd of the phase detector sensitivity of the phase detector, K is the total number of times the frequency of the voltage controlled oscillator output frequency, Wn is the natural resonant frequency of the loop, E is the coefficient of resistance Qiao, SSB into the loop bandwidth of the frequency sweep range eqSweepRange input set of input frequency sweep rate eqSweepRate set, CN is the loop SNR , NF is the noise figure of the receiver phase lock, InputMinPower for the minimum input signal, PhaseElrror the loop steady state phase error, FastCap1: ureBW faster capture band.

[0099] 基于相同的发明构思,本发明还提供了一种参数计算器,包括输入模块和计算模块; [0099] Based on the same inventive concept, the present invention also provides a parameter calculator comprising an input module and a calculation module;

[0100] 所述输入模块用于: [0100] The input module configured to:

[0101] 初始化条件参数, [0101] initialization condition parameters,

[0102] 对环路部件测试获得环路部件指标数据, [0102] Data obtained loop index of the loop member testing means,

[0103] W及设置一阶有源滤波器的电阻和电容参数; [0103] W and provided with a first order active filter parameters of resistance and capacitance;

[0104] 所述计算模块用于: [0104] The calculation module is configured to:

[01化]根据所述条件参数、环路部件指标数据、一阶有源滤波器的电阻和电容参数W及预设规则获得锁相接收机环路参数,所述锁相接收机环路参数包含单边带环路带宽、自然谐振频率、阻巧系数、环路输入信噪比、环路信噪比、稳态相位误差、快捕带。 [Of 01] obtained receiver phase locked loop parameters according to the condition parameter, index data loop member, the resistance and capacitance parameters W and a preset rule order active filter, the receiver phase locked loop parameters comprising a single sideband loop bandwidth, natural resonant frequency, Qiao resistance coefficient, a loop input SNR, SNR loop, steady state phase error, with fast acquisition.

[0106] 其中,所述预设规则为: [0106] wherein the preset rule is:

[0107] Kv=Kv.Text*1000*2*3. 14/m, [0107] Kv = Kv.Text * 1000 * 2 * 3. 14 / m,

[0108] K= (RreqmultipleTime.Text+1)体d*Kv,其中,(RreqmultipleTime)+l为晶振总的倍频次数 [0108] K = (RreqmultipleTime.Text + 1) body d * Kv, wherein, (RreqmultipleTime) + l is the total number of frequency doubling crystal

[0109] T1 = (C.Text) * (Rl.Text) * (1+ 巧2.Text) / 巧3.Text))/lOOO [0109] T1 = (C.Text) * (Rl.Text) * (1+ clever 2.Text) / Qiao 3.Text)) / lOOO

[0110] T2 = (C.Text) * (R2.Text)/lOOO [011UA=巧3.Texd/ 巧1.Texd, [0110] T2 = (C.Text) * (R2.Text) / lOOO [011UA = clever 3.Texd / Qiao 1.Texd,

[0112] 其中,时间常蠻 [0112] wherein very time constant

Figure CN104821821AD00092

时间常数T2 =R2XC,滤波器直流增益A= R3/R1 Time constant T2 = R2XC, filter DC gain A = R3 / R1

[011 引Wn=SqHK/Tl) [011 cited Wn = SqHK / Tl)

[0114] E= (Wn/2) * (T化1/ (A*K)) [0114] E = (Wn / 2) * (T of 1 / (A * K))

[0115] 化=Wn* (E/化1/巧巧)) [0115] of = Wn * (E / of 1 / Qiaoqiao))

[0116] CN= 174-NF+I吨utMinPower-10*Log炬L)/Log(10)-3 [0116] CN = 174-NF + I t utMinPower-10 * Log torch L) / Log (10) -3

[0117] PhaseError= (FreqSweepRange.Text) *1000*36〇/K/A+巧reqSweepRate. Text)*1000*360/(Wn*Wn) [0117] PhaseError = (FreqSweepRange.Text) * 1000 * 36〇 / K / A + clever reqSweepRate. Text) * 1000 * 360 / (Wn * Wn)

[0118] FastCapUireBW= 2 巧*Wn/6. 18 [0118] FastCapUireBW = 2 Qiao * Wn / 6. 18

[0119] 其中,Kv为压控晶振的压控灵敏度,Kv.Text为测量得到的压控灵敏度结果, Kd为鉴相器的鉴相灵敏度,K为压控晶振输出频率总的倍频次数,Wn为环路自然谐振频率,E为阻巧系数,化为单边带环路带宽,化eqSweepRange为设置的输入频率扫描范围, 化eqSweepRate为设置的输入频率扫描速率,CN为环路信噪比,NF为锁相接收机噪声系数, InputMinPower为最小输入信号,PhaseElrror为环路稳态相位误差,FastCap1:ureBW为快捕-W- J巿'〇 [0119] wherein the voltage control sensitivity Kv of the voltage controlled oscillator, Kv.Text voltage control sensitivity of the measured result, for the Kd of the phase detector sensitivity of the phase detector, K is the total number of times the frequency of the voltage controlled oscillator output frequency, Wn is the natural resonant frequency of the loop, E is the coefficient of resistance Qiao, SSB into the loop bandwidth of the frequency sweep range eqSweepRange input set of input frequency sweep rate eqSweepRate set, CN is the loop SNR , NF is the noise figure of the receiver phase lock, InputMinPower for the minimum input signal, PhaseElrror the loop steady state phase error, FastCap1: ureBW faster capture market -W- J 'square

[0120] 作为一种实施例,还包括一比较模块,判断是否同时满足: [0120] As an embodiment, further comprising a comparison module determines whether simultaneously satisfied:

[0121] 所述比较模块用于判断是否同时满足: [0121] The comparison module for determining whether simultaneously satisfied:

[0122] 所述环路信噪比大于6地, [0122] The loop 6 is greater than the signal to noise ratio,

[0123] 所述阻巧系数自0. 65-0. 75范围内, [0123] Since the resistance coefficient in the range of 0.5 Qiao 65-0. 75,

[0124] 所述稳态相位误差小于20°, [0124] The steady state phase error is less than 20 °,

[01巧]若不同时满足,则输出"设置有误"并返回步骤2, [Qiao 01] not satisfied at the same time, the "setting error" and returns to step 2,

[01%] 若同时满足,则输出和/或保存所述单边带环路带宽、自然谐振频率、阻巧系数、 环路输入信噪比、环路信噪比、稳态相位误差、快捕带的数值。 [01%], if satisfied, and / SSB loop bandwidth, natural resonant frequency, Qiao resistance coefficient, a loop input SNR, SNR loop, the steady state phase error is output or stored, fast Numerical capture band.

[0127] 图1为本发明一种锁相接收机环路参数计算流程图,其中所述参数库至少设置有:噪声系数(单位地)、中频带宽(单位KHz)、最小输入信号(单位地m)、晶振倍频次数、 输入信号频率变化范围和变化率(单位分别为KHz/s和KHz)。 [0127] FIG. 1. A phase-locked loop receiver parameter calculation flowchart of the present invention, wherein the parameter database provided with at least: noise factor (in units), the intermediate frequency bandwidth (KHz), minimum input signal (in units of m), the number of the crystal frequency, the input signal frequency range and rate of change (unit respectively KHz / s and KHz).

[0128] 测量环路部件指标包括:压控晶振的压控灵敏度(单位KHz/V)、鉴相器的鉴相灵敏度(单位v/rad)。 [0128] Indicators measuring loop member comprising: a voltage control sensitivity of the voltage controlled oscillator (in KHz / V), the phase sensitivity of the phase detector (in v / rad).

[0129] 需要外部输入的环路滤波器参数为;一阶有源滤波器电阻和电容参数。 [0129] The loop filter parameters required for the external input; a first order active filter resistance and capacitance parameters.

[0130] 最终获得的环路参数结果为:单边带环路带宽(单位化)、自然谐振频率(单位rad/s)、阻巧系数、环路信噪比(单位地)、稳态相位误差(单位° )、快捕带(单位Hz); [0130] The final result of loop parameters is obtained: loop bandwidth single sideband (unit of) the natural resonant frequency (rad / s), Qiao resistance coefficient, a loop signal to noise ratio (in units), steady state phase error (in °), with rapid acquisition (in Hz);

[0131] 较佳的,环路输入信噪比不能小于-10地,当输入信号功率过小时该软件将自动提示"环路输入信噪比不能小于-10地",环路信噪比计算公式为: [0131] Preferably, the loop input SNR is not less than -10, when the input signal power is too small, the software will automatically prompt "loop to the input SNR is not less than -10", the loop is calculated SNR The formula is:

[0132] I吨utCN= 174-NF+I吨utMinPower-10*Log炬L)/Log(10)-3 [0132] I t utCN = 174-NF + I t utMinPower-10 * Log torch L) / Log (10) -3

[0133] InputCN为环路输入信噪比,NF为锁相接收机噪声系数,InputMinPower为最小输入信号,InputBW为输入信号中频带宽。 [0133] InputCN input SNR of the loop, NF is the noise figure of the receiver phase lock, InputMinPower for the minimum input signal, InputBW IF bandwidth of the input signal.

[0134] 较佳的,可W通过测量得到压控晶振的压控灵敏度、鉴相器的鉴相灵敏度,其中鉴相器的鉴相灵敏度与输入功率大小有关,测量方法为先标定进入鉴相器的输入信号大小, 然后保持相同条件将鉴相器输入端断开,输入信号源产生的差拍信号,确保与标定值相等, 使用示波器测量差拍波形,过中间点斜率为鉴相灵敏度,结果为示波器测量差拍波峰的峰值/n。 [0134] Preferably, W may be obtained by measuring the voltage controlled oscillator is a voltage control sensitivity, the sensitivity of the phase of the phase detector, wherein the phase sensitivity of the input power magnitude related to the phase detector, the calibration measurement for the first phase into the input signal's magnitude and phase conditions remain the same input terminal is disconnected, the input signal is a difference beat signal generated by the source, to ensure equal calibration value, measured using an oscilloscope waveform of the beat, through the intermediate point of the phase slope sensitivity, results beat peaks measured peak / n oscilloscope.

[0135] 较佳的,针对不同的应用场合可W在参数库中预设有不同的输入频率扫描范围和输入频率变化率。 [0135] Preferably, for different applications may be preset in the parameter W library has a different input frequency sweep range and rate of change of the input frequency.

[0136] 较佳的,可W设置不同的环路滤波器参数,本发明中滤波器仅有3个一阶有源滤波器电阻和1个一阶有源滤波器电容需要外部输入改变。 [0136] Preferably, W may be a different set of loop filter parameters, the filter of the present invention, only three first-order active filter resistor and a first-order active filter capacitors need to change the external input.

[0137] 较佳的,通过合理设计可W自动测量得到锁相环路主要参数,单边带环路带宽、自然谐振频率、阻巧系数、环路信噪比、稳态相位误差、快捕带,相关预设规则为; [0137] Preferably, W may be designed through rational automatically measured parameters main PLL, the loop bandwidth SSB, natural resonant frequency, Qiao resistance coefficient, a loop signal to noise ratio, the steady state phase error, rapid acquisition with relevant preset rules;

[0U8]Kv=Kv.Text*1000*2*3. 14/m, [0U8] Kv = Kv.Text * 1000 * 2 * 3. 14 / m,

[0139] K= (RreqmultipleTime.Text+1)体d*Kv,其中,(RreqmultipleTime)+1 为晶振总的倍频次数 [0139] K = (RreqmultipleTime.Text + 1) body d * Kv, wherein, (RreqmultipleTime) +1 is the total number of frequency doubling crystal

[0140] T1 = (C.Text)*(Rl.Text)*(l+巧2.Text)/巧3.Text))/1000 [0140] T1 = (C.Text) * (Rl.Text) * (l + clever 2.Text) / Qiao 3.Text)) / 1000

[0141] T2 = (C.Text)*(R2.Text)/lOOO [014引A=巧3.Text:)/巧1.Text:), [0141] T2 = (C.Text) * (R2.Text) / lOOO [014 primer A = Qiao 3.Text:) / Qiao 1.Text :),

[0143] 其中,时间常数 [0143] wherein the time constant

Figure CN104821821AD00111

,时间常数T2 =R2XC,滤波器直流增益A= R3/R1 , The time constant T2 = R2XC, filter DC gain A = R3 / R1

[0144] Wn=SqHK/Tl) [0144] Wn = SqHK / Tl)

[0145] E= (Wn/2) * (T化1/ (A*K)) [0145] E = (Wn / 2) * (T of 1 / (A * K))

[0146] 化=Wn* (E/化1/巧巧)) [0146] of = Wn * (E / of 1 / Qiaoqiao))

[0147]CN= 174-NF+I吨utMinPower-10*Log炬L)/Log(10)-3 [0147] CN = 174-NF + I t utMinPower-10 * Log torch L) / Log (10) -3

[0148]PhaseError= (FreqSweepRange.Text) *1000*36〇/K/A+巧reqSweepRate. Text)*1000*360/(Wn*Wn) [0148] PhaseError = (FreqSweepRange.Text) * 1000 * 36〇 / K / A + clever reqSweepRate. Text) * 1000 * 360 / (Wn * Wn)

[0149] FastCap化reBW= 2 巧*Wn/6. 18 [0149] FastCap coincidence of reBW = 2 * Wn / 6. 18

[0150] 其中,Kv为压控晶振的压控灵敏度,Kv.Text为测量得到的压控灵敏度结果, Kd为鉴相器的鉴相灵敏度,K为压控晶振输出频率总的倍频次数,Wn为环路自然谐振频率,E为阻巧系数,化为单边带环路带宽,化eqSweepRange为设置的输入频率扫描范围, 化eqSweepRate为设置的输入频率扫描速率,CN为环路信噪比,NF为锁相接收机噪声系数, InputMinPower为最小输入信号,PhaseElrror为环路稳态相位误差,FastCap1:ureBW为快捕-W- J巿'〇 [0150] wherein the voltage control sensitivity Kv of the voltage controlled oscillator, Kv.Text voltage control sensitivity of the measured result, for the Kd of the phase detector sensitivity of the phase detector, K is the total number of times the frequency of the voltage controlled oscillator output frequency, Wn is the natural resonant frequency of the loop, E is the coefficient of resistance Qiao, SSB into the loop bandwidth of the frequency sweep range eqSweepRange input set of input frequency sweep rate eqSweepRate set, CN is the loop SNR , NF is the noise figure of the receiver phase lock, InputMinPower for the minimum input signal, PhaseElrror the loop steady state phase error, FastCap1: ureBW faster capture market -W- J 'square

[0151] 较佳的,锁相接收机中环路信噪比应大于6地,且越大越好,阻巧系数约等于0. 7, 环路稳态相位误差小于20°,快捕带越大越好。 [0151] Preferably, the receiver phase locked loop to noise ratio should be greater than 6, and the bigger the better, Qiao resistance coefficient approximately equal to 0.7, the loop steady state phase error of less than 20 °, with larger and more rapid acquisition it is good.

[0152] 综上所述,利用本发明将极大减少锁相接收机调试工作量,可广泛应用于各种频段统一测控体制锁相接收机中。 [0152] As described above, with the present invention will greatly reduce the workload debug lock receiver it can be widely used in various measurement and control system of uniform frequency lock receiver.

[0153] W上所述仅为本发明的较佳实施例,本领域技术人员知悉,在不脱离本发明的精神和范围的情况下,可W对该些特征和实施例进行各种改变或等同替换。 [0153] The preferred embodiments of the present invention only the W embodiment, those skilled in the art knows, without departing from the spirit and scope of the invention, such features may be W and the various modifications or embodiments equivalents. 另外,在本发明的教导下,可W对该些特征和实施例进行修改W适应具体的情况及材料而不会脱离本发明的精神和范围。 Further, the teachings of the present invention, some features of the W and W embodiments can be modified to adapt to a particular situation and material without departing from the spirit and scope of the invention. 因此,本发明不受此处所公开的具体实施例的限制,所有落入本申请的权利要求范围内的实施例都属于本发明的保护范围。 Accordingly, the present invention is not limited to the specific embodiments disclosed herein, embodiments within the scope of the present invention fall within the protection scope of all to fall within the present application.

Claims (7)

1. 一种锁相接收机环路参数确定方法,其特征在于,包括: 步骤1,初始化条件参数,和对环路部件测试获得环路部件指标数据; 步骤2,设置一阶有源滤波器的电阻和电容参数; 步骤3,根据所述条件参数、环路部件指标数据、一阶有源滤波器的电阻和电容参数以及预设规则获得锁相接收机环路参数,所述锁相接收机环路参数包含单边带环路带宽、自然谐振频率、阻尼系数、环路输入信噪比、环路信噪比、稳态相位误差、快捕带; 步骤4,判断是否同时满足: 所述环路信噪比大于6dB, 所述阻尼系数自0. 65-0. 75范围内, 所述稳态相位误差小于20°, 若不同时满足,则返回步骤2, 若同时满足,则输出和/或保存所述单边带环路带宽、自然谐振频率、阻尼系数、环路输入信噪比、环路信噪比、稳态相位误差、快捕带的数值。 A phase-locked loop receiver parameter determination method comprising: a step 1, the initialization condition parameters, and access to the loop index of the loop member member test data; step 2, a set order active filter the resistance and capacitance parameters; step 3, to obtain the receiver phase locked loop parameters according to the condition parameter, index data loop member, the resistance and capacitance parameters and a preset rule order active filter, said lock receiving machine comprising a single sideband loop bandwidth loop parameters, natural resonant frequency, damping, loop input SNR, SNR loop, steady state phase error, with fast acquisition; step 4, it is determined whether or not simultaneously satisfied: the 6dB SNR is greater than said loop, the damping coefficient in a range from 0. 65-0. 75, the steady state phase error is less than 20 °, while not satisfied, return to step 2, while if satisfied, the output and / or storing the loop bandwidth single sideband, natural resonant frequency, damping, loop input SNR, SNR loop, steady state phase error, with the value of the rapid acquisition.
2. 根据权利要求1所述的一种锁相接收机环路参数确定方法,其特征在于,所述条件参数包括噪声系数、中频带宽、最小输入信号、晶振倍频次数、输入信号频率变化范围和频率变化率; 所述指标数据包括压控晶振的压控灵敏度和鉴相器的鉴相灵敏度。 2. A method according to one determined parameter of the phase-locked loop receiver as claimed in claim 1, wherein the condition parameter comprises a noise factor, IF bandwidth, minimum input signal, the number of crystal multiplier, the input signal frequency range and a frequency change rate; the index data comprises a phase sensitive phase detector and a voltage control sensitivity of the voltage controlled crystal oscillator.
3. 根据权利要求2所述的一种锁相接收机环路参数确定方法,其特征在于,所述对环路部件测试并获得鉴相器的鉴相灵敏度的过程为: 步骤1. 1,测量获得所述鉴相器的输入端信号幅度, 步骤1. 2,其他条件不变仅断开所述频谱分析仪与所述鉴相器输入端的连接,外接信号源输出信号至向所述鉴相器输入端, 步骤1. 3,设置所述信号源输出信号幅度为步骤I. 1中测量获得的输入端信号幅度, 步骤1. 4,通过示波器测量获取差拍波形,示波器测量差拍波峰的峰峰值/ 31为所述鉴相器的鉴相灵敏度。 3. According to a phase locked loop receiver parameter determination method according to claim 2, wherein, during said discriminators and the loop member to obtain a test phase of the phase detector sensitivity: Step 1.1, input signal amplitude obtained by the measurement of the phase detector, step 1.2, the other conditions remain unchanged only disconnected spectrum analyzer connected to an input terminal of the phase detector, to the external signal source output signal to the discriminator phase input terminal, step 1.3, provided the signal source output signal amplitude of input signal amplitude measured in step I. 1 obtained in step 1.4, the oscilloscope by measuring the beat waveform acquisition, measurement oscilloscope beat peaks phase peak sensitivity / 31 to the phase detector.
4. 根据权利要求1所述的一种锁相接收机环路参数确定方法,其特征在于,所述预设规则为: Kv = Kv. Text*1000*2*3. 14/m, K = (FreqmultipleTime. Text+l)*Kd*Kv,其中,(FreqmultipleTime)+l 为晶振总的倍频次数Tl = (C. Text) * (Rl. Text) * (1+ (R2. Text) / (R3. Text)) /1000 T2= (C. Text)*(R2. Text)/1000 A = (R3. Text)/(Rl. Text), 4. According to one determined parameter of the phase-locked loop receiver as claimed in claim 1, characterized in that the preset rule is:.. Kv = Kv Text * 1000 * 2 * 3 14 / m, K = (FreqmultipleTime. Text + l) * Kd * Kv, wherein, (FreqmultipleTime) + l is the total number of crystal multiplier Tl = (C. Text) * (Rl. Text) * (1+ (R2. Text) / ( R3. Text)) / 1000 T2 = (C. Text) * (R2. Text) / 1000 A = (R3. Text) / (Rl. Text),
Figure CN104821821AC00021
Wn = Sqr (K/Tl) E = (ffn/2)*(T2+l/(A*K)) BL = ffn*(E/2+l/(8*E)) CN = 174-NF+InputMinPower-10*Log(BL)/Log(10)-3 PhaseError = (FreqSweepRange. Text)*1000*360/K/A+(FreqSweepRate. Text)*1000*360/(ffn*ffn) FastCaptureBff = 2*E*ffn/6. 18 其中,Kv为压控晶振的压控灵敏度,Kv. Text为测量得到的压控灵敏度结果,Kd为鉴相器的鉴相灵敏度,K为压控晶振输出频率总的倍频次数,Wn为环路自然谐振频率,E为阻尼系数,BL为单边带环路带宽,FreqSweepRange为设置的输入频率扫描范围,FreqSweepRate 为设置的输入频率扫描速率,CN为环路信噪比,NF为锁相接收机噪声系数,InputMinPower 为最小输入信号,PhaseError为环路稳态相位误差,FastCaptureBW为快捕带。 Wn = Sqr (K / Tl) E = (ffn / 2) * (T2 + l / (A * K)) BL = ffn * (E / 2 + l / (8 * E)) CN = 174-NF + InputMinPower-10 * Log (BL) / Log (10) -3 PhaseError = (FreqSweepRange. Text) * 1000 * 360 / K / A + (FreqSweepRate. Text) * 1000 * 360 / (ffn * ffn) FastCaptureBff = 2 * E * ffn / 6. 18 where, Kv is a voltage-controlled oscillator of a voltage control sensitivity, Kv. results Text voltage control sensitivity is measured, Kd is the phase sensitivity of the phase detector, K is the total times of the voltage controlled oscillator output frequency frequency number, Wn is the natural resonant frequency of the loop, E is the damping coefficient, BL is the loop bandwidth single sideband, FreqSweepRange input frequency sweep range setting, FreqSweepRate frequency sweep rate of the input set, CN is the loop SNR , NF is the noise figure of the receiver phase lock, InputMinPower for the minimum input signal, PhaseError the loop steady state phase error, FastCaptureBW faster capture band.
5. -种参数计算器,其特征在于,包括输入模块和计算模块; 所述输入模块用于: 初始化条件参数, 对环路部件测试获得环路部件指标数据, 以及设置一阶有源滤波器的电阻和电容参数; 所述计算模块用于: 根据所述条件参数、环路部件指标数据、一阶有源滤波器的电阻和电容参数以及预设规则获得锁相接收机环路参数,所述锁相接收机环路参数包含单边带环路带宽、自然谐振频率、阻尼系数、环路输入信噪比、环路信噪比、稳态相位误差、快捕带。 5. - kind of parameter calculator, characterized by comprising an input module and a calculation module; the input module configured to: initialize condition parameters to obtain the data indicator member loop the loop component testing, and setting a first-order active filter the resistance and capacitance parameters; the computing module is configured to: obtain a phase locked loop parameters according to the condition of a receiver parameter, a loop index data member, the resistance and capacitance parameters and a preset rule order active filter, the said phase locked loop parameters comprising a single sideband receiver loop bandwidth, natural resonant frequency, damping, loop input SNR, SNR loop, steady state phase error, with fast acquisition.
6. 根据权利要求5所述的一种参数计算器,其特征在于,所述预设规则为: Kv = Kv. Text*1000*2*3. 14/m, K = (FreqmultipleTime. Text+l)*Kd*Kv,其中,(FreqmultipleTime)+l 为晶振总的倍频次数Tl = (C. Text) * (Rl. Text) * (1+ (R2. Text) / (R3. Text)) /1000 T2= (C. Text)*(R2. Text)/1000 A = (R3. Text)/(Rl. Text), 6. A parametric calculator according to claim 5, wherein the preset rule is:... Kv = Kv Text * 1000 * 2 * 3 14 / m, K = (FreqmultipleTime Text + l ) * Kd * Kv, wherein, (FreqmultipleTime) + l is the total number of crystal multiplier Tl = (C. Text) * (Rl. Text) * (1+ (R2. Text) / (R3. Text)) / 1000 T2 = (C. Text) * (R2. Text) / 1000 A = (R3. Text) / (Rl. Text),
Figure CN104821821AC00031
Wn = Sqr (K/Tl) E = (ffn/2)*(T2+l/(A*K)) BL = ffn*(E/2+l/(8*E)) CN = 174-NF+InputMinPower-10*Log(BL)/Log(10)-3 PhaseError = (FreqSweepRange. Text)*1000*360/K/A+(FreqSweepRate. Text)*1000*360/(ffn*ffn) FastCaptureBff = 2*E*ffn/6. 18 其中,Kv为压控晶振的压控灵敏度,Kv. Text为测量得到的压控灵敏度结果,Kd为鉴相器的鉴相灵敏度,K为压控晶振输出频率总的倍频次数,Wn为环路自然谐振频率,E为阻尼系数,BL为单边带环路带宽,FreqSweepRange为设置的输入频率扫描范围,FreqSweepRate 为设置的输入频率扫描速率,CN为环路信噪比,NF为锁相接收机噪声系数,InputMinPower 为最小输入信号,PhaseError为环路稳态相位误差,FastCaptureBW为快捕带。 Wn = Sqr (K / Tl) E = (ffn / 2) * (T2 + l / (A * K)) BL = ffn * (E / 2 + l / (8 * E)) CN = 174-NF + InputMinPower-10 * Log (BL) / Log (10) -3 PhaseError = (FreqSweepRange. Text) * 1000 * 360 / K / A + (FreqSweepRate. Text) * 1000 * 360 / (ffn * ffn) FastCaptureBff = 2 * E * ffn / 6. 18 where, Kv is a voltage-controlled oscillator of a voltage control sensitivity, Kv. results Text voltage control sensitivity is measured, Kd is the phase sensitivity of the phase detector, K is the total times of the voltage controlled oscillator output frequency frequency number, Wn is the natural resonant frequency of the loop, E is the damping coefficient, BL is the loop bandwidth single sideband, FreqSweepRange input frequency sweep range setting, FreqSweepRate frequency sweep rate of the input set, CN is the loop SNR , NF is the noise figure of the receiver phase lock, InputMinPower for the minimum input signal, PhaseError the loop steady state phase error, FastCaptureBW faster capture band.
7. 根据权利要求5所述的一种参数计算器,其特征在于,还包括一比较模块,判断是否同时满足: 所述比较模块用于判断是否同时满足: 所述环路信噪比大于6dB, 所述阻尼系数自0. 65-0. 75范围内, 所述稳态相位误差小于20°, 若不同时满足,则输出"设置有误"并返回步骤2, 若同时满足,则输出和/或保存所述单边带环路带宽、自然谐振频率、阻尼系数、环路输入信噪比、环路信噪比、稳态相位误差、快捕带的数值。 7. A parametric calculator according to claim 5, characterized by further comprising a comparison module determines whether the satisfied simultaneously: a comparison module for determining whether satisfied simultaneously: the loop SNR greater than 6dB the damping factor in the range of 0. 65-0. 75 from the steady state phase error is less than 20 °, while if not satisfied, "setting error" and returns to step 2, while if satisfied, the output, and / or store the single sideband loop bandwidth, natural resonant frequency, damping, loop input SNR, SNR loop, steady state phase error, with the value of the rapid acquisition.
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CN101915932A (en) * 2010-06-12 2010-12-15 北京航空航天大学 Radio frequency front-end device for dual-system and dual-frequency navigation receiver
CN102104411A (en) * 2010-12-29 2011-06-22 浙江大学 Receiver circuit used for pico-satellite
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US20110250926A1 (en) * 2009-12-21 2011-10-13 Qualcomm Incorporated Dynamic antenna selection in a wireless device
CN101915932A (en) * 2010-06-12 2010-12-15 北京航空航天大学 Radio frequency front-end device for dual-system and dual-frequency navigation receiver
CN102104411A (en) * 2010-12-29 2011-06-22 浙江大学 Receiver circuit used for pico-satellite

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