CN104798002A - Enforcing a power consumption duty cycle in a processor - Google Patents

Enforcing a power consumption duty cycle in a processor Download PDF

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Publication number
CN104798002A
CN104798002A CN201280076797.2A CN201280076797A CN104798002A CN 104798002 A CN104798002 A CN 104798002A CN 201280076797 A CN201280076797 A CN 201280076797A CN 104798002 A CN104798002 A CN 104798002A
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Prior art keywords
power
processor
power consumption
restriction
limit
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CN201280076797.2A
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CN104798002B (en
Inventor
A·万玛
K·西斯特拉
M·T·罗兰德
B·J·格里非斯
V·D·维克曼
J·R·道策特
E·J·德哈默
V·加吉
C·普艾里耶
J·J·谢拉
A·N·阿南塔克里什南
S·H·冈瑟
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Intel Corp
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Intel Corp
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/06—Clock generators producing several clock signals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/44—Encoding
    • G06F8/443—Optimisation
    • G06F8/4432—Reducing the energy consumption
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a plurality of graphics engines each to independently perform graphics operations; and, a power control unit coupled to the plurality of cores to control power consumption of the processor, where the power control unit includes a power excursion control logic to limit a power consumption level of the processor from being above a defined power limit for more than a duty cycle portion of an operating period. Other embodiments are described and claimed.

Description

Implement power consumption dutycycle within a processor
Background
The development of semiconductor machining and logical design has allowed the amount of the logic that can be present in integrated circuit (IC)-components to increase.Therefore, computer system configurations has been evolved to multiple hardware threads, Duo Gehe, multiple equipment and/or the complete system on each integrated circuit from the single or multiple integrated circuit system.In addition, along with integrated circuit density increases, the power demand of computing system (from embedded system to server) also progressively improves.In addition, software is inefficient and the requirement of hardware has also been caused to the raising of computing equipment energy consumption.In fact, some researchs show that computing equipment consumes the remarkable number percent in the whole electric power supply of country (such as the U.S.).Therefore, exist the efficiency be associated with integrated circuit and energy-conservation crucial requirement.When server, desktop computer, notebook, super, panel computer, mobile phone, processor, embedded system etc. become (from being included in normatron, automobile and televisor to being included in biotechnology) even more prevailing, these needs will increase.
For the power management of the integrated circuit of such as processor (in server and client) and so on based on the estimation to current processor power consumption.What the various assemblies of processor may have them is modulated into voltage in the power limit that remains on and specify and frequency.This is like this, because the power supply unit in computer platform (PSU) has very concrete restriction to the peak power that they can provide.These PSU have usually can ad infinitum/continuable power level of heat of maintaining continuously, and can only maintain the continuable power level of higher electricity of concrete duration and dutycycle.The average power provided by power supply in the heat effective time period can not exceed hot continuable rank.By too much for power supply size design can increased in size, cost and efficiency to tackle worst case, and power supply size design obtained too small meeting cause catastrophic consequence.
Accompanying drawing is sketched
Fig. 1 is the block diagram of system according to an embodiment of the invention.
Fig. 2 is the process flow diagram of method according to an embodiment of the invention.
Fig. 3 be according to one embodiment of the invention for storing the block diagram for the various configuration of Duty ratio control and the storer of other values.
Fig. 4 is the graphic extension of dutycycle enforcement technology according to an embodiment of the invention.
Fig. 5 is another graphic extension of dutycycle enforcement technology according to an embodiment of the invention.
Fig. 6 is the block diagram of processor according to an embodiment of the invention.
Fig. 7 is the block diagram of multi-domain processing device according to another embodiment of the invention.
Fig. 8 is the block diagram of system according to an embodiment of the invention.
Embodiment
In embodiments, provide a kind of mechanism based on processor, for implementing constraint, to allow the rated peak power supply of suitable size to be used for providing electric energy in the mode ensured to the power consumption of processor.For this reason, each embodiment implements such constraint, the power consumption of processor and dynamic range expansion to close to, but ensure the design restriction not exceeding power supply.
So, processor is configured with the power limit of the restriction that it attempts to be adjusted to.Prevent the worst case power excursion higher than this power limit have higher than limit maximum power level P maxsize.In addition, this worst case power excursion higher than power limit is also prevented to have the time to peak being longer than worst case duration T 1.In addition, also the duration of being longer than duration T 2 can not had higher than the power excursion of the power limit limited.And, any skew higher than power limit be limited to not higher than d% dutycycle (higher than the limit time/T.T., time_above_limit/total_time).By utilizing constraint manipulation processor above, rated peak power supply can operate close to its design restriction, without the need to unnecessary buffer zone (extra cost), if or violate design restriction, electric fault (extra risk) can not be produced.
Although scope of the present invention is unrestricted in this regard, Duty ratio control as described herein can pass through firmware, hardware, software, and its combination realizes, so, for all skews higher than the power limit limited, implement fixing dutycycle and maximum length in time.
With reference now to Fig. 1, shown in be the block diagram of a part for system according to an embodiment of the invention.As shown in Figure 1, system 100 can comprise various assembly, comprises processor 110, and as shown in the figure, this processor 110 is polycaryon processors.Processor 110 can be coupled to power supply 150 by external voltage regulator 160, and this regulator 160 can perform the first voltage transitions, to provide the voltage be tentatively conditioned to processor 110.
Can find out, processor 110 can be comprise multiple core 120 a-120 nsingle die processor.In addition, each core can also with single voltage regulator 125 a-125 nbe associated.Correspondingly, fully-integrated voltage regulator (FIVR) can be provided to realize, to allow to carry out fine-grained control to the voltage of each single core, thus fine-grained control is carried out to power and performance.So, each core can operate under independent voltage and frequency, allows large dirigibility, and is provided for the chance widely of balanced power consumption and performance.
Still with reference to figure 1, extra assembly may reside in processor, comprises input/output interface 132, another interface 134 and integrated Memory Controller 136.Can find out, each in these assemblies can by another integrated voltage regulator 125 xpower.In one embodiment, interface 132 can meet fast path interconnection (QPI) agreement, this agreement provides point-to-point (PtP) link in cache coherent protocol, and this cache coherent protocol comprises multiple layer, comprises Physical layer, link layer and protocol layer.Interface 134 can meet again periphery component interconnection (PCIe fast tM) specification, such as, PCI Express tMnormative foundation specification version 2.0 (on January 17th, 2007).
Also show power control unit (PCU) 138, this power control unit (PCU) 138 can comprise and performs the hardware of power management operation, software and/or firmware for processor 110.In embodiments, PCU 138 can comprise and performs Duty ratio control according to one embodiment of present invention, the skew higher than the power limit limited to be restricted to a part and the logic of limited duration in operating cycle.In addition, PCU138 can also be coupled to external voltage regulator 160 by special purpose interface.So, PCU 138 can provide the voltage be conditioned of request by instructed voltage regulator to processor.In addition, voltage regulator 160 can provide the information of carrying about its electric current to processor.In different realizations, this information can be stored in the register of the voltage regulator of PCU access by voltage regulator 160.Or the current sensor in voltage regulator 160 or between voltage regulator 160 and PCU 138 path can provide this information.This current information and corresponding power consumption are determined (such as, power detector by PCU) power consumption that can be used for based on processor by occupancy controller (the power excursion logic of such as PCU 138), limit higher than other skew of the power-consumption level limited.So, the current sensor based on voltage regulator directly can measure the electric current supplied to processor by voltage regulator 160.When being multiplied by supply voltage, this can provide the measured value of processor power consumption.
Although not shown for ease of illustrating, be appreciated that extra assembly may reside in processor 100, such as un-core logic and other assemblies, such as internal storage, such as, buffer memory hierarchical structure of one or more rank etc.In addition, although be utilize shown in integrated voltage regulator in the realization of Fig. 1, each embodiment is not restrictive.
Although the following examples are reference examples as the energy-conservation and efficiency in the specific integrated circuit of computing platform or processor describes, but other embodiment is applicable to integrated circuit and the logical device of other type.Similar technology and the instruction of embodiment described here are applicable to the circuit or semiconductor devices that also can benefit from better efficiency and other energy-conservation type.Such as, disclosed embodiment is not limited to the computer system of any particular type, and also can be used for miscellaneous equipment, such as handheld device, system on chip (SoC) and Embedded Application.Some examples of handheld device comprise cell phone, the Internet protocol devices, digital camera, personal digital assistant (PDA) and Hand held PC.Embedded Application generally comprises microcontroller, digital signal processor (DSP), network computer (net book), Set Top Box, hub, wide area network (WAN) switch maybe can perform the function of teaching below and other system any of operation.In addition, the device described in the application, method and system are not limited to physical computing devices, but also relate to for energy-conservation and software optimization that is efficiency.Become apparent as will be described in the following, the embodiment (no matter being about hardware, firmware, software or their combination) of methods, devices and systems described herein will be vital for " green technology " future, such as the energy-conservation and energy efficiency comprising the economic most product of US.
Note, power described herein controls can independent of the mechanism based on operating system (OS), such as advanced configuration and platform interface (ACPI) standard (such as, the Rev.3.0b that on October 10th, 2006 is issued), and complementary with it.According to ACPI, processor may operate in various performance state or rank, that is, from P0 to PN.Generally speaking, P1 performance state can correspond to the performance state of the highest guarantee can asked by OS.Except this P1 state, OS can also ask superior performance state, that is, P0 state.So, this P0 state can be opportunistic state, and wherein, when having electric energy and/or heat budget is available, processor hardware can configuration processor or its at least some part, so that with higher than the frequencies operations ensured.In many realizations, processor can comprise first frequency (bin frequency) of multiple so-called maximum frequency (being also referred to as P1 frequency) higher than ensureing.By controlling some processor parameter as described herein, the performance class of OS request can not be allowed to occur, to implement power delivery system constraint.
As an example of the Duty ratio control that can perform, can maintain the dynamic frequency limit, this dynamic frequency limit is the maximum operation frequency that processor is allowed to that point runs in preset time.Various power/performance management algorithm may ask the performance the frequency being up to this limit (but not higher).In each evaluation interval (Tp), can measurement processor power consumption, to judge that whether it is higher than the power limit limited.In various embodiments, this measurement can be passed through from voltage regulator, or the embedded power estimator in processor is directly measured.If power P is higher than the power limit PL (P>PL) limited, so, frequency limitation can be lowered, and such as, reaches a step-length.This is new frequency limitation, and remains minimum and hold time, T min_hold.Due to the majorant that processor power is processor frequencies, therefore, this can reduce power consumption.In one embodiment, duty_cycle=Tp/ (Tp+T can be passed through min_hold), derive T from desired dutycycle min_hold.If in holding time, power still exceeds the limit (P>PL) of restriction, then again can reduce frequency limitation, such as, reduces another step-length, holds time and again can extend T min_hold.
Given possible worst case power excursion (P max), can calculate the quantity of power reduction to the frequency step of the limit (PL), cause worst case shift duration: T max_excursion=max_num_steps*Tp
In certain embodiments, so-called " clashing into for the N time " behavior can be realized.That is, the maximum length in time of skew depends on the size (P of skew max-PL), the size of each frequency step and Tp.By power consumption being reduced to a known power state can be restricted to the maximal value of N*Tp the duration, this known power state ensures when N secondary frequencies step lower than PL, and wherein, N is predetermined constant.
In certain embodiments, the different power control mechanism that can realize is by the control to electrical design point (EDP) budget.Follow the tracks of this budget, to guarantee to produce unsafe situation in electricity.The frequency of the module on given various tube core or state, the worst case electric current that this budget tracking can consume, to guarantee that it can not exceed the given momentary current limit.Replace reduce frequency limitation, EDP budget (such as, reduce several step value or be reduced to intended level) can be reduced, and and non-reduced frequency limitation because the different territory of processor can operate with different frequency.
Referring now to Fig. 2, illustrated therein is the process flow diagram of method according to an embodiment of the invention.As shown in Figure 2, method 200 can be realized by the logic of PCU.More specifically, method 200 can be realized by the power excursion steering logic of PCU, and this power excursion steering logic can receive and process the information that the instantaneous power about processor consumes.Can find out, method 200 is (rhombus 210) from whether the power consumption rank of decision processor is greater than the power limit of restriction.Note, this judgement can regularly be made, such as, in evaluation interval, as a part for the regular execution of the power control logic of PCU, and the so-called P code such as performed in PCU or in other parts of processor or firmware.This scheduled cycle can be roughly each millisecond (ms).This power limit limited in configuration register can be stored in, can be fixed, such as, in the system product by original equipment manufacturer (OEM) (OEM).Or the power limit of restriction can be that user controls, with allow user determine can power-limiting skew power level.
Still with reference to figure 2, next, at rhombus 220, can judge whether the overstep the extreme limit number of times of power detection of continuous print is greater than number of thresholds.That is, if successive ignition points out situation about overstepping the extreme limit, this means, the current power consumption level of processor is too high, and does not reduce with fully fast speed.Correspondingly, control to enter frame 240, there, the frequency limitation of processor can be lowered to predetermined value.In one embodiment, this predetermined value can corresponding to guaranteeing that the power consumption of processor drops to the rank under the power limit of restriction.Otherwise if at rhombus 220, it is fixed to judge whether, because the quantity of the power detection that oversteps the extreme limit is less than this threshold value, then control to enter frame 230, there, frequency limitation can reduce to reach a step value.Exemplarily, this step value can correspond to first frequency, and in a specific implementation, this yuan of frequency can correspond to reference clock frequency, such as, and 100 megahertzes (MHz).
Note, in any one situation, the reduction of frequency limitation will cause reducing of the operating frequency of at least some part of processor again.Such as, in response to this reduction of frequency limitation, their operating frequency can reduce by the core field of processor and figure territory.In some implementations, can be carried out this immediately change when the renewal frequency limit.In other realize, can occur in the analytic process of the routine to operating frequency, such as, as a part for P code this adjustment of operating frequency.
Still with reference to figure 2, control to enter frame 250 from frame 230 and 240, there, adjustment of holding time can be reached minimum value of holding time.This holds time and corresponds to the duration that current power consumption level (that is, here, the power consumption rank of reduction) will be maintained before the increase allowing power consumption.So, this holds time and partly allows to maintain given dutycycle, because the power consumption of processor is only allowed to the power limit higher than limiting in the part in whole operating cycle.Although scope of the present invention is unrestricted in this regard, this power limit limited may depend on the type of processor and different, such as, in certain embodiments, for flush bonding processor, roughly 100 milliwatts, for processor-server, 200 watts.
Next, control to enter rhombus 260, whether there, can judge to hold time completes.If no, then can reduce at frame 270 and hold time.Such as, the length of the evaluation interval that can reduce method 200 of holding time, such as, 1 millisecond.Otherwise increase if judge to have held time again can carry out potential power consumption, control to enter frame 280, there, frequency limitation can improve.Although scope of the present invention is unrestricted in this regard, in one embodiment, this raising can be step value.Note, this increase of frequency limitation not necessarily may cause the corresponding increase of the operating frequency of one or more domain processor, because if system software does not ask upper frequency, then can maintain current operating frequency rank.Although represent with so high-level in the embodiment of Fig. 2, but be appreciated that scope of the present invention is not limited thereto aspect.
As discussed above, various information is for judging the existence of power excursion and correspondingly controlling them.With reference now to Fig. 3, shown in be block diagram for storing the storer for the various configuration in such operation and other values.As shown in Figure 3, storer 300 can be Parasites Fauna in processor or other storage mechanism.Exemplarily, storer 300 can be configuration in the power control unit of processor and status register at least partially.So, in various element illustrated in fig. 3, each can correspond to the register storing one or more value.Replace register, the storer of another kind of type can be there is, such as comprise multiple destination memories, such as, cache memory, the such as storer of static RAM (SRAM) or other types.
Can find out, storer 300 comprises the first memory 310 storing the dynamic frequency limit.So, this dynamic limit can be arranged by PCU in the implementation of method 200, is in particular value so to cause frequency limitation.After this, PCU can access this value in performance/power management operation process, to judge whether the performance class allowing request occurs.Such as, suppose software asks is made for so-called P0 performance class (supposing to occur in the frequency limitation of 3.5 kilo-mega cycles per seconds (GHz)).If storer 310 comprises the frequency limitation of 3.0GHz, then do not carry out the change to this P0 performance class, processor performance be limited to utilize 3.0GHz operating frequency can performance.
Storer 300 also comprises storer 320 of holding time, this hold time storer 320 can in the implementation of method 200 accessed and upgrade, to judge whether holding power to reduce.Next, storer 300 also comprises power limit storer 330 and the second power limit storer 340 limited of the first restriction.These values can be as discussed above, that is, store the Configuration Values of short-term and the long term power limit respectively.Dutycycle storer 350 can be used to store dutycycle, in one embodiment, dutycycle can be that Configuration Values is so to identify the limit, such as, the limit of the number percent of total running time of the power limit (such as, the first power limit limited) of restriction can be exceeded corresponding to processor operations.
Still with reference to figure 3, storer 300 also comprises shift duration storer 360 and peak excursion duration memory 370.These storeies can stored configuration value, namely, shift duration, this shift duration is the time quantum that power consumption is allowed to higher than the power limit limited, and the peak excursion duration, this peak excursion duration corresponds to power consumption and is allowed to be in the time quantum that the worst case higher than power limit offsets.(note, this duration is set to lower duration ratio deviation duration).Finally, storer 300 comprises continuous print and to overstep the extreme limit detection threshold storer 380, and this storer 380 can store the Configuration Values of the number of thresholds detected that to overstep the extreme limit corresponding to the continuous print be allowed to.If reach this threshold value (such as, n=5), mean, five continuous print power consumption readings, higher than the power limit limited, can be carried out and frequency limitation is reduced to the frequency of guaranteed output consumption lower than the power limit limited immediately.Although be utilize shown in these particular storage element in storer 300, but, be appreciated that scope of the present invention is unrestricted in this regard, other storeies of these and other storer in PCU or processor can comprise other information segments many.
With reference now to Fig. 4, shown in be the graphic extension of dutycycle enforcement technology according to an embodiment of the invention.As shown in Figure 4, suppose that processor is configured to the power limit of the restriction with 100 watts (W).Also in this example, hypothesis evaluation interval (Tp) corresponding to 1ms, the minimum (T that holds time min_hold) be 3 milliseconds, dutycycle is set to 25%.As shown in Figure 4, the power consumption of processor starts to exceed its power limit limited, and rises to the rank of 120W.When this power consumption rank exceeds the power limit of restriction, this rank of hypothesis can not exceed higher worst case power limit further.So, in the evaluation interval occurred after increasing in this power consumption, there is the detection to situation about overstepping the extreme limit.So, can frequency limitation be reduced, in addition, can also arrange and hold time.As a result, the reduction of frequency limitation causes other reduction of power-consumption level, power consumption rank is taken to the power limit of restriction.
In addition, be also set to owing to holding time, such as, minimumly hold time, note, before this has held time, larger power consumption can not occur.Then, now, again can improve frequency limitation, cause another rising of power consumption.Suppose that pattern illustrated in fig. 4 continues in operation, such as, the dutycycle of the configuration of 25% is maintained, so that the power consumption of processor can not exceed the power level of restriction within being greater than this duty and making a gesture of measuring.So, implement dutycycle, there is the effective guarantee of power constraints.Certainly, should be appreciated that the different mode controlling to hold time is fine, plural power limit can be provided further, the various power control mechanisms except reducing operating frequency are also provided.
With reference now to Fig. 5, shown in be another graphic extension of dutycycle enforcement technology according to an embodiment of the invention.In this example, suppose the power limit 100W of identical restriction, same evaluation interval 1ms and the minimum 3ms that holds time, cause same duty cycle 25%.In the example of hgure 5, note, power consumption increases along with larger skew (such as, reaches the P of 160W maxthe offset levels of permitted maximum).So, the repeatedly reduction (and the operating frequency of correspondence reduces) of the occurrence frequency limit, reduces back to allow processor the power limit limited by its power consumption rank.So, hold time and extend pro rata.Because the duration here higher than the power excursion of the power limit limited is longer, therefore, figure 5 illustrates long the holding time of the enforcement of the dutycycle remaining identical.Although utilize these particular example to illustrate in the diagram of Figure 4 and 5, be appreciated that the various other technologies that can exist and implement to be greater than the dutycycle of the power consumption of the power limit of restriction.Given possible worst case power excursion (Pmax), can calculate the quantity of power reduction to the frequency step of the power limit limited, provide worst case shift duration: T max_excursion=max_num_steps x Tp.
In one embodiment, hot continuable power level can maintain the time period of roughly 5-10 second, and electric continuable power level can maintain instantaneous time section, such as, and several microsecond.In one embodiment, this hot continuable power level can be in or substantially approximately be in the first power level (such as, PL1 rank), and electric continuable power level can be in or be substantially approximately in the second power level (such as, PL2 rank).
Embodiment can realize in the processor for multiple market, comprises processor-server, desktop computer processor, mobile processor etc.Referring now to Fig. 6, illustrated therein is the block diagram of processor according to an embodiment of the invention.As shown in Figure 6, processor 400 can be multi-core processor, comprises multiple core 410 a-410 n.In one embodiment, what each was such endorses is independent power territory, and can be configured to based on working load, enters and exit active state and/or maximum performance state.Respectively endorse the non-core 420 being coupled to System Agent via interconnection 415 or comprising multiple assembly.As will be seen, non-core 420 can comprise shared cache memory 430, and it can be most last level cache.In addition, non-endorsing comprises integrated Memory Controller 440, various interface 450 and power control unit 455.
In embodiments, according to one embodiment of present invention, power control unit 455 can comprise power excursion steering logic 459.As described above, this logic can receive about processor operating adopted power level and processor be allowed to perform residing for the information of frequency limitation.Based on this information, when power consumption exceeds the power level of the selection in one or more such rank, logic 459 can cause the reduction of power consumption in a specific way, implements this and reduce within given duration and/or dutycycle.So, processor 400 can be configured to when close to its design load, uses rated peak power supply to operate, with minimum boundary belt, without the need to being concerned about electric fault.
With further reference to Fig. 6, processor 400 can (such as via memory bus) communicate with system storage 460.In addition, by interface 450, the outer assembly of various chips can be connected to, such as, peripherals, mass storage, etc.Although illustrate to have this specific implementation in the embodiment in fig 6, scope of the present invention is not limited thereto aspect.
Referring now to Fig. 7, illustrated therein is the block diagram of multi-domain processing device according to another embodiment of the present invention.As shown in the embodiment of fig.7, processor 500 comprises multiple territory.Specifically, core field 510 can comprise multiple core 510 0– 510 n, figure territory 520 can comprise one or more graphics engine, and can there is System Agent territory 550.In certain embodiments, System Agent territory 550 can perform with the independent frequency being different from core field, and can keep if having time powering up to tackle power controlling events and power management, can be controlled to dynamically enter and exit high power and low power state to make these territories 510 and 520.Under each territory 510,520 can be operated in different voltage and/or power.Note, although illustrate only three territories, but be appreciated that scope of the present invention is not limited to this aspect and can there is additional territory in other embodiment.Such as, multinuclear territory can be there is, its each comprise at least one core.
In general, except each performance element and additional treatment element, each core 510 can comprise lower level of cache further.And then, respectively endorse coupled to each other and be coupled to by last level cache (LLC) 540 0– 540 nthe shared cache memory that formed of multiple unit.In embodiments, LLC 540 can share among core and graphics engine and media treatment circuit.Can find out, therefore each core be coupled by ring interconnect 530, and provide each core, interconnection between figure territory 520 and System Agent Circuits System 550.In one embodiment, interconnection 530 can be a part for core field.But in other embodiments, ring interconnection can be itself territory.
As further seen, System Agent territory 550 can comprise display controller 552, and it can provide control and interface to the display be associated.Can find out further, according to one embodiment of present invention, System Agent territory 550 can comprise power control unit 555, and this power control unit 555 can comprise power excursion steering logic 559, dynamically the skew of the power consumption of processor is restricted to maximum length in time and/or dutycycle.In embodiments, this logic can perform the algorithm described in prior figures 2.
Seen by Fig. 7 further, processor 500 can comprise integrated Memory Controller (IMC) 570 further, and it can provide interface to the system storage of such as dynamic RAM (DRAM) and so on.Multiple interface 580 can be there is 0– 580 nto realize the interconnection between processor and other Circuits System.Such as, in one embodiment, at least one direct media interface (DMI) interface and one or more high-speed peripheral assembly interconnect (PCI Express can be provided tM(PCIe tM)) interface.Further, for providing communication between other agencies of such as extra processor or other circuit and so on, the one or more interfaces meeting Intel fast path interconnection (QPI) agreement can also be provided.Although represent with so high-level in the embodiment of Fig. 7, but be appreciated that scope of the present invention is not limited thereto aspect.
Embodiment can realize in many different system types.Referring now to Fig. 8, illustrated therein is the block diagram of system according to an embodiment of the invention.As shown in Figure 8, multicomputer system 600 is point-to-point interconnection systems, and comprises first processor 670 and second processor 680 of the coupling by point-to-point interconnection 650.As shown in Figure 8, each in processor 670 and 680 can be polycaryon processor, comprise the first and second processor cores (that is, processor core 674a and 674b and processor core 684a and 684b), although potentially more multinuclear may reside in processor.The PCU of each the comprised execution power consumption restriction in processor or other logics, and the operating frequency of correspondence and/or EDP control, and are maintained, as described herein with the constraint of guaranteed output induction system.
Still with reference to figure 8, first processor 670 also comprises memory controller hub (MCH) 672 and point-to-point (P-P) interface 676 and 678.Similarly, the second processor 680 comprises MCH 682 and P-P interface 686 and 688.As shown in Figure 8, processor is coupled to corresponding storer by MCH 672 and 682, that is, storer 632 and storer 634, and they can be the parts that this locality is connected to the system storage (such as, DRAM) of corresponding processor.First processor 670 and the second processor 680 can be coupled to chipset 690 via P-P interconnection 662 and 664 respectively.As shown in Figure 8, chipset 690 comprises P-P interface 694 and 698.
In addition, chipset 690 comprises the interface 692 for chipset 690 and high performance graphics engine 638 being carried out being coupled by P-P interconnection 639.Chipset 690 can be coupled to the first bus 616 by interface 696 again.As shown in Figure 8, various I/O (I/O) equipment 614 and bridge 618 can be coupled to the first bus 616, and the first bus 616 is coupled to the second bus 620 by bridge 618.In one embodiment, various equipment can be coupled to the second bus 620, comprises such as keyboard/mouse 622, communication facilities 626 and data storage cell 628, as comprised disk drive or other mass-memory units of code 630.In addition, audio frequency I/O 624 can be coupled to the second bus 620.Each embodiment can be integrated in the system of other types, comprises the mobile device of such as smart cellular phone, flat computer, net book, Ultrabook etc. and so on.
So, each embodiment provides the pressure mechanism to power supply constraint, to guarantee that power supply assembly (such as, voltage regulator, power supply, battery etc.) can not be breakdown.So, dutycycle can be maintained and force mechanism, being no more than in this duty cycle time length, to allow the skew higher than the power limit limited.Make the logic of purpose processor, implement these constraints, so that the guarantee that the worst case that there is such assembly to upstream Power conveying assembly is not exceeded.
The embodiment of the application of the invention, can ensure that processor implements dutycycle in all skews higher than given power limit.So, processor can use safely together with rated peak power supply, and this can support high electric load, supposes that they do not exceed the dutycycle of specifying.Correspondingly, compared with maintaining the power supply of the power of maximum possible in long-time, platform cost can be reduced with design.Each embodiment also reduce deficient designing power supply risk and under the extreme situation of rareness the risk of electrical overloads.Each embodiment can also prevent the malicious attack (power virus) attempting to cause harm to the system by triggering very high transient power consumption (execution by synthetic workload).If malice high-power operation load runs comprising in the system with the processor of Duty ratio control described herein, then implement the guarantee accurately to duration and dutycycle, to prevent the operation of the expansion of high power consumption rank.
Each embodiment can use in many dissimilar systems.Such as, in one embodiment, communication facilities may be arranged to and performs each Method and Technology described herein.Certainly, scope of the present invention is not limited to communication facilities, but other embodiments can for the device of the other types for the treatment of instruction or the one or more machine readable medias comprising instruction, it is one or more that described instruction causes this equipment to perform in Method and Technology described herein in response to being performed on the computing device.
Embodiment can the form of code realize, and stored thereonly can store and can be used for System Programming to perform on the non-provisional storage medium of these instructions.Storage medium can include but not limited to: comprise floppy disk, CD, solid-state drive (SSD), compact disk ROM (read-only memory) (CD-ROM), can the disk of any type of rewriteable compact disc (CD-RW) and magneto-optic disk; The semiconductor devices of the random access memory (RAM), Erarable Programmable Read only Memory (EPROM), flash memory, EEPROM (Electrically Erasable Programmable Read Only Memo) (EEPROM) and so on of such as ROM (read-only memory) (ROM), such as dynamic RAM (DRAM), static RAM (SRAM) and so on; Magnetic or optical card, or the medium of any other type being suitable for store electrons instruction.
Although describe the present invention for limited embodiment, it will be understood to those of skill in the art that the numerous modifications and variations therefrom drawn.Claims are intended to cover all such modifications and change of falling into true spirit of the present invention and scope.

Claims (26)

1. a processor, comprising:
Multiple core, each core performs instruction independently; And
Be coupled to the power control unit (PCU) of described multiple core, for controlling the power consumption of described processor, described PCU comprises power excursion steering logic, for limiting the power consumption rank of described processor in order to avoid higher than the power limit limited in the more than one duty cycle portion in operating cycle.
2. processor as claimed in claim 1, it is characterized in that, described power excursion steering logic is further used in more than one shift duration, limit described power consumption rank in order to avoid higher than the power limit of described restriction, the value of described shift duration is stored in the first config memory of described processor.
3. processor as claimed in claim 2, it is characterized in that, the power limit of described restriction is stored in the second config memory of described processor, and the power limit of described restriction can be arranged by the original equipment manufacturer (OEM) (OEM) of the system comprising described processor.
4. processor as claimed in claim 3, comprise the 3rd config memory for storing the peak excursion duration further, the described peak excursion duration corresponds to described processor can with the maximum length in time of peak power offset operation, wherein said power excursion steering logic by described for restriction power consumption rank in order to avoid be in described peak power and offset and be longer than the described peak excursion duration.
5. processor as claimed in claim 1, it is characterized in that, power detector from described processor is obtained described power consumption rank by described power excursion steering logic, and when described power consumption rank is greater than the power level of described restriction, reduce the frequency limitation that described processor will operate with it.
6. processor as claimed in claim 5, it is characterized in that, when described power consumption rank is greater than the power limit of described restriction and is less than the second power limit, described frequency limitation reduction reaches a step value, when described power consumption level is in described second power limit, described frequency limitation reduction reaches the first value being greater than described step value, and described second power limit is greater than the power limit of described restriction.
7. processor as claimed in claim 5, it is characterized in that, when described power consumption rank is greater than the power limit of described restriction, described power excursion steering logic will upgrade described frequency limitation further by holding time of being maintained.
8. processor as claimed in claim 7, it is characterized in that, when described power consumption rank is greater than the power limit of described restriction, described power excursion steering logic is held time described in increase, during each evaluation interval, holds time described in reducing.
9. processor as claimed in claim 8, it is characterized in that, after described having held time, described power excursion steering logic will improve described frequency limitation.
10. processor as claimed in claim 5, it is characterized in that, when the operating frequency of described augmented performance rank is greater than described frequency limitation, the software asks prevented augmented performance rank is performed by described PCU.
11. 1 kinds of methods, comprising:
In the power control unit (PCU) of processor, judge whether the power consumption rank of described processor is greater than the power limit of the restriction of described processor; And
If so, then dutycycle is implemented, so that the time that described power consumption rank exceeds the power limit of described restriction is no more than described dutycycle.
12. methods as claimed in claim 11, is characterized in that, comprise several times and judge that described power consumption rank is greater than the power limit of described restriction continuously, then frequency limitation is reduced to the first value if implement described dutycycle.
13. methods as claimed in claim 11, is characterized in that, implement described dutycycle and comprise frequency limitation is reduced a step value.
14. methods as claimed in claim 11, comprise further by the minimum value of holding time of adjustment one of holding time.
15. methods as claimed in claim 14, comprise further described in repeatedly reducing and holding time, until described in held time.
16. methods as claimed in claim 15, comprise the power limit after this allowing described power dissipation limits to exceed described restriction further.
17. methods as claimed in claim 14, comprise further described in repeatedly increasing and holding time, until described power dissipation limits is less than the power limit of described restriction.
18. 1 kinds of systems, comprising:
Polycaryon processor, comprising:
Multiple core, each core performs instruction independently;
Multiple graphics engine, each graphics engine performs graphic operation independently; And
Be coupled to the power control unit (PCU) of described multiple core, for controlling the power consumption of described polycaryon processor, described PCU comprises steering logic, for allowing the power consumption rank of described polycaryon processor in the part in operating cycle higher than the power limit limited, described part is corresponding to the dutyfactor value be stored in the config memory of described polycaryon processor;
Be coupled to described polycaryon processor to provide the power supply unit of the voltage be conditioned to described polycaryon processor; And
Be coupled to the dynamic RAM (DRAM) of described polycaryon processor.
19. systems as claimed in claim 18, it is characterized in that, described polycaryon processor comprises storer, for storing the frequency limitation value of the operating frequency of the maximum permission corresponding to described polycaryon processor, store and correspond to the first off-set value that described polycaryon processor is allowed to the first duration of the power limit higher than described restriction, and store and correspond to the second off-set value that described polycaryon processor is allowed to be in the second duration that the peak power higher than the power limit of described restriction offsets, described second off-set value is less than described first off-set value.
20. systems as claimed in claim 19, it is characterized in that, described PCU is being greater than the operating frequency operation of described frequency limitation value by preventing described polycaryon processor, if wherein judge that the power limit that described power consumption rank is greater than described restriction reaches threshold number continuously, then described steering logic by described frequency limitation value is reduced to the first value, will implement described dutyfactor value.
21. systems as claimed in claim 19, it is characterized in that, the power limit preventing described power consumption rank from exceeding described restriction is reached the time of being longer than described first off-set value by described PCU, and prevents described processor from reaching the time of being longer than described second off-set value at described peak power offset operation.
22. systems as claimed in claim 18, is characterized in that, described power supply unit comprise to provide to described polycaryon processor described in the battery of voltage that is conditioned.
23. communication facilitiess being configured to the method according to any one of claim 11 to 17 of performing.
24. at least one machine readable media, at least one machine readable media described comprises multiple instruction, and in response to being performed on the computing device, described instruction causes the method for described computing equipment execution according to any one of claim 11 to 17.
25. 1 kinds of equipment for the treatment of instruction, are configured to perform the method as described in claim arbitrary in claim 11 to 17.
26. 1 kinds of equipment, comprise the device for performing the method according to any one in claim 11 to 17.
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