CN104796213A - Clock synchronizing control system and method of multi-redundancy controller - Google Patents
Clock synchronizing control system and method of multi-redundancy controller Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0652—Synchronisation among time division multiple access [TDMA] nodes, e.g. time triggered protocol [TTP]
- H04J3/0655—Synchronisation among time division multiple access [TDMA] nodes, e.g. time triggered protocol [TTP] using timestamps
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
- H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
Abstract
The invention discloses a clock synchronizing control system and method of a multi-redundancy controller. A multi-redundancy system comprises at least two clock synchronizing systems which are independent from each other. Each clock synchronizing system comprises a processor, a clock synchronizing module, a clock diagnosing module and a system monitoring module, wherein the processor is connected with the clock synchronizing module; the clock synchronizing module sends synchronizing signals and clock signals and receives synchronizing signals from other clock synchronizing systems; the clock diagnosing module conducts diagnosis on the clock signals of the clock synchronizing system and the clock signals of other clock synchronizing systems, and then sends corresponding state signals to the clock synchronizing module; the system monitoring module is connected with the clock synchronizing module and the clock diagnosing module, and conducts monitoring on the clock synchronizing module and the clock diagnosing module. The clock synchronizing method comprises the step that the clock synchronizing modules accomplish logical judgment according to the synchronizing signals, the state signals and priority information, so that all the clock synchronizing systems accomplish clock synchronization.
Description
Technical field
The present invention relates to a kind of clock synchronous control system and method, particularly a kind of clock synchronous control system for multiple redundancy system and method.
Background technology
Because the uncertain factor of industrial environment is more, so have very high requirement to the reliability of industrial control system and fail safe.Raising system reliability and fail safe in, fault avoidance and fault-tolerant be two kinds of guardian techniques.Namely fault avoidance is avoided makeing mistakes, and namely adopts correct design and method of quality control to avoid wrong introduction system as far as possible, also namely uses high reliability device etc.But because the index of high reliability device is by technology, the impacts such as cost, and no matter adopt which kind of technology, how to control the generation that manufacturing process all can not avoid fault, so limited to system reliability Improvement.Fault-toleranr technique and fault tolerant, by increasing suitable design margin and replacing the impact that working method etc. eliminates product bug, make product when limited fault occurs its part, still can normally work.And redundancy realizes the fault-tolerant a kind of important means of product.Redundant technique mainly by increasing more function passage for assignment of mission in the product, to ensure that product still can complete assignment of mission when the channel failure of limited quantity.Conventional is dual redundancy and three-scale redundancy.And when building multiplex redundancy platform, the most important thing is two functions, one is data syn-chronization, and one is clock synchronous.
In clock synchronous theory, generally clock synchronous is divided into two classes: close coupling clock synchronous and loose couplings clock synchronous.Close coupling clock synchronous refers under same clock control, the execution clock Complete Synchronization of all CPU, and this kind of method provides desirable synchronised clock can to each redundant module, but very easily produces common mode failure; Loose couplings clock synchronous, refers to that each system adopts respective clock, and by the clock synchronous of mutual feedback regulation property performance period between system, this method effectively can suppress common mode failure, but realizes complicated.
From realization rate, clock synchronous also can be divided into two kinds: software simulating and hardware implementing.Software simulating is relatively more flexible, and applicability, compatibility are better, but owing to the communication between each system existing inborn, inevitably larger delay, synchronous effect is not good.Hardware implementing is owing to adopting directly connection communication physically, and the error in communication can almost be ignored, and synchronizing speed is fast, and synchronous effect is good, and antijamming capability is strong.
Summary of the invention
In order to overcome the defect of prior art, the object of this invention is to provide a kind of clock synchronous control system and method for multiple redundancy controller, the present invention mixes the theory of close coupling clock synchronous and loose couplings clock synchronous, achieves a kind of clock synchronizing method being applied to multiple redundancy system in the mode of software and hardware combining.
Object of the present invention is achieved through the following technical solutions:
A kind of clock synchronous control system of multiple redundancy controller, it is characterized in that: this system comprises controller and forms with the same number of clock system of controller, described clock system is all arranged in each controller, and each controller is communicated to connect mutually by synchronous signal line, clock cable; Described clock system comprises: clock synchronization module, processor, clock diagnostic module and system monitoring module, wherein:
Described clock synchronization module output signal comprises synchronizing signal, clock signal, synchronous signal line, clock cable described in its output signal end connects, input signal end connects clock diagnostic module, is connected with described processor and systems axiol-ogy module communication meanwhile;
Described clock diagnostic module output signal is status signal, and its output signal end connects described clock synchronization module, and the clock cable described in input signal end connects, is connected with described systems axiol-ogy module communication meanwhile.
Described clock synchronization module comprises: signal generating unit, signal capture unit, clock detecting unit and coprocessor, wherein:
Described signal generating unit, export synchronizing signal and the clock signal of local controller, output signal is connected respectively to described synchronous signal line, time signal line;
Described signal capture unit, its connect described in synchronous signal line, catch each controller synchronizing signal comprising local controller, connect described clock diagnostic module, obtain each controller state information comprising local controller that this clock diagnostic module exports;
Synchronous signal line described in described clock detecting unit connects, obtains each controller synchronizing signal comprising local controller;
Described coprocessor and described signal generating unit, signal capture unit, clock detecting unit communicate to connect.
Described clock diagnostic module comprises: clock diagnosis unit and status signal generating unit, wherein:
Described clock diagnosis unit, the clock cable described in its input signal end connects obtains each controller clock signal comprising local controller, and output is connected with status signal generating unit;
Described status signal generating unit, export each controller state signal comprising local controller, the signal capture unit of the clock synchronization module described in its output signal end connects, described status signal marks each controller clock for " normally " or "abnormal".
Described system monitoring module comprises: export back inspection unit and Function detection unit, wherein:
Inspection unit is returned in described output, clock diagnostic module described in its input signal end connects and described clock synchronization module, the status signal that acquisition clock diagnostic module sends and the status signal that clock synchronization module receives, output connects described clock synchronization module, and exporting back inspection result is " unanimously " or " inconsistent ";
Described Function detection unit is the automatic detection unit for described clock diagnostic module, the clock diagnostic module described in its control connection, and control signal is that clock diagnostic module runs " normally " or "abnormal".
The step of the clock synchronization control method of the clock synchronous control system of multiple redundancy controller is as follows:
1), after multiple redundancy control system starts, processor is sequentially written in the priority level of local controller according to each controller priority logic of native system to coprocessor;
2) clock synchronization module export synchronizing signal to comprise local controller each controller clock system in clock synchronization module; Clock signal is to the clock diagnostic module in the clock system comprised in each controller of local controller;
3) clock diagnostic module is diagnosed the clock signal from the clock system comprised in each controller of local controller received, diagnosis exports the status signal of each controller clock synchro system, and status signal is exported to the clock synchronization module of this clock system, described state information marks each controller clock for " normally " or "abnormal";
4) system monitoring module is when clock diagnostic module works, and runs monitor clock diagnostic module, if clock diagnostic module dysfunction, system monitoring module is forced clock diagnostic module to export all status signals and is set to exception, and enters lower step; If clock diagnostic module function is normal, system brings the state information that step 3 is diagnosed into next step automatically;
5) consistency of status signal that the status signal that sends diagnostic module of systems axiol-ogy module and clock synchronization module receive compares, if inconsistent, system monitoring module is forced clock synchronization module to be received the status signal of makeing mistakes and is set to exception, enters next step; If consistent, system brings the status signal that clock synchronization module receives into next step automatically;
6) signal capture unit included by clock synchronization module catch from the clock system comprised in each controller of local controller synchronizing signal and carry out the status signal of self-clock diagnostic module, be transferred to the coprocessor of clock synchronization module; Coprocessor, according to synchronizing signal triggered interrupts signal, makes processor execution cycle task;
7) clock detecting unit included by clock synchronization module catches the cycle from the synchronizing signal of the clock system comprised in each controller of local controller, is transferred to the coprocessor of clock synchronization module;
8) coprocessor analysis receives the cycle of synchronizing signal, be abnormal when certain clock system cycle of diagnosis, and to receive its status signal be normal, and the status signal of this clock system is set to exception by coprocessor pressure;
9) coprocessor carries out a reference source selection according to the state information of each clock system after step 8 process, a reference source selection mode is reference signal according to the synchronizing signal of each controller priority logic selective sequential limit priority clock system, and by the state information upload process device of each clock system;
10) cycle of the synchronizing signal that coprocessor contrast is local and the synchronizing signal of a reference source, if circular error be greater than maximum can permissible error, adjustment local signal generating unit parameter, makes the cycle of local synchronization signal consistent with the cycle of a reference source synchronizing signal, returns step 2; As circular error be less than maximum can permissible error, system carries out next step;
11) whether the synchronizing signal that coprocessor is more local is consistent with the phase place of the synchronizing signal of a reference source, if the phase error of local synchronization signal and reference amble signal be greater than maximum can permissible error, system call interception local signal generating unit parameter enters horizontal phasing control, make the consistent with the phase place of a reference source synchronizing signal of local synchronization signal, system returns step 2; If phase place is consistent, system directly returns step 2.
Described native system each controller priority logic order refers to that native system is to the sequential encoding of each controller distributing uniform, and each controller is when selection reference source reference, and automatic prioritizing selection is arranged in front and the status signal of its clock system is normal controller.
Described phase place adjustment refers to: in synchronize local clocks system when entering phase place adjustment, and the synchronous signal cycle of fine setting synchronize local clocks system, after local synchronization signal is consistent with the phase place of reference amble signal, recovers the local synchronization signal period.
Described status signal is represented by high and low level, and it is normal that permanent High level looks status signal, and low level looks status signal for abnormal.
Described multiple redundancy system just enters synchronous regime after completing selection of reference frame, follow-up cycle and phase place adjustment be for benchmark switch because of exception time, interference and service are not caused to multiple redundancy system.
The present invention controls for the clock synchronous of multiple redundancy controller, multiple redundancy controller comprises two and above controller, clock synchronous control system is made up of the same number of clock system with controller, clock system is all arranged in each controller, and each controller is communicated to connect mutually by synchronous signal line, clock cable.
Processor, after the state receiving each clock system, can perform according to the quantity that is normal and abnormality of clock system: normally export, fault is declared or failure to the safe side, can guarantee availability and the fail safe of system.
Advantage of the present invention is: the Clock Synchronization Procedure of control system of the present invention has been come by coprocessor substantially, significantly reduces processor burden, makes processor more Effec-tive Function.And mixed the theory of close coupling clock synchronous and loose couplings clock synchronous due to technology itself, it is not only each synchronization module and provides desirable synchronised clock, under making all CPU be operated in same timeticks, and effectively inhibit the generation of common mode failure.From implementation, the mode of software and hardware combining of the present invention, make its synchronizing speed not only with hardware mode fast, the advantage that precision is high, also has the flexibility of software mode, the advantages such as applicability and compatibility.
Accompanying drawing explanation
Fig. 1 is the structural representation of triplex level redundancy system in the multiple redundancy system that the present invention relates to.
Fig. 2 is a kind of structural representation of the clock system that the present invention relates to.
Fig. 3 is the another kind of structural representation of the clock system that the present invention relates to.
Fig. 4 is that the clock system that the present invention relates to uses a kind of structural representation of triplex level redundancy system.
Fig. 5 is a kind of waveform schematic diagram of synchronizing signal phase place of the present invention adjustment.
Fig. 6 is workflow diagram of the present invention.
Embodiment
In order to be illustrated more clearly in the embodiment of the present invention, be briefly described embodiment below in conjunction with accompanying drawing, accompanying drawing for setting forth general principle, thus only sets forth the aspect for understanding needed for general principle.Accompanying drawing is not drawn to scale.
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
Control system provided by the invention and clock synchronizing method are applied in multiple redundancy system, this multiple redundancy system refers to and comprises two or more separate controllers, and each controller comprises a clock system, the present embodiment is introduced for triplex level redundancy system.
Refer to Fig. 1, it illustrates the overall structure schematic diagram of the present invention in triplex level redundancy system, wherein each controller (i.e. controller 1, controller 2, controller 3) comprises an independently clock system, and the composition of each clock system, refers to Fig. 2.Have the alternating transmission of synchronizing signal and clock signal in Clock Synchronization Procedure between controller, complete the clock synchronous between controller with this.The data syn-chronization of multiple redundancy system be by each controller between data syn-chronization bus come, the present invention only relates to clock synchronous control system and the method for multiple redundancy controller, so just seldom set forth.
Refer to Fig. 2, it illustrates the structural representation of clock system of the present invention, comprising: clock synchronization module 101, clock diagnostic module 102, system monitoring module 103 and processor 104.
Clock synchronization module 101, for receiving the synchronizing signal of all clock systems, and with the synchronizing signal of limit priority clock system for benchmark carries out clock adjustment, and then sends local synchronization signal.Write when priority level is started by processor at first, in running, select the clock system of limit priority to be benchmark always, when the clock system of limit priority occurs abnormal, select the clock system of next priority to be benchmark.The condition adjudgement of clock system, the status signal sent according to clock diagnostic module carries out.To be clock synchronization module send to synchronize local clocks system with natural frequency to clock signal and the clock diagnostic module of other clock systems, guarantees that clock synchronization module is working properly with this.
In the present embodiment, the structural representation of clock synchronization module refers to Fig. 3, and it comprises: signal generating unit 201, signal capture unit 202, clock detecting unit 203 and coprocessor 204.
Signal generating unit 201, for generation of synchronizing signal and clock signal.Clock signal is exported with fixed clock frequency by signal generating unit, and the determination of frequency is relevant with control cycle.The original frequency of synchronizing signal is also determined by control cycle, but after a reference source in redundant system is determined, the synchronizing signal of each clock system can be carried out synchronous with the synchronizing signal of a reference source.
Signal capture unit 202, for the trailing edge of trap state signal and the synchronizing signal from all clock systems, and is uploaded to coprocessor by related data.In the present embodiment, what signal capture unit caught is controller 1, controller 2 and the status signal of controller 3 and the trailing edge of synchronizing signal.Signal capture unit ceaselessly counts in the mode of counting clock, when finding the trailing edge of synchronizing signal, current count value can be preserved.And for status signal, its permanent High level is considered as normally, low level is considered as exception, and can be uploaded to processor by coprocessor.
Clock detecting unit 203, the cycle for the synchronizing signal exported each clock system is detected, and relevant information is preserved.In the present embodiment, what clock detecting unit detected is controller 1, controller 2 and controller 3 synchronizing signal.Its operation principle and signal capture unit 202 similar, with the cycle count between two trailing edges of the mode recording synchronism signal of counting clock, and preserve count value.
Coprocessor 204, the information recorded for the signal generating unit 201 to clock synchronization module, signal capture unit 202 and clock detecting unit 203 carries out Logic judgment, complete preferred logic and synchronous logic, and upload state information and the activation period tasks interrupt of each clock system to processor.
Wherein, it is normal that preferred logic refers to that all clock systems all follow controller 1() 2(is normal for > controller) 3(is normal for > controller), also namely when the clock system of controller 1 is normal, reference signal source will be controller 1 always.When the clock system of controller 1 is abnormal, controller 2 becomes reference signal source, and when the clock system of controller 1 and controller 2 is all abnormal, controller 3 becomes reference signal source.But, when the clock system of all controllers is all abnormal, no longer preferred logic will be carried out.When controller by abnormal restoring to after normal, after waiting guard time, priority also will be recovered.
Before execution preferred logic, coprocessor 204 also can detect the cycle of the status signal captured and synchronizing signal.The detection of status signal refers to and judges whether it is become normally from abnormal, mourn in silence if the clock system that this status signal represents will be set to by coprocessor 204, to guarantee the thrashing that system can not produce the recovery because of the clock system of high priority and causes.Be set to the clock system of mourning in silence, be force to make its state be set to exception, after maximum lock in time (maximum duration needed for system synchronization), revert to normal state.The detection in the cycle of synchronizing signal refers to that whether the cycle judging synchronizing signal is abnormal, if the status signal being diagnosed as exception and receiving is normal, coprocessor also can force the status signal of this clock system to be set to exception.
Meanwhile, after coprocessor 204 completes preferred logic, synchronous logic starts to perform.First coprocessor 204 can according to the cycle count of the synchronizing signal of each clock system of clock detecting unit preservation, when error is greater than tolerance value between the two, the synchronizing signal of the signal generating unit of adjustment synchronize local clocks system produces parameter, makes local synchronization signal consistent with the cycle of the synchronizing signal of a reference source.When error is less than tolerance value, enter phase place adjustment modes between the two.
Further, after entering phase place adjustment modes, the trailing edge counting of the synchronizing signal of each clock system that coprocessor 204 can be preserved according to signal capture unit 202, the synchronizing signal of contrast local synchronization signal and a reference source, carry out the synchronous of the synchronizing signal of local synchronization signal and a reference source, refer to Fig. 5, which depict a kind of waveform schematic diagram of the phase place adjustment of synchronizing signal.According to Fig. 5, phase place adjusts in two kinds of situation: (1) is all 10 when the cycle of local synchronization signal and reference amble signal, and local synchronization signal is when lagging behind reference amble signal, the amendment local synchronization signal period is that 9(amendment amplitude is less than synchronous signal cycle error tolerance value), several all after dates, when the trailing edge alignment of local synchronization signal and reference amble signal, the cycle of recovering local synchronization signal is 10, and now local synchronization signal and reference amble signal complete synchronous.(2) be all 10 when the cycle of local synchronization signal and reference amble signal, and local synchronization signal is when being ahead of reference amble signal, the amendment local synchronization signal period is that 11(amendment amplitude is less than synchronous signal cycle error tolerance value), several all after dates, when the trailing edge alignment of local synchronization signal and reference amble signal, the cycle of recovering local synchronization signal is 10, and now local synchronization signal and reference amble signal complete synchronous.
Clock diagnostic module 102, diagnoses for the clock signal of sending each clock system, and according to diagnostic result (normal or abnormal), informs the state of each clock system of clock synchronization module by sending status signal.
In the present embodiment, the structural representation of clock diagnostic module refers to Fig. 3, and it comprises: clock diagnosis unit 205 and status signal generating unit 206.
Clock diagnosis unit 205, for diagnosing the clock signal from each clock system received.Its operation principle is identical with clock detecting unit 203, but implementation and equipment are slightly different.Clock diagnosis unit carries out periodic recording to the clock signal from each clock system received in the mode of counting clock, and compares with the cycle count that this locality prestores.When error is greater than the limits of error, be considered as this clock system abnormal; When error is less than the limits of error, be considered as this clock system normal.Finally diagnostic result is passed to status signal generating unit 206.
Status signal generating unit 206, for the diagnostic result of the clock signal according to each clock system, sends the clock synchronization module 101 of status signal to this clock system of each clock system.Its output signal is permanent High level or lasting low level; Permanent High level represents that the clock system representated by status signal is normal, otherwise lasting low level represents that the clock system representated by status signal is abnormal.But when system monitoring module 103 detects that exception occurs clock diagnostic module 102, all status signals sent can be set to low level by status signal generating unit 206.
System monitoring module 103, for detecting the function of clock diagnostic module 102 and ensureing that the status signal that clock synchronization module 101 receives and the status signal that clock diagnostic module 102 sends are consistent.
In the present embodiment, the structural representation of system monitoring module 103 refers to Fig. 3, and it comprises: export back inspection unit 207 and Function detection unit 208.
Export back inspection unit 207, whether consistent for detecting the status signal that status signal that clock diagnostic module 102 sends and clock synchronization module 101 receive.When the status signal that the status signal that clock diagnostic module 102 sends and clock synchronization module 101 receive is inconsistent, exports back and examine unit 207 and can force to make this status signal be set to exception.Otherwise, when the status signal that clock diagnostic module 102 sends is consistent with the status signal that clock synchronization module 101 receives, then do not process.
Function detection unit 208, for detecting the operating state of clock diagnostic module 102.When clock diagnostic module 102 function occurs abnormal upon this detection, Function detection unit 208 can be forced to make all status signals be set to exception.
Processor 104, for obtaining the interrupt signal of clock synchronization module 101 transmission with execution cycle task, and understands the state of each clock system that receive clock synchronization module 101 is uploaded.When all clock systems are all normal, the normal execution cycle task of processor; When there being 1 clock system abnormal, the normal execution cycle task of processor, and alerts triggered faulty indication; When there being 2 clock systems abnormal, the normal execution cycle task of processor, and trigger risk of disturbance instruction; When all clock systems are abnormal, processor is execution cycle task no longer, and system enters safe mode.
Refer to Fig. 6, it illustrates workflow schematic diagram of the present invention, the concrete steps of the clock synchronizing method that also namely the present invention relates to, are further described below:
Step 601, each controller electrifying startup, completes initialization, and clock system is started working, and processor 104 pairs of clock synchronization modules 101 write local first level grade, enter step 602.
Step 602, clock synchronization module 101 sends synchronizing signal and clock signal, enters step 603.
Step 603, by the Function detection object information that system monitoring module 103 sends, clock diagnostic module 102 judges that whether itself is normal, if clock diagnostic module 102 is normal; If clock diagnostic module 102 is abnormal, enter step 605.
Step 604, whether clock diagnostic module 102 detects the clock signal from each clock system received normal.If clock signal is normal, enter step 606; If clock signal is abnormal, enter step 607
Step 605, it is abnormal that clock diagnostic module 102 exports all status signals, and system monitoring module 102 also can force to make all status signals be set to exception, and to prevent, clock diagnostic module 102 is abnormal causes output to make mistakes, and enters step 608.
Step 606, clock diagnostic module 102 output state is normal status signal, enters step 608.
Step 607, clock diagnostic module 102 output state is abnormal status signal, enters step 608.
Step 608, status signal that inspection unit sends clock diagnostic module 102 is returned in the output of system monitoring module 103 and the status signal that clock synchronization module 101 receives carries out consistency detection.If the status signal that clock diagnostic module 102 sends and the status signal that clock synchronization module 101 receives inconsistent, enter step 609; If the status signal that clock diagnostic module 102 sends and clock synchronous mould 101 pieces of status signals received are consistent, enter step 610.
Step 609, system monitoring module 103 status signal that pressure made to make mistakes is set to exception, enters step 610.
Step 610, detects whether capture status signal, and information is preserved, and enters step 611.
Step 611, whether detected state signal there occurs from extremely becoming normal saltus step.If status signal is become normally from abnormal really, enter step 612; If status signal is not become normally from abnormal, enter step 613.
Step 612, makes this enter silent mode from the clock system extremely become representated by normal status signal, enters step 613.
Step 613, detects the trailing edge whether capturing synchronizing signal and the cycle detecting synchronizing signal, and information is preserved; Coprocessor interrupts with the trailing edge Trigger processor periodic duty of synchronizing signal; Enter step 614.
Step 614, whether the testing result detecting the cycle of synchronizing signal is stated consistent with status signal.If the result of the cycle detection of synchronizing signal and the statement of status signal inconsistent, enter step 615; If the result of the cycle detection of synchronizing signal is consistent with the statement of status signal, enter step 616.
Step 615, pressure makes the status signal of the clock system of synchronous signal cycle exception be set to exception by coprocessor 204, enters step 616.
Step 616, coprocessor 204 starts to perform preferred logic, to complete the selection of a reference source, enters step 617.
Step 617, coprocessor 204 starts to perform synchronous logic, judges that whether the cycle of local synchronization signal is consistent with the cycle of the synchronizing signal of a reference source.If the error in the cycle of the cycle of local synchronization signal and the synchronizing signal of a reference source is greater than tolerance value, enter step 618; If the error in the cycle of the cycle of local synchronization signal and the synchronizing signal of a reference source is less than tolerance value, enter step 619.
Step 618, amendment local synchronization signal parameter, makes its cycle consistent with the cycle of the synchronizing signal of a reference source, enters step 602.
Step 619, judges that whether the phase place of local synchronization signal is consistent with the phase place of the synchronizing signal of a reference source.If the error of the phase place of the phase place of local synchronization signal and the synchronizing signal of a reference source is less than tolerance value, enter step 602; If the error of the phase place of the phase place of local synchronization signal and the synchronizing signal of a reference source is greater than tolerance value, enter step 620.
Step 620, enters phase place adjustment modes, enters step 602.
Refer to Fig. 4, it illustrates clock system of the present invention and use a kind of structural representation of triplex level redundancy system, and indicated the signal interaction scenario between each clock system, much more no longer to set forth at this.
In sum, the embodiment of the invention discloses a kind of clock synchronizing method being applied to multiple redundancy system, it is in conjunction with the theory of close coupling and loose couplings clock synchronous, with the execution mode of software and hardware combining, achieve that to have synchronizing speed fast, precision is high, and flexibility is high and can provide the clock synchronizing method of each redundant module ideal synchronisation clock.
Last it is noted that above embodiment is only in order to illustrate technical scheme of the present invention, be not intended to limit; Although with reference to previous embodiment to invention has been detailed description, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein portion of techniques feature; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the spirit and scope of various embodiments of the present invention technical scheme.
Claims (6)
1. the clock synchronous control system of a multiple redundancy controller, it is characterized in that: this system comprises controller and forms with the same number of clock system of controller, described clock system is all arranged in each controller, and each controller is communicated to connect mutually by synchronous signal line, clock cable; Described clock system comprises: clock synchronization module, processor, clock diagnostic module and system monitoring module, wherein:
Described clock synchronization module output signal comprises synchronizing signal, clock signal, and its output signal end connects synchronous signal line, clock cable, and input signal end connects clock diagnostic module, is connected with described processor and systems axiol-ogy module communication meanwhile;
Described clock diagnostic module output signal is status signal, and its output signal end connects clock synchronization module, and input signal end connects clock cable, is connected with described systems axiol-ogy module communication meanwhile.
2. the clock synchronous control system of multiple redundancy controller according to claim 1, is characterized in that: described clock synchronization module comprises: signal generating unit, signal capture unit, clock detecting unit and coprocessor, wherein:
Described signal generating unit, export synchronizing signal and the clock signal of local controller, output signal is connected respectively to described synchronous signal line, time signal line;
Described signal capture unit, its connect described in synchronous signal line, catch each controller synchronizing signal comprising local controller, connect described clock diagnostic module, obtain each controller state information comprising local controller that this clock diagnostic module exports;
Synchronous signal line described in described clock detecting unit connects, obtains each controller synchronizing signal comprising local controller;
Described coprocessor and described signal generating unit, signal capture unit, clock detecting unit communicate to connect;
Described clock diagnostic module comprises: clock diagnosis unit and status signal generating unit, wherein:
Described clock diagnosis unit, the clock cable described in its input signal end connects obtains each controller clock signal comprising local controller, and output is connected with status signal generating unit;
Described status signal generating unit, export each controller state signal comprising local controller, the signal capture unit of the clock synchronization module described in its output signal end connects, described status signal marks each controller clock for " normally " or "abnormal";
Described system monitoring module comprises: export back inspection unit and Function detection unit, wherein:
Inspection unit is returned in described output, clock diagnostic module described in its input signal end connects and described clock synchronization module, the status signal that acquisition clock diagnostic module sends and the status signal that clock synchronization module receives, output connects described clock synchronization module, and exporting back inspection result is " unanimously " or " inconsistent ";
Described Function detection unit is the automatic detection unit for described clock diagnostic module, the clock diagnostic module described in its control connection, and control signal is that clock diagnostic module runs " normally " or "abnormal".
3. a clock synchronization control method for the clock synchronous control system of multiple redundancy controller according to claim 1, is characterized in that: the step of this clock synchronization control method is as follows:
1), after multiple redundancy control system starts, processor is sequentially written in the priority level of local controller according to each controller priority logic to coprocessor;
2) clock synchronization module export synchronizing signal to comprise local controller each controller clock system in clock synchronization module; Clock signal is to the clock diagnostic module in the clock system comprised in each controller of local controller;
3) clock diagnostic module is diagnosed the clock signal from the clock system comprised in each controller of local controller received, diagnosis exports the status signal of each controller clock synchro system, and status signal is exported to the clock synchronization module of this clock system, described state information marks each controller clock for " normally " or "abnormal";
4) system monitoring module is when clock diagnostic module works, and runs monitor clock diagnostic module, if clock diagnostic module dysfunction, system monitoring module is forced clock diagnostic module to export all status signals and is set to exception, and enters lower step; If clock diagnostic module function is normal, system brings the state information that step 3 is diagnosed into next step automatically;
5) consistency of status signal that the status signal that sends diagnostic module of systems axiol-ogy module and clock synchronization module receive compares, if inconsistent, system monitoring module is forced clock synchronization module to be received the status signal of makeing mistakes and is set to exception, enters next step; If consistent, system brings the status signal that clock synchronization module receives into next step automatically;
6) signal capture unit included by clock synchronization module catch from the clock system comprised in each controller of local controller synchronizing signal and carry out the status signal of self-clock diagnostic module, be transferred to the coprocessor of clock synchronization module; Coprocessor, according to synchronizing signal triggered interrupts signal, makes processor execution cycle task;
7) clock detecting unit included by clock synchronization module catches the cycle from the synchronizing signal of the clock system comprised in each controller of local controller, is transferred to the coprocessor of clock synchronization module;
8) coprocessor analysis receives the cycle of synchronizing signal, be abnormal when certain clock system cycle of diagnosis, and to receive its status signal be normal, and the status signal of this clock system is set to exception by coprocessor pressure;
9) coprocessor carries out a reference source selection according to the state information of each clock system after step 8) process, a reference source selection mode is reference signal according to the synchronizing signal of each controller priority logic selective sequential limit priority clock system, and by the state information upload process device of each clock system;
10) cycle of the synchronizing signal that coprocessor contrast is local and the synchronizing signal of a reference source, if circular error be greater than maximum can permissible error, adjustment local signal generating unit parameter, makes the cycle of local synchronization signal consistent with the cycle of a reference source synchronizing signal, returns step 2); As circular error be less than maximum can permissible error, system carries out next step;
11) whether the synchronizing signal that coprocessor is more local is consistent with the phase place of the synchronizing signal of a reference source, if the phase error of local synchronization signal and reference amble signal be greater than maximum can permissible error, system call interception local signal generating unit parameter enters horizontal phasing control, make the consistent with the phase place of a reference source synchronizing signal of local synchronization signal, system returns step 2); If phase place is consistent, system directly returns step 2.
4. the clock synchronization control method of the clock synchronous control system of multiple redundancy controller according to claim 3, it is characterized in that: described each controller priority logic order refers to that native system is to the sequential encoding of each controller distributing uniform, each controller is when selection reference source reference, and automatic prioritizing selection is arranged in front and the status signal of its clock system is normal controller.
5. the clock synchronization control method of the clock synchronous control system of multiple redundancy controller according to claim 3, it is characterized in that: phase place adjustment described in step 11) refers to: in synchronize local clocks system when entering phase place adjustment, the synchronous signal cycle of fine setting synchronize local clocks system, after local synchronization signal is consistent with the phase place of reference amble signal, recover the local synchronization signal period.
6. the clock synchronization control method of the clock synchronous control system of the multiple redundancy controller according to claim 3 or 4 or 5, it is characterized in that: described status signal is represented by high and low level, it is normal that permanent High level looks status signal, and low level looks status signal for abnormal.
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