CN104756191A - Resistive devices and methods of operation thereof - Google Patents

Resistive devices and methods of operation thereof Download PDF

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Publication number
CN104756191A
CN104756191A CN201380047372.3A CN201380047372A CN104756191A CN 104756191 A CN104756191 A CN 104756191A CN 201380047372 A CN201380047372 A CN 201380047372A CN 104756191 A CN104756191 A CN 104756191A
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China
Prior art keywords
pulse
voltage
switching device
resistive switching
coupled
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CN201380047372.3A
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Chinese (zh)
Inventor
F·S·考珊
M·A·范巴斯柯克
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Adesto Technologies Corp
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Adesto Technologies Corp
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Priority claimed from US13/610,690 external-priority patent/US8953362B2/en
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Publication of CN104756191A publication Critical patent/CN104756191A/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/24—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using capacitors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0009—RRAM elements whose operation depends upon chemical change
    • G11C13/0011—RRAM elements whose operation depends upon chemical change comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/003—Cell access
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0061—Timing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/0071—Write using write potential applied to access device gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/0073—Write using bi-directional cell biasing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/74—Array wherein each memory cell has more than one access device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/79—Array wherein the access device being a transistor

Abstract

A method of operating a memory cell can include applying a select pulse at a gate of a select transistor having a first node and a second node, the first node coupled to the first access terminal of the access device, wherein the second node is coupled to a bit line potential node; charging a capacitor having a first plate and a second plate, the first plate coupled to the first node of the select transistor and to the first access terminal of the access device during the select pulse; activating the access device after charging the capacitor; deactivating the select transistor after activating the access device; and discharging the charged capacitor through the resistive switching device.

Description

Resistive elements and method of operating thereof
Technical field
The present invention generally relates to electron device, particularly relates to resistive elements and method of operating thereof.
Background technology
Semi-conductor industry depends on device bi-directional scaling thus transmits the performance of improvement at lower cost.Flash memory is the main flow nonvolatile memory in current market.But flash memory has and has to the sustainable development of memory technology the multiple limitation significantly threatened.Therefore, alternative storer is being explored in the industry to replace flash memory.The rival of future memory technology comprises magnetic storage random access memory (MRAM), ferroelectric
RAM (FeRAM) and resistive switch storage, this resistive switch storage is phase transformation RAM (PCRAM), resistive RAM (RRAM), ion storage device such as, and this ion storage device comprises programmable metallization unit (PMC) or conducting bridge random access memory (CBRAM).These storeies are also referred to as emerging memory.
In order to feasible, emerging memory must be better than flash memory more than one in the Software Metrics of such as scalability, performance, efficiency, ON/OFF quantitative (ration), operating temperature, CMOS compatibility and reliability and so on.The a lot of items of CBRAM technology in these Software Metrics show promising result.
Summary of the invention
According to embodiments of the invention, the method operating resistive switching device (switching device) is included in first of the access device (access device) with the first access terminal and the second access terminal and accesses signal terminal applying to comprise pulse.Second access terminal is coupled to the first terminal of the resistive switching device of two-terminal.Resistive switching device has the first terminal and the second terminal.Resistive switching device has the first state and the second state.Pulse be included in the second slope from the first slope of the first voltage to the second voltage, from the second voltage to tertiary voltage on the second time cycle on the cycle very first time and on the 3rd time cycle from tertiary voltage to the 3rd slope of the 4th voltage.Second slope and the 3rd slope have the slope contrary with the first slope.The cycle very first time and the second time cycle sum were less than for the 3rd time cycle.
According to alternate embodiment of the present invention, the method for operation storage unit (memory cell) is included in the grid place applying strobe pulse of the selection transistor with first node and Section Point.Storage unit comprises the resistive switching device with the first terminal and the second terminal and the access device with the first access terminal and the second access terminal.Second access terminal is coupled to the first terminal of resistive switching device.First node is coupled to the first access terminal of access device, and Section Point is coupled to bit line potential node.The method also comprises the capacitor charging to having the first plate and the second plate.During strobe pulse, the first plate is coupled to selects the first node of transistor and the first access terminal being coupled to access device.The method also comprises: to capacitor charging after activate access device, activation access device after stop using this selection transistor and by resistive switching device to the capacitor discharge charged.
According to alternate embodiment of the present invention, semiconductor devices comprises the resistive switching device of two-terminal, and this switching device has the first terminal and the second terminal and has the first state and the second state.This semiconductor devices comprises access device and is configured to produce the signal generator of the signal comprising pulse, and this access device has the first access terminal and accesses terminal with second of the first terminal being coupled to this resistive switching device.Pulse be included in the second slope from the first slope of the first voltage to the second voltage, from the second voltage to tertiary voltage on the second time cycle on the cycle very first time and on the 3rd time cycle from tertiary voltage to the 3rd slope of the 4th voltage.Second slope and the 3rd slope have the slope contrary with the first slope.The cycle very first time and the second time cycle sum were less than for the 3rd time cycle.This semiconductor devices comprises the access circuit being configured to apply signal on the first access terminal further.Resistive switching device is configured to be changed to the second state in response to this signal from the first state.
According to alternate embodiment of the present invention, the first terminal that the method operating resistive switching device is included in the resistive switching device of the two-terminal with the first terminal and the second terminal applies the signal comprising pulse.Resistive switching device has the first state and the second state.Pulse to be included on the cycle very first time from the first slope of the first voltage to the second voltage, on the second time cycle from the second slope of tertiary voltage to the first voltage and the 3rd slope from the 4th voltage to tertiary voltage.The cycle very first time is at least 0.1 times of cycle T.T. of pulse.First slope and the second slope have the oblique variability contrary with the oblique variability on the 3rd slope.
According to alternate embodiment of the present invention, the first terminal that the method operating resistive switching device is included in the resistive switching device of the two-terminal with the first terminal and the second terminal applies the signal comprising pulse.This resistive switching device has the first state and the second state.Pulse be included in the second slope from the first slope of the first voltage to the second voltage, from the second voltage to tertiary voltage on the second time cycle on the cycle very first time and on the 3rd time cycle from tertiary voltage to the 3rd slope of the 4th voltage.Second slope and the 3rd slope have the slope contrary with the first slope.The cycle very first time and the second time cycle sum were less than for the 3rd time cycle.
Accompanying drawing is sketched
The Fig. 1 comprising Figure 1A-1E illustrates sectional view and the operation of resistive switch storage, wherein Figure 1A illustrates the sectional view of conventional ion storer, wherein Figure 1B illustrates the storer under programming operation, wherein Fig. 1 D illustrates the sequential chart of corresponding programming pulse, wherein Fig. 1 C illustrates the storer under erase operation, and wherein Fig. 1 E illustrates the sequential chart of corresponding erasing pulse;
The Fig. 2 comprising Fig. 2 A-2F illustrates the outstanding sequential chart illustrating the programming pulse being applied to mnemon (memory unit) according to the embodiment of the present invention;
The Fig. 3 comprising Fig. 3 A-3F illustrates the outstanding sequential chart illustrating the erase operation of erasing pulse according to the embodiment of the present invention;
The Fig. 4 comprising Fig. 4 A-4B illustrates the storage unit according to the embodiment of the present invention;
The Fig. 5 comprising Fig. 5 A-5B illustrates the outstanding sequential chart representing the procedure operation of the program pulse of asserting in wordline and bit line place, and wherein Fig. 5 A illustrates regular programming pulses and wherein Fig. 5 B illustrates the programming pulse according to the embodiment of the present invention;
The Fig. 6 comprising Fig. 6 A-6B illustrates and outstandingly represents at wordline and corresponding bit line and/or the sequential chart of erase operation of erasing pulse selecting line place, and wherein Fig. 6 A illustrates conventional erase pulse and wherein Fig. 6 B illustrates the erasing pulse according to the embodiment of the present invention;
The Fig. 7 comprising Fig. 7 A-7B illustrates storage unit according to the embodiment of the present invention and corresponding program/erase operations;
The Fig. 8 comprising Fig. 8 A and Fig. 8 B illustrates the various memory cell arrays realizing embodiments of the invention; And
The Fig. 9 comprising Fig. 9 A-9B illustrates the memory device realized according to the embodiment of the present invention.
Corresponding numbering in different accompanying drawing and mark refer generally to corresponding parts, unless otherwise prescribed.Accompanying drawing in order to clearly illustrated embodiments related fields and draw and not necessarily draw in proportion.
Embodiment
Discuss making and using of each embodiment below in detail.But should be appreciated that and the invention provides many applicable inventive concept, they can be embodied in the specific background of wide range.The specific embodiment discussed only illustrates makes and uses ad hoc fashion of the present invention, and is not construed as limiting scope of the present invention.
By referring to each embodiment (such as, the ion storage device of such as conducting bridge storer) under specific background, present invention is described.But the present invention also can be applicable to the storer of other type, be especially applied to any resistive memories of such as two-terminal resistive memories and so on.Memory device although described herein, but embodiments of the invention also can be applicable to other types of devices of being formed by resistive switch, resistive switch such as processor, dynamically can heavy-route electron device, photoswitch, field programmable gate array and microfluidic valve and other nanoparticle device.
The Fig. 1 comprising Figure 1A-1E illustrates sectional view and the operation of resistive switch storage, wherein Figure 1A illustrates the sectional view of conventional ion storer, wherein Figure 1B illustrates the storer under programming operation, wherein Fig. 1 D illustrates the sequential chart of corresponding programming pulse, wherein Fig. 1 C illustrates the storer under erase operation, and wherein Fig. 1 E illustrates the sequential chart of corresponding erasing pulse;
Figure 1A illustrates the mnemon 10 with the variable resistance layer 30 be placed between the first conductive layer 20 and the second conductive layer 40.This variable resistance layer 30 can solid electrolyte layer, such as, by applying this solid electrolyte layer able to programme of such as current potential, heat, magnetic field and other outside stimulus.In other words, the resistance at variable resistance layer 30 two ends is changed by applying programming operation and corresponding erase operation.Such as, after a program operation, variable resistance layer 30 has low-resistance (ON state), and after the erase operation, variable resistance layer 30 has high resistant (OFF state).The operation of storage unit relates to the nanometer scale migration of conduction atom and rearranges, this conduction atom such as metallic atom passing through variable resistance layer 30 and so on.Alternatively, storage unit can due to defect motion and operate, the point defect in defect such as variable resistance layer 30.By applying electric signal to perform program/erase operations between first node 1 and Section Point 2.
As shown in Figure 1A, (disburse) nanophase 50 can be paid in variable resistance layer 30.In certain embodiments, nanophase 50 can be conduction.But the resistivity of this variable resistance layer 30 is higher in the off condition, such as, be greater than 500M Ω, and the resistivity of this variable resistance layer 30 depends on cellar area.By applying the resistance state reading voltage and reading cells between the first and second nodes 1 and 2.But, read voltage and be insignificant (generally at about-200mV with about between 200mV) and the state not changing storage unit.
Figure 1B illustrates the mnemon during conventional programming operation.Quiescent voltage or dynamic pulse can be used to complete programming operation.Typically, use programming pulse as shown in figure ip to perform programming, Fig. 1 D illustrates the potential difference (PD) applied between first node 1 and Section Point 2.
When such as shown in Figure 1B and Fig. 1 D, when first and second these two ends of node 1 and 2 apply positive voltage, the conduction atom from the second conductive layer 40 can oxidized formation conductive ion, and then this conductive ion is accelerated due to the electric field in variable resistance layer 30.Programming pulse, such as, depend on variable resistance layer 30, can have the current potential V higher than threshold voltage pROG, this current potential V pROGabout 300mV or higher typically also is about 450mV in one example.Such as, programming pulse can have the current potential V of about 1V to about 1.5V pROG.Conductive ion drifts about to first conductive layer 20 that can be negative electrode.In variable resistance layer 30, conductive ion can use nanophase 50 to move, and the conductive ion that this nanophase 50 Absorbable rod drifts about also discharges same or another conductive ion.Finally, the conductive ion near the first conductive layer absorbs the electronics from Section Point 2 and reverts back conduction atom.The conduction atom of reduction is deposited on the first conductive layer 20.During programming pulse, increasing conductive ion is brought to the first conductive layer 20 from the second conductive layer 40, and this measure finally causes forming conductive filament in variable resistance layer 30.The flowing of conductive ion also causes program current I pROGby the flowing of variable resistance layer 30.By variable resistance layer 30 by the first conductive layer 20 and the second conductive layer 40 bridge joint after, the resistivity of variable resistance layer 30 significantly decline also can use read operation to measure/read.
Fig. 1 C illustrates the mnemon during conventional erase operation.Quiescent voltage or dynamic pulse can be used to complete erase operation.Typically, use erasing pulse as referring to figure 1e to perform erasing, Fig. 1 E illustrates the potential difference (PD) be applied between first node 1 and Section Point 2.
When such as shown in Fig. 1 C and Fig. 1 E, when first and second these two ends of node 1 and 2 apply negative voltage, the conduction atom in the conductive filament before formed is oxidized to conductive ion, and this conductive ion drifts to the second conductive layer 40 due to electric field.At the second conductive layer 40 place, these conductive ions absorb the electronics from first node 1 and are reduced to conduction atom, again form initial high-impedance state.Conductive ion causes wiping electric current I to the flowing of the second conductive layer 40 eRASEflow through variable resistance layer 30.Different from the second conductive layer 40, the first conductive layer 20 is inertia and does not therefore contribute conduction atom.Therefore, once all conduction atoms in variable resistance layer 30 are reorientated, then erase process stops.In one embodiment, erasing pulse can have the current potential V being less than about-200mV (more negative) eRASE, such as about-1V.
As explained orally above, programming and erasing pulse are step functions, and wherein pulse voltage suddenly changes to high state (as V from low state (as 0V) pROG).In other words, a series of square pulse/rect.p. of conventional use performs programming and erasing.As shown in Figure 2 and Figure 4, embodiments of the invention use different potential pulses for programming and erasing mnemon.
The Fig. 2 comprising Fig. 2 A-2F illustrates the outstanding sequential chart being applied to the programming pulse of mnemon according to the embodiment of the present invention;
Fig. 2 A illustrates the sequential chart of expression according to upward change (ramp up) potential pulse applied between the first node in mnemon of the embodiment of the present invention and Section Point.
According to embodiments of the invention, be increased to crest voltage in the potential difference (PD) at first and second these two ends of node 1 and 2, this crest voltage can be identical with conventional square-wave pulse.Thus, due to applied pulse, first node 1 is in (just) current potential higher than Section Point 2.
But as shown in the figure, this voltage suddenly declines after being unlike in and arriving peak programming voltage like that in conventional programming.But, program voltage (V pROG) become to declivity lentamente from peak programming voltage PPV.As shown in Figure 2 A, in one or more embodiments, this follows index or para-curve rate of change to declivity time variant voltage.
In the illustrated embodiment of Fig. 2 A, programming pulse suddenly (or rapidly) upwardly fades to peak programming voltage PPV, fades to low voltage and then fade to maintenance voltage to declivity lentamente rapidly to declivity
In embodiments, programming pulse can have the peak programming voltage PPV of at least 500mV.In one or more embodiments, peak programming voltage PPV is at least 1V.In one or more embodiments, peak programming voltage PPV is about 750mV to about 1000mV.In one or more embodiments, peak programming voltage PPV is about 1V to about 1.5V.In one or more embodiments, peak programming voltage PPV is about 1.5V to about 2V.In one or more embodiments, peak programming voltage PPV is about 2V to about 2.5V.
In embodiments, programming pulse can have the programming pulse width t of at least 0.01 μ s pW.In one or more embodiments, programming pulse width t pWfor at least 0.02 μ s.In one or more embodiments, programming pulse width t pWfor about 0.01 μ s to about 1 μ s.In one or more embodiments, programming pulse width t pWfor about 0.04 μ s to about 0.08 μ s.In one or more embodiments, programming pulse width t pWfor about 0.06 μ s.In certain embodiments, programming pulse width t pW0.01 μ s can be greater than but be less than 100 μ s.
In embodiments, program voltage comprises initial part, higher than this initial part then current potential tiltedly fade to peak programming voltage fast.In embodiments, program voltage can be arrived in 10ns.In one or more embodiments, program voltage can be arrived in 1ns.In one or more embodiments, program voltage can be arrived in 0.5ns to about 10ns.In one or more embodiments, program voltage can be arrived in 1ns to about 5ns.
In embodiments, program voltage does not have the retention time under peak programming voltage.In other words, after arrival peak programming voltage, program voltage is dragged down at once.In embodiments, the retention time under peak programming voltage can be less than 10ns.In one or more embodiments, the retention time under peak programming voltage can be less than 1ns.In one or more embodiments, the retention time under peak programming voltage can be less than 0.1ns.In one or more embodiments, the retention time under peak programming voltage can between 0.1ns to 1ns.In one or more embodiments, the retention time under peak programming voltage can be less than total pulsewidth t pW1%.In one or more embodiments, the retention time under peak programming voltage can at total pulsewidth t pW0.1% to total pulsewidth t pW1% between.
In embodiments, program voltage comprises center section, higher than this center section then current potential reduce fast from peak programming voltage.In embodiments, program voltage is being less than total pulsewidth t pW20% time in reduce.In one or more embodiments, program voltage is being less than total pulsewidth t pW10% time in reduce.In one or more embodiments, program voltage is at total pulsewidth t pW1% to total pulsewidth t pWthe time about between 20% in reduce.In one or more embodiments, program voltage is at total pulsewidth t pW5% to total pulsewidth t pWthe time about between 10% in reduce.
In embodiments, program voltage comprises last part, higher than this last part then current potential slowly decline.In embodiments, program voltage can reduce under the speed slower than about 100mV/ μ s.Specifically, have Part I at higher voltages and Part II to declivity varied curve, this Part II is low voltage stage LVP.
In embodiments, programming pulse can be modified to any suitable curve to declivity varied curve.Specifically, depend on the programming characteristic of voltage stage mnemon, low voltage stage LVP can be corrected to increase or reduce oblique variability.In embodiments, the time cycle (t of LVP lVP) ratio be total pulsewidth t pWat least 10%.In embodiments, the time cycle (t of LVP lVP) ratio be total pulsewidth t pWat least 50%.In embodiments, the time cycle (t of LVP lVP) ratio be total pulsewidth t pWabout 10% to about between 50%.In embodiments, the time cycle (t of LVP lVP) ratio be total pulsewidth t pWabout 50% to about between 100%.Will, according to various embodiments of the present invention, Fig. 2 B-2F be used to describe the example of these corrections.
In addition, Fig. 2 A illustrates embodiments of the invention, applies the exponential to declivity varied curve of low voltage stage (LVP) period between the first and second nodes that this embodiment is included in mnemon (as Figure 1B).As shown in Figure 2 B, index is that slow index is to make program voltage at programming pulse width t in one or more embodiments pWabout half after lower than the half of peak programming voltage PPV.Only as explaining orally, program voltage (PV) during low voltage stage can follow the index of such as PV (t)=PVP* (1-exp (-t/RC)) and so on, wherein PVP is peak programming voltage, t is the time, RC is RC time constant (as resistance and electric capacity long-pending).
Fig. 2 B illustrates the programming pulse applied between the first and second nodes of mnemon according to another embodiment.According to embodiment, upward change stage (RUP) comprises linear segment, and during this linear segment, program voltage linearly increases.In one embodiment, program voltage is with PV (t)=(PVP × t/ (t pW-t 0)), increase linearly, wherein PVP is peak programming voltage, t is the time, is pulsewidth and t 0reducible 0.85 to about 0.995.In alternative embodiments, program voltage increases by multiple linear ladder.As shown in Figure 2 B, after arrival peak programming voltage, voltage is quick as described above to be become to declivity and decays lentamente on the longer time.
Fig. 2 C illustrates the programming pulse applied between the first and second nodes of mnemon according to another embodiment.In this embodiment, the program voltage of upward change can be nonlinear, such as, be index in one embodiment.In another embodiment, the program voltage of upward change can be parabolical.
Fig. 2 D illustrates the programming pulse applied between the first and second nodes of mnemon according to another embodiment.
In this embodiment, programming pulse can comprise the superposition of multiple pulse.Such as, in one embodiment, square-wave pulse can superpose (Fig. 2 D) with another shorter square-wave pulse of high voltage.In alternative embodiments, exponential pulse can superpose with square wave low voltage pulse (Fig. 2 E).
Fig. 2 F illustrates the linear programming pulse applied between the first and second nodes of mnemon according to another embodiment.Such as, at center section, program voltage declines fast, and at last part, this program voltage slowly reduces.As shown in the figure, program voltage is increased to peak programming voltage at upward change part (RUP) period fast linear.After arrival peak programming voltage, program voltage linearly reduced rapidly in high voltage part (HVP) period, and after this program voltage linearly reduced lentamente in low-voltage part (LVP) period.In other embodiment, programming pulse can comprise the superposition of multiple linear, square, index shape, parabola shaped oblique change.
In embodiments, the embodiment described in Fig. 2 A-2F may be combined.
As above in embodiments explain, programming pulse has at least four characteristics: become to the quick upward change part of peak programming voltage, minimum hold time under peak programming voltage, quick from peak programming voltage to declivity and slow in low-voltage part becomes to declivity.Advantageously, apply fast, higher energy pulse promptly forms low-resistance store status (as formed conductive filament in mnemon 10).So, the possibility generating multiple filament in a device reduces.
The Fig. 3 comprising Fig. 3 A-3F illustrates the sequential chart of the erase operation of the outstanding expression erasing pulse according to the embodiment of the present invention.
Fig. 3 A-3F illustrates the sequential chart represented according to the oblique time variant voltage erasing pulse applied between the first and second nodes of mnemon of the embodiment of the present invention.According to embodiments of the invention, be reduced to crest voltage in the potential difference (PD) at first and second these two ends of node 1 and 2.Therefore, be similar to Fig. 1 C, due to applied pulse, first node 1 is in (bearing) current potential lower than Section Point 2.
But as shown in each embodiment, erasing voltage is unlike in conventional erase like that suddenly to be increased and reduces.But, erasing voltage (V eRASE) fade to peak erase voltage PEV to declivity rapidly.As shown in Figure 3A, in one embodiment, suddenly can become to declivity in the initial part of erasing pulse to declivity time variant voltage.In the embodiment shown by Fig. 3 A, erasing pulse is at short upward change time (ER rd) in fade to intermediate erase voltage from peak erase voltage PEV is upward rapidly.Then, on the longer time, erasing voltage is upward fades to maintenance voltage.Therefore, while storage unit exposes and reaches the short period near peak erase voltage, low erasing voltage reaches the long period in the upper applying of low-voltage part (LVP).
In embodiments, erasing pulse can have the peak erase voltage PEV of at least-200mV.In one or more embodiments, peak erase voltage PEV is at least-1V.In one or more embodiments, peak erase voltage PEV is about-750mV to about-1V.In one or more embodiments, peak erase voltage PEV is about-1V to about-1.5V.In one or more embodiments, peak erase voltage PEV is about-1.5V to about-2V.In one or more embodiments, peak erase voltage PEV is about-2V to about-3V.
In embodiments, erasing pulse can have the pulsewidth of at least 0.1 μ s.In one or more embodiments, pulsewidth is at least 1 μ s.In one or more embodiments, pulsewidth is that about 1 μ s is to about 10 μ s.In one or more embodiments, pulsewidth is that about 2.5 μ s are to about 7.5 μ s.In one or more embodiments, pulsewidth is that about 5 μ s are to about 15 μ s.
In embodiments, erasing voltage comprises initial part, higher than this initial part then current potential fade to peak erase voltage to declivity fast.In embodiments, erasing voltage can be arrived in 10ns.In one or more embodiments, erasing voltage can be arrived in 1ns.In one or more embodiments, erasing voltage can be arrived in 0.5ns to about 10ns.In one or more embodiments, erasing voltage can be arrived in 1ns to about 5ns.
In embodiments, erasing voltage does not have the retention time under peak erase voltage.In other words, after arrival peak erase voltage, erasing voltage is driven high at once.In embodiments, the retention time under peak erase voltage can be less than 10ns.In one or more embodiments, the retention time under peak erase voltage can be less than 1ns.In one or more embodiments, the retention time under peak programming voltage can be less than 0.1ns.In one or more embodiments, the retention time under peak erase voltage can between 0.1ns to 1ns.In one or more embodiments, the retention time under peak erase voltage can be less than 1% of total pulsewidth.In one or more embodiments, the retention time under peak erase voltage can 0.1% of total pulsewidth to total pulsewidth 1% between.
In embodiments, erasing voltage comprises center section, higher than the then current potential quick increase from peak erase voltage of this center section.In embodiments, erasing voltage increases within the time being less than total pulsewidth 20%.In one or more embodiments, erasing voltage increases within the time being less than total pulsewidth 10%.In one or more embodiments, erasing voltage increases to the time of total pulsewidth about between 20% in 1% of total pulsewidth.In one or more embodiments, erasing voltage increases to the time of total pulsewidth about between 10% in 5% of total pulsewidth.
In embodiments, erasing voltage comprises last part, if higher than this last part, current potential slowly increases.In embodiments, the speed that erasing voltage comparable about 100mV/ μ s is slower increases.Specifically, have at higher voltages and the Part I of short time and Part II from the curve of the upward change of peak erase voltage, this Part II is the low-voltage part (LVP) of long period.
In embodiments, the upward varied curve of erasing pulse can be corrected for any suitable curve.Specifically, depend on the programming characteristic of mnemon, low voltage stage (phase) LVP can be revised.In embodiments, the time cycle (t of LVP lVP) ratio be total pulsewidth t pWat least 10%.In embodiments, the time cycle (t of LVP lVP) ratio be total pulsewidth t pWat least 50%.In embodiments, the time cycle (t of LVP lVP) ratio be total pulsewidth t pWabout 10% to about between 50%.In embodiments, the time cycle (t of LVP lVP) ratio be total pulsewidth t pWabout 50% to about between 95%.
As shown in Figure 3A, in one or more embodiments, index slowly can be followed, with the half making this erasing voltage be less than peak erase voltage PEV at the erasing voltage (EV) of Part I (low voltage stage LVP) period.Only exemplarily, can follow such as EV (t)=PEV (1-exp (t/RC)) at the erasing voltage (EV) of low voltage stage (LVP) period, index, wherein PEV is peak erase voltage (being negative), being the time, is time constant.
Will, according to various embodiments of the present invention, Fig. 3 B-3F be used to describe the example revised further.
Fig. 3 illustrates embodiments of the invention, this embodiment be included in be applied to mnemon the first and second nodes between linear in declivity varied curve.
According to an embodiment, upward change stage (RDP) comprises linear segment, and during this linear segment, program voltage reduces linearly.In one embodiment, erasing voltage is with EV (t)=(PEV × t/ (t pW-t 0)), reduce linearly, wherein PVP is peak programming voltage (being negative), is the time, is pulsewidth and can is about 0.85 to about 0.995.In alternative embodiments, program voltage reduces by multiple linear ladder.As shown in Figure 2 B, after arrival peak programming voltage, voltage quick upward change decaying lentamente on the longer time as previously mentioned.
Erasing pulse between Fig. 3 C illustrates according to first and second nodes being applied to mnemon of another embodiment.In this embodiment, becoming to declivity of erasing voltage can be nonlinear, such as in one embodiment, is index.In another embodiment, becoming to declivity of erasing voltage can be parabolical.
Erasing pulse between Fig. 3 D illustrates according to first and second nodes being applied to mnemon of another embodiment.
In this embodiment, erasing pulse can comprise the superposition of multiple pulse.Such as, in one embodiment, square-wave pulse can superpose (Fig. 3 D) with another shorter square-wave pulse more high-tension.In alternative embodiments, exponential pulse can overlapping with square wave low voltage pulse (Fig. 3 E).
Linear erasure pulse between Fig. 3 F illustrates according to first and second nodes being applied to mnemon of another embodiment.Such as, at center section, erasing voltage increases fast, and at last part, this erasing voltage slowly reduces.As shown in the figure, erasing voltage is linearly decreased to peak erase voltage rapidly during becoming part (RDP) to declivity.After arrival peak erase voltage, erasing voltage linearly increased rapidly in high voltage part (HVP) period, and after this, program voltage linearly reduced lentamente in low-voltage part (LVP) period.In other embodiment, erasing pulse can comprise the superposition of multiple linear, square, index shape, parabola shaped oblique change.In embodiments, the embodiment described in Fig. 3 A-3F may be combined.
As described in embodiments above, erasing pulse has at least four characteristics: quick to declivity change part, the minimum hold time under peak erase voltage, the quick upward change from peak erase voltage and the slow upward change in low-voltage part to peak erase voltage.
Advantageously, apply fast, higher energy pulse promptly destroys memory state (e.g., destroying the conductive filament in mnemon 10).But, after filament destroys at once, between destroyed filament, have dropped larger current potential.High electric field region can cause the permanent damage of solid electrolyte (being separated the electrolyte of destroyed filament).Therefore, low-voltage part is used to the solid electrolyte layer of breaking-up terminate when not damaging to(for) filament.In addition, low-voltage part can help cleaning bunch lump with other and require the filament in longer erasing time.This imperfection in solid electrolyte otherwise can increase statistics expansion (spread) of erase process.
The Fig. 4 comprising Fig. 4 A-4B illustrates the storage unit according to the embodiment of the present invention.
In one embodiment, storage unit 15 can be the storage unit (memory cell) of an access device and a mnemon (memory unit) (1-AD 1-MU).Storage unit 15 is by wordline WL, bit line BL and select line SL to be connected to multiple similar storage unit, forms memory array by this.Storage unit 15 is included in the mnemon 10 described in each embodiment of the application.Mnemon 10 can comprise the resistive switch storage carrying out switch based on heat, electricity and/or galvanomagnetic effect.
In one or more embodiments, mnemon 10 can comprise ion storage device.This ion storage device can relate to the unit based on anion transport or cation transport.The example of ion storage device comprises conducting bridge random access memory.CBRAM can comprise the solid electrolyte layer be sandwiched between inert electrode and electrochemical activity electrode.Solid electrolyte layer can comprise such as based on sulfide (the such as GeS of germanium 2) chalcogenide material.In embodiments, solid electrolyte layer can comprise the WO of copper doped 3, Cu/Cu 2s, Cu/Ta 2o 5, Cu/SiO 2, Ag/Zn xcd 1-xs, Cu/Zn xcd 1-xs, Zn/Zn xcd 1-xs, GeTe, GST, As-S, Zn xcd 1-xs, TiO 2, ZrO 2, SiO 2.In certain embodiments, solid electrolyte 60 can comprise multilayer and can comprise bilayer, such as Ge xse y/ SiO x, Ge xse y/ Ta 2o 5, Cu xs/Cu xo, Cu xs/SiO 2and combination.In embodiments, electrochemical activity electrode can comprise silver, copper, zinc and/or copper-tellurium.
In another embodiment, mnemon 10 can comprise RRAM, in certain embodiments, as the oxide based on metal.In alternative embodiments, mnemon 10 can comprise phase change memory unit.
See Fig. 4 A, mnemon 10 is deployed between first node (e.g., anode) and Section Point 2 (e.g., negative electrode).First node 1 is coupled to selects line SL, and Section Point 2 is coupled to bit line BL by access device 100.
In embodiments, access device 100 can comprise switching device.In one embodiment, access device 100 is diodes.In an alternative em bodiment, access device 100 is transistors.Access device 100 can provide the conductive path from Section Point 2 to bit line BL.Wordline WL (and bit line BL and selection line SL) can be used to enable or control access device 100.Wordline WL can be coupled to word line driver (WLD) 110, and this word line driver (WLD) 110 jointly can be shared by the multiple storage unit sharing same wordline WL.As will be descr, WLD 110 can use the one or more potential pulse curves described in each embodiment to drive wordline.
Similarly, bit line BL can be coupled to bit line driver BLD 120 and is coupled or driven by bit line driver BLD120, and selects line SL can be coupled to selection line drive SLD 130.Jointly BLD 120 and SLD 130 can be shared in the multiple storage unit sharing same bit line and same selection line.As will be descr, BLD 120 and/or SLD 130 can use in each embodiment the one or more pulse curves described drive bit line respectively and select line.
Fig. 4 B illustrates the storage unit comprising transistor and mnemon according to embodiments of the invention.
In this embodiment, access device 100 is transistors.In one embodiment, transistor can be metal-insulator field effect transistor.In other embodiments, transistor can be other type of transistor comprising bipolar transistor.In one embodiment, storage unit 15 can be a transistor and a mnemon (1-T 1-MU) storage unit.As shown in Figure 4 B, the grid of access device 100 is coupled to wordline WL.First source/drain node of access device 100 is coupled to bit line BL, and the second source/drain node of access device 100 is coupled to mnemon by Section Point 2.Therefore, mnemon 10 is coupled to bit line BL by the channel region of access device 100.
As will be described in Fig. 5-7, by applying tiltedly to become pulse to one or more nodes of storage unit, the embodiments of the invention that composition graphs 2-3 describes can be embodied as storage unit above.
The Fig. 5 comprising Fig. 5 A-5B illustrates the outstanding sequential chart illustrating the procedure operation of the program pulse of asserting in wordline and bit line place, and wherein Fig. 5 A illustrates regular programming pulses, and wherein 5B illustrates the programming pulse according to the embodiment of the present invention.
Programming pulse shown in Fig. 5 can be applied to the storage unit that Fig. 4 describes.During the programming of mnemon 10, bit line BL can be grounded, and selects line to be driven high to positive potential.Alternatively, in certain embodiments, select that line SL can be grounded and bit line BL can be pulled low to negative potential.The wordline WL of access device 100 is activated with conducting access device 100, the final conducting mnemon 10 (being pushed into low resistance state) of this measure.Such as, in order to enable the access device comprising n slot field-effect transistor, positive bias is applied to wordline WL.
Shown in Figure 5, for the pulse in a series of pulse, voltage V on the select line sLwith the voltage V in wordline wL.Although multiple pulse can be used in embodiments to carry out programming and erase operation, but Fig. 5 for clarity sake shows individual pulse.Each embodiment that the embodiment that Fig. 5 describes can describe in application drawing 2.
In Fig. 5 A, regular programming pulses is shown.As shown in Figure 5A, line SL and wordline WL is selected to be driven high to such as program voltage V pROG.As previously described, in conventional programming, program voltage V pROGsuddenly tiltedly become (approach infinity slope) and can assert wordline WL and select line SL simultaneously.As shown in the figure, the corresponding forward position of bit line pulse and rear edge can be mated in the forward position of word line pulse and rear edge.
For the various application of the inventive embodiments of Fig. 2 description before Fig. 5 B illustrates.
See Fig. 5 B, in one embodiment, can assert in wordline that square-wave pulse can apply asymmetric pulse on bit line simultaneously, line ground connection (alternatively can simultaneously select line negative sense tiltedly to become bit line ground connection) will be selected simultaneously.As shown in the figure, word line pulse is at time cycle t wLon be asserted, this time cycle t wLthan the duration t of the asymmetry pulse of asserting on bit line bLlonger.Can assert to given pulse and assert bit line after wordline, and similarly, can before the rear edge of word line pulse, bit-line voltage becomes to declivity.
In embodiments, the voltage V of bit line bLcomprise initial quick fraction, higher than this initial quick fraction then current potential be increased to peak program/erasing voltage fast.In embodiments, the voltage V of bit line bLmedium voltage can be decreased to quite rapidly from crest voltage.Then, bit-line voltage V bLsuch as with the speed lower than about 100mV/ μ s, reduce lentamente.
Asymmetry pulse shown in Fig. 5 B is similar to the programming pulse described for Fig. 2 B.Embodiments of the invention also can comprise the asymmetry pulse described in Fig. 2 A and Fig. 2 C-2F.
The Fig. 6 comprising Fig. 6 A-6B illustrates outstanding illustrating at wordline and corresponding bit line and/or the sequential chart of erase operation of erasing pulse selecting line place, and wherein Fig. 6 A illustrates conventional erase pulse, and wherein Fig. 6 B illustrates the erasing pulse according to the embodiment of the present invention.
Be similar to programming pulse, asserting after word line voltage, triggering the bit-line voltage of erasing pulse.As shown in Figure 6A, by asserting that wordline and bit line are to conventional erase pulse of programming simultaneously.For an example of the various application of the inventive embodiments of Fig. 3 description before Fig. 6 B illustrates.
The embodiment of the present invention according to Fig. 6 B, apply erasing pulse at bit line place after word line pulse asserting, Fig. 6 B illustrates the example realizing the erasing pulse described for Fig. 3 B.As described before, erasing pulse is decreased to peak erase voltage rapidly, and after this it drops to medium voltage and then slow-decay on long-time rapidly.In one embodiment, erasing voltage can be decayed as previously described exponentially.
The Fig. 7 comprising Fig. 7 A-7B illustrates storage unit according to alternate embodiment of the present invention and corresponding program/erase operations.
Fig. 7 A illustrates the memory cell array according to an embodiment of the invention with the storage unit comprising transistor and mnemon.As described for Fig. 4 before, storage unit 15 comprises access device 100 and is deployed in the mnemon 10 between first node 1 (as anode) and Section Point 2 (as negative electrode).First node 1 is coupled to selects line SL, and Section Point 2 is coupled to bit line BL by access device 100.The grid of access device 100 is coupled to wordline, and operates this access device 100 by word line driver 110.Another plate being not attached to the capacitor 122 of this column selection transistor 121 is coupled to earthing potential.
As shown, the often row of memory cell array can be coupled to column selection transistor 121 and capacitor 122.As used further, Fig. 7 B describes, capacitor 122 can be configured to generate asymmetry pulse.
Fig. 7 B illustrates the program/erase asymmetry pulse using the memory cell array described in Fig. 7 A to generate.By asserting the column selection voltage (V at gate node 3 place of column selection transistor 121 3) disconnect (open) column selection transistor 121, thus start program/erase operations.Therefore, when column selection voltage is asserted, the current potential at bit line place charges to capacitor 122.In access device 100 not conducting now, this current potential charges to capacitor 122.
As shown in Figure 7 B, by asserting potential pulse in wordline and conducting access device 100.Then, word line potential is asserted, and overlaps with the rear edge of column selection potential pulse to make the forward position of word line voltage pulse.Therefore, directly bit-line voltage is not applied to mnemon 10.But after column selection voltage cuts off bit-line voltage, capacitor 122 discharges, produce current potential at Section Point 2 place of mnemon 10.The Part II that the electric discharge carrying out sufficient power from capacitor 122 has the pulse of quick upward change, the quick Part I to declivity change with the gained current potential that index reduces also therefore cathode node 3 place and characterized by slow index shape decay.Quick upward change be column selection constant-voltage sequential with the result overlapped with word line voltage, the Part I simultaneously become to declivity and Part II are derived from the electric discharge of capacitor 122.
In embodiments, as the current potential (V at Section Point 2 place of the cathode node of mnemon 10 2) can change according to following formula: V 2(t)=PV × (1-exp (-t/ ((R 10+ R 100) × C))), the electric capacity of the capacitor 122 that is wherein crest voltage, is the time, is and be the resistance of mnemon 10 but the conducting state resistance of access device 100.In embodiments, the electric capacity of configurable capacitor 122 discharges before word line pulse terminates completely to make capacitor 122.In one or more embodiments, the time cycle t of word line pulse wLthe electric capacity being less than the resistance of mnemon 10 and capacitor 122 is long-pending.
The Fig. 8 comprising Fig. 8 A and Fig. 8 B illustrates the various memory cell arrays realizing embodiments of the invention.
The mnemon 10 implementing previously described each embodiment can be used to form memory cell array 200.Mnemon 10 can be formed as described in Fig. 1 and/or Fig. 4.
In the embodiment of shown in Fig. 8 A, memory cell array 200 can be formed by storage unit 15, describes and the access device 100 of Fig. 5-7 operation relatively and mnemon 10 before this storage unit 15 comprises for Fig. 4.
In the alternate embodiment shown in Fig. 8 B, memory cell array 200 can be implemented as cross point memory array, such as, be embodied as cellar array.In one suchembodiment, mnemon 10 can comprise switching device (as diode) and resistor at same device.In certain embodiments, these arrays also can be used to form logical device.Mnemon 10 is coupling between more than first line 301 and more than second line 302.More than first and second line 301 and 302 can be perpendicular to one another.Mnemon 10 can be coupled to First Line in more than first line 301 in the first metal layer face, in the vertical direction higher or lower than the First Line in more than second line 302 in the metal level in the first metal layer face.
The Fig. 9 comprising Fig. 9 A-9B illustrates the memory device realizing the embodiment of the present invention.
With reference to Fig. 9 A, memory device comprises memory cell array 200 (as Fig. 8 describes), access circuit 210 and program/erase circuitry 220.Memory cell array 200 can comprise multiple mnemon 10 as described previously.Access circuit 210 provides electrical connection to memory cell array 200, thus able to programme, erasing and read mnemon 10.Access circuit 210 can be placed in the one side or the multi-lateral of memory cell array 200.Such as, access circuit 210 can be placed on two opposite sides to make to apply current potential at mnemon two ends.Exemplarily, access circuit 210 can comprise the wordline, bit line and the selection line drive that describe in Fig. 4.
Programming and erasing circuit 220 can provide programming and erase signal (such as P/E to access circuit 210 1, P/E 2), these signals are applied to memory cell array 200 by this access circuit 210.Programming and erase signal can be included in the curve as described in embodiment each in Fig. 2, Fig. 3 and Fig. 5-7.Programming and erase signal can comprise outside or inside circuit can generate asymmetric potential pulse.In one embodiment, programming and erasing circuit 220 comprise the ramp generator 221 for generating asymmetrical voltage pulse.Ramp generator 221 can comprise pulse, function or signal generator.In one embodiment, ramp generator 221 comprises constant current source, and this constant current source is to capacitor charging to obtain upward change and/or to become to declivity, and it is such that such as, an embodiment in Fig. 7 describes.In one embodiment, ramp generator 221 comprises comparer thus cuts off current source when reaching predetermined voltage.In embodiments, ramp generator 221 can comprise any appropriate circuitry known to persons of ordinary skill in the art.In certain embodiments, current mirroring circuit can be used dynamically to maintain the maximum current flowing through mnemon.
Peak program or erasing voltage can higher or lower than supply voltages.Programming and erasing circuit can comprise the charge pump circuit for generating higher than supply voltage, or generate the step down voltage redulator etc. lower than supply voltage.In certain embodiments, programming and erasing circuit also can from external circuit receive programming signal and erase signal one or more.In certain embodiments, programming can comprise with erasing circuit the programmed circuit be physically separated with erasing circuit.
Fig. 9 B illustrates the another embodiment of memory device.Memory device comprises programming as Fig. 9 A describes and erasing circuit 220 and memory cell array 200.Access circuit can comprise column decoder 230 and row decoder 240.In response to address date, columns and rows demoder 230 and 240 select storage unit group can be used for reading, programming, erasing.In addition, memory device can comprise and the reading circuit 250 be separated with erasing circuit 220 of programming.This reading circuit 250 can comprise electric current and/or voltage sense amplifier.Memory device can comprise register 260 further, for store from memory cell array 200 read data value or store will be written into mnemon array 200 data.In embodiments, register 260 can input and output data concurrently (that is, byte, word and other).In certain embodiments, register 260 is accessed by serial data path.
I/O (I/O) circuit 270 can receive address values and write data value, and exports read data value.The address value received can be applied to columns and rows demoder 230 and 240 with select storage unit.Read data from register 260 can be output on I/O circuit 270.Similarly, writing data and can be stored in register 260 on I/O circuit 270.Command decoder 290 can receive order data, and this order data can be transferred to steering logic 280.Steering logic 280 can provide signal with each circuit of control store equipment.
Although with reference to illustrative embodiment, invention has been described, but this explanation is not intended to make explanations in a limiting sense.The various correction of illustrative embodiment and combination and other embodiments of the invention are those skilled in that art with reference to easy understand after instructions.Exemplarily, the embodiment described in Fig. 2-7 in embodiments can combination with one another.Therefore, claims are intended to contain any such correction or embodiment.
Although described the present invention and advantage thereof in detail, should be appreciated that and can make various change, replacement and change wherein, and do not deviated from the spirit and scope of the present invention that appended claims limits.Such as, those skilled in that art will readily appreciate that, many features described herein, function, technique and material can change and still be within the scope of the present invention.
And, the scope of the application be not intended to be limited to describe in the description technique, machine, manufacture, material composition, means, method and step specific embodiment.Just as those of ordinary skill in the art easily understand from the disclosure of invention, can adopt according to the present invention and perform to the basic identical function of corresponding embodiment described herein or realize the existing of basic identical result or the technique later developed, machine, manufacture, material composition, means, method or step.Therefore, claims are intended to such technique, machine, manufacture, material composition, means, method or step to comprise within the scope of the appended claims.

Claims (20)

1. one kind operates the method for storage unit, described storage unit comprises the resistive switching device with the first terminal and the first terminal and the access device with the first access terminal and the second access terminal, described second access terminal is coupled to the first terminal of described resistive switching device, and described method comprises:
Apply strobe pulse at the grid place of the selection transistor with first node and Section Point, described first node is coupled to the described first access terminal of described access device, and described Section Point is coupled to bit line potential node;
To have the first plate and the second plate capacitor charging, during described strobe pulse described first plate be coupled to described selection transistor described first node and be coupled to described access device described first access terminal;
Described access device is activated after to described capacitor charging;
Inactive described selection transistor after the described access device of activation; And
By described resistive switching device to the capacitor discharge charged.
2. the method for claim 1, is characterized in that, activate with the first pulse and stop using described selection transistor, wherein activate described access device with the second pulse, and the rear edge of wherein said first pulse overlaps with the forward position of described second pulse.
3. the method for claim 1, it is characterized in that, activate with the first pulse and stop using described selection transistor, wherein activates described access device with the second pulse, and the electric capacity of capacitor described in wherein said second ratio of pulse length to the total cycle length and the resistance of described resistive switching device is long-pending longer.
4. the method for claim 1, is characterized in that, described resistive switching device comprises conducting bridge storer.
5. the method for claim 1, is characterized in that, is comprising the current potential of asserting in the wordline of coupled in common to the access device of multiple twin bit cell to the described access device of the rear activation of described capacitor charging.
6. the method for claim 1, is characterized in that, comprises pulse is applied to described resistive switching device to the capacitor discharge charged, and described pulse has the first slope, the second slope and the 3rd slope; Wherein
Second and the 3rd slope be on different directions from described first slope.
7. method as claimed in claim 6, is characterized in that, the first slope rises, the second slope declines and the 3rd slope declines, and
Described first Slope Facies declines than described second slope with speed rising faster.
8. the method for claim 1, it is characterized in that, if by described resistive switching device to the capacitor discharge charged comprise described resistive switching device be not in or close to second, higher resistance, then described resistive switching device is from the first resistance variations to described second, higher resistance.
9. the method for claim 1, it is characterized in that, if by described resistive switching device to the capacitor discharge charged comprise described resistive switching device be not in or close to second, lower resistance, described resistive switching device is from the first resistance variations to described second, lower resistance.
10. the method for claim 1, is characterized in that, comprises the solid electrolyte layer that generation electric current flows through described resistive switching device by described resistive switching device to the capacitor discharge charged.
11. the method for claim 1, is characterized in that, to be comprised conductive ion is moved by the layer in described resistive switching device by described resistive switching device to the capacitor discharge charged.
12. 1 kinds of equipment, comprising:
At least one storage unit, comprising:
Resistive switching device, it has the first terminal and the second terminal; And
Access device, have the first access terminal and the second access terminal, described second access terminal is coupled to the described the first terminal of described resistive switching device;
Selector, the first node with the described first access terminal being coupled to described access device, the Section Point being coupled to bit line and be configured to receive the Controlling vertex of strobe pulse, described selector responds described strobe pulse and provides voltage path between the first and second nodes; And
Charging capacitor, described capacitor has the first plate, described first plate be coupled to described selection transistor described first node and be coupled to described access device described first access terminal, wherein
Described access device is configured at described charging capacitor by the discharge path enabled after charging from described capacitor to described resistive switching device.
13. equipment as claimed in claim 12, is characterized in that, also comprise the word line driver of the Controlling vertex being coupled to described access device; Wherein in response to described word line driver assert described access device the enabling current potential of Controlling vertex place and enable described access device.
14. equipment as claimed in claim 13, is characterized in that, once the cut-off of described selector, described word line driver is just asserted and enable current potential described in the Controlling vertex place of described access device.
15. equipment as claimed in claim 13, is characterized in that:
At least one storage unit described comprises multiple storage unit, and each storage unit makes the Controlling vertex coupled in common of their access device to same wordline; And
Described word line driver enables current potential described in asserting in described wordline.
16. equipment as claimed in claim 1, it is characterized in that, at least one storage unit described comprises multiple storage unit, and each storage unit makes the Section Point of their selector jointly be coupled to same bit line.
17. equipment as claimed in claim 1, it is characterized in that, at least one storage unit described comprises multiple storage unit, each storage unit makes the second terminal of their resistive switching device jointly be coupled to same selection line, and each storage unit makes the Controlling vertex of their access device jointly be coupled to same wordline, described selection line is different from described wordline.
18. equipment as claimed in claim 1, it is characterized in that, described resistive switching device comprises solid electrolyte layer.
19. equipment as claimed in claim 1, it is characterized in that, described resistive switching device comprises the material chosen from lower group: the WO that copper (Cu) adulterates 3, Cu/Cu 2s, Cu/Ta 2o 5, Cu/SiO 2, Ag/Zn xcd 1-xs, Cu/Zn xcd 1-xs, Zn/Zn xcd 1-xs, GeTe, GST, As-S and Zn xcd 1-xs.
20. equipment as claimed in claim 1, it is characterized in that, described resistive switching device comprises the material chosen from lower group: WO 3, Ta 2o 5, TiO 2, ZrO 2, and SiO 2.
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