CN104734488A - DCM flyback PFC convertor capable of efficiently and lowly outputting voltage ripples - Google Patents

DCM flyback PFC convertor capable of efficiently and lowly outputting voltage ripples Download PDF

Info

Publication number
CN104734488A
CN104734488A CN201510112903.3A CN201510112903A CN104734488A CN 104734488 A CN104734488 A CN 104734488A CN 201510112903 A CN201510112903 A CN 201510112903A CN 104734488 A CN104734488 A CN 104734488A
Authority
CN
China
Prior art keywords
input
resistance
circuit
output
operational amplifier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201510112903.3A
Other languages
Chinese (zh)
Inventor
姚凯
付晓勇
李辉
王小平
周旭峰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nanjing University of Science and Technology
Original Assignee
Nanjing University of Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nanjing University of Science and Technology filed Critical Nanjing University of Science and Technology
Priority to CN201510112903.3A priority Critical patent/CN104734488A/en
Publication of CN104734488A publication Critical patent/CN104734488A/en
Pending legal-status Critical Current

Links

Classifications

    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02BCLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The invention discloses a DCM flyback PFC convertor capable of efficiently and lowly outputting voltage ripples. The DCM flyback PFC convertor comprises a main power circuit and a control circuit; in the control circuit, the output end A of a first branch voltage follower circuit is connected with one input end of an added circuit, the output end B of a second branch voltage amplifying circuit is connected with the other input end of the added circuit and the second input end of a multiplying unit, the output end C of the added circuit is connected with the third input end of the multiplying unit, the output end of an error adjusting circuit is connected with the first input end of the multiplying unit, the output end P of the multiplying unit is connected with the input end of a sawtooth wave comparing and switch tube driving circuit, and the output end of the sawtooth wave comparing and switch tube driving circuit is connected with the gate pole of a main power circuit switch tube Qb. According to the DCM flyback PFC convertor capable of efficiently and lowly outputting the voltage ripples, the boundary inductance is increased, the conversion efficiency is improved, and voltage ripple outputting or energy-storage capacitor outputting can be reduced.

Description

The DCM flyback pfc converter of efficient low output voltage ripple
Technical field
The present invention relates to the A.C.-D.C. converter field of electrical energy changer, particularly a kind of DCM flyback pfc converter of efficient low output voltage ripple.
Background technology
Power factor correction (Power Factor Correction, PFC) converter can reduce Harmonics of Input, improves input power factor, is used widely.Pfc converter is divided into active and passive two kinds of modes, and relative to passive mode, active mode has that input power factor is high, volume is little, low cost and other advantages.
Active PFC converter can adopt multiple circuit to open up and control method, wherein anti exciting converter is one of conventional several pfc converters, according to the whether constant conduction of secondary side diode electric current in switching tube blocking interval, three kinds of mode of operations can be divided into, i.e. continuous current mode pattern (Continuous Current Mode, CCM), critical current mode continuous mode (Critical Continuous Current Mode, CRM), discontinous mode (Discontinuous Current Mode, DCM).
DCM flyback pfc converter is generally applied in middle low power occasion, its advantage be switching tube zero current turning-on, secondary side diode without Reverse recovery and switching frequency constant etc.But owing to being operated in discontinuous mode, the transmission of energy does not take whole switch periods, its inductive current peak and effective value larger, switching tube and diode as the same, while exacerbates power device current stress, also bring the increase of conduction loss and switching tube turn-off power loss, affect the raising of efficiency.
Summary of the invention
The object of the present invention is to provide a kind of DCM flyback pfc converter of efficient low output voltage ripple, control by proposing a kind of new switch periods optimal utilization rate, increase threshold inductance value, reduce main power device current peak and effective value, improve conversion efficiency, also reduce output voltage ripple simultaneously or export storage capacitor.
The technical solution realizing the object of the invention is: a kind of DCM flyback pfc converter of efficient low output voltage ripple, comprise main power circuit and control circuit, described main power circuit comprises input voltage source v in, electromagnetic interface filter, diode rectifier circuit RB, transformer T 1, switching tube Q b, diode D b, filter capacitor C owith load R ld, wherein input voltage source v inbe connected with the input port of electromagnetic interface filter, the output port of electromagnetic interface filter is connected with the input port of diode rectifier circuit RB, and the output negative pole of diode rectifier circuit RB is reference potential zero point, the output cathode of diode rectifier circuit RB and transformer T 1winding N pdifferent name end connect, transformer T 1winding N psame Name of Ends access switching tube Q bdrain electrode, switching tube Q bsource electrode be connected zero point with reference potential, transformer T 1winding N ssame Name of Ends and diode D banode connect, diode D bnegative electrode respectively with filter capacitor C oone end and load R ldone end connect, filter capacitor C othe other end and load R ldthe other end all connect reference potential zero point, load R ldthe voltage at two ends is output voltage V o;
Described control circuit comprises sawtooth waveforms and compares and switch tube driving circuit, the first dividing potential drop follow circuit, the second dividing potential drop amplifying circuit, add circuit, multiplier, output voltage feedback circuit; Wherein sawtooth waveforms compares and the output of switch tube driving circuit and switching tube Q bgate pole connect; The input of the first dividing potential drop follow circuit and input voltage sampled point V gnamely the output cathode of diode rectifier circuit RB connects, and the output terminals A of the first dividing potential drop follow circuit is connected with an input of add circuit; The input of the second dividing potential drop amplifying circuit connects the output voltage V of main power circuit opositive pole, the output B of the second dividing potential drop amplifying circuit is connected with another input of addition electricity and the second input of multiplier respectively; The input of add circuit is connected with the output terminals A of the first dividing potential drop follow circuit and the output B of the second dividing potential drop amplifying circuit respectively, and the output C of add circuit is connected with the 3rd input of multiplier; The input of output voltage feedback circuit connects the output voltage V of main power circuit opositive pole, the output of output voltage feedback circuit is connected with the first input end of multiplier; The output P of multiplier compares with sawtooth waveforms and the input of switch tube driving circuit is connected.
Compared with prior art, its remarkable advantage is in the present invention: (1), under the prerequisite meeting IEC61000-3-2Class D standard, increases threshold inductance value, reduces conduction loss and switching tube turn-off power loss, improves conversion efficiency; (2) greatly reduce output voltage ripple or export storage capacitor.
Accompanying drawing explanation
Fig. 1 is flyback pfc converter main circuit schematic diagram.
Fig. 2 is the inductive current oscillogram of DCM flyback pfc converter.
Fig. 3 is the threshold inductance value change curve under different input voltage.
Fig. 4 is switch periods utilance change curve in half power frequency period.
Fig. 5 is the inductive current oscillogram in pi/2 and 0 approximate angle switch periods, and wherein (a) angle is pi/2, and (b) angle is 0.
The relation curve of Fig. 6 threshold inductance value and M and α and surface chart, the wherein graph of relation of (a) threshold inductance value and M and α, the relation surface chart of (b) threshold inductance value and M and α.
Fig. 7 is switching tube drive singal and inductive current oscillogram, and wherein (a) determines Duty ratio control, and (b) switch periods optimal utilization rate controls (L p1=200uH), (c) switch periods optimal utilization rate controls (L p1=275uH).
Fig. 8 is the PF curve chart under different control modes.
Fig. 9 is input current waveform figure in half power frequency period under two kinds of control modes.
Figure 10 is the change curve that switch periods optimal utilization rate controls lower 3,5,7 subharmonic and the ratio of first-harmonic.
Figure 11 is the change curve that switch periods optimal utilization rate controls lower 3,5,7 subharmonic and the ratio of power.
Figure 12 is the curve chart that under two kinds of control modes, former limit inductive current effective value changes with input voltage.
Figure 13 is the curve chart that under two kinds of control modes, secondary inductance current effective value changes with input voltage.
Figure 14 is the change curve of former limit inductive current peak in half power frequency period under two kinds of control modes.
Figure 15 is the change curve of Instantaneous input power perunit value in half power frequency period under two kinds of control modes.
Figure 16 is the change curve of output voltage ripple under two kinds of control modes.
Figure 17 is the electrical block diagram of the DCM flyback pfc converter of the efficient low output voltage ripple of the present invention.
Embodiment
Below in conjunction with drawings and the specific embodiments, the present invention is described in further detail.
The operation principle of 1 DCM flyback (Flyback) pfc converter
Fig. 1 is flyback pfc converter main circuit.
In order to easy analysis, first make the following assumptions: 1. all devices are ideal element; 2. output voltage ripple is very little compared with its DC quantity; 3. switching frequency is far above input voltage frequency.
Without loss of generality, the expression formula defining input ac voltage is
V in=V msin ω t (1) wherein V mfor input voltage peak value, ω=2 π f linefor input voltage angular frequency, f linefor input voltage frequency.
Voltage so after input rectifying is
v g=V m|sinωt| (2)
Switch periods inner conversion device inductive current waveform when Fig. 2 gives DCM.As switching tube Q bduring conducting, diode D bcut-off, former limit inductance L pthe voltage at two ends is v g, its current i pwith v by zero g/ L pslope linearly rise, so i ppeak value be
i Lp _ pk = V m | sin ωt | · D y L p f s - - - ( 3 )
Wherein D yfor switching tube duty ratio, f sfor switching frequency.
In a switch periods, former limit inductive current mean value i lp_avfor
i Lp _ av = 1 2 · i Lp _ pk · D y = V m | sin ωt | · D y 2 2 L p f s - - - ( 4 )
So input current i infor
i in = i Lp _ av = V m sin ωt · D y 2 2 L p f s - - - ( 5 )
As can be seen from formula (5), as duty ratio D ywhen remaining unchanged in power frequency period, input current is proportional to input voltage, automatically can realize PFC, now PF=1.
Work as Q bturn off, diode D bconducting, the energy transferring being stored in transformer primary side to secondary, by secondary inductance L safterflow, now L sthe voltage at two ends is-V o, i swith V o/ L sslope from secondary current peak value i ls_pkdecline, it drops to the time t of zero rfor
t r = i Ls _ pk V o / L s = n i Lp _ pk n 2 · V o / L p = V m | sin ωt | · D y n V o f s - - - ( 6 )
Wherein n is the transformer primary secondary turn ratio, L sfor transformer secondary inductance, i ls_pkfor secondary inductance current peak.
Then secondary current drops to the duty ratio D corresponding to zero rfor
D R = t r T s = V m | sin ωt | · D y n · V o - - - ( 7 )
Under anti exciting converter is operated in DCM, therefore as diode D belectric current drop to after zero and there is one section of dead band, then start new switch periods.
By formula (1) and formula (5), the average value P of input power in half power frequency period can be obtained in
P in = 1 π ∫ 0 π v in i in dωt = V m 2 D y 2 4 L p f s - - - ( 8 )
Suppose that transducer effciency is 1 (same afterwards), so input average power and equal power output, i.e. P in=P o.Switching tube duty ratio D can be obtained by formula (8) yfor
D y = 2 V m L p f s P o - - - ( 9 )
2 switch periods optimal utilization rate control strategies
For the ease of analyzing, proposing the concept of switch periods utilance, being defined as β
β=D y+D R(10)
Formula (7) is substituted into formula (10) obtain
β = D y ( 1 + V m | sin ωt | n · V o ) - - - ( 11 )
For making discontinuous current mode, β≤1 must be met.
Make α=V m/ nV o, and formula (9) is substituted into formula (11), can obtain
L p ≤ V m 2 4 P o f s ( 1 + α | sin ωt | ) 2 - - - ( 12 )
As can be seen from the above equation, transducer parameters one timing, in half power frequency period, threshold inductance value that all angles place requires is different, and wherein, threshold inductance value corresponding to pi/2 place is minimum, and namely determining Duty ratio control lower critical inductance value is
L p 1 ≤ V m 2 4 P o f s ( 1 + α ) 2 - - - ( 13 )
In conjunction with 4.1 joint parameter designing indexs, can obtain Fig. 3, can find out by formula (13), when determining Duty ratio control, threshold inductance value is 200 μ H.By L p1=200 μ H and formula (9) substitute into formula (11), when can to make input voltage be 176V, 220V and 264V, and β 1curve in half power frequency period [0, π] scope, as Fig. 4.As can be seen from Figure 4, under each input voltage, β 1in [0, pi/2], become increasing trend, minimum near angle 0, namely switch periods utilance is low, and discontinuous current mode degree is the highest, maximum near angle pi/2, and namely switch periods utilance is high, and discontinuous current mode degree is minimum.
Fig. 5 gives the waveform of the inductive current in half power frequency period near pi/2 and 0 in switch periods, make following imagination, the threshold inductance value that maintenance is determined under Duty ratio control is constant, slightly duty ratio is reduced at pi/2 approximate angle, then switch periods utilance also corresponding reduction, discontinuous current mode degree increases; And in order to keep power output constant, near angle 0, needing the corresponding duty ratio that slightly increases, the also corresponding increase of switch periods utilance, discontinuous current mode degree reduces.Reduce further near pi/2 and 0 and increase duty ratio, the switch periods utilance so near respective angles will reduce further and increase, and discontinuous current degree also will increase further and reduce.In other words, along with the difference of the duty ratio near pi/2 and 0 progressively expands, β 1close to 1 that is inductive current close to critical continuous mode switch periods residing for power frequency angle transit near 0 near pi/2 gradually.Can predict, in the process, there is the duty ratio by the change of certain rule, make [0, pi/2] in all lower i.e. discontinuous current mode degree of the switch periods utilance at arbitrarily angled place comparatively large, thus can increase threshold inductance value on the basis of original Duty ratio control, to improve switch periods utilance and to reduce discontinuous current mode degree, thus reduce inductive current peak and effective value, improve conversion efficiency.Below will to this labor.
According to above imagination, need to reduce and increase duty ratio near pi/2 and 0, and the input voltage of converter is sinusoidal form, SIN function is introduced in change in duty cycle rule, to realize switch periods optimal utilization rate by the present invention's research.The duty ratio expression formula that definition switch periods optimal utilization rate controls is
D y = D o 1 + M | sin ωt | - - - ( 14 )
Wherein M is undetermined coefficient, D 0with relating to parameters such as M and converter input and output voltage, power output, switching frequency and inductance value.
The calculating of 3 maximum threshold inductance values
Formula (14) is substituted into formula (5), and can obtain input current expression formula is
i in = V m sin ωt · D o 2 2 L p f s ( 1 + M | sin ωt | ) 2 - - - ( 15 )
The power output of converter can be obtained by formula (1) and formula (15)
P o = P in = 1 π ∫ 0 π v in i in dωt = V m 2 D o 2 2 π L p f s ∫ 0 π sin 2 ωt ( 1 + M | sin ωt | ) 2 dωt - - - ( 16 )
Can be obtained by formula (16)
D o = 1 V m 2 π L p f s P o / ∫ 0 π sin 2 ωt ( 1 + M | sin ωt | ) 2 dωt - - - ( 17 )
Formula (17) is substituted into formula (14), can obtain
D y = 1 V m 2 π L p f s P o / ∫ 0 π sin 2 ωt ( 1 + M | sin ωt ) 2 dωt 1 + M | sin ωt | - - - ( 18 )
Formula (18) is substituted into formula (11), can obtain
L p ≤ V m 2 2 π P o f s · ∫ 0 π sin 2 ωt ( 1 + M | sin ωt ) 2 dωt / ( 1 + α | sin ωt | 1 + M | sin ωt | ) 2 - - - ( 19 )
Analyze above formula, as M >=α, obtain minimum value when ω t=0, as M< α, obtain minimum value when ω t=pi/2, so threshold inductance value is
L p 2 ( M , &alpha; ) = V m 2 2 &pi; P o f s &CenterDot; &Integral; 0 &pi; sin 2 &omega;t ( 1 + M | sin &omega;t | ) 2 d&omega;t M &GreaterEqual; &alpha; V m 2 2 &pi; P o f s &CenterDot; &Integral; 0 &pi; sin 2 &omega;t ( 1 + M | sin &omega;t | ) 2 d&omega;t ( 1 + &alpha; 1 + M ) 2 M < &alpha; - - - ( 20 )
Can be made the graph of a relation of threshold inductance value and M and α by formula (20), as Fig. 6, convolution (20) is known with Fig. 6, as M>=α, and L p2for subtraction function, as M< α, L p2for increasing function, therefore L during M=α p2obtain maximum.M=α is substituted into formula (18) and formula (20), and duty ratio and the threshold inductance value that can obtain the control of switch periods optimal utilization rate are respectively
D y = 1 V m 2 &pi; L p f s P o / &Integral; 0 &pi; sin 2 &omega;t ( 1 + &alpha; | sin &omega;t | ) 2 d&omega;t 1 + &alpha; | sin &omega;t | - - - ( 21 )
L p 2 = V m 2 2 &pi; P o f s &CenterDot; &Integral; 0 &pi; sin 2 &omega;t ( 1 + &alpha; | sin &omega;t | ) 2 d&omega;t - - - ( 22 )
In conjunction with the design parameter of 4.1 joint converters, Fig. 3 can be obtained by formula (22).Can find out, the threshold inductance value under switch periods optimal utilization rate controls is 275 μ H, and determines compared with duty ratio, and threshold inductance value increases to some extent.
4 performance comparison
4.1 switch periods utilances
For ease of analyzing, design parameter is as follows:
Input voltage effective value V in_rms=176 ~ 264VAC; Power output P o=60W; Output voltage V o=24V; Former secondary turn ratio n=4; Filter capacitor C o=3300uH; Switching frequency f s=100kHz.
The design parameter of associative transformation device, can be made respectively by formula (11) and formula (21) adopts switch periods optimal utilization rate to control, inductance value is 200 μ H and 275 μ H, switch periods utilance when input voltage is 176V, 220V and 264V, as shown in Figure 4.
Fig. 7 sets forth and determines Duty ratio control, in three kinds of situations that switch periods optimal utilization rate controls (maintaining the constant and inductance value of former inductance value to increase), and switching tube drive singal and inductive current waveform schematic diagram.
As can be seen from Fig. 4 and Fig. 7 (a), when Duty ratio control is determined in employing, when input voltage angle changes from 0 to pi/2, switch periods utilance raises gradually, discontinuous current mode degree reduces gradually, variation tendency in [pi/2, π] interval is symmetrical consistent with [0, pi/2].The switch periods utilance at pi/2 place is the highest, and 0 and π place minimum.Input voltage effective value is higher, and switch periods utilance is lower.When input voltage is 176V, the utilance at pi/2 place is 1.
As can be seen from Fig. 4 and Fig. 7 (b), when adopting switch periods optimal utilization rate to control, if keep the threshold inductance value under original Duty ratio control constant, compared with (a) figure, the switch periods utilance of pi/2 approximate angle reduces, discontinuous current mode degree increases, and the change of 0 angle accessory is contrary.In [0, π], the switch periods utilance at arbitrarily angled place is equal and be less than 1, and therefore, switch periods utilance has the space of improving further.
As can be seen from Fig. 4 and Fig. 7 (c), switch periods optimal utilization rate is adopted to control and under corresponding threshold inductance value, [0, π] in, the switch periods utilance at arbitrarily angled place is equal, and when input voltage is 176V, utilance is 1, when input voltage is 220V and 264V, utilance is close to 1.
4.2 input power factors and current harmonics
The PF that can be obtained under the control of switch periods optimal utilization rate by formula (1), formula (5) and formula (21) is
PF = P in V in _ rms I in _ rms = 1 &pi; &Integral; 0 &pi; v in i in d&omega;t V m 2 1 &pi; &Integral; 0 &pi; i in 2 d&omega;t = 2 &pi; &CenterDot; &Integral; 0 &pi; sin 2 &omega;t ( 1 + &alpha; | sin &omega;t | ) 2 d&omega;t &Integral; 0 &pi; sin 2 &omega;t ( 1 + &alpha; | sin &omega;t | ) 4 d&omega;t - - - ( 23 )
Corresponding PF curve can be made, as shown in Figure 8 by formula (23).As can be seen from the figure, and determine compared with Duty ratio control, switch periods optimal utilization rate controls lower PF value reduction.
Formula (9) and formula (21) are substituted into formula (5) respectively, obtain determine Duty ratio control and switch periods optimal utilization rate control under input current be
i in = 2 P o V m sin &omega;t - - - ( 24 )
i in = &pi; P o V m &Integral; 0 &pi; sin 2 &omega;t ( 1 + &alpha; | sin &omega;t | ) 2 d&omega;t &CenterDot; sin &omega;t ( 1 + &alpha; | sin &omega;t | ) 2 - - - ( 25 )
By α=V m/ nV osubstitute into above formula, two kinds can be made by formula (24), (25) and control input current waveform in lower half power frequency period, as shown in Figure 9.
In order to analyze the harmonic wave of input current, carry out Fourier decomposition to it, the fourier decomposition form of input current is
i in = &Sigma; n = 1 &infin; b n sin n&omega;t ( n = 1,3,5 &CenterDot; &CenterDot; &CenterDot; ) - - - ( 26 )
Wherein
b n = 2 &pi; &Integral; 0 &pi; i in &CenterDot; sin n&omega;td&omega;t - - - ( 27 )
Simultaneous formula (25) and formula (27) can obtain switch periods optimal utilization rate control lower first-harmonic and 3,5,7 subharmonic current values, thus the change curve of the ratio of harmonic wave and first-harmonic and input power can be obtained, distinguish as shown in Figure 10 and Figure 11.
From formula (5), DCM anti exciting converter can realize Active PFC automatically when determining Duty ratio control, and namely 3,5,7 subharmonic content are 0.As can be seen from Figure 10, with determine compared with Duty ratio control, after adopting switch periods optimal utilization rate to control, in input current containing a certain amount of 3,5,7 subharmonic and its amplitude increase with the increase of input voltage, input voltage is when 264V, and 3,5,7 subharmonic amplitudes reach maximum.
According to IEC 61000-3-2, Class D to the regulation of pfc converter input current, 3,5,7 subharmonic amplitudes and the ratio of input power should be less than 3.4 respectively, 1.9,1.0mA/W.As can be seen from Figure 11, the Harmonics of Input under the control of switch periods optimal utilization rate meets standard-required.
The change of 4.3 design of transformer and inductive current effective value and peak value
Former limit inductive current effective value I in power frequency period lp_rmsfor
I Lprms = V m L p f s 1 3 &pi; &CenterDot; &Integral; 0 &pi; sin 2 &omega;t &CenterDot; D y 3 d&omega;t - - - ( 28 )
Secondary inductance current effective value I in power frequency period ls_rmsfor
I Ls _ rms = 1 L p f s n V m 3 3 &pi; V o &Integral; 0 &pi; ( D y sin &omega;t ) 3 d &omega;t - - - ( 29 )
By formula (9), L p1=200 μ H and formula (21), L p2=275 μ H, substitute into formula (28) and formula (29) respectively, can obtain the former limit inductive current effective value I under two kinds of control modes lp1_rmsand I lp2_rmschange curve, as shown in figure 12.Secondary inductance current effective value I ls1_rmsand I ls2_rms, as shown in figure 13.As can be seen from the figure, and determine compared with Duty ratio control, after adopting switch periods optimal utilization rate to control, former secondary inductance current effective value reduces, the current effective value of the main power devices such as switching tube is also corresponding to diminish, and is conducive to the conduction loss reducing converter, improves conversion efficiency.
By formula (9), L p1=200 μ H and formula (21), L p2=275 μ H substitute into formula (3) respectively, and when can to obtain input voltage be 176V, 220V and 265V, the change curve of former limit inductive current peak in half power frequency period under two kinds of control modes, as Figure 14.As can be seen from the figure, when determining Duty ratio control, former limit inductive current peak and input voltage have nothing to do; With determine compared with Duty ratio control, after adopting switch periods optimal utilization rate to control, the maximum of former limit inductive current peak reduces, when input voltage is 176V, former limit inductive current peak (i.e. switching tube peak current) is reduced to 2.52A from 3.47A, and current stress significantly reduces.
Transformer primary side inductance L pnumber of turn N p, winding sectional area S 1, secondary inductance L snumber of turn N s, winding sectional area S 2, magnetic core Packing coefficient K u, magnetic core air gap δ is respectively
N p = L p I Lp _ pk _ max &Delta;B A e - - - ( 30 ) , S 1 = I Lp _ rms _ max J - - - ( 31 ) , N s = N p n - - - ( 32 )
S 2 = I Ls _ rms _ max J - - - ( 33 ) , K &mu; = N p S 1 + N s S 2 A w - - - ( 34 ) , &delta; = &mu; 0 N p 2 A e L p - - - ( 35 )
Wherein I lp_pk_maxfor former limit inductive current peak-peak, Δ B is magnetic flux density, A efor magnetic core effective area, I lp_rms_maxfor the maximum effective value of former limit inductive current, I ls_rms_maxfor the maximum effective value of secondary inductance electric current, J is current density, A wfor magnetic core window area, μ 0for magnetic permeability.
Formula (30), (31), (32) and (33) are substituted into formula (34) and can obtain
K &mu; = L p I Lp _ pk _ max &Delta;B A w A e J ( I Lp _ rms _ max + I Ls _ rms _ max n ) - - - ( 36 )
Formula (30) is substituted into formula (35) can obtain
&delta; = &mu; 0 L p I Lppk max 2 &Delta; B 2 A e - - - ( 37 )
By L p1=200 μ H, I lp_pk_max=3.47A, I lp_rms_max=0.75A, I ls_rms_max=4.43A and L p2=275 μ H, I lp_pk_max=2.52A, I lp_rms_max=0.71A, I ls_rms_max=3.89A substitutes into formula (36) and (37) respectively, can find out, after adopting switch periods optimal utilization rate to control, and the Packing coefficient K of magnetic core usubstantially constant with air gap delta, can use the magnetic core identical with determining Duty ratio control, volume of transformer and weight are substantially constant.Its reason is, although inductance value increases, its current peak and effective value reduce.
The reduction of 4.4 output voltage ripples
By formula (1), formula (24) and formula (25) can obtain converter determine Duty ratio control and switch periods optimal utilization rate control under Instantaneous input power be respectively
p in1=v ini in=2P osin 2ωt 38(a)
p in 2 = v in i in = &pi; P o &Integral; 0 &pi; sin 2 &omega;t ( 1 + &alpha; | sin &omega;t | ) 2 d&omega;t &CenterDot; sin 2 &omega;t ( 1 + &alpha; | sin &omega;t | ) 2 - - - ( 38 ( b ) )
Thus Instantaneous input power perunit value (fiducial value is power output) is respectively
p in 1 * = v in i in P o = 2 sin 2 &omega;t - - - ( 39 ( a ) )
p in 2 * = v in i in P o = &pi; &Integral; 0 &pi; sin 2 &omega;t ( 1 + &alpha; | sin &omega;t | ) 2 d&omega;t &CenterDot; sin 2 &omega;t ( 1 + &alpha; | sin &omega;t ) 2 - - - ( 39 ( b ) )
When by formula (39), can to make input voltage be 176V, 220V and 264V, the change curve of Instantaneous input power perunit value in half power frequency period under two kinds of control modes, as shown in figure 15.When time, storage capacitor C ocharging; When time, C oelectric discharge.Suppose from ω t=0, determine Duty ratio control and switch periods optimal utilization rate control under the waveform time shaft coordinate corresponding with first intersection point of 1 be respectively ω t 1with ω t 2.
As seen from Figure 15, in half power frequency period [0, π], when Duty ratio control is determined in employing, input power perunit value and 1 has and only has 2 intersection points, first intersection point ω t 1=π/4 and not changing with the change of input voltage, therefore, the area surrounded with 1 is constant, and output voltage ripple is steady state value in whole input voltage range.When adopting switch periods optimal utilization rate to control, input power perunit value and 1 has and only has 2 intersection points, and input voltage is higher, first intersection point ω t 2the closer to 0, the area surrounded with 1 is less, and corresponding output voltage ripple is less.
Storage capacitor C othe ceiling capacity perunit value (fiducial value is the output energy in half power frequency period) stored in half power frequency period is respectively
&Delta; E 1 * = 2 &Integral; 0 &omega; t 1 ( 1 - p in 1 * ) d&omega;t / &pi; - - - ( 40 ( a ) )
&Delta; E 2 * = 2 &Integral; 0 &omega; t 1 ( 1 - p in 2 * ) d&omega;t / &pi; - - - ( 40 ( b ) )
According to the computing formula of capacitance energy storage, this ceiling capacity perunit value can be expressed as again
&Delta; E 1 * = 1 2 C o ( V o + &Delta; V o 1 2 ) 2 - 1 2 C o ( V o - &Delta; V o 1 2 ) 2 P o T line / 2 = 2 C o V o &Delta; V o 1 P o T line - - - ( 41 ( a ) )
&Delta; E 2 * = 1 2 C o ( V o + &Delta; V o 2 2 ) 2 - 1 2 C o ( V o - &Delta; V o 2 2 ) 2 P o T line / 2 = 2 C o V o &Delta; V o 2 P o T line - - - ( 41 ( b ) )
Wherein Δ V o_1with Δ V o_2it is the output voltage ripple value under two kinds of control modes.
Can be obtained by formula (40-41)
&Delta; V o 1 = 2 P o &Integral; 0 &omega; t 1 ( 1 - p in 1 * ) d&omega;t / &omega; C o V o - - - ( 42 ( a ) )
&Delta; V o 2 = 2 P o &Integral; 0 &omega; t 2 ( 1 - p in 2 * ) d&omega;t / &omega; C o V o - - - ( 42 ( b ) )
Figure 16 can be made by formula (42), can find out, when input voltage changes between 176-264VAC, the output voltage ripple perseverance of determining under Duty ratio control is 2.41V, and the output voltage ripple under switch periods optimal utilization rate controls is reduced to 1.25V gradually from 1.44V.With determine compared with Duty ratio control, the output voltage ripple under switch periods optimal utilization rate controls significantly reduces.In other words, if keep the maximum ripple of output voltage constant, storage capacitor value can be reduced to original 51.8%.
The DCM flyback pfc converter of the efficient low output voltage ripple of 5 the present invention
In conjunction with Figure 17, input voltage v gthrough the first resistance R 1with the second resistance R 2dividing potential drop obtains v a=k vgv m| sin ω t|, k here vgdividing potential drop coefficient, k vg=R 2/ (R 1+ R 2).Output voltage V othrough the 5th resistance R 5with the 6th R 6dividing potential drop is again through the 3rd resistance R 3, the 4th resistance R 4, the 3rd operational amplification circuit A 3the amplifier of composition obtains v b=k vgnV o, wherein R 1/ R 2=R 5/ R 6, R 4/ R 3=n-1.V aand v baccess add circuit, wherein R 7=R 8=R 9=R 11=2R 10, then export as v c=k vg(nV o+ V m| sin ω t|), output voltage V othrough the 12 resistance R 12with the 13 resistance R 13with given voltage V after dividing potential drop ogcompare, then via the 14 resistance R 14with the first electric capacity C 1the regulating error device of composition obtains error signal v eA, V here og=5.1V, R 12=3.7R 13.V b, v cwith v eAaccess multiplier, it exports v p=v eAv b/ v c=v eA/ [1+V m| sin ω t|/nV o], by v p(amplitude is V with sawtooth waveforms ramp) hand over the duty ratio of cutting and can obtain such as formula Changing Pattern (21) Suo Shi.Wherein v a, v b, v c, v pbe respectively the voltage output value of the first dividing potential drop follow circuit 3, second dividing potential drop amplifying circuit 4, add circuit 5, multiplier 6.Physical circuit is as follows:
The DCM flyback pfc converter of efficient low output voltage ripple of the present invention, comprise main power circuit 1 and control circuit, described main power circuit comprises input voltage source v in, electromagnetic interface filter, diode rectifier circuit RB, transformer T 1, switching tube Q b, diode D b, filter capacitor C owith load R ld, wherein input voltage source v inbe connected with the input port of electromagnetic interface filter, the output port of electromagnetic interface filter is connected with the input port of diode rectifier circuit RB, and the output negative pole of diode rectifier circuit RB is reference potential zero point, the output cathode of diode rectifier circuit RB and transformer T 1winding N pdifferent name end connect, transformer T 1winding N psame Name of Ends access switching tube Q bdrain electrode, switching tube Q bsource electrode be connected zero point with reference potential, transformer T 1winding N ssame Name of Ends and diode D banode connect, diode D bnegative electrode respectively with filter capacitor C oone end and load R ldone end connect, filter capacitor C othe other end and load R ldthe other end all connect reference potential zero point, load R ldthe voltage at two ends is output voltage V o;
Described control circuit employing change in duty cycle rule is output signal driving switch pipe Q b, comprise sawtooth waveforms and compare and switch tube driving circuit 2, first dividing potential drop follow circuit 3, second dividing potential drop amplifying circuit 4, add circuit 5, multiplier 6, output voltage feedback circuit 7; Wherein sawtooth waveforms compares and the output of switch tube driving circuit 2 and switching tube Q bgate pole connect; The input of the first dividing potential drop follow circuit 3 and input voltage sampled point V gnamely the output cathode of diode rectifier circuit RB connects, and the output terminals A of the first dividing potential drop follow circuit 3 is connected with an input of add circuit 5; The input of the second dividing potential drop amplifying circuit 4 connects the output voltage V of main power circuit 1 opositive pole, the output B of the second dividing potential drop amplifying circuit 4 is connected with another input of add circuit 5 and the second input of multiplier 6 respectively; The input of add circuit 5 is connected with the output terminals A of the first dividing potential drop follow circuit 3 and the output B of the second dividing potential drop amplifying circuit 4 respectively, and the output C of add circuit 5 is connected with the 3rd input of multiplier 6; The input of output voltage feedback circuit 7 connects the output voltage V of main power circuit 1 opositive pole, the output of output voltage feedback circuit 7 is connected with the first input end of multiplier 6; The output P of multiplier 6 compares with sawtooth waveforms and the input of switch tube driving circuit 2 is connected.
Described sawtooth waveforms compares and switch tube driving circuit 2 comprises rest-set flip-flop, driving, saw-toothed wave generator, the first operational amplifier A 1, clock; R end and first operational amplifier A of rest-set flip-flop 1output connect, the Q of rest-set flip-flop end is connected with the input of driving, and the input of saw-toothed wave generator is connected with one end of clock, the output of saw-toothed wave generator and the first operational amplifier A 1positive input connect, one end of clock is held with the S of rest-set flip-flop and is connected, and the other end of clock is connected with the input of saw-toothed wave generator.
The first described dividing potential drop follow circuit 3 comprises the second operational amplifier A 2, the first resistance R 1, the second resistance R 2; Wherein the first resistance R 1one end and input voltage sampled point V gnamely the output cathode of diode rectifier circuit RB connects, the first resistance R 1the other end and the second resistance R 2one end connects, and the first resistance R 1with the second resistance R 2common port access the second operational amplifier A 2input in the same way, the second resistance R 2the other end be connected zero point with reference potential, the first operational amplifier A 1reverse input end be directly connected with output terminals A, form in-phase voltage follower.
Described second dividing potential drop amplifying circuit 4 comprises the 3rd resistance R 3, the 4th resistance R 4, the 5th resistance R 5, the 6th resistance R 6, the 3rd operational amplifier A 3; Wherein the 3rd resistance R 3termination reference potential zero point, the 3rd resistance R 3the other end and the 4th resistance R 4one end connect and common port access the 3rd operational amplifier A 3reverse input end, the 4th resistance R 4the other end and the 3rd operational amplifier A 3output B connect, the 5th resistance R 5one end and the output voltage V of main power circuit (1) opositive pole connects, the 5th resistance R 5the other end and the 6th resistance R 6one end connect and common port accesses four-operational amplifier A 4input in the same way.
Described add circuit 5 comprises the 7th resistance R 7, the 8th resistance R 8, the 9th resistance R 9, the tenth resistance R 10, the 11 resistance R 11, four-operational amplifier A 4; Wherein the 7th resistance R 7one end is connected with the output terminals A of the first dividing potential drop follow circuit (3), the other end accesses the 5th operational amplifier A 4input in the same way, the 8th resistance R 8one end is connected with the output B of the second dividing potential drop amplifying circuit (4), the other end accesses the 5th operational amplifier A 4input in the same way, the 9th resistance R 9one end and four-operational amplifier A 4input in the same way connect, other end access reference potential zero point, the tenth resistance R 10four-operational amplifier A is accessed in one end 4reverse input end, other end access reference potential zero point, the 11 resistance R 11access four-operational amplifier A 4reverse input end and output C between.
Described output voltage feedback circuit 7 comprises the 12 resistance R 12, the 13 resistance R 13, the 14 resistance R 14, the first electric capacity C 1, the 5th operational amplifier A 5; Wherein 12 resistance R 12one end and the output voltage V of main power circuit (1) opositive pole connect, the other end connect the 13 resistance R 13one end, and the 12 resistance R 12with the 13 resistance R 13common port access the 5th operational amplifier A 5inverting input, the 13 resistance R 13the other end connect reference potential zero point, the 14 resistance R 14with the first electric capacity C 1access the 5th operational amplifier A after series connection 5inverting input and output between, the 5th operational amplifier A 5in-phase input end and input voltage reference point V ogconnect.
In sum, the DCM flyback pfc converter of efficient low output voltage ripple of the present invention, switch periods optimal utilization rate is adopted to control, under the prerequisite meeting IEC61000-3-2Class D standard, threshold inductance value both can have been made to increase, improve conversion efficiency, turn reduce output voltage ripple or export storage capacitor.

Claims (6)

1. a DCM flyback pfc converter for efficient low output voltage ripple, is characterized in that, comprises main power circuit (1) and control circuit, and described main power circuit (1) comprises input voltage source v in, electromagnetic interface filter, diode rectifier circuit RB, transformer T 1, switching tube Q b, diode D b, filter capacitor C owith load R ld, wherein input voltage source v inbe connected with the input port of electromagnetic interface filter, the output port of electromagnetic interface filter is connected with the input port of diode rectifier circuit RB, and the output negative pole of diode rectifier circuit RB is reference potential zero point, the output cathode of diode rectifier circuit RB and transformer T 1winding N pdifferent name end connect, transformer T 1winding N psame Name of Ends access switching tube Q bdrain electrode, switching tube Q bsource electrode be connected zero point with reference potential, transformer T 1winding N ssame Name of Ends and diode D banode connect, diode D bnegative electrode respectively with filter capacitor C oone end and load R ldone end connect, filter capacitor C othe other end and load R ldthe other end all connect reference potential zero point, load R ldthe voltage at two ends is output voltage V o;
Described control circuit comprises sawtooth waveforms and compares and switch tube driving circuit (2), the first dividing potential drop follow circuit (3), the second dividing potential drop amplifying circuit (4), add circuit (5), multiplier (6), output voltage feedback circuit (7); Wherein sawtooth waveforms compares and the output of switch tube driving circuit (2) and switching tube Q bgate pole connect; The input of the first dividing potential drop follow circuit (3) and input voltage sampled point V gnamely the output cathode of diode rectifier circuit RB connects, and the output terminals A of the first dividing potential drop follow circuit (3) is connected with an input of add circuit (5); The input of the second dividing potential drop amplifying circuit (4) connects the output voltage V of main power circuit (1) opositive pole, the output B of the second dividing potential drop amplifying circuit (4) is connected with another input of add circuit (5) and the second input of multiplier (6) respectively; The input of add circuit (5) is connected with the output terminals A of the first dividing potential drop follow circuit (3) and the output B of the second dividing potential drop amplifying circuit (4) respectively, and the output C of add circuit (5) is connected with the 3rd input of multiplier (6); The input of output voltage feedback circuit (7) connects the output voltage V of main power circuit (1) opositive pole, the output of output voltage feedback circuit (7) is connected with the first input end of multiplier (6); The output P of multiplier (6) compares with sawtooth waveforms and the input of switch tube driving circuit (2) is connected.
2. the DCM flyback pfc converter of efficient low output voltage ripple according to claim 1, it is characterized in that, described sawtooth waveforms compares and switch tube driving circuit (2) comprises rest-set flip-flop, driving, saw-toothed wave generator, the first operational amplifier A 1, clock; R end and first operational amplifier A of rest-set flip-flop 1output connect, the Q of rest-set flip-flop end is connected with the input of driving, and the input of saw-toothed wave generator is connected with one end of clock, the output of saw-toothed wave generator and the first operational amplifier A 1positive input connect, one end of clock is held with the S of rest-set flip-flop and is connected, and the other end of clock is connected with the input of saw-toothed wave generator.
3. the DCM flyback pfc converter of efficient low output voltage ripple according to claim 1, is characterized in that, the first described dividing potential drop follow circuit (3) comprises the second operational amplifier A 2, the first resistance R 1, the second resistance R 2; Wherein the first resistance R 1one end and input voltage sampled point V gnamely the output cathode of diode rectifier circuit RB connects, the first resistance R 1the other end and the second resistance R 2one end connect, and the first resistance R 1with the second resistance R 2common port access the second operational amplifier A 2input in the same way, the second resistance R 2the other end be connected zero point with reference potential, the first operational amplifier A 1reverse input end be directly connected with output terminals A, form in-phase voltage follower.
4. the DCM flyback pfc converter of efficient low output voltage ripple according to claim 1, is characterized in that, described second dividing potential drop amplifying circuit (4) comprises the 3rd resistance R 3, the 4th resistance R 4, the 5th resistance R 5, the 6th resistance R 6, the 3rd operational amplifier A 3; Wherein the 3rd resistance R 3termination reference potential zero point, the 3rd resistance R 3the other end and the 4th resistance R 4one end connect and common port access the 3rd operational amplifier A 3reverse input end, the 4th resistance R 4the other end and the 3rd operational amplifier A 3output B connect, the 5th resistance R 5one end and the output voltage V of main power circuit (1) opositive pole connects, the 5th resistance R 5the other end and the 6th resistance R 6one end connect and common port accesses four-operational amplifier A 4input in the same way.
5. the DCM flyback pfc converter of efficient low output voltage ripple according to claim 1, is characterized in that, described add circuit (5) comprises the 7th resistance R 7, the 8th resistance R 8, the 9th resistance R 9, the tenth resistance R 10, the 11 resistance R 11, four-operational amplifier A 4; Wherein the 7th resistance R 7one end is connected with the output terminals A of the first dividing potential drop follow circuit (3), the other end accesses the 5th operational amplifier A 4input in the same way, the 8th resistance R 8one end is connected with the output B of the second dividing potential drop amplifying circuit (4), the other end accesses four-operational amplifier A 4input in the same way, the 9th resistance R 9one end and four-operational amplifier A 4input in the same way connect, other end access reference potential zero point, the tenth resistance R 10four-operational amplifier A is accessed in one end 4reverse input end, other end access reference potential zero point, the 11 resistance R 11access four-operational amplifier A 4reverse input end and output C between.
6. the DCM flyback pfc converter of efficient low output voltage ripple according to claim 1, is characterized in that, described output voltage feedback circuit (7) comprises the 12 resistance R 12, the 13 resistance R 13, the 14 resistance R 14, the first electric capacity C 1, the 5th operational amplifier A 5; Wherein 12 resistance R 12one end and the output voltage V of main power circuit (1) opositive pole connect, the other end connect the 13 resistance R 13one end, and the 12 resistance R 12with the 13 resistance R 13common port access the 5th operational amplifier A 5inverting input, the 13 resistance R 13the other end connect reference potential zero point, the 14 resistance R 14with the first electric capacity C 1access the 5th operational amplifier A after series connection 5inverting input and output between, the 5th operational amplifier A 5in-phase input end and input voltage reference point V ogconnect.
CN201510112903.3A 2015-03-13 2015-03-13 DCM flyback PFC convertor capable of efficiently and lowly outputting voltage ripples Pending CN104734488A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201510112903.3A CN104734488A (en) 2015-03-13 2015-03-13 DCM flyback PFC convertor capable of efficiently and lowly outputting voltage ripples

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201510112903.3A CN104734488A (en) 2015-03-13 2015-03-13 DCM flyback PFC convertor capable of efficiently and lowly outputting voltage ripples

Publications (1)

Publication Number Publication Date
CN104734488A true CN104734488A (en) 2015-06-24

Family

ID=53458040

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510112903.3A Pending CN104734488A (en) 2015-03-13 2015-03-13 DCM flyback PFC convertor capable of efficiently and lowly outputting voltage ripples

Country Status (1)

Country Link
CN (1) CN104734488A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105226931A (en) * 2015-09-25 2016-01-06 南京理工大学 Improve the control device of DCM Buck pfc converter PF value
CN108231391A (en) * 2017-05-31 2018-06-29 上海申世电气有限公司 Design method is lost in a kind of core of reactor for rotor-side variable frequency device
CN109314398A (en) * 2016-06-02 2019-02-05 Ntn株式会社 Battery charger

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101562922A (en) * 2009-05-31 2009-10-21 南京航空航天大学 High brightness LED driving power without electrolytic capacitor
CN101764528A (en) * 2010-01-08 2010-06-30 南京航空航天大学 High power factor DCM Boost PFC converter
CN102882378A (en) * 2012-09-25 2013-01-16 西南交通大学 Control method and device for unit power factor flyback converter in critical continuous mode
CN103346669A (en) * 2013-07-18 2013-10-09 南京理工大学 Boost power factor correction (PFC) converter adopting small-capacity long-service-life energy-storage capacitor
CN103414334A (en) * 2013-08-19 2013-11-27 南京理工大学 DCM Boost PFC convertor with long service life and PF as 1

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101562922A (en) * 2009-05-31 2009-10-21 南京航空航天大学 High brightness LED driving power without electrolytic capacitor
CN101764528A (en) * 2010-01-08 2010-06-30 南京航空航天大学 High power factor DCM Boost PFC converter
CN102882378A (en) * 2012-09-25 2013-01-16 西南交通大学 Control method and device for unit power factor flyback converter in critical continuous mode
CN103346669A (en) * 2013-07-18 2013-10-09 南京理工大学 Boost power factor correction (PFC) converter adopting small-capacity long-service-life energy-storage capacitor
CN103414334A (en) * 2013-08-19 2013-11-27 南京理工大学 DCM Boost PFC convertor with long service life and PF as 1

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
阎铁生等: "反激PFC 变换器输出电压纹波分析", 《电力自动化设备》 *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105226931A (en) * 2015-09-25 2016-01-06 南京理工大学 Improve the control device of DCM Buck pfc converter PF value
CN105226931B (en) * 2015-09-25 2017-12-12 南京理工大学 Improve the control device of DCM Buck pfc converter PF values
CN109314398A (en) * 2016-06-02 2019-02-05 Ntn株式会社 Battery charger
CN108231391A (en) * 2017-05-31 2018-06-29 上海申世电气有限公司 Design method is lost in a kind of core of reactor for rotor-side variable frequency device
CN108231391B (en) * 2017-05-31 2019-12-10 上海申世电气有限公司 Reactor iron core loss design method for rotor frequency converter

Similar Documents

Publication Publication Date Title
CN104242692B (en) The CRM Boost pfc converters of optimal frequency excursion
CN101764528B (en) High power factor DCM Boost PFC converter
CN102882378B (en) Control method and device for unit power factor flyback converter in critical continuous mode
CN103414334B (en) PF is the long-life DCM Boost pfc converter of 1
CN104734487A (en) CRM Flyback PFC converter achieving constant switching frequency
CN103813591B (en) The CRM Flyback LED driver of low output current peak-to-average force ratio
CN102377354A (en) Converter
CN106533152A (en) Device and method for improving PF of Boost three-level converter
CN104702131A (en) CRM Buck PFC convertor with optimal frequency variation range
CN105226931B (en) Improve the control device of DCM Buck pfc converter PF values
CN104617761A (en) High-power factor buck type power factor correction converter
CN109149963A (en) The DCM of switch periods optimal utilization rate control is depressured pfc converter
CN104734488A (en) DCM flyback PFC convertor capable of efficiently and lowly outputting voltage ripples
CN107294389A (en) One kind can freely commutate two-way DC/DC converters and its control method
CN109309447B (en) Constant switching frequency controlled CRM buck PFC converter
CN111682768A (en) LCLCL high-order direct current converter based on stacked bridge and control method
CN104883046A (en) High-power factor critical continuous mode buck-boost power factor correction converter
CN104702108A (en) Critical continuous boost converter employing constant-frequency control
CN110829827A (en) CRM boost-buck PFC converter with constant switching frequency
CN104734543A (en) Efficient three-phase single-tube DCM Boost PFC converter
CN104539179A (en) Intermittent boost converter with lowest capacitance ripple current effective value
CN105162316B (en) The CRM Buck pfc converter of High Power Factor
CN203039585U (en) Critical continuous mode unity power factor flyback converter
CN104967323B (en) Low output voltage ripple discontinuous mode flyback power factor correction converter
CN104836461A (en) Intermittent boost converter controlled by switching period optimum utilization rate

Legal Events

Date Code Title Description
PB01 Publication
C06 Publication
SE01 Entry into force of request for substantive examination
C10 Entry into substantive examination
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20150624

WD01 Invention patent application deemed withdrawn after publication