CN104717466B - Based on the fpga hd-sdi video processing board - Google Patents

Based on the fpga hd-sdi video processing board Download PDF

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CN104717466B
CN104717466B CN201510067059.7A CN201510067059A CN104717466B CN 104717466 B CN104717466 B CN 104717466B CN 201510067059 A CN201510067059 A CN 201510067059A CN 104717466 B CN104717466 B CN 104717466B
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module
fpga
sdi
chip
processing board
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CN201510067059.7A
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CN104717466A (en
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周清海
黄芳
陈耀宗
关则昂
张建国
赵新颖
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深圳市振华微电子有限公司
中国振华(集团)科技股份有限公司
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Abstract

本发明涉及种基于FPGA的HD‑SDI视频处理板,包括FPGA芯片,FPGA芯片包括GTX IP硬核、多通道数据采集模块、图像压缩模块、UDP打包模块、以太网控制器、AXI总线,GTX IP硬核接收视频信号并输出至多通道数据采集模块进行解码,再经过图像压缩模块进行压缩处理,通过UDP打包模块进行封装,最后通过以太网控制器输出,从而在FPGA芯片上完成HD‑SDI视频信号的采集、解码、压缩、传输的功能。 The present invention relates to species FPGA-based HD-SDI video processing board, comprising a FPGA chip, FPGA chip comprising GTX IP hard core, multi-channel data acquisition module, an image compression module, UDP module package, Ethernet controller, the AXI bus, GTX IP hard core receives a video signal and outputs the multichannel data acquisition module decoding and then after the image compression module for compression processing, packing module encapsulation over UDP, and finally output through the Ethernet controller, thereby completing the HD-SDI video signal on a FPGA chip acquisition, decoding, compression, transfer function.

Description

一种基于FPGA的HD-SDI视频处理板 FPGA-based HD-SDI video processing board

技术领域 FIELD

[0001 ]本发明涉及视频图像处理领域,更具体地说,涉及一种基于FPGA的HD-SD I视频处理板。 [0001] The present invention relates to video image processing, and more particularly, to a FPGA-based HD-SD I video processing board.

背景技术 Background technique

[0002]随着社会的发展,人们对视频或图像的要求越来越高,如对高分辨的要求、实时性的要求等,要满足这些要求,必须有足够强大的视频信号采集以及前端处理能力的设备,传统的基于DSP或ASIC等视频板,由于在芯片引脚资源及串行处理机制等限制,在采集视频通道数量及数据的处理能力方面都有很大的瓶颈,无法满足这些要求。 [0002] With the development of society, people demand more and more video or images, such as requirements for high-resolution, real-time requirements, etc., to meet these requirements, there must be strong enough video signal acquisition and processing front-end equipment capacity, the conventional DSP or ASIC-based video board and the like, since the restriction pin chip resources and serial processing mechanism, in terms of processing power and the number of channels of video data acquisition has a large bottleneck, can not meet these requirements .

发明内容 SUMMARY

[0003]本发明要解决的技术问题在于,针对现有技术的上述缺陷,提供一种基于FPGA的HD-SDI视频处理板。 [0003] The present invention is to solve the technical problem, for the above-described drawbacks of the prior art, there is provided a FPGA-based HD-SDI video processing board.

[0004]本发明解决其技术问题所采用的技术方案是:构造一种基于FPGA的HD-SDI视频处理板。 [0004] aspect of the present invention to solve the technical problem that is: configuration of FPGA-based HD-SDI video processing board.

[0005] 在本发明所述的基于FPGA的HD-SDI视频处理板,包括FPGA芯片,所述FPGA芯片包括GTX IP硬核、多通道数据采集模块、图像压缩模块、UDP打包模块、以太网控制器、AXI总线, [0005] FPGA-based HD-SDI video processing board according to the present invention, comprising a FPGA chip, FPGA chip comprises GTX IP said hard-core, multi-channel data acquisition module, an image compression module, UDP module package, Ethernet control device, the AXI bus,

[0006] 所述GTX IP硬核,用于接收视频信号并输出; [0006] The hard core GTX IP, for receiving the video signal and outputting;

[0007] 所述多通道数据采集模块,与所述GTX IP硬核及所述AXI总线通信连接,用于接收所述GTX IP硬核输出的所述视频信号并进行解码得到原始视频数据,且将所述原始视频数据输出至所述AXI总线; [0007] The multi-channel data acquisition module, is connected to the hard core and GTX IP communication with the AXI bus, for receiving said video signal output of the hard core GTX IP and decoding to obtain the original video data, and the original video data is output to the AXI bus;

[0008] 所述图像压缩模块,与所述AXI总线通信连接,用于接收所述原始视频数据进行压缩,得到视频压缩码流并输出; [0008] The image compression module connected in communication with the AXI bus, for receiving the raw video data is compressed to obtain compression video stream and outputs the symbol;

[0009] 所述UDP打包模块,与所述图像压缩模块连接,用于接收所述视频压缩码流并进行封装,得到封装视频压缩码流; [0009] The UDP packetization module, connected to the image compression module, for receiving the compressed video stream and packaged to obtain the package compressed video stream;

[0010] 所述以太网控制器,与所述UDP打包模块连接,用于接收所述封装视频压缩码流并输出。 [0010] The Ethernet controller module is connected with the UDP package, the package for receiving the compressed video stream for output.

[0011] 优选地,所述多通道数据采集模块包括SDI解码模块和VDMW模块,所述SDI解码模块与所述VDMW模块通信连接,所述SDI解码模块用于接收所述GTXIP硬核输出的所述视频信号并进行解码得到所述原始视频数据,所述VDMfff吴块用于将所述原始视频数据输出至所述AXI总线。 The [0011] Preferably, the multi-channel data acquisition module comprises a decoding module SDI and VDMW module, the module and the SDI decoder VDMW communication module connected to a SDI decoder means for receiving the output of the hard core GTXIP decoding said video signal and to obtain the original video data, the NG VDMfff block for outputting the original video data to the AXI bus.

[0012] 优选地,所述基于FPGA的HD-SDI视频处理板还包括SDI芯片和以太网芯片,所述SDI芯片与所述FPGA芯片通信连接,用于输出所述视频信号至所述FPGA芯片; [0012] Preferably, the FPGA-based HD-SDI video processing board and further comprising a SDI chip Ethernet chip, the SDI chip in communication with the FPGA chip is connected, for outputting the video signal to the FPGA chip ;

[0013] 所述以太网芯片与所述以太网控制器通信连接,用于接收所述以太网控制器输出的所述封装视频压缩码流并输出至PC机。 [0013] The Ethernet chip Ethernet controller in communication with said connector, the Ethernet controller for receiving the output of the package compressed video stream and outputs it to the PC.

[0014] 优选地,所述GTX IP硬核、所述SDI解码模块、所述VDMW模块相等且至少有8个,且所述GTX IP硬核、所述SDI解码模块、所述VDMW模块--对应。 Equivalent [0014] Preferably, the GTX IP hard core, the SDI decoder module, and the module VDMW of at least 8, and the GTX IP hard core, the SDI decoder module, the module VDMW - correspond.

[0015] 优选地,所述基于FPGA的HD-SDI视频处理板还包括晶体振荡器和BPI模块,所述晶体振荡器与所述FPGA芯片连接,用于输出时钟信号至所述FPGA芯片。 [0015] Preferably, the FPGA-based HD-SDI video processing board further includes a crystal oscillator and BPI module, the crystal oscillator connected to the FPGA chip for outputting a clock signal to the FPGA chip.

[0016] 所述BPI模块与所述FPGA芯片连接,用于存储所述FPGA芯片的配置电路及用于启动所述FPGA芯片初始化的软件文件。 [0016] The BPI FPGA chip module and the connector, for storing the configuration circuit of the FPGA chip and for activating the FPGA chip initialization software files.

[0017] 优选地,所述FPGA芯片还设置有解密模块,用于对所述配置电路中的比特流进行解密。 [0017] Preferably, the FPGA chip is also provided with a decryption module for the configuration of a bit stream decrypting circuit.

[0018] 优选地,所述FPGA芯片还包括微处理器,所述微处理器与所述AXI总线通信连接, 用于获取所述BPI模块中的软件文件并生成软件运行指令,且将所述软件文件及所述软件运行指令输出至所述AXI总线。 [0018] Preferably, the FPGA chip further comprising a microprocessor in communication with the AXI bus connection, for acquiring the software files BPI generation software module and the operation command, and the software and the software file operation command is output to the AXI bus.

[0019] 优选地,所述基于FPGA的HD-SDI视频处理板还包括存储模块,所述FPGA芯片还包括内存控制器, [0019] Preferably, the FPGA-based HD-SDI video processing board further includes a storage module, the FPGA chip further comprises a memory controller,

[0020] 所述内存控制器与所述AXI总线通信连接,用于接收所述原始视频数据并控制所述存储模块写入所述原始视频数据,及获取所述软件文件和所述软件运行指令并输出; [0020] The AXI memory controller connected to said bus in communication with, for receiving the raw video data storage module and controls the writing of the original video data, and access to said software and said software operation command file and output;

[0021] 所述存储模块与所述内存控制器连接,用于写入所述原始视频数据并缓存,以及获取所述内存控制器输出的所述软件文件和所述软件运行指令,并运行所述软件文件,以启动所述FPGA芯片的初始化。 [0021] The storage module is connected to the memory controller for writing data and the original video buffer, and acquires the software file output by the memory controller and the software operating instructions, and run said software file to start the initialization of the FPGA chip.

[0022] 优选地,所述基于FPGA的HD-SDI视频处理板还包括HDMI接口模块,所述HDMI接口模块与所述FPGA芯片连接,用于显示所述原始视频数据, [0022] Preferably, the FPGA-based HD-SDI video processing board further includes a HDMI interface module, the HDMI interface module connected to the FPGA chip, the original video data for displaying,

[0023] 所述FPGA芯片还包括显示控制器,所述显示控制器与所述AXI总线通信连接,用于通过所述AXI总线获取所述存储模块中缓存的所述原始视频数据并输出至所述HDMI接口模块显不。 [0023] The FPGA chip further includes a display controller, the display controller and the communication connection AXI bus, said storage module configured to obtain the raw video data cache via the bus and outputs it to the AXI said HDMI interface module is not significant.

[0024] 优选地,所述基于FPGA的HD-SDI视频处理板还包括JTAG接口模块和电源芯片,所述JTAG接口模块与所述FPGA芯片连接,用于对所述FPGA芯片进行下载调试; [0024] Preferably, the FPGA-based HD-SDI video processing board JTAG interface module further comprises a power supply and a chip, the JTAG interface module connected to the FPGA chip, FPGA chip for downloading the debugging;

[0025] 所述电源芯片分别与所述FPGA芯片、所述SDI芯片、所述存储模块、所述BPI模块连接,用于将输入电压转化成所述FPGA芯片、所述SDI芯片、所述存储模块、所述BPI模块需要的工作电压并输出。 [0025] The power chip of the FPGA chip, respectively, the SDI chip, the memory module, the module is connected BPI, for an input voltage is converted into the FPGA chip, the SDI chip, said memory module, the module needs BPI operating voltage and outputs.

[0026] 实施本发明的基于FPGA的HD-SDI视频处理板,具有以下有益效果:通过FPGA芯片内部的GTX IP模块接收视频信号并输出至多能道数据采集模块,多能道数据采集模块对视频信号进行解码得到原始视频数据通过AXI总线输出至图像压缩模块进行压缩,得到压缩视频压缩码流后通过UDP打包模块进行封装得到封装视频压缩码流,再通过以太网控制器输出,从而在FPGA芯片上完成HD-SDI视频信号的采集、解码、压缩、传输的功能。 [0026] The embodiment of the present invention is based on FPGA HD-SDI video processing board, has the following advantages: receiving a video signal through the internal FPGA chip GTX IP module and outputs the most energy channel data acquisition module, multi-energy channel data acquisition module video signal is decoded to obtain the original video data compressed by the AXI bus output to the image compression module, compressed to obtain the compressed video code stream obtained by encapsulating UDP module package packing the compressed video stream, and then output via the Ethernet controller to the FPGA chip on completion of the acquisition of the HD-SDI video signal, decoding, compression, transfer function.

附图说明 BRIEF DESCRIPTION

[0027]下面将结合附图及实施例对本发明作进一步说明,附图中: [0027] The accompanying drawings and the following embodiments of the present invention is further illustrated drawings in which:

[0028] 图1是本发明基于FPGA的HD-SDI视频处理板的结构示意图。 [0028] FIG. 1 is a schematic structural diagram of FPGA-based HD-SDI video processing board of the present invention.

具体实施方式 Detailed ways

[0029] 如图1所示,图1为本发明的基于FPGA的HD-SDI视频处理板的结构示意图,在本发明的基于FPGA的HD-SDI视频处理板第一实施例中,包括FPGA芯片1,FPGA芯片包括GTX IP硬核101、多通道数据采集模块102、图像压缩模块104、UDP打包模块105、以太网控制器106、 AXI总线103。 [0029] As illustrated, the schematic structure of HD-SDI video processing board based on the FPGA, the FPGA-based HD-SDI video processing board according to the present invention, a first embodiment of the present invention, FIG 1 embodiment, FPGA chip comprising 1, FPGA chip comprising a hard GTX IP core 101, the multi-channel data acquisition module 102, an image compression module 104, UDP packetization module 105, Ethernet controller 106, AXI bus 103. 本实施例中,FPGA芯片1采用的是xilinx的XC7K325T-2FFG900芯片,该芯片具有接近900个引脚及300多万门逻辑资源。 In this embodiment, FPGA chip 1 is used in the XC7K325T-2FFG900 xilinx chip, which has 900 pins, and nearly 3 million gate logic resources.

[0030] 其中,GTX IP硬核101用于接收视频信号并输出。 [0030] wherein, GTX IP hard core 101 for receiving a video signal and outputs. 在本实施例中,GTX IP硬核101用于接收HD-SDI高分辨率视频信号,本实施例中,GTX IP硬核至少有8个。 In the present embodiment, GTX IP hard core 101 for receiving high resolution video signal HD-SDI, in this embodiment, GTX IP hard core at least 8.

[0031] 多通道数据采集模块102与GTX IP硬核101及AXI总线103通信连接,用于接收GTX IP硬核101输出的视频信号并进行解码得到原始视频数据,且将原始视频数据输出至AXIS 线103。 [0031] The multi-channel data acquisition module 101 and 102 connected to the communication bus 103 GTX IP AXI hard core and, for the received video signal GTX IP hard core 101 and outputs decoded original video data, and the original video data is output to the AXIS line 103. 多通道数据采集模块102包括SDI解码模块1021和VDMW模块1022, SDI解码模块1021 与VDMW模块1022通信连接,SDI解码模块1021用于接收GTX IP硬核101输出的视频信号并进行解码得到原始视频数据,VDMW模块用于将原始视频数据输出至AXI总线103。 Multi-channel data acquisition module 102 includes a decoder module 1021 and VDMW SDI module 1022, module 1021 connected to the SDI decoder module 1022 and a communication VDMW, SDI decoder module 1021 for receiving a video signal hard GTX IP core 101 outputs the decoded and the original video data , VDMW means for outputting the original video data to the AXI bus 103. 在本实施例中,SDI解码模块1021、GTX IP硬核101、VDMW模块1022的数量相同,均至少有8个,且GTX IP 硬核101、SDI解码模块1021、VDMff模块1022——对应。 Embodiment, the SDI decoding module 1021, GTX IP hard core 101, VDMW same number of modules 1022, there are at least 8, and a hard core GTX IP 101, SDI decoding module 1021, VDMff 1022-- module corresponding to the present embodiment.

[0032] 图像压缩模块104与AXI总线103通信连接,用于接收所述原始视频数据进行压缩, 得到视频压缩码流并输出。 [0032] The image compression module 104 AXI 103 connected to the communication bus, for receiving the raw video data is compressed to obtain compression video stream and outputs. 在本实施例中,图像压缩模块104可对大尺寸町PEG格式的图像进行压缩。 In the present embodiment, the image compression module 104 may compress the image format large town PEG.

[0033] UDP打包模块105与图像压缩模块104连接,用于接收视频压缩码流并进行封装,得到封装视频压缩码流。 [0033] UDP packetization module 105 connected to the image compression module 104, for receiving a video stream compressed and packaged, the package obtained compressed video stream.

[0034] 以太网控制器106与UDP打包模块105连接,用于接收封装视频压缩码流并输出。 [0034] The Ethernet controller 106 is connected with the UDP packetization module 105, for receiving a compressed video stream encapsulation and outputs.

[0035] 本实施例中,进一步地,基于FPGA的HD-SDI视频处理板还包括SDI芯片3,SDI芯片3 与FPGA芯片1通信连接,用于输出视频信号至FPGA芯片1。 [0035] In this embodiment, further, the HD-SDI FPGA-based video processing board further including SDI chip 3, the chip 3 is connected to the communication SDI FPGA chip 1 and for outputting a video signal to the FPGA chip. SDI芯片3可对视频信号进行equalize处理,通过equalize处理可调整不同频段视频信号的增益值。 SDI chip 3 may be processed to equalize the video signal, adjust the gain by different frequency bands of the video signal processing equalize. 本实施例中,SDI芯片3采用的型号是LMH0387SL,有8个,与上述GTX IP硬核101的数量相等,该种型号的SDI芯片3可支持双向最高3G-SDI视频信号处理。 In this embodiment, SDI chip 3 uses the model is LMH0387SL, has eight, equal to the number of the above-described hard core GTX IP 101, which models the SDI chip 3 may support two-way up 3G-SDI video signal processing. 利用上述FPGA芯片1内部集成的GTX IP硬核101 与SDI芯片3相连来组成8通道的HD-SDI采集接口。 1 using the FPGA chip integrated within GTX IP SDI chip 101 and the hard core 3 is connected to the channel 8 consisting of HD-SDI acquisition interface.

[0036] 基于FPGA的HD-SDI视频处理板还包括以太网芯片4,以太网芯片4与FPGA芯片1中的以太网控制器106通信连接,用于接收以太网控制器106输出的封装视频压缩码流并输出至PC机。 [0036] FPGA-based HD-SDI video processing board further includes a communication 4, the FPGA chip 4 Ethernet Ethernet chip 1 chip Ethernet controller 106 is connected to encapsulate video output controller 106 receives the compressed Ethernet stream and outputs it to the PC. 该PC机可以是笔记本电脑、台式电脑、平板电脑等。 This can be a PC, laptop computers, desktop computers, tablets and so on. 本实施例中以太网芯片4采用的是96PIN的M88E1111-96-BCC芯片,支持每秒千兆或者百兆的传输速度,通过16位并行数据接口与FPGA芯片1连接。 The present embodiment uses the Ethernet chip 4 of M88E1111-96-BCC 96PIN chip support gigabit per second or Mbps transfer rate, the data interface FPGA chip are connected by a 16-bit parallel.

[0037] 基于FPGA的HD-SDI视频处理板还包括晶体振荡器5,晶体振荡器5与FPGA芯片1连接,用于输出时钟信号至FPGA芯片1。 [0037] FPGA-based HD-SDI video processing board 5 further comprises a crystal oscillator, the crystal oscillator connected to a FPGA chip 5 and for outputting a clock signal to a FPGA chip. 本实施例中,晶体振荡器5采用的是100MHz单端有源晶振,工作电压为3.3V。 In this embodiment, the crystal oscillator 5 is used in a single-ended 100MHz active crystal, the operating voltage is 3.3V.

[0038] 基于FPGA的HD-SDI视频处理板还包括BPI模块6,BPI模块6与FPGA芯片1连接,用于存储FPGA芯片1的配置电路及用于启动FPGA芯片1初始化的软件文件。 [0038] BPI module 6, module 61 connected to the BPI, for storing FPGA chip 1 and the circuit configuration for actuating a FPGA chip initialization software files and FPGA-based FPGA chip HD-SDI video processing board further comprises. 在本实施例中,BPI模块采用的是镁光的PC28F00AG18FE,16位位宽,容量128MB,当基于FPGA的HD-SDI视频处理板上电时,FPGA芯片1自动从该BPI模块6加载软件文件启动。 In the present embodiment, the module uses a BPI Micron PC28F00AG18FE, 16-bit wide, the capacity of 128MB, when the HD-SDI video processing circuit board based on FPGA, an FPGA chip from the autostart module 6 loading the software files BPI .

[0039] FPGA芯片1还设置有解密模块11 〇,解密模块11 〇用于对BP I模块中存储的配置电路中的比特流进行解密。 [0039] FPGA chip 1 is further provided with a square decryption module 11, the decryption module 11 billion for BP I bitstream configuration circuit module decrypts stored. 当FPGA芯片1中设置了解密模块110之后,比特流在传输至FPGA芯片1 中时被加密可防止被拷贝。 After the FPGA chip 1 is provided with a decryption module 110, the transmission bit stream to the FPGA chip 1 is prevented from being copied encrypted. 在本实施例中,解密模块110具有AES解密功能。 In the present embodiment, the decryption module 110 has AES decryption.

[0040] FPGA芯片1还包括微处理器107,微处理器107与AXI总线103通信连接,用于获取BPI模块6中的软件文件并生成软件运行指令,且将软件文件及软件运行指令输出至AXIS 线103。 [0040] FPGA chip 1 further comprises a microprocessor 107, microprocessor 107 and communication connection AXI bus 103 for acquiring module 6 BPI software file and generates run software instructions, and the document output software instructions to run the software and AXIS line 103.

[0041] 基于FPGA的HD-SDI视频处理板还包括存储模块7^?04芯片1还包括内存控制器108。 [0041] FPGA-based HD-SDI video processing board further includes a storage module 7 ^? 1 04 further comprises a memory controller chip 108. 内存控制器108与AH总线103通信连接,用于接收原始视频数据并控制存储模块7写入原始视频数据,及获取软件文件和软件运行指令并输出。 The memory controller 108 is connected with a communication bus AH 103 for receiving the original video data and control module 7 stores the original video data is written, and access files and software to run software instructions and outputs. 存储模块7与内存控制器1〇8连接, 用于写入原始视频数据并缓存,以及获取内存控制器108输出的软件文件和软件运行指令, 并运行软件文件,当存储模块7运行该软件文件时,输出初始化控制指令至FPGA芯片1,FPGA 芯片进行初始化操作。 A storage module 7 and the memory controller 1〇8 connection, and for writing the original video data cache, and memory controller 108 takes the output files and software instructions to run the software, and run the software file, the memory module when running the software file 7 when outputting a control command to initialize. 1 FPGA chip, FPGA chip initialization. 本实施例中,存储模块7采用的是镁光MT8KTF25664HZ-1G6M1内存条, 该内存条具有1GB容量,内存位宽为64位、频率1600MHz,最大带宽达到12.8GB/s。 In this embodiment, the memory module 7 uses a Micron MT8KTF25664HZ-1G6M1 memory, the memory having a capacity of 1GB, the memory bit width is 64 bits, the frequency of 1600MHz, the maximum bandwidth of 12.8GB / s.

[0042] 在本实施例中,进一步地,基于FPGA的HD-SDI视频处理板还包括HDMI接口模块8, HDMI接口模块8与FPGA芯片1连接,用于显示原始视频数据。 [0042] In the present embodiment, further, the FPGA-based HD-SDI video processing board further includes a HDMI interface modules 8, 8 is connected to the HDMI interface module FPGA chip 1, for displaying the original video data. FPGA芯片1还包括显示控制器109, 显示控制器109与AXI总线103通信连接,用于通过AXI总线103获取存储模块7中缓存的原始视频数据并输出至HDMI接口模块8显示。 FPGA chip 1 further includes a display controller 109, a display controller 109 and the communication AXI bus 103 connected to the storage module 103 obtains via the AXI bus buffer 7 and outputs the original video data to the display 8 HDMI interface module. 通过HDMI接口模块8将原始视频数据显示,可方便视频信号采集、处理开发的调试。 8 through the HDMI interface module will display the original video data, the video signal can be easily acquired, debugging process development.

[0043] 基于FPGA的HD-SDI视频处理板还设置有JTAG接口模块2,JTAG接口模块2与FPGA芯片1连接,用于对FPGA芯片1进行下载调试。 [0043] Based on HD-SDI video processing board is further provided with a FPGA JTAG interface module 2, module 2 and the JTAG interface FPGA chip connection, for an FPGA chip debug download.

[0044] 基于FPGA的m)-SDI视频处理板还包括电源芯片(图中未示出),电源芯片分别与FPGA芯片1、SDI芯片3、存储模块7、BPI模块6连接,用于将输入电压转化成FPGA芯片1、SDI芯片3、存储模块7、BPI模块6需要的工作电压并输出至FPGA芯片1、SDI芯片3、存储模块7、BPI 模块6,为FPGA芯片1、SDI芯片3、存储模块7、BPI模块6提供工作电压。 [0044] Based on the FPGA m) -SDI video processing board further includes a power chip (not shown), respectively, the power chip 1, SDI chip 3, a storage module 7, BPI module 6 is connected to the input of the FPGA chip voltage is converted into the FPGA chip 1, SDI chip 3, a storage module 7, BPI module 6 the required operating voltage and outputs to the FPGA chip 1, SDI chip 3, a storage module 7, BPI module 6, the FPGA chip 1, SDI chip 3, a storage module 7, BPI module 6 provides the operating voltage.

[0045] 综上所述,FPGA芯片1通过内部的GTX IP硬核101接收SDI芯片输出的视频信号后又输出至多通道数据采集模块102,多通道数据采集模块102将视频信号进行解码得到原始视频数据后输出至MI总线103,AXI总线103将原始视频数据输出至图像压缩模块104,图像压缩模块104接收MI总线103输出的原始视频数据后进行压缩,得到视频压缩码流并输出至UDP打包模块105进行封装,得到封装视频压缩码流输出至以太网控制器106,以太网控制器106将封装视频压缩码流通过以太网芯片4输出至PC机上。 [0045] In summary, FPGA chip and then outputs a video signal to the multichannel data acquisition module receives the SDI chip output through the inside of the hard core 101 GTX IP 102, multi-channel data acquisition module 102 decodes the video signal to obtain the original video after data is output to MI bus 103, the AXI bus 103 to the original video data output to the image compression module 104, an image compression compression module 104 of the original video data reception output MI bus 103 is obtained after a video compressed stream and output to the UDP package module package 105, the package obtained compressed video stream output 106 to the Ethernet controller, the Ethernet controller 106 encapsulates the compressed video stream output via Ethernet chip 4 to the PC. 另一方面,FPFA芯片1内部的微处理器107获取来自BPI模块的软件文件并在存储模块7中运行,启动FPGA芯片完成初始化操作。 On the other hand, FPFA inside the chip 1 from the microprocessor 107 acquires the file BPI software module running in the storage module and 7, the FPGA chip startup initialization operation is completed. 利用FPGA芯片1内部的丰富逻辑资源可设计GTX IP硬核101、多能道数据采集模块102、AX I总线103、图像压缩模块104、UDP打包模块105、以太网控制器106来构建视频信号处理的芯片级系统平台,完成多通道HD-SDI视频信号的采集、处理、压缩、传输等功能。 1 using the FPGA chip internal logic resources may be rich in design GTX IP hard core 101, multi-channel data acquisition module can 102, AX I bus 103, an image compression module 104, UDP packetization module 105, the Ethernet controller 106 to construct a video signal processing the system on a chip platform to complete the multi-channel acquisition HD-SDI video signal processing, compression, transmission and other functions.

[0046]可以理解的,以上实施例仅表达了本发明的优选实施方式,其描述较为具体和详细,但并不能因此而理解为对本发明专利范围的限制;应当指出的是,对于本领域的普通技术人员来说,在不脱离本发明构思的前提下,可以对上述技术特点进行自由组合,还可以做出若千变形和改进,这些都属于本发明的保护范围;因此,凡跟本发明权利要求范围所做的等同变换与修饰,均应属于本发明权利要求的涵盖范围。 [0046] It will be appreciated, the above embodiments are only expressed the preferred embodiments of the present invention, which is described more specifically and in detail, it can not therefore be understood as limiting the scope of the present invention; to be noted that, for those skilled in the of ordinary skill in the art, without departing from the spirit of the present invention, the premise of the above-described technical features may be freely combined, may be made if one thousand variations and modifications which fall within the protection scope of the present invention; therefore, with the present invention, where transformation and equivalent scope of the claims modifications may be made while belonging to the scope of the claims of the invention.

Claims (9)

1. 一种基于FPGA的P1D-SDI视频处理板,包括FPGA芯片,其特征在于,所述FPGA芯片包括GTX IP硬核、多通道数据采集模块、图像压缩模块、UDP打包模块、以太网控制器、AXI总线, 所述GTX IP硬核,用于接收视频信号并输出; 所述多通道数据采集模块,与所述61^ IP硬核及所述AXI总线通信连接,用于接收所述GTX IP硬核输出的所述视频信号并进行解码得到原始视频数据,且将所述原始视频数据输出至所述AXI总线; 所述图像压缩模块,与所述AXI总线通信连接,用于接收所述原始视频数据进行压缩, 得到视频压缩码流并输出; 所述UDP打包模块,与所述图像压缩模块连接,用于接收所述视频压缩码流并进行封装,得到封装视频压缩码流; 所述以太网控制器,与所述UDP打包模块连接,用于接收所述封装视频压缩码流并输出所述多通道数据采集模块包括SDI解码模块和VDMW An FPGA-based P1D-SDI video processing board, comprising a FPGA chip, wherein said chip comprises GTX IP FPGA hard-core, multi-channel data acquisition module, an image compression module, UDP module package, Ethernet controller , AXI bus, the GTX IP hard core for receiving a video signal and outputting; the multi-channel data acquisition module, ^ IP hard core and the communication connection with the AXI bus 61, for receiving the GTX IP the video signal output from the hard core and decoded original video data, and output the raw video data to the AXI bus; receiving the image compression module connected in communication with the AXI bus for the original video data is compressed to obtain compression video stream and outputs the symbol; the UDP packetization module, connected to the image compression module, for receiving the compressed video stream and packaged to obtain the package compressed video stream; said ether network controller, connected to the UDP packetization module for receiving the compressed video stream encapsulation and output the multi-channel data acquisition module comprises a decoding module SDI and VDMW 块;所述GTX IP硬核、所述SDI解码模块、所述VDMff模块数量相等,均至少有8个;且所述GTX IP硬核、所述SDI解码模块、所述VDMW模块一'一对应。 Block; the GTX IP hard core, the SDI decoder module, the number of modules equal VDMff are at least eight; GTX IP and the hard core, the SDI decoder module, the module VDMW a 'corresponding to a .
2. 根据权利要求1所述的基于FPGA的HD-SDI视频处理板,其特征在于,所述SDI解码模块与所述VDMW模块通信连接,所述SDI解码模块用于接收所述GTX IP硬核输出的所述视频信号并进行解码得到所述原始视频数据,所述VDMW模块用于将所述原始视频数据输出至所述AXI总线。 2. The HD-SDI FPGA-based video processing board according to claim 1, wherein the SDI decoder module VDMW communicating with the connection, the SDI decoder means for receiving said hard core GTX IP the decoded output of the video signal and to obtain the original video data, the VDMW means for outputting the original video data to the AXI bus.
3. 根据权利要求1所述的基于FPGA的HD-SDI视频处理板,其特征在于,所述基于FPGA的HD-SDI视频处理板还包括SDI芯片和以太网芯片,所述SDI芯片与所述FPGA芯片通信连接, 用于输出所述视频信号至所述FPGA芯片; 所述以太网芯片与所述以太网控制器通信连接,用于接收所述以太网控制器输出的所述封装视频压缩码流并输出至PC机。 3. The FPGA-based HD-SDI video processing board according to claim 1, wherein said FPGA-based HD-SDI video processing board and further comprising a SDI chip Ethernet chip, the chip and the SDI FPGA chip communication connection, for outputting the video signal to the FPGA chip; chip connected to the Ethernet and the Ethernet controller in communication with the Ethernet controller for receiving the output of the video compression code package stream and output to a PC.
4. 根据权利要求3所述的基于FPGA的m)-SDI视频处理板,其特征在于,所述基于FPGA的HD-SDI视频处理板还包括晶体振荡器和BPI模块,所述晶体振荡器与所述FPGA芯片连接,用于输出时钟信号至所述FPGA芯片; 所述BPI模块与所述FPGA芯片连接,用于存储所述FPGA芯片的配置电路及用于启动所述FPGA芯片初始化的软件文件。 FPGA-based claimed m claim 3) -SDI video processing board, characterized in that said FPGA-based HD-SDI video processing board further includes a crystal oscillator and BPI module, the crystal oscillator the FPGA chip is connected, for outputting a clock signal to the FPGA chip; BPI the FPGA chip are connected to the module, for storing the configuration circuit of the FPGA chip and for activating the FPGA chip initialization software files .
5. 根据权利要求4所述的基于FPGA的HD-SDI视频处理板,其特征在于,所述FPGA芯片还设置有解密模块,用于对所述配置电路中的比特流进行解密。 According to claim FPGA-based HD-SDI video processing board of claim 4, wherein said FPGA chip further provided with a decryption module for the configuration of a bit stream decrypting circuit.
6. 根据权利要求4所述的基于FPGA的HD-SDI视频处理板,其特征在于,所述FPGA芯片还包括微处理器,所述微处理器与所述A)CI总线通信连接,用于获取所述BPI模块中的软件文件并生成软件运行指令,且将所述软件文件及所述软件运行指令输出至所述An总线。 The FPGA-based HD-SDI video processing board according to claim 4, wherein said FPGA chip further comprises a microprocessor and said A) CI bus communication connection, for BPI obtain the software file generation software module and the operation command, and the output of said software and said software file operation command to the bus An.
7. 根据权利要求6所述的基于FPGA的HD-SDI视频处理板,其特征在于,所述基于FPGA的HD-SDI视频处理板还包括存储模块,所述FPGA芯片还包括内存控制器, 所述内存控制器与所述A)(I总线通信连接,用于接收所述原始视频数据并控制所述存储模块写入所述原始视频数据,及获取所述软件文件和所述软件运行指令并输出; 所述存储模块与所述内存控制器连接,用于写入所述原始视频数据并缓存,以及获取所述内存控制器输出的所述软件文件和所述软件运行指令,并运行所述软件文件,以启动所述FPGA芯片的初始化。 7. FPGA-based HD-SDI video processing board according to claim 6, wherein said FPGA-based HD-SDI video processing board further includes a memory module, said memory controller further includes a FPGA chip, the said memory controller and said A) (I communication bus connector, for receiving the original video data and storing said control module writes the original video data, and access to said software and said software file operation command and output; the storage module is connected to the memory controller for writing data and the original video buffer, and acquires the software file output by the memory controller and the software operation instruction, and operation of the software file to start the initialization of the FPGA chip.
8.根据权利要求7所述的基于FPGA的HD-SDI视频处理板,其特征在于, 所述基于FPGA的HD-SDI视频处理板还包括HDMI接口模块,所述HDMI接口模块与所述FPGA芯片连接,用于显示所述原始视频数据, 所述FPGA芯片还包括显示控制器,所述显示控制器与所述AXI总线通信连接,用于通过所述AXI总线获取所述存储模块中缓存的所述原始视频数据并输出至所述HDMI接口模块显不。 According to claim FPGA-based HD-SDI video processing board of claim 7, wherein said FPGA-based HD-SDI video processing board further includes a HDMI interface module, the HDMI interface module and the FPGA chip connector, for displaying the original video data, the FPGA chip further includes a display controller, the display controller and the AXI bus communication connection, the storage module for acquiring the cache bus via the AXI said original video data and outputs it to the HDMI interface module is not significant.
9.根据权利要求8所述的基于FPGA的HD-SDI视频处理板,其特征在于,所述基于FPGA的HD-SDI视频处理板还包括JTAG接口模块和电源芯片,所述JTAG接口模块与所述FPGA芯片连接,用于对所述FPGA芯片进行下载调试; 所述电源芯片分别与所述FPGA芯片、所述SDI芯片、所述存储模块、所述BPI模块连接, 用于将输入电压转化成所述FPGA芯片、所述SDI芯片、所述存储模块、所述BPI模块需要的工作电压并输出。 9. The FPGA-based HD-SDI video processing board according to claim 8, wherein said FPGA-based HD-SDI video processing board JTAG interface module further comprises a power supply and a chip, and that the JTAG interface module said FPGA chip connection for downloading the FPGA chip debug; the power chip to the FPGA chip, respectively, the SDI chip, the memory module, the module is connected BPI, for converting the input voltage is converted into the FPGA chip, the SDI chip, the memory module, the module needs BPI operating voltage and outputs.
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