CN104698747A - Process method for improving two-dimensional graph resolution - Google Patents
Process method for improving two-dimensional graph resolution Download PDFInfo
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- CN104698747A CN104698747A CN201510144159.5A CN201510144159A CN104698747A CN 104698747 A CN104698747 A CN 104698747A CN 201510144159 A CN201510144159 A CN 201510144159A CN 104698747 A CN104698747 A CN 104698747A
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Abstract
The invention relates to the technical field of semiconductor technologies, and provides a process method for improving two-dimensional graph resolution. According to the method, a double-exposure mode is adopted, and for the region where circular beads are generated easily and shortened easily in a final design graph, in the first exposure process, a first graph of a first metal pattern plate is preprocessed to outwards extend by a certain distance; in the second exposure process, a second photoetching glue layer is coated, a second metal pattern plate is used for blocking a pre-extension region, the finally-formed graph is made to be consistent with the design graph through exposure etching, the phenomena that the graph generates corners and becomes round, and the line end is shortened are avoided, graph distortion is prevented, and the resolution of the two-dimension graph is improved.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to a kind of process improving X-Y scheme resolution.
Background technology
Along with the continuous progress of SIC (semiconductor integrated circuit) manufacturing process, the continuous minimizing of live width, the area of semiconductor devices is just becoming more and more less.SIC (semiconductor integrated circuit) is also from initial integrated circuit to large scale integrated circuit, and VLSI (very large scale integrated circuit), until the ULSI of today, its function is more comprehensive, powerful.Consider the restriction of the complicacy of technique research and development, chronicity and high cost etc. unfavorable factor, the integration density how improving device on the basis of existing technology further, the area reducing chip, obtain Effective number of chips with as much as possible on same piece of silicon chip, thus raising overall efficiency, be more and more subject to the attention of chip designer, manufacturer.
In SIC (semiconductor integrated circuit) manufacturing process, photoetching technique is undoubtedly a ring of wherein most critical.Before carrying out ion implantation or etching, need to form photoetching agent pattern by photoetching process, to pre-define out the region of to be etched or ion implantation.Thus, the minimum dimension that whole chip technology can reach is determined by photoetching process.
Photoetching process (photolithography) is an important step in process for fabrication of semiconductor device, this step utilizes exposure and is developed on photoresist layer and portrays geometric figure structure, then by etching technics by the Graphic transitions on photomask on substrate.
Photoetching process roughly processing procedure is: on mask, first obtain specific graphic structure (as electrical circuit), then passes through optical lithography equipment by the graph copying on mask on silicon chip.But produce the process of figure by optical lithography and can produce distortion more or less, constantly reducing especially along with live width, distortion is also further serious.Typically, as turning becomes circle (Corner Rounding) or line end shortens phenomenons such as (Line End Shortening).Refer to Fig. 1 and Fig. 2, Fig. 1 is the figure designed in advance, and Fig. 2 is the figure of actual formation, and comparison diagram 1 and Fig. 2 can obviously find out, the figure that the actual figure formed designs more in advance, creates the problem that turning becomes circle and line end shortening.The reason of these phenomenons above-mentioned is caused to be that optical proximity effect OPE is caused by the nonlinear filtering of optical imaging system due to optical proximity effect (Optical Proximity Effect is called for short OPE).
In sum, those skilled in the art need badly provides a kind of process improving X-Y scheme resolution, avoids figure to produce the phenomenon that turning becomes round and line end shortens, prevents aliasing, improve the resolution of X-Y scheme.
Summary of the invention
The object of the invention is to provide a kind of process improving X-Y scheme resolution, avoids figure to produce the phenomenon that turning becomes round and line end shortens, prevents aliasing, improve the resolution of X-Y scheme.
To achieve these goals, the invention provides a kind of process improving X-Y scheme resolution, comprise the following steps:
Step S1, provide semi-conductor silicon chip, described semi-conductor silicon chip is coated with the first photoresist layer; Wherein, described silicon chip comprises substrate, layer to be etched and hard mask layer from the bottom up successively;
Step S2, first mask plate with the first figure is adopted to carry out exposure imaging to described first photoresist layer, and by the first Graphic transitions on the first mask plate in described first photoresist layer; Wherein, described first figure has the predeterminable area being greater than design configuration;
Step S3, for mask, described hard mask layer to be etched with described first photoresist layer, make in described first Graphic transitions to described hard mask layer;
Step S4, remove described first photoresist layer, and be coated with the second photoresist layer on the surface of described hard mask layer;
Step S5, second mask with second graph is adopted to carry out exposure imaging to described second photoresist, the second graph of described second mask covers described predeterminable area, by the Conjugative tiansfer of the first figure and second graph in described second photoresist layer, layer to be etchedly to etch described;
Step S6, remove described second photoresist layer and hard mask layer, described silicon chip has design configuration.
Preferably, in described step S2, the summation of described design configuration and predeterminable area is described first figure.
Preferably, described predeterminable area is that straight line extends 10 ~ 50nm on the basis of design configuration.
Preferably, in described step S5, described second graph covers described predeterminable area, and extends predeterminable range to the both sides of the vertical direction of described predeterminable area.
Preferably, described predeterminable range is 100 ~ 500nm.
Preferably, described second graph extends 100 ~ 500nm to the extend direction of described predeterminable area.
Preferably, described design configuration and the first figure are flagpole pattern.
Preferably, positive glue is adopted respectively in described first photoresist layer and described second photoresist layer.
The invention provides a kind of process improving X-Y scheme resolution, have employed the mode of re-expose, for the region easily producing fillet and shortening in final design figure, when first time exposes, first figure of the first mask plate is pre-processed into the certain distance that stretches out, when second time exposes, painting is covered with the second photoresist layer, second mask is used for the regional occlusion to extending in advance, etch through overexposure, make the final figure formed consistent with design configuration, figure is avoided to produce the phenomenon that turning becomes round and line end shortens, prevent aliasing, improve the resolution of X-Y scheme.
Accompanying drawing explanation
The figure that Fig. 1 designs in advance for photoetching process in prior art;
The figure that reality that Fig. 2 is formed by photoetching process in prior art;
Fig. 3 is the schematic flow sheet that the present invention improves the process of X-Y scheme resolution;
Fig. 4 is the structural representation of the first figure of the first mask in the present invention;
Fig. 5 is the structural representation of the second graph of the second mask in the present invention;
Fig. 6 to Figure 10 by the present invention to improve in the process preferred embodiment of X-Y scheme resolution the cross-sectional view of formation design configuration.
Reference numeral in figure is:
10. design configuration, 20. actual graphical, 30. predeterminable areas, 40. second photoresist layers, 50. substrates, 60. is layer to be etched, 70. hard mask layers, 80. first photoresist layers, 90. first figures, 100. second graphs.
Embodiment
For making content of the present invention clearly understandable, below in conjunction with Figure of description, content of the present invention is described further.Certain the present invention is not limited to this specific embodiment, and the general replacement known by those skilled in the art is also encompassed in protection scope of the present invention.Secondly, the present invention's detailed statement that utilized schematic diagram to carry out, when describing example of the present invention in detail, for convenience of explanation, schematic diagram, should in this, as limitation of the invention not according to general ratio partial enlargement.
Above-mentioned and other technical characteristic and beneficial effect, by conjunction with the embodiments and the process of accompanying drawing 1 to Figure 10 to raising X-Y scheme resolution of the present invention be described in detail.The figure that Fig. 1 designs in advance for photoetching process in prior art; The figure that reality that Fig. 2 is formed by photoetching process in prior art; Fig. 3 is the schematic flow sheet that the present invention improves the process of X-Y scheme resolution; Fig. 4 is the structural representation of the first figure of the first mask in the present invention; Fig. 5 is the structural representation of the second graph of the second mask in the present invention; Fig. 6 to Figure 10 by the present invention to improve in the process preferred embodiment of X-Y scheme resolution the cross-sectional view of formation design configuration.
Refer to Fig. 3, Fig. 3 is the FB(flow block) of the process improving X-Y scheme resolution in the present invention; In the present embodiment, the invention provides a kind of process improving X-Y scheme resolution, comprise the following steps:
Step S1, provide semi-conductor silicon chip, semi-conductor silicon chip is coated with the first photoresist layer 80; Wherein, silicon chip comprises substrate 50, layer to be etched 60 and hard mask layer 70 from the bottom up successively.(as shown in Figure 6)
Concrete, in the present embodiment, the first photoresist layer 80 can adopt positive glue, described substrate 50, layer to be etched 60 and the material of hard mask layer 70 can select according to routine and determine.
Step S2, adopt first mask plate with the first figure 90 to carry out exposure imaging to described first photoresist layer 80, and the first figure 90 on the first mask plate is transferred in the first photoresist layer 80; Wherein, described first figure 90 has the predeterminable area 30 being greater than design configuration 10.(as shown in Fig. 4,6)
In the present embodiment, design configuration 10 and the first figure 90 are preferably flagpole pattern, because the phenomenon of fillet and drop-head easily appears in actual graphical 20, therefore when design the first figure 90, the basis of design configuration 10 increases predeterminable area 30, and namely design configuration 10 is the first figure 90 with the summation of predeterminable area 30.Preferably, predeterminable area 30 is that straight line extends 10 ~ 50nm on the basis of design configuration 10.
Step S3, for mask, hard mask layer 70 to be etched with the first photoresist layer 80, the first figure 90 is transferred in hard mask layer 70.(as shown in Figure 7)
In this step, there is fillet and drop-head phenomenon in the figure formed in hard mask layer 70, in predeterminable area 30 corresponding before this phenomenon appears at.
Step S4, remove described first photoresist layer 80, and be coated with the second photoresist layer 40 on the surface of hard mask layer 70.(as shown in Figure 8)
In this step, the second photoresist layer 40 can adopt positive glue.
Step S5, second mask with second graph 100 is adopted to carry out exposure imaging to the second photoresist layer 40, the second graph 100 of the second mask covers predeterminable area 30, by the Conjugative tiansfer of the first figure 90 and second graph 100 in the second photoresist layer 40, etch layer to be etched 60.(as shown in Figure 9)
As shown in Figure 5, the second graph 100 of the second mask covers the predeterminable area 30 of the first figure 90, and can extend predeterminable range to the both sides of the vertical direction of predeterminable area 30 and extend direction, and its predeterminable range is preferably 100 ~ 500nm.
Due to the fillet sheltering from hard mask layer 70 and the drop-head region of the second graph 100 of the second mask, etch layer to be etched 60 with the mask that is combined into of the first figure 90 and second graph 100, the phenomenon of fillet or drop-head can not be occurred on layer to be etched 60.
Step S6, remove the second photoresist layer 40 and hard mask layer 70, silicon chip has design configuration.(as shown in Figure 10)
Finally the second photoresist layer 40 and hard mask layer 70 are removed, it is removed technique and can determine according to common process, and the design configuration finally formed on silicon chip there will not be the phenomenon of fillet and drop-head, and the actual figure formed is consistent with design configuration.
In sum, the invention provides a kind of process improving X-Y scheme resolution, have employed the mode of re-expose, for the region easily producing fillet and shortening in final design figure, when first time exposes, first figure of the first mask plate is pre-processed into the certain distance that stretches out, when second time exposes, painting is covered with the second photoresist layer, second mask is used for the regional occlusion to extending in advance, etch through overexposure, make the final figure formed consistent with design configuration, figure is avoided to produce the phenomenon that turning becomes round and line end shortens, prevent aliasing, improve the resolution of X-Y scheme.
The above is only the description of the preferred implementation of invention; should be understood that; due to the finiteness of literal expression; and objectively there is unlimited concrete structure; for those skilled in the art; under the premise without departing from the principles of the invention, can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.Any simple modification, equivalent variations and modification, all still belong in the scope of technical solution of the present invention protection.
Claims (8)
1. improve a process for X-Y scheme resolution, it is characterized in that, comprise the following steps:
Step S1, provide semi-conductor silicon chip, described semi-conductor silicon chip is coated with the first photoresist layer; Wherein, described silicon chip comprises substrate, layer to be etched and hard mask layer from the bottom up successively;
Step S2, first mask plate with the first figure is adopted to carry out exposure imaging to described first photoresist layer, and by the first Graphic transitions on the first mask plate in described first photoresist layer; Wherein, described first figure has the predeterminable area being greater than design configuration;
Step S3, for mask, described hard mask layer to be etched with described first photoresist layer, make in described first Graphic transitions to described hard mask layer;
Step S4, remove described first photoresist layer, and be coated with the second photoresist layer on the surface of described hard mask layer;
Step S5, second mask with second graph is adopted to carry out exposure imaging to described second photoresist, the second graph of described second mask covers described predeterminable area, by the Conjugative tiansfer of the first figure and second graph in described second photoresist layer, layer to be etchedly to etch described;
Step S6, remove described second photoresist layer and hard mask layer, described silicon chip has design configuration.
2. the process of raising X-Y scheme resolution according to claim 1, is characterized in that, in described step S2, the summation of described design configuration and predeterminable area is described first figure.
3. the process of raising X-Y scheme resolution according to claim 2, is characterized in that, described predeterminable area is that straight line extends 10 ~ 50nm on the basis of design configuration.
4. the process of raising X-Y scheme resolution according to claim 1, is characterized in that, in described step S5, described second graph covers described predeterminable area, and extends predeterminable range to the both sides of the vertical direction of described predeterminable area.
5. the process of raising X-Y scheme resolution according to claim 4, is characterized in that, described predeterminable range is 100 ~ 500nm.
6. the process of raising X-Y scheme resolution according to claim 4, is characterized in that, described second graph extends 100 ~ 500nm to the extend direction of described predeterminable area.
7. the process of raising X-Y scheme resolution according to claim 1, is characterized in that, described design configuration and the first figure are flagpole pattern.
8., according to the process of the arbitrary described raising X-Y scheme resolution of claim 1 ~ 7, it is characterized in that, in described first photoresist layer and described second photoresist layer, adopt positive glue respectively.
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| CN201510144159.5A CN104698747B (en) | 2015-03-30 | 2015-03-30 | A kind of process improving X-Y scheme resolution |
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| CN104977803A (en) * | 2015-07-22 | 2015-10-14 | 上海华力微电子有限公司 | Method for forming one-dimensional and two-dimensional photoresist graphs simultaneously |
| CN105161409A (en) * | 2015-09-27 | 2015-12-16 | 上海华力微电子有限公司 | Method for forming U-shaped gate |
| CN106328499A (en) * | 2016-08-25 | 2017-01-11 | 西安派瑞功率半导体变流技术股份有限公司 | Vacuum film-plating process for gate pattern of semiconductor chip shielded by mask at high accuracy |
| CN109917616A (en) * | 2017-12-12 | 2019-06-21 | 中芯国际集成电路制造(北京)有限公司 | The production method and double patterning method of mask for double patterning |
| CN110277372A (en) * | 2019-07-23 | 2019-09-24 | 南方电网科学研究院有限责任公司 | A kind of IC etching arbor, preparation method and integrated circuit |
| WO2022198886A1 (en) * | 2021-03-23 | 2022-09-29 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method therefor |
| US11710642B2 (en) | 2021-03-23 | 2023-07-25 | Changxin Memory Technologies, Inc. | Semiconductor structure and manufacturing method thereof |
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| US20030124847A1 (en) * | 2001-12-28 | 2003-07-03 | Houston Theodore W. | Double pattern and etch of poly with hard mask |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104977803A (en) * | 2015-07-22 | 2015-10-14 | 上海华力微电子有限公司 | Method for forming one-dimensional and two-dimensional photoresist graphs simultaneously |
| CN104977803B (en) * | 2015-07-22 | 2019-06-28 | 上海华力微电子有限公司 | A method of being formed simultaneously a peacekeeping two dimension photoetching offset plate figure |
| CN105161409A (en) * | 2015-09-27 | 2015-12-16 | 上海华力微电子有限公司 | Method for forming U-shaped gate |
| CN106328499A (en) * | 2016-08-25 | 2017-01-11 | 西安派瑞功率半导体变流技术股份有限公司 | Vacuum film-plating process for gate pattern of semiconductor chip shielded by mask at high accuracy |
| CN106328499B (en) * | 2016-08-25 | 2018-11-20 | 西安派瑞功率半导体变流技术股份有限公司 | Mask plate high-precision blocks semiconductor chip gate pole figure Vacuum Deposition processing film technique |
| CN109917616A (en) * | 2017-12-12 | 2019-06-21 | 中芯国际集成电路制造(北京)有限公司 | The production method and double patterning method of mask for double patterning |
| CN109917616B (en) * | 2017-12-12 | 2022-07-05 | 中芯国际集成电路制造(北京)有限公司 | Manufacturing method of mask for double patterning and double patterning method |
| CN110277372A (en) * | 2019-07-23 | 2019-09-24 | 南方电网科学研究院有限责任公司 | A kind of IC etching arbor, preparation method and integrated circuit |
| WO2022198886A1 (en) * | 2021-03-23 | 2022-09-29 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method therefor |
| US11710642B2 (en) | 2021-03-23 | 2023-07-25 | Changxin Memory Technologies, Inc. | Semiconductor structure and manufacturing method thereof |
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