CN104616990B - The forming method of metal gates - Google Patents
The forming method of metal gates Download PDFInfo
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- CN104616990B CN104616990B CN201310541712.XA CN201310541712A CN104616990B CN 104616990 B CN104616990 B CN 104616990B CN 201310541712 A CN201310541712 A CN 201310541712A CN 104616990 B CN104616990 B CN 104616990B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
Abstract
A kind of forming method of metal gates, including：Semiconductor substrate is provided；The first dummy grid and the second dummy grid being connected are formed on the semiconductor substrate；Remove in the first dummy grid formation first groove, recessed second dummy grid of side wall of the first groove and form side groove；Form filling block and fill up the side groove；The first metal gates are formed in the first groove.The side groove that methods described occurs by being formed filling block to fill up in manufacturing process, form the first groove in the absence of side groove, therefore the first workfunction layers and the first metal gates can be normally formed in first groove, do not influenceed by the side groove occurred during making, improve the reliability of transistor.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly, to a kind of forming method of metal gates.
Background technology
Main devices in integrated circuit especially super large-scale integration are Metal-oxide-semicondutor (metal
Oxide semiconductor, MOS) field-effect transistor, abbreviation MOS transistor.Since MOS transistor is by invention, its
Physical dimension is constantly reducing always.In the case, various actual and basic limitation and technological challenge start to occur, device
The further diminution of part size is just becoming more and more difficult.
In prepared by MOS transistor device and circuit, most challenge is complementary MOS
(Complementary Metal-Oxide-Semiconductor, CMOS) transistor device is during diminution, due to two
The gate oxide thickness that silica (or silicon oxynitride) is constituted reduces the higher grid leakage current brought.Therefore, having proposed
Solution be, using metal gates and high-k (K) gate dielectric layer substitute traditional heavily doped polysilicon grid and
Silica (or silicon oxynitride) gate dielectric layer.
CMOS transistor digital integrated electronic circuit includes PMOS transistor and nmos pass transistor.In some use occasions, need
By PMOS transistor together with the fabrication of nmos pass transistor, such as in six transistor CMOS SRAMs
(static random access memory, SRAM).
For PMOS transistor and nmos pass transistor with metal gates and high-K gate dielectric layer, in order to prevent gold
Belong to grid in manufacturing process, influenceed by high-temperature technology, it is necessary to first make dummy grid, after other processing steps are completed, gone
Except dummy grid formation groove, groove formation metal gates, i.e., so-called post tensioned unbonded prestressed concrete technique are refilled.Also, due to PMOS crystal
Workfunction layers used in pipe are different from workfunction layers used in nmos pass transistor, therefore, in manufacturing process
Need successively to remove the dummy grid of PMOS transistor and the dummy grid of nmos pass transistor.
Fig. 1 is refer to, Fig. 1 is shown makes MOS transistor on a semiconductor substrate 100, when PMOS transistor and NMOS
The fabrication of transistor together when, the dummy grid of script PMOS transistor and the dummy grid of nmos pass transistor are connected as a single entity
(not shown), when removing the dummy grid (not shown) formation groove of PMOS transistor, the dummy grid 101 of meeting pair nmos transistor
Certain corrasion is caused, side groove 103 is formd while resulting in groove 102, PMOS transistor is removed in etching
Dummy grid, it usually needs overetch is to ensure that etching is complete, and overetch can further increase side groove 103.Side groove 103
Presence have impact on the formation of follow-up PMOS transistor metal gates, cause the reliability decrease of PMOS transistor.
For this reason, it may be necessary to a kind of forming method of new metal gates, to prevent the reliability decrease of transistor.
The content of the invention
The problem of present invention is solved is to provide a kind of forming method of metal gates, to solve metal gates in manufacturing process
In the problem of there is side groove, so as to ensure the formation of metal gates, improve the reliability of transistor.
To solve the above problems, the present invention provides a kind of forming method of metal gates, including：
Semiconductor substrate is provided；
The first dummy grid and the second dummy grid being connected are formed on the semiconductor substrate；
Remove in the first dummy grid formation first groove, recessed second dummy grid of side wall of the first groove
Form side groove；
Form filling block and fill up the side groove；
The first metal gates are formed in the first groove.
Optionally, the formation filling block, which fills up the side groove, includes：
Using the full first groove of packed layer filling and the side groove；
The packed layer is etched using anisotropic etch process until reopening the first groove, the packed layer
Remainder forms the filling block and fills up the side groove.
Optionally, the material of the packed layer is organosiloxane.
Optionally, the thickness range of the packed layer is
Optionally, the anisotropic etch process is plasma etch process.
Optionally, the gas that the plasma etch process is used includes at least one of CF4 and C4F8, and
CH2F2, C4F8And CF4Total flow scope be 10sccm~50sccm, CH2F2Range of flow be 2sccm~20sccm, it is described
The pressure range of plasma etch process is 2mTorr~50mTorr, and the radio-frequency power of the plasma etch process is
100W~2000W.
Optionally, formed in the first groove after the first metal gates, the forming method also includes：
The second dummy grid formation second groove is removed, the filling block is located at second groove side wall；
Remove the filling block；
The second metal gates are formed in the second groove.
Optionally, the filling block is removed using wet-etching technology, the solution that the wet-etching technology is used is hydrogen
Oxidation of alkyl ammonium salt solution.
Optionally, there is high-K gate dielectric layer and cap layer extremely between first dummy grid and the Semiconductor substrate
It is few one of them, have between second dummy grid and the Semiconductor substrate high-K gate dielectric layer and cap layer at least its
One of.
Optionally, first dummy grid is the dummy grid of PMOS transistor and second dummy grid is nmos pass transistor
Dummy grid, or dummy grid that first dummy grid is nmos pass transistor and second dummy grid is PMOS transistor
Dummy grid.
Compared with prior art, technical scheme has advantages below：
In technical scheme, when removing the first dummy grid formation first groove, the first groove
Side groove is formed in recessed second dummy grid of side wall, the side groove is filled up by forming filling block, so as to ensure in institute
State the first metal gates of formation in first groove is not influenceed by side groove, improves the reliability of transistor.
Further, it is used to be formed to have in the filling block, organosiloxane as packed layer using organosiloxane and contains
The organic group of carbon, during being etched, organosiloxane can generate polymer simultaneously and be covered in sidewall surfaces, protect side
Wall is not etched by and destroyed, and side wall formation side groove is prevented, so as to be more effectively prevented from the generation of side groove.
Brief description of the drawings
Fig. 1 is the forming method schematic diagram of existing metal gates；
Fig. 2 to Fig. 9 is the forming method schematic diagram of metal gates of the embodiment of the present invention.
Embodiment
In existing method, when remove PMOS (or NMOS) transistor dummy grid formation groove when, can to NMOS (or
NMOS) dummy grid of transistor causes certain corrasion, and side groove is formd while resulting in groove.Side groove
In the presence of the formation that have impact on follow-up PMOS (or NMOS) transistor metal grid, cause the reliability of PMOS (or NMOS) transistor
Decline.
Therefore, the present invention provides a kind of forming method of metal gates, methods described is removing the first dummy grid shape
During into first groove, side groove is formed in recessed second dummy grid of side wall of the first groove, by forming filling block
The side groove is filled up, so as to ensure that the first metal gates are formed in the first groove not to be influenceed by side groove, is improved
The reliability of transistor.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
The embodiment of the present invention provides a kind of forming method of metal gates, refer to Fig. 2 to Fig. 9.
Refer to Fig. 2, there is provided Semiconductor substrate 200.
In the present embodiment, Semiconductor substrate 200 can be silicon substrate or germanium silicon substrate etc. or semiconductor-on-insulator
Conductor substrate 200, the present embodiment is by taking silicon substrate as an example.Semiconductor substrate 200 provides a load to form various semiconductor devices
Body.
Have in the present embodiment, in Semiconductor substrate 200 in shallow channel isolation area 201, Semiconductor substrate 200 and be formed with height
K gate dielectric layers 202 and cap layer 203, wherein high-K gate dielectric layer 202 are located in Semiconductor substrate 200, and cap layer 203 is located at height
On K gate dielectric layers 202.
In the present embodiment, the material of high-K gate dielectric layer 202 can be hafnium oxide, hafnium silicon oxide, lanthana, lanthana
Aluminium, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, yittrium oxide, aluminum oxide,
The one or more of lead oxide scandium tantalum or lead niobate zinc etc..
In the present embodiment, the material of cap layer 203 can be titanium nitride or tantalum nitride.Cap layer 203 on the one hand can be with
The uniformity of film surface is improved, on the other hand can change work function, the threshold value of grid in the transistor that is subsequently formed is prevented
Overtension.
Please continue to refer to Fig. 2, the first dummy grid 210 and the second pseudo- grid being connected are formed on semiconductor substrate 200
Pole 220.
In Fig. 2, the two is distinguished with the dotted line (not marking) in the middle of the first dummy grid 210 and the second dummy grid 220, institute
State dotted line and be located exactly at shallow channel isolation area 201, therefore, although described two dummy grids are connected as a single entity, but shallow channel isolation area
201 can be isolated the active area of two transistors of correspondence.
The first dummy grid 210 being connected as a single entity in Fig. 2 and the both sides of the second dummy grid 220 are side wall, specifically, the
The right side of one dummy grid 210 is side wall 204, is side wall 205 in the left side of the second dummy grid 220, side wall 204 and side wall 205 are limited
The position actually of first dummy grid 210 and the second dummy grid 220, and autoregistration mask can be used as when carrying out ion doping
A part.
In the present embodiment, the first dummy grid 210 is used to form PMOS transistor, and the second dummy grid 220 is used to form NMOS
Transistor.The material of first dummy grid 210 and the second dummy grid 220 can be polysilicon (poly silicon).Need explanation
, in other embodiments of the invention or the first dummy grid 210 is used to form nmos pass transistor, the second pseudo- grid
Pole 220 is used to form PMOS transistor.
In the present embodiment, during the dummy grid and the side wall is formed, while form nmos pass transistor and
The source area (not shown) and drain region (not shown) of PMOS transistor, and it is possible to continue the source area in PMOS transistor
With formation stress SiGe (not shown) in drain region, to increase the compression stress of PMOS transistor channel region, improve hole and carry
Flow the mobility of son.
In the present embodiment, although do not show, but can be in the first dummy grid 210, the second dummy grid 220 and semiconductor
The surface of substrate 200 forms interlayer dielectric layer (not shown), and carries out planarization to interlayer dielectric layer until exposing the first dummy grid
210 surfaces and the upper surface of the second dummy grid 220, after planarization, the first dummy grid 210, the second dummy grid 220 and interlayer are situated between
The upper surface flush of matter layer, the i.e. upper surface of the first dummy grid 210 and the second dummy grid 220 is exposed after planarization,
As shown in Figure 2.
Fig. 3 is refer to, the first dummy grid 210 formation first groove 211 in Fig. 2 is removed, the side wall of first groove 211 is recessed
Enter formation side groove 231 in the second dummy grid 220.
In the present embodiment, the first dummy grid 210 in Fig. 2 is removed using anisotropic etch process, in etching process,
Protective layer (such as photoresist layer) first can be formed as mask on the surface of the second dummy grid 220, then the first dummy grid 210 is entered
Row etching, forms first groove 211.
Which kind of, due to either etching technics, it is impossible to unidirectionally be etched completely, that is to say, that even with each
Anisotropy etching technics is etched on vertical shown in Fig. 3 to the first dummy grid 21, still, the anisotropic etching work
Skill still can have certain etching action in the transverse direction shown in Fig. 3.And the first dummy grid 210 and the second dummy grid 220 connect
It is integrated, and both materials are identical, and therefore, the second dummy grid 220 can be influenceed by the anisotropic etch process, quilt
Etch to the recessed side groove 231 of the second dummy grid 220, as shown in Figure 3.
The presence of side groove 231, can cause follow-up workfunction layers to be difficult to the bottom for being completely filled in first groove 211
With side wall, and can further result in it is follow-up be difficult in first groove 211 form metal gates, so as to cause formed crystal
Pipe reliability is reduced.Therefore, the present embodiment is subsequently through filling block filling side groove 231 is formed, so as to ensure first groove 211
It is interior to form intact workfunction layers and metal gates, improve formed transistor reliability.
Incorporated by reference to Fig. 4 and Fig. 5 is referred to, form filling block 207 and fill up side groove shown in Fig. 3 231.
Referring first to Fig. 4, the first groove 211 and side groove 231 in full Fig. 3 are filled using packed layer 206.
In the present embodiment, the material of packed layer 206 can be that organosiloxane (organo-siloxane) its chemical formula is
Rx(CH3)ySiOz, wherein R represents organic chromophoric group (organic chromophore), and organosiloxane has good fill out
Performance is filled, therefore first groove 211 and side groove 231 can completely be filled.
, can be using spin-coating method (spin on coating) formation packed layer 206 in the present embodiment, and packed layer 206
Thickness range is can be controlled inOn the one hand the full first groove 211 of the filling of packed layer 206 and side groove are ensured
231, on the other hand convenient follow-up removal.
Next referring to Fig. 5, using packed layer 206 shown in anisotropic etch process etch figures(s) 4 until reopening the
One groove 211, the remainder of packed layer 206 formation filling block 207 fills up side groove shown in Fig. 3 231.
In the present embodiment, the anisotropic etch process be plasma etch process, and the plasma carve
Etching technique uses range of flow for 10sccm~50sccm CF4With the CH that range of flow is 2sccm~20sccm2F2, Liang Zhejie
Close the plasma produced has preferable etching action to the packed layer 206 of organosiloxane material, and in etching process
In organosiloxane can be caused to produce more polymer, preferably protect the side wall formed in etching process.In addition, described
Both combine the plasma produced has higher selection ratio, i.e., described plasma to the dummy grid 220 of packed layer 206 and second
Body can quickly remove packed layer 206, and very trickle to the etching action of the second dummy grid 220, can ignore substantially.Need
Illustrate, in other embodiments of the invention, C can also be used4F8Some or all of replacement CF4For packed layer 206
Etching.
In the present embodiment, the pressure range of the plasma etch process is 2mTorr~50mTorr, so as to ensure to carve
Product can be removed totally in time after erosion, and the radio-frequency power of the plasma etch process is 100W~2000W, so as to ensure
Etch rate.
The present embodiment is used to form filling block 207 using organosiloxane as packed layer 206, due in organosiloxane
With carbon containing organic group, therefore it by plasma etching technique during being etched, and polymer can be generated simultaneously
Be covered in the sidewall surfaces of etching generation, protective side wall is not etched by and destroys, prevent side wall formation side groove, thus more added with
Prevent the generation of side groove to effect.
Because the partial occlusion of the second dummy grid 220 is in the upper end of side groove 231, and above-mentioned plasma etch process condition
There is higher selection ratio to the dummy grid 220 of packed layer 206 and second, therefore, the portion of side groove 231 is located in packed layer 206
Branch is retained to form filling block 207, i.e. the present embodiment by above-mentioned steps after, can be in original side groove 231
Form filling block 207.
In addition to being retained except the packed layer in side groove 231 and to form filling block 207, other parts
Packed layer 206 is removed clean, therefore, and first groove 211 is switched on again, that is, has re-formed groove 211, and now
Form side groove and be filled block 207 and fill up, now side groove is not present in first groove 211 in other words, as shown in Figure 5.
Fig. 6 is refer to, the first workfunction layers 212 and the first metal gates 213 are formed in Fig. 5 first grooves 211.
In the present embodiment, because the first dummy grid 210 is used to form PMOS transistor, therefore, the first workfunction layers
212 material can be the double-level-metal layer of Fluorin doped.
In the present embodiment, the material of the first metal gates 213 can be aluminium.But in other embodiments of the invention,
The material of first metal gates 213 can also be one or a combination set of following metal：Copper, ruthenium, palladium, platinum, cobalt, nickel, ruthenium-oxide,
Tungsten, titanium, tantalum, hafnium and zirconium.
In the present embodiment, after the first metal gates 213 are formed, flatening process can be carried out, until the first metal
The surface of grid 213 is flushed with the surface of the second dummy grid 220, i.e., the surface of the second dummy grid 220 is exposed again, in order to follow-up
Remove the second dummy grid 220.
The present embodiment is formed filling block and fills up the side groove occurred in manufacturing process, formd not by above steps
There is the first groove of side groove, therefore the first workfunction layers and the first metal gates can be normally formed in first groove
It is interior, do not influenceed by the side groove occurred during making, improve the reliability of transistor.
After completing the aforementioned steps, the present embodiment can also continue to make the second follow-up metal gates.
Fig. 7 is refer to, the second dummy grid 220 formation second groove 221 is removed, now filling block 207 is located at second groove
221 side walls.
In the present embodiment, the detailed process for forming second groove 221 refers to be formed the process of first groove 211, can be with
With reference to the content of this specification appropriate section.
Fig. 8 is refer to, filling block 207 is removed.
In the present embodiment, the filling block can be removed using wet-etching technology, what the wet-etching technology was used
Solution is alkyl ammonium hydroxide solution, and alkyl ammonium hydroxide solution can remove the filling block 207 of organosiloxane material rapidly,
And will not other structures impact.
Fig. 9 is refer to, the second workfunction layers 222 and the second metal gates 223 are formed in second groove 221.
In the present embodiment, because the second dummy grid 220 is used to form nmos pass transistor, therefore, the second workfunction layers
222 material can be the double-level-metal layer of carbon doping.
In the present embodiment, the material of the second metal gates 223 equally can be aluminium.But in other embodiments of the invention
In, the material of the second metal gates 223 equally can be one or a combination set of following metal：Copper, ruthenium, palladium, platinum, cobalt, nickel, oxidation
Ruthenium, tungsten, titanium, tantalum, hafnium and zirconium.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, are not departing from this
In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope of restriction is defined.
Claims (10)
1. a kind of forming method of metal gates, it is characterised in that including：
Semiconductor substrate is provided；
The first dummy grid and the second dummy grid being connected are formed on the semiconductor substrate；
Remove and formed in the first dummy grid formation first groove, recessed second dummy grid of side wall of the first groove
Side groove；
Form filling block and fill up the side groove；
The first metal gates are formed in the first groove.
2. the forming method of metal gates as claimed in claim 1, it is characterised in that the formation filling block fills up the side
Groove includes：
Using the full first groove of packed layer filling and the side groove；
The packed layer is etched using anisotropic etch process until reopening the first groove, the packed layer is remaining
Part forms the filling block and fills up the side groove.
3. the forming method of metal gates as claimed in claim 2, it is characterised in that the material of the packed layer is organosilicon
Oxygen alkane.
4. the forming method of metal gates as claimed in claim 2, it is characterised in that the thickness range of the packed layer is
5. the forming method of metal gates as claimed in claim 2, it is characterised in that the anisotropic etch process for etc.
Plasma etching technique.
6. the forming method of metal gates as claimed in claim 5, it is characterised in that the plasma etch process is used
Gas include CF4And C4F8At least one and CH2F2, C4F8And CF4Total flow scope for 10sccm~
50sccm, CH2F2Range of flow be 2sccm~20sccm, the pressure range of the plasma etch process for 2mTorr~
50mTorr, the radio-frequency power of the plasma etch process is 100W~2000W.
7. the forming method of metal gates as claimed in claim 2, it is characterised in that form first in the first groove
After metal gates, the forming method also includes：
The second dummy grid formation second groove is removed, the filling block is located at second groove side wall；Filled out described in removing
Fill block；
The second metal gates are formed in the second groove.
8. the forming method of metal gates as claimed in claim 7, it is characterised in that removed using wet-etching technology described
Filling block, the solution that the wet-etching technology is used is alkyl ammonium hydroxide solution.
9. the forming method of metal gates as claimed in claim 1, it is characterised in that first dummy grid is partly led with described
There is at least one of high-K gate dielectric layer and cap layer, second dummy grid is served as a contrast with the semiconductor between body substrate
There is at least one of high-K gate dielectric layer and cap layer between bottom.
10. the forming method of metal gates as claimed in claim 1, it is characterised in that first dummy grid is PMOS brilliant
The dummy grid of body pipe and second dummy grid are the dummy grid of nmos pass transistor, or first dummy grid is NMOS crystal
The dummy grid of pipe and second dummy grid are the dummy grid of PMOS transistor.
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| CN201310541712.XA CN104616990B (en) | 2013-11-05 | 2013-11-05 | The forming method of metal gates |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1890798A (en) * | 2003-10-02 | 2007-01-03 | 英特尔公司 | Method and apparatus for improving stability of a 6T CMOS sram cell |
| CN101393862A (en) * | 2007-09-20 | 2009-03-25 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for gate lateral wall layer and semi-conductor device |
| CN102881590A (en) * | 2011-07-12 | 2013-01-16 | 联华电子股份有限公司 | Forming method for repair layer and metal oxide semiconductor transistor structure |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19910353A1 (en) * | 1999-03-09 | 2000-09-21 | Siemens Ag | Semiconductor read-only memory arrangement with substrate contact and polysilicon bridging cell |
| JP2006114719A (en) * | 2004-10-15 | 2006-04-27 | Jsr Corp | Composition for surface hydrophobing, method of hydrophobing surface, semiconductor device and its manufacturing method |
| US7544561B2 (en) * | 2006-11-06 | 2009-06-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Electron mobility enhancement for MOS devices with nitrided polysilicon re-oxidation |
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2013
- 2013-11-05 CN CN201310541712.XA patent/CN104616990B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1890798A (en) * | 2003-10-02 | 2007-01-03 | 英特尔公司 | Method and apparatus for improving stability of a 6T CMOS sram cell |
| CN101393862A (en) * | 2007-09-20 | 2009-03-25 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for gate lateral wall layer and semi-conductor device |
| CN102881590A (en) * | 2011-07-12 | 2013-01-16 | 联华电子股份有限公司 | Forming method for repair layer and metal oxide semiconductor transistor structure |
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