CN104600074A - The semiconductor device - Google Patents

The semiconductor device Download PDF

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Publication number
CN104600074A
CN104600074A CN201410528576.5A CN201410528576A CN104600074A CN 104600074 A CN104600074 A CN 104600074A CN 201410528576 A CN201410528576 A CN 201410528576A CN 104600074 A CN104600074 A CN 104600074A
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transistor
source
electrode
oxide semiconductor
potential
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CN201410528576.5A
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Chinese (zh)
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山崎舜平
小山润
加藤清
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株式会社半导体能源研究所
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Publication of CN104600074A publication Critical patent/CN104600074A/en

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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/24Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using capacitors
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/405Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/112Read-only memory structures [ROM] and multistep manufacturing processes therefor
    • H01L27/115Electrically programmable read-only memories; Multistep manufacturing processes therefor
    • H01L27/11517Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate
    • H01L27/11551Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/112Read-only memory structures [ROM] and multistep manufacturing processes therefor
    • H01L27/115Electrically programmable read-only memories; Multistep manufacturing processes therefor
    • H01L27/11517Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate
    • H01L27/1156Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate the floating gate being an electrode shared by two or more components
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2211/00Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/401Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C2211/4016Memory devices with silicon-on-insulator cells
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688Integrated circuits having a three-dimensional layout
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/11Static random access memory structures
    • H01L27/1104Static random access memory structures the load element being a MOSFET transistor
    • H01L27/1108Static random access memory structures the load element being a MOSFET transistor the load element being a thin film transistor

Abstract

An object is to provide a semiconductor device having a novel structure. A first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor including a first gate electrode, a first source electrode, and a first drain electrode; a second transistor including a second gate electrode, a second source electrode, and a second drain electrode are included. The first transistor is provided over a substrate including a semiconductor material and a second transistor includes an oxide semiconductor layer.

Description

半导体装置 The semiconductor device

[0001] 本申请是申请日为2009年11月6日、申请号为201080049931.0,发明名称为"半导体装置"发明专利申请的分案申请。 [0001] This application is filed November 6, 2009, Application No. 201080049931.0, entitled divisional applications "semiconductor device" in the invention patent applications.

技术领域 FIELD

[0002] 本发明涉及一种使用半导体元件的半导体装置及其制造方法。 [0002] The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device.

背景技术 Background technique

[0003] 使用半导体元件的存储装置大体上分为:易失性存储装置,当电源停止时丢失它们的存储内容;和非易失性存储装置,当电源停止时能够保留它们的存储内容。 [0003] using a semiconductor memory device is largely divided into elements: a volatile memory means, the stored content thereof is lost when the power is stopped; and nonvolatile memory device, when the power supply is stopped can retain storage contents thereof.

[0004] 作为易失性存储装置的典型例子,给出动态随机存取存储器(DRAM)。 [0004] As a typical example of a volatile memory device, is given a dynamic random access memory (DRAM). 在DRAM中, 选择存储元件中所包括的晶体管并且在电容器中积聚电荷,从而存储数据。 In a DRAM, a transistor included in the selected memory element and electric charge accumulated in the capacitor, thereby storing data.

[0005] 由于上述原理,当在DRAM中读出数据时,电容器中的电荷丢失;因此,必须再次执行写入以使在读取数据之后再次存储数据。 [0005] Due to the above principle, when the read data in the DRAM, the charge in the capacitor is lost; therefore, must be performed again to write the memory data again after data is read. 另外,在存储元件中所包括的晶体管中存在漏电流,并且即使未选择晶体管,存储在电容器中的电荷也流动或者电荷流入到电容器中,由此数据保持时间段是短的。 Further, the presence of the transistor in the memory element included in the leakage current, even if not selected and the transistor, the charge stored in the capacitor charges also flow or flows into the capacitor, whereby the data holding time period is short. 因此,必须在预定周期中再次执行写入(刷新操作)并且难以充分地减小功耗。 Therefore, writing must be performed again in a predetermined period (refresh operation) and it is difficult to sufficiently reduce power consumption. 另外,由于当未向DRAM供电时存储内容丢失,所以对于长时间存储的存储内容,需要使用磁性材料或光学材料的其他存储装置。 Further, since when the stored content is not lost when power DRAM, so the content stored in long term storage, it is necessary to use a magnetic material or other storage device optical material.

[0006] 作为易失性存储装置的其他例子,给出静态随机存取存储器(SRAM)。 [0006] As another example of a volatile memory device, a static random access memory give (SRAM). 在SRAM中, 使用诸如双稳态多谐振荡器的电路保留存储内容,从而不需要刷新操作。 In SRAM, a memory circuit to retain the contents, such as flip-flops, so that no refresh operation. 考虑到这一点, SRAM优于DRAM。 With this in mind, SRAM is superior to DRAM. 然而,存在这样的问题:因为使用了诸如双稳态多谐振荡器的电路,每存储容量的成本变高。 However, there is a problem: because of the use of such a bistable multivibrator circuit, the cost per storage capacity is increased. 另外,考虑到当未供电时存储内容丢失这一点,SRAM并不优于DRAM。 In addition, when taking into account the loss of this stored content, SRAM is not superior to DRAM when not powered.

[0007] 作为非易失性存储装置的典型例子,给出闪速存储器。 [0007] As typical examples of a nonvolatile memory device, a flash memory is given. 闪速存储器包括位于晶体管中的栅电极和沟道形成区域之间的浮栅。 The flash memory comprises a transistor gate electrode and the channel forming region between the floating gate. 闪速存储器通过在浮栅中保留电荷存储存储内容,从而数据保持时间段极长(半永久),并因此具有这样的优点:不需要在易失性存储装置中必需的刷新操作(例如,参见专利文件1)。 Flash memory by retaining charge storage contents stored in the floating gate, so that the data holding period is extremely long (semi-permanent), and thus has the advantages: does not require the refresh operation required in the volatile storage device (e.g., see Patent File 1).

[0008] 然而,在闪速存储器中,存在这样的问题,即在执行写入预定次数之后,存储元件不工作,因为存储元件中所包括的栅极绝缘层由于当执行写入时发生的隧穿电流而劣化。 [0008] However, in flash memory, there is a problem that, after a predetermined number of times writing is performed, the memory element does not work, because the tunnel when the writing occurs in a storage element includes a gate insulating layer due to the tunneling current deteriorates. 为了缓解这个问题的影响,例如,采用例如均衡存储元件的写入操作的次数的方法。 To mitigate the effects of this problem, for example, a method using, for example, the number of write operations equalization storage element. 然而, 实现该方法需要复杂的外围电路。 However, implementation of the method requires a complicated peripheral circuit. 即使采用这种方法,也未解决使用寿命的基本问题。 Even with this method, but also did not solve the basic problems of life. 也就是说,闪速存储器不适合以高频率写入数据的应用。 That is, the flash memory is not suitable for application to write data at a high frequency.

[0009] 另外,需要高电压以在浮栅中保留电荷或者去除电荷。 [0009] In addition, high voltage is necessary to retain charge in the floating gate or removal of charges. 另外,保留或去除电荷需要相对较长的时间,并且不能容易地增加写入和擦除的速度。 Further, retaining or removing the charge takes a relatively long time, and can not easily increase the speed of writing and erasing.

[0010] [参考资料] [0010] [Reference]

[0011] [专利文件] [0011] [Patent Document]

[0012] [专利文件1] [0012] [Patent Document 1]

[0013] 日本公开专利申请No.S57-105889 [0013] Japanese Patent Application Publication No.S57-105889

发明内容 SUMMARY

[0014] 考虑到以上问题,本发明的实施例的目的在于提供一种半导体装置,该半导体装置具有能够在未供电的状态下保留存储的内容并且对写入的次数没有限制的新型结构。 [0014] In view of the above problems, an object of embodiments of the present invention is to provide a semiconductor device having the semiconductor device capable of retaining stored in the unpowered state and the contents of the new structure is not limited to the number of writes.

[0015] 本发明的实施例是具有叠层的半导体装置,该叠层包括使用氧化物半导体的晶体管和使用除氧化物半导体之外的材料的晶体管。 Example [0015] The present invention is a semiconductor device having a stack, the stack comprising a transistor using an oxide semiconductor and a transistor using a material other than an oxide semiconductor. 例如,该半导体装置能够采用下面的结构。 For example, the semiconductor device can employ the following configuration.

[0016] 本发明的实施例是一种半导体装置,包括:源极线;位线;第一信号线;多个第二信号线;多个字线;多个存储单元,在源极线和位线之间彼此并联;用于第二信号线和字线的驱动器电路,地址信号输入到该驱动器电路,并且该驱动器电路驱动所述多个第二信号线和所述多个字线,从而从所述多个存储单元选择由地址信号指定的存储单元;用于第一信号线的驱动器电路,选择多个写入电位中的任何一个写入电位并将其输出到第一信号线;读取电路,位线的电位和多个参考电位输入到该读取电路,并且该读取电路比较位线的电位和所述多个参考电位以读出数据;和电位产生电路,产生所述多个写入电位和所述多个参考电位并将其提供给用于第一信号线的驱动器电路和读取电路。 Example [0016] The present invention is a semiconductor device, comprising: a source line; bit lines; a first signal line; a plurality of second signal lines; a plurality of word lines; a plurality of memory cells, the source line and each other in parallel between the bit lines; a second circuit for driving signal lines and word lines, the address signal is input to the drive circuit and the drive circuit drives the plurality of second signal lines and said plurality of word lines, whereby selecting from the plurality of memory locations designated by the address signal; a first signal line driver circuit selects a plurality of write any writing potential potentials and outputs it to a first signal line; read extracting circuit, and a plurality of bit line potential to the reference voltage input of the reading circuit, and comparing the potential of the bit line and said plurality of circuit reference potential to read the read data; and a potential generation circuit, generating said plurality a plurality of writing potential and the reference potential and supplies it to a first signal line driver circuit and the reading circuit. 所述多个存储单元之一包括:第一晶体管,包括第一栅电极、第一源电极和第一漏电极;第二晶体管,包括第二栅电极、第二源电极和第二漏电极;和第三晶体管,包括第三栅电极、第三源电极和第三漏电极。 One of said plurality of memory cells comprises: a first transistor including a first gate electrode, first source electrode and first drain electrode; a second transistor including a second gate electrode, a second source electrode and second drain electrode; and a third transistor including a third gate electrode, a third source and a third drain electrode. 第一晶体管布置在包括半导体材料的衬底上。 A first transistor disposed on the substrate comprises a semiconductor material. 第二晶体管包括氧化物半导体层。 The second transistor includes an oxide semiconductor layer. 第一栅电极以及第二源电极和第二漏电极中的一个彼此电连接。 A first gate electrode and the second source electrode and a second drain electrode electrically connected to each other. 源极线和第一源电极彼此电连接。 A first source line and a source electrode electrically connected to each other. 第一漏电极和第三源电极彼此电连接。 A first drain electrode and a third source electrode electrically connected to each other. 位线和第三漏电极彼此电连接。 The third bit line and a drain electrode electrically connected to each other. 第一信号线以及第二源电极和第二漏电极中的另一个彼此电连接。 A first signal line and the other second source electrode and second drain electrode electrically connected to each other. 所述多个第二信号线之一和第二栅电极彼此电连接。 One of said plurality of second signal lines and the second gate electrode electrically connected to each other. 所述多个字线之一和第三栅电极彼此电连接。 One of said plurality of word lines and a third gate electrode electrically connected to each other.

[0017] 另外,在以上结构中,半导体装置还包括:电容器,电连接到第一栅电极以及所述第二源电极和第二漏电极中的一个。 [0017] Further, in the above structure, the semiconductor device further comprising: a capacitor electrically connected to the first gate electrode and the second source electrode and a drain electrode of a second.

[0018] 本发明的实施例是一种半导体装置,包括:源极线;位线;第一信号线;多个第二信号线;多个字线;多个存储单元,在源极线和位线之间彼此并联;用于第二信号线和字线的驱动器电路,地址信号输入到该驱动器电路,并且该驱动器电路驱动所述多个第二信号线和所述多个字线,从而从所述多个存储单元选择由地址信号指定的存储单元;用于第一信号线的驱动器电路,选择多个写入电位中的任何一个写入电位并将其输出到第一信号线;读取电路,位线的电位和多个参考电位输入到该读取电路,该读取电路包括参考存储单元,并且该读取电路比较指定的存储单元的电导和参考存储单元的电导以读出数据;和电位产生电路,产生所述多个写入电位和所述多个参考电位并将其提供给用于第一信号线的驱动器电路和读取电路。 Example [0018] The present invention is a semiconductor device, comprising: a source line; bit lines; a first signal line; a plurality of second signal lines; a plurality of word lines; a plurality of memory cells, the source line and each other in parallel between the bit lines; a second circuit for driving signal lines and word lines, the address signal is input to the drive circuit and the drive circuit drives the plurality of second signal lines and said plurality of word lines, whereby selecting from the plurality of memory locations designated by the address signal; a first signal line driver circuit selects a plurality of write any writing potential potentials and outputs it to a first signal line; read extracting circuit, and a plurality of bit line potential to the reference voltage input of the reading circuit, the reading circuit comprises a reference memory cell, and the conductivity and conductivity reference memory cell of a memory cell specified by the reading circuit for comparing the readout data to ; potential generation circuit and generating said plurality of writing potential and the plurality of reference potential and supplies it to a first signal line driver circuit and the reading circuit. 所述多个存储单元之一包括:第一晶体管,包括第一栅电极、第一源电极和第一漏电极;第二晶体管,包括第二栅电极、第二源电极和第二漏电极;和第三晶体管,包括第三栅电极、第三源电极和第三漏电极。 One of said plurality of memory cells comprises: a first transistor including a first gate electrode, first source electrode and first drain electrode; a second transistor including a second gate electrode, a second source electrode and second drain electrode; and a third transistor including a third gate electrode, a third source and a third drain electrode. 第一晶体管布置在包括半导体材料的衬底上。 A first transistor disposed on the substrate comprises a semiconductor material. 第二晶体管包括氧化物半导体层。 The second transistor includes an oxide semiconductor layer. 第一栅电极以及第二源电极和第二漏电极中的一个彼此电连接。 A first gate electrode and the second source electrode and a second drain electrode electrically connected to each other. 源极线和第一源电极彼此电连接。 A first source line and a source electrode electrically connected to each other. 第一漏电极和第三源电极彼此电连接。 A first drain electrode and a third source electrode electrically connected to each other. 位线和第三漏电极彼此电连接。 The third bit line and a drain electrode electrically connected to each other. 第一信号线以及第二源电极和第二漏电极中的另一个彼此电连接。 A first signal line and the other second source electrode and second drain electrode electrically connected to each other. 所述多个第二信号线之一和第二栅电极彼此电连接。 One of said plurality of second signal lines and the second gate electrode electrically connected to each other. 所述多个字线之一和第三栅电极彼此电连接。 One of said plurality of word lines and a third gate electrode electrically connected to each other.

[0019] 本发明的实施例是一种半导体装置,包括:源极线;位线;第一信号线;多个第二信号线;多个字线;多个存储单元,在源极线和位线之间彼此并联;用于第二信号线和字线的驱动器电路,地址信号和多个参考电位输入到该驱动器电路,该驱动器电路驱动所述多个第二信号线和所述多个字线,从而从所述多个存储单元选择由地址信号指定的存储单元,并且该驱动器电路选择所述多个参考电位中的任何一个参考电位并将其输出到从字线选择的一个字线;用于第一信号线的驱动器电路,选择多个写入电位中的任何一个写入电位并将其输出到第一信号线;读取电路,连接到位线并通过读出指定的存储单元的电导来读出数据;和电位产生电路,产生所述多个写入电位和所述多个参考电位并将其提供给用于第一信号线的驱动器电路和读取电路。 Example [0019] The present invention is a semiconductor device, comprising: a source line; bit lines; a first signal line; a plurality of second signal lines; a plurality of word lines; a plurality of memory cells, the source line and each other in parallel between the bit lines; a second circuit for driving signal lines and word lines, a plurality of address signal and a reference voltage input to the drive circuit, the drive circuit drives the plurality of second signal lines and a plurality of said a word line to select memory cells specified by address signals from said plurality of memory cells, and the driver circuit selects said any of a plurality of reference potential in the reference potential and outputs it to a selected word line from the word line ; a first circuit for driving the signal line, selecting a plurality of write any writing potential and outputs it to the first signal line potential; a reading circuit connected to the bit line and reads out the specified memory cell conductance reading data; potential generation circuit and generating said plurality of writing potential and the plurality of reference potential and supplies it to a first signal line driver circuit and the reading circuit. 所述多个存储单元之一包括:第一晶体管,包括第一栅电极、第一源电极和第一漏电极;第二晶体管,包括第二栅电极、第二源电极和第二漏电极;和电容器。 One of said plurality of memory cells comprises: a first transistor including a first gate electrode, first source electrode and first drain electrode; a second transistor including a second gate electrode, a second source electrode and second drain electrode; and capacitors. 第一晶体管布置在包括半导体材料的衬底上。 A first transistor disposed on the substrate comprises a semiconductor material. 第二晶体管包括氧化物半导体层。 The second transistor includes an oxide semiconductor layer. 第一栅电极、第二源电极和第二漏电极中的一个以及电容器的一个电极彼此电连接。 A first gate electrode, a source electrode of the second electrode and the second drain electrode, and a capacitor electrically connected to each other. 源极线和第一源电极彼此电连接。 A first source line and a source electrode electrically connected to each other. 位线和第一漏电极彼此电连接。 A first bit line and a drain electrode electrically connected to each other. 第一信号线以及第二源电极和第二漏电极中的另一个彼此电连接。 A first signal line and the other second source electrode and second drain electrode electrically connected to each other. 所述多个第二信号线之一和第二栅电极彼此电连接。 One of said plurality of second signal lines and the second gate electrode electrically connected to each other. 所述多个字线之一和电容器的另一个电极彼此电连接。 The other electrode of one of the plurality of word lines and a capacitor electrically connected to each other.

[0020] 在以上结构中,第一晶体管包括:沟道形成区域,布置在所述包括半导体材料的衬底上;杂质区域,沟道形成区域布置在该杂质区域之间;第一栅极绝缘层,位于沟道形成区域上方;第一栅电极,位于第一栅极绝缘层上方;以及第一源电极和第一漏电极,分别电连接到杂质区域。 [0020] In the above structure, the first transistor comprising: a channel forming region, disposed in said substrate comprises a semiconductor material; impurity region, a channel region formed between the impurity region is disposed; a first gate insulating layer located above the channel forming region; a first gate electrode located above the first gate insulating layer; and a first source electrode and first drain electrode respectively electrically connected to the impurity region.

[0021] 另外,在以上结构中,第二晶体管包括:第二栅电极,位于所述包括半导体材料的衬底上方;第二栅极绝缘层,位于第二栅电极上方;氧化物半导体层,位于第二栅极绝缘层上方;以及第二源电极和第二漏电极,电连接到氧化物半导体层。 [0021] Further, in the above structure, the second transistor comprising: a second gate electrode located above said substrate comprising a semiconductor material; a second gate insulating layer over the second gate electrode; an oxide semiconductor layer, located above the second gate insulating layer; and a second source electrode and second drain electrode electrically connected to the oxide semiconductor layer.

[0022] 另外,在以上结构中,第三晶体管包括:沟道形成区域,布置在所述包括半导体材料的衬底上;杂质区域,沟道形成区域布置在该杂质区域之间;第三栅极绝缘层,位于沟道形成区域上方;第三栅电极,位于第三栅极绝缘层上方;以及第三源电极和第三漏电极,分别电连接到杂质区域。 [0022] Further, in the above structure, the third transistor comprising: forming a channel region, disposed in said substrate comprises a semiconductor material; impurity region, a channel region formed between the impurity region is disposed; the third gate a gate insulating layer, located above the channel forming region; a third gate electrode over the third gate insulating layer; and a third source and a third drain electrode respectively electrically connected to the impurity region.

[0023] 另外,在以上结构中,作为包括半导体材料的衬底,优选地使用单晶半导体衬底。 [0023] Further, in the above structure, the substrate comprises a semiconductor material, preferably single crystal semiconductor substrate. 特别地,半导体材料优选地是硅。 In particular, the semiconductor material is preferably silicon. 另外,SOI衬底可用作包括半导体材料的衬底。 Further, SOI substrate comprises a substrate of a semiconductor material may be used.

[0024] 另外,在以上结构中,氧化物半导体层优选地包括基于In-Ga-Zn-O的氧化物半导体材料。 [0024] Further, in the above structure, the oxide semiconductor layer preferably includes an oxide semiconductor material based on In-Ga-Zn-O's. 特别地,氧化物半导体层优选地包括In2Ga2ZnO7的晶体。 In particular, the oxide semiconductor layer preferably comprises In2Ga2ZnO7 crystals. 另外,氧化物半导体层中的氢浓度优选地小于或等于5XIO19原子/cm3。 Further, the hydrogen concentration in the oxide semiconductor layer is preferably less than or equal 5XIO19 atoms / cm3. 第二晶体管的截止电流优选地小于或等于IXKT13A。 Off current of the second transistor is preferably less than or equal IXKT13A.

[0025] 另外,在以上结构中,第二晶体管能够布置在与第一晶体管重叠的区域中。 [0025] Further, in the above structure, the second transistor can be disposed in the overlapping region of the first transistor.

[0026] 需要注意的是,在本说明书等中,在部件之间的物理关系的描述中,"在…上方" 和"在…下方"未必分别意味着"直接在…上面"和"直接在…下面"。 [0026] Note that, in this specification and the like, in the description of the physical relationship between the components, "... in the above" and "below ..." are not necessarily mean "directly above ..." and "directly …below". 例如,"在栅极绝缘层上方的第一栅电极"的表达可表不这样的情况:另一部件位于栅极绝缘层和第一栅电极之间。 For example, the expression "over the gate insulating layer, a first gate electrode" in the table may not be such a situation: a further part positioned between the gate insulating layer and the first gate electrode. 另外,术语"在…上方"和"在…下方"仅为了解释的方便而使用,并且除非另外指出, 否则它们能够互换。 In addition, the term "... above" and "below ..." explanation only used for convenience, and unless otherwise indicated, they can be interchanged.

[0027] 在本说明书等中,术语"电极"或"配线"不限制部件的功能。 [0027] In the present specification and the like, the term "electrode" or "wiring" does not limit the member function. 例如,"电极"能够用作"配线"的一部分,并且"配线"能够用作"电极"的一部分。 For example, an "electrode" can be used as part of the "wiring", and "wiring" can be used as part of the "electrode". 另外,术语"电极"或"配线" 也能够表示例如多个"电极"和"配线"的组合。 Further, the term "electrode" or "wiring" can be represented, for example, a combination of a plurality of "electrode" and "wiring" of.

[0028]另外,例如,当采用具有不同极性的晶体管或者电流的方向在电路操作中改变时, "源极"和"漏极"的功能在一些情况下调换。 [0028] Further, for example, when a transistor having a different polarity or current changes in the direction of the circuit operation, a "source" and "drain" are exchanged in some cases. 因此,在本说明书中,术语"源极"和"漏极"能够调换。 Accordingly, in the present specification, the term "source" and "drain" can be replaced.

[0029]需要注意的是,在本说明书中,"电连接"的表达包括通过"具有任何电功能的物体"的电连接的情况。 [0029] Note that, in this specification, "electrically connected" includes the case where the expression by electroporation "of the object having any electric function" connection. 这里,对"具有任何电功能的物体"不存在特定的限制,只要该物体能够在该物体连接的部件之间实现电信号的发送和接收即可。 Here, the "object having any electric function" particular limitation does not exist, the object can be achieved as long as electrical connection between the object components can be transmitted and received.

[0030] 例如,在"具有任何电功能的物体"中,包括开关元件(诸如,晶体管)、电阻器、电感器、电容器和具有几种功能的其它元件以及电极和配线。 [0030] For example, in the "object having any electric function", including the switching element (such as a transistor), resistors, inductors, capacitors, and other elements and the electrodes and the wiring has several functions.

[0031] 通常,术语"SOI衬底"表示在绝缘表面上方具有硅半导体层的衬底。 [0031] Generally, the term "SOI substrate" means a substrate having an insulating surface above the silicon semiconductor layer. 在本说明书等中,术语"SOI衬底"还表示在绝缘表面上方具有使用除硅之外的材料的半导体层的衬底。 In the present specification and the like, the term "SOI substrate" also means a substrate having an insulating surface above the semiconductor layer using a material other than silicon. 也就是说,"SOI衬底"中所包括的半导体层不限于硅半导体层。 That is, the semiconductor layer "SOI substrate" is not limited to those included in the silicon semiconductor layer. 另外,"SOI衬底"中的衬底不限于半导体衬底(诸如,硅晶圆),并且可以是非半导体衬底(诸如,玻璃衬底、石英衬底、 蓝宝石衬底和金属衬底)。 Further, "the SOI substrate" is not limited to a semiconductor substrate, a substrate (such as silicon), and may be a non-semiconductor substrate (such as a glass substrate, a quartz substrate, a sapphire substrate and a metal substrate). 也就是说,"SOI衬底"还包括导电衬底和绝缘衬底,在所述导电衬底和绝缘衬底上方,使用半导体材料形成一层。 That is, "the SOI substrate" also includes a conductive substrate and an insulating substrate, a conductive substrate and over the insulating substrate, a layer formed using a semiconductor material. 另外,在本说明书等中,"半导体衬底"表示仅半导体材料的衬底,并且还表示包括半导体材料的材料的一般衬底。 Further, in the present specification and the like, "semiconductor substrate" means a substrate of a semiconductor material only, and further shows the general material of the semiconductor substrate comprises material. 换句话说,在本说明书等中,"S0I衬底"也被包括在"半导体衬底"的大类中。 In other words, in the present specification and the like, "SOI substrate" it is also included in the category "semiconductor substrate" in.

[0032] 本发明的一个实施例提供一种半导体装置,该半导体装置包括位于它的下部的使用除氧化物半导体之外的材料的晶体管和位于它的上部的使用氧化物半导体的晶体管。 An embodiment [0032] The present invention provides a semiconductor device, the semiconductor device includes a transistor including a material other than an oxide semiconductor, and its lower portion located in a transistor using an oxide semiconductor its upper portion.

[0033] 使用氧化物半导体的晶体管具有极低的断态电流;因此,通过使用该晶体管,存储内容能够保留极长时间。 [0033] using an oxide semiconductor transistor having a low off-state current; Thus, by using the transistor, a very long time to retain the stored contents. 也就是说,刷新操作能够变得不必要或者刷新操作的频率能够显著减小,从而功耗能够充分地减小。 That is, the refresh operation can be made unnecessary or the frequency of refresh operation can be reduced significantly, so that power consumption can be sufficiently reduced. 另外,即使在未供电的情况下,存储内容也能够长时间保留。 Further, even when power is not supplied, the stored contents can be retained for a long time.

[0034]另外,对于写入数据而言不需要高电压并且不存在元件的劣化的问题。 [0034] Further, for purposes of the write data does not require high voltage and the problem of deterioration of the element is present. 另外,根据晶体管的导通状态和截止状态执行数据的写入,从而能够容易地实现高速操作。 Further, writing of data to perform the ON state and OFF state of the transistor, whereby high speed operation can be easily realized. 另外,存在这样的优点:当执行数据的重写入时,不需要用于擦除以前数据的操作。 Further, there is an advantage: When the rewriting of data is performed in, the operation does not need to erase the previous data.

[0035]另外,使用除氧化物半导体之外的材料的晶体管能够工作于足够高的速度,由此能够以高速读出存储内容。 [0035] Further, using a material other than an oxide semiconductor transistor capable of operating at sufficiently high speed, it is possible to read out the stored content at a high speed.

[0036]因此,通过提供使用除氧化物半导体材料之外的材料的晶体管和使用氧化物半导体的晶体管的组合,能够实现具有前所未有的特征的半导体装置。 [0036] Thus, by providing the use of a material other than an oxide semiconductor material, a combination of a transistor and a transistor using an oxide semiconductor, a semiconductor device can be realized with unprecedented features.

附图说明 BRIEF DESCRIPTION

[0037] 在附图中: [0037] In the drawings:

[0038] 图1是用于解释半导体装置的电路图; [0038] FIG. 1 is a circuit diagram for explaining a semiconductor device;

[0039] 图2A和2B分别是用于解释半导体装置的截面图和俯视图; [0039] FIGS. 2A and 2B are a cross-sectional view for explaining a semiconductor device and a top view;

[0040] 图3A至3H是用于解释半导体装置的截面图; [0040] Figures 3A to 3H are sectional views for explaining a semiconductor device;

[0041] 图4A至4G是用于解释半导体装置的制造步骤的截面图; [0041] FIGS 4A to 4G are cross-sectional view to explain a manufacturing step of the semiconductor device;

[0042] 图5A至是用于解释半导体装置的制造步骤的截面图; [0042] FIG 5A is a cross-sectional view to explain the steps for manufacturing a semiconductor device;

[0043] 图6是用于解释半导体装置的截面图; [0043] FIG. 6 is a sectional view for explaining a semiconductor device;

[0044] 图7A和7B是用于解释半导体装置的截面图; [0044] FIGS. 7A and 7B are sectional views for explaining a semiconductor device;

[0045] 图8A和8B是用于解释半导体装置的截面图; [0045] FIGS. 8A and 8B are a cross-sectional view for explaining a semiconductor device;

[0046] 图9A和9B是用于解释半导体装置的截面图; [0046] FIGS. 9A and 9B are a cross-sectional view for explaining a semiconductor device;

[0047] 图10是用于解释存储元件的电路图; [0047] FIG. 10 is a circuit diagram for explaining a memory element;

[0048] 图11是用于解释半导体装置的电路图; [0048] FIG. 11 is a circuit diagram for explaining a semiconductor device;

[0049] 图12是用于解释驱动器电路的电路图; [0049] FIG. 12 is a circuit diagram for explaining a driver circuit;

[0050] 图13是用于解释驱动器电路的电路图; [0050] FIG. 13 is a circuit diagram for explaining a driver circuit;

[0051] 图14是用于解释驱动器电路的电路图; [0051] FIG. 14 is a circuit diagram for explaining a driver circuit;

[0052] 图15是用于解释驱动器电路的电路图; [0052] FIG. 15 is a circuit diagram for explaining a driver circuit;

[0053] 图16A和16B是用于解释操作的时序图; [0053] FIGS. 16A and 16B are timing charts for explaining the operation;

[0054] 图17是用于解释半导体装置的电路图; [0054] FIG. 17 is a circuit diagram for explaining the semiconductor device;

[0055] 图18是用于解释半导体装置的电路图; [0055] FIG. 18 is a circuit diagram for explaining the semiconductor device;

[0056] 图19是用于解释半导体装置的电路图; [0056] FIG. 19 is a circuit diagram for explaining the semiconductor device;

[0057] 图20是用于解释驱动器电路的电路图; [0057] FIG. 20 is a circuit diagram for explaining a driver circuit;

[0058] 图21是用于解释操作的时序图; [0058] FIG. 21 is a timing chart for explaining the operation;

[0059] 图22是用于解释存储元件的电路图; [0059] FIG. 22 is a circuit diagram for explaining a memory element;

[0060] 图23是用于解释半导体装置的电路图; [0060] FIG. 23 is a circuit diagram for explaining the semiconductor device;

[0061]图24是用于解释驱动器电路的电路图; [0061] FIG. 24 is a circuit diagram for explaining a driver circuit;

[0062] 图25是用于解释驱动器电路的电路图; [0062] FIG. 25 is a circuit diagram for explaining a driver circuit;

[0063] 图26是用于解释操作的时序图; [0063] FIG. 26 is a timing chart for explaining the operation;

[0064] 图27是显示节点A的电位和字线的电位之间的关系的曲线图; [0064] FIG. 27 is a graph showing the relationship between the potential and the potential of the node A word line display;

[0065] 图28是用于解释驱动器电路的电路图; [0065] FIG. 28 is a circuit diagram for explaining a driver circuit;

[0066] 图29是用于解释操作的时序图; [0066] FIG. 29 is a timing chart for explaining the operation;

[0067] 图30A至30F表示电子设备; [0067] FIGS. 30A to 30F indicates an electronic device;

[0068] 图31是包括氧化物半导体的晶体管的截面图; [0068] FIG. 31 is a sectional view of a transistor including an oxide semiconductor;

[0069]图32是沿图31的线A-A'获得的能带图(示意图); [0069] FIG 32 is an energy band diagram (schematic) of FIG. 31 along line A-A 'obtained;

[0070] 图33A是显示在正电压(+VsX))施加于栅极(GEl)的状态下的示图,并且图33B是显示在负电压(_\〈0)施加于栅极(GEl)的状态下的示图。 [0070] FIG. 33A is a positive voltage (+ VsX)) is applied to the gate in a state shown in FIG. (GEL), and FIG 33B is a negative voltage (_ \ <0) is applied to the gate (GEL) under a state shown in FIG.

[0071]图34显示真空能级和金属的功函数((K)之间的关系以及真空能级和氧化物半导体的电子亲和势(X)之间的关系。 [0071] FIG. 34 is a relationship between the vacuum level and the relationship between metal work function ((K) and the vacuum level and an oxide semiconductor electron affinity (X) is displayed.

具体实施方式 Detailed ways

[0072] 以下,将参照附图描述本发明的实施例的例子。 [0072] Hereinafter, examples of embodiments of the present invention are described with reference to the accompanying drawings. 需要注意的是,本发明不限于下面的描述,并且本领域技术人员将会容易地理解,在不脱离本发明的精神和范围的情况下能够以各种方法修改实施方式和细节。 It should be noted that the present invention is not limited to the following description, and those skilled in the art will readily appreciate that embodiments and details can be modified in various ways without departing from the spirit and scope of the invention. 因此,本发明不应解释为局限于下面的实施例的描述。 Accordingly, the present invention should not be construed as limited to the embodiments described below. [0073] 需要注意的是,为了容易理解,在附图等中表示的每个部件的位置、尺寸、范围等在一些情况下不是实际的位置、尺寸、范围等。 [0073] Note that, for easy understanding, the position of each component and the like shown in the drawings, the size, range, etc. In some cases, instead of the actual position, size, range, and the like. 因此,本发明不限于在附图等中公开的位置、 尺寸、范围等。 Accordingly, the present invention is not limited to the disclosed drawings like position, size, range, and the like.

[0074] 需要注意的是,在本说明书等中,使用序数(诸如,"第一"、"第二"和"第三")以便避免部件之间的混淆,但这些术语并不在数量方面限制部件。 [0074] Note that, in the use of ordinal numbers in this specification and the like (such as "first," "second" and "third") in order to avoid confusion between the members, but these terms are not limiting in the number of component.

[0075][实施例1] [0075] [Example 1]

[0076] 在这个实施例中,参照图1、图2A和2B、图3A至3H、图4A至4G、图5A至图6、 图7A和7B、图8A和8B以及图9A和9B描述根据公开的发明的一个实施例的半导体装置的结构和制造方法。 [0076] In this embodiment, with reference to FIGS. 1, 2A and 2B, FIGS. 3A to 3H, 4A to 4G, 5A to FIG. 6, 7A and 7B, 8A and 8B and FIGS. 9A and 9B described in accordance with a structure and manufacturing method of the semiconductor device according to an embodiment of the disclosed invention.

[0077]〈半导体装置的电路结构〉 [0077] <circuit configuration of a semiconductor device>

[0078] 图1表示半导体装置的电路结构的例子。 [0078] FIG. 1 shows an example of a circuit configuration of a semiconductor device. 半导体装置包括使用除氧化物半导体之外的材料形成的晶体管160和使用氧化物半导体形成的晶体管162。 The semiconductor device formed using a material including an oxide semiconductor other than the transistor 160 and a transistor 162 formed using an oxide semiconductor. 需要注意的是,标记"0S"添加到图1中的晶体管162以显示晶体管162是使用氧化物半导体(OS)形成的。 Note that the marker "0S" added to the transistor 162 in FIG. 1 to show the transistor 162 is an oxide semiconductor (OS) is formed.

[0079] 这里,晶体管160的栅电极电连接到晶体管162的源电极和漏电极中的一个。 [0079] Here, the gate electrode of the transistor 160 is connected to a source electrode and a drain electrode of the transistor 162. 第一配线(表示为"第一线"并且也称为源极线)和第二配线(表示为"第二线"并且也称为位线)分别电连接到晶体管160的源电极和晶体管160的漏电极。 A first wire (denoted as "line" and also known as source lines) and the second wiring (denoted as "second-line" and is also referred to as bit line) are electrically connected to the source electrode of the transistor 160 and the transistor the drain electrode 160. 另外,第三配线(表示为"第三线"并且也称为第一信号线)和第四配线(表示为"第四线"并且也称为第二信号线)分别电连接到晶体管162的源电极和漏电极中的另一个以及晶体管162的栅电极。 Further, a third line (denoted as "third line", and also referred to as a first signal line) and a fourth line (denoted as "a fourth line" and is also referred to as a second signal line) are electrically connected to the transistor 162 another transistor 162 and the gate electrode of the source electrode and the drain electrode.

[0080] 使用除氧化物半导体之外的材料形成的晶体管160能够高速工作。 [0080] using a material other than an oxide semiconductor can be formed of transistor 160 high-speed operation. 因此,通过使用晶体管160,能够实现存储内容的高速读取等。 Thus, by using the transistor 160, it is possible to realize high-speed reading of the stored content and the like. 另外,在使用氧化物半导体形成的晶体管162中,截止电流极小。 Further, the transistor 162 is formed using an oxide semiconductor, the off current is very small. 因此,当晶体管162截止时,晶体管160的栅电极的电位能够保留极长时间。 Thus, when the transistor 162 is turned off, the potential of the gate electrode of transistor 160 to retain a very long time. 另外,在使用氧化物半导体形成的晶体管162中,不太可能引起短沟道效应,这是有益的。 Further, the transistor 162 formed using an oxide semiconductor, is unlikely to cause a short channel effect, which is beneficial.

[0081] 栅电极的电位能够保留极长时间的优点使得能够如下所述执行数据的写入、保持和读取。 [0081] The potential of the gate electrode is extremely long to retain the advantage of making it possible to perform the following write data, and read retention.

[0082] 首先描述数据的写入和保持。 [0082] First, writing and holding of data is described. 首先,第四配线的电位设置为使晶体管162导通的电位,由此使晶体管162处于导通状态。 First, the potential of the fourth wiring is set to the potential of the transistor 162 is turned on, whereby the transistor 162 in a conducting state. 相应地,第三配线的电位施加于晶体管160的栅电极(数据的写入)。 Accordingly, the potential of the third wiring is applied to the gate electrode of the transistor 160 (writing data). 其后,第四配线的电位设置为使晶体管162截止的电位,由此使晶体管162处于截止状态;相应地,保持晶体管160的栅电极的电位(数据的保持)。 Thereafter, the potential of the fourth wiring is set to a potential that the transistor 162 is turned off, whereby the transistor 162 in an off state; accordingly, the holding potential of the gate electrode of the transistor 160 (held data).

[0083] 由于晶体管162的截止电流极小,所以晶体管160的栅电极的电位长时间保留。 [0083] Since the current of the transistor 162 is extremely small, the potential of the gate electrode of the transistor 160 is retained for a long time. 例如,当晶体管160的栅电极的电位是使晶体管160导通的电位时,晶体管160的导通状态长时间保留。 For example, when the potential of the gate electrode of the transistor 160 is turned on so that the potential of the transistor 160, the conduction state of the transistor 160 is retained for a long time. 当晶体管160的栅电极的电位是使晶体管160截止的电位时,晶体管160的截止状态长时间保留。 When the potential of the gate electrode of the transistor 160 is turned off so that the potential of the transistor 160, the off state of the transistor 160 is retained for a long time.

[0084] 接下来,描述数据的读取。 [0084] Next, the read data. 当如上所述保持晶体管160的导通状态或截止状态并且给定电位(低电位)施加于第一配线时,第二配线的电位的值根据晶体管160的状态(导通状态或截止状态)而不同。 When the state is kept turned on or off state of the transistor 160 as described above and a given potential (low potential) is applied to the first wiring, the second wiring value of the potential of the transistor 160 depending on the state (ON state or OFF state ) is different. 例如,当晶体管160处于导通状态时,第二配线的电位通过受第一配线的电位影响而降低。 For example, when the transistor 160 in a conducting state, the potential of the second wiring is reduced by the influence of the potential of the first wiring. 另一方面,当晶体管160处于截止状态时,第二配线的电位不变。 On the other hand, when the transistor 160 is in the off state, the second constant potential wiring.

[0085] 以这种方式,通过在保持数据的状态下比较第一配线的电位和第二配线的电位, 能够读出数据。 [0085] In this manner, by comparing the potential of the potential of the first wiring and the second wiring in the state of holding data, data can be read.

[0086] 然后,描述数据的重写入。 [0086] Then, description data rewritten. 以类似于上述数据的写入和保持的方式执行数据的重写入。 In a manner similar to the above-described writing and holding of data is performed the data is rewritten. 也就是说,第四配线的电位设置为使晶体管162导通的电位,由此使晶体管162处于导通状态。 That is, the potential of the fourth wiring is set to the potential of the transistor 162 is turned on, whereby the transistor 162 in a conducting state. 相应地,第三配线的电位(与新数据相关的电位)施加于晶体管160的栅电极。 Accordingly, the potential of the third wiring (associated with the new data potential) is applied to the gate electrode of the transistor 160. 其后,第四配线的电位设置为使晶体管162截止的电位,由此使晶体管162处于截止状态; 相应地,保持新数据。 Thereafter, the potential of the fourth wiring is set to a potential that the transistor 162 is turned off, whereby the transistor 162 in an off state; accordingly, new data is kept.

[0087]如上所述,在根据公开的发明的一个实施例的半导体装置中,通过再次执行数据的写入能够直接重写入数据。 [0087] As described above, in the semiconductor device in accordance with one embodiment of the disclosed embodiment of the invention, data can be directly rewritten by the write data is performed again. 因此不需要在闪速存储器等中需要的擦除操作;因此,能够抑制由于擦除操作导致的操作速度的降低。 Erase operation is not required in the flash memory required; thus, the erasing operation can be suppressed since the resulting reduction operation speed. 换句话说,实现了半导体装置的高速操作。 In other words, to achieve a high speed operation of the semiconductor device.

[0088] 需要注意的是,在以上描述中,使用了使用电子作为载流子的n型晶体管(n沟道晶体管);然而,当然能够使用以空穴作为载流子的P沟道晶体管替代n沟道晶体管。 [0088] Note that, in the above description, the n-type transistor (n-channel transistor) using electrons as carriers; however, of course possible to use P-channel transistors holes as carriers alternative n-channel transistor.

[0089]〈半导体装置的平面结构和截面结构〉 [0089] <planar structure and a sectional structure of a semiconductor device>

[0090] 以上半导体装置的结构的例子表示在图2A和2B中。 [0090] Examples of the above configuration of the semiconductor device shown in FIGS. 2A and 2B. 图2A和2B分别是半导体装置的截面图及其俯视图。 2A and 2B are sectional views and a top view of the semiconductor device of FIG. 这里,图2A对应于沿图2B的线A1-A2和线B1-B2获得的截面。 Here, FIG. 2A corresponds to the section and line B1-B2 in FIG. 2B along line obtained by the A1-A2. 图2A和2B中表示的半导体装置包括位于下部的使用除氧化物半导体之外的材料形成的晶体管160和位于上部的使用氧化物半导体形成的晶体管162。 Transistors 160 and the upper portion of an oxide semiconductor Figures 2A and 2B show a semiconductor device includes a lower portion using a material other than an oxide semiconductor formed by forming 162. 需要注意的是,虽然n沟道晶体管被描述为晶体管160和162,但可采用p沟道晶体管。 It is noted that, although described as being n-channel transistor 162 and transistor 160, p-channel transistor may be employed. 特别地,p沟道晶体管能够用作晶体管160。 Specifically, p-channel transistor 160 can be used as the transistor.

[0091] 晶体管160包括:沟道形成区域116,针对包含半导体材料的衬底100提供;杂质区域114和高浓度杂质区域120,沟道形成区域116被夹在杂质区域114之间,并且沟道形成区域116被夹在高浓度杂质区域120之间(杂质区域114和高浓度杂质区域120也统称为杂质区域);栅极绝缘层l〇8a,布置在沟道形成区域116上方;栅电极110a,布置在栅极绝缘层l〇8a上方;以及源或漏电极130a和源或漏电极130b,电连接到杂质区域114。 [0091] The transistor 160 includes: a channel forming region 116, for providing a substrate 100 comprising a semiconductor material; impurity region 114 and the high concentration impurity region 120, a channel formation region 116 sandwiched between the impurity regions 114 and the channel forming region 116 is sandwiched between a 120 (impurity region 114 and the high concentration impurity region 120 is also referred to as an impurity region) of high impurity concentration region; l〇8a a gate insulating layer disposed over the region 116 is formed in the channel; the gate electrode 110a , l〇8a disposed above the gate insulating layer; and a source or drain electrode 130a and the source or drain electrode 130b, is electrically connected to the impurity region 114.

[0092] 这里,为栅电极IlOa的侧表面提供侧壁绝缘层118。 [0092] Here, the sidewall insulating layer to provide a side surface of the gate electrode 118 of IlOa. 另外,在当在俯视图中观看时衬底100的不与侧壁绝缘层118重叠的区域中,布置高浓度杂质区域120,并且另外的金属化合物区域124布置在高浓度杂质区域120上方。 Further, when viewed in the plan view area 118 does not overlap the sidewalls of the insulating layer of the substrate 100, a high concentration impurity region 120 is arranged, and above the additional metal compound region 124 is disposed in a high concentration impurity region 120. 在衬底100上,提供元件隔离绝缘层106 以包围晶体管160,并且提供层间绝缘层126和层间绝缘层128以覆盖晶体管160。 On the substrate 100, the element isolation insulating layer 106 is provided to surround the transistor 160, and an interlayer insulating layer 126 and the interlayer insulating layer 128 to cover the transistor 160. 源或漏电极130a和源或漏电极130b通过形成在层间绝缘层126和128中的开口而电连接到金属化合物区域124。 Source or drain electrode 130a and the source or drain electrode 130b interlayer insulating layer 126 and the opening 128 are electrically connected to the metal region 124 is formed in the compound. 换句话说,源或漏电极130a和源或漏电极130b经金属化合物区域124 电连接到高浓度杂质区域120和杂质区域114。 In other words, the source or drain electrode 130a and the source or drain electrode 130b connected to the high concentration impurity region 120 and the impurity region 114 through the region 124 is electrically metal compound. 另外,栅电极IlOa电连接到以类似于源或漏电极130a和源或漏电极130b的方式提供的电极130c。 The gate electrode is electrically connected to the IlOa similar to the source or drain electrode 130c and the source electrode or the drain electrode 130b is provided by way of 130a.

[0093] 晶体管162包括:栅电极136d,布置在层间绝缘层128上方;栅极绝缘层138,布置在栅电极136d上方;氧化物半导体层140,布置在栅极绝缘层138上方;以及源或漏电极142a和源或漏电极142b,布置在氧化物半导体层140上方并电连接到氧化物半导体层140。 [0093] The transistor 162 includes: a gate electrode 136d, disposed above the interlayer insulating layer 128; a gate insulating layer 138 disposed over the gate electrode 136d; the oxide semiconductor layer 140 is disposed over the gate insulating layer 138; and a source and the source or drain electrode 142a or drain electrode 142b, is disposed over the oxide semiconductor layer 140 and electrically connected to the oxide semiconductor layer 140.

[0094] 这里,栅电极136d布置为嵌入在绝缘层132中,绝缘层132形成在层间绝缘层128 上方。 [0094] Here, the gate electrode 136d are arranged to be embedded in the insulating layer 132, the insulating layer 132 is formed over the interlayer insulating layer 128. 另外,类似于栅电极136d,形成电极136a、电极136b和电极136c并且它们分别与源或漏电极130a、源或漏电极130b和电极130c接触。 Further, similar to the gate electrode 136d, formed 136a, the electrode 136b and the electrode 136c and the electrode respectively to the source or drain electrode 130a, the source electrode or drain electrode 130b, and 130c, respectively.

[0095] 在晶体管162上方,提供保护绝缘层144并且保护绝缘层144与氧化物半导体层140的一部分接触。 [0095] In the above transistor 162, and the protective insulating layer 144 provided in contact with a portion of the protective insulating layer 144 and the oxide semiconductor layer 140. 层间绝缘层146布置在保护绝缘层144上方。 The interlayer insulating layer 146 is disposed over the protective insulating layer 144. 这里,在保护绝缘层144 和层间绝缘层146中,形成到达源或漏电极142a和源或漏电极142b的开口。 Here, in the inter-layer insulating layer 144 and the protective insulating layer 146 is formed reaching the source or drain electrode 142a and the source or drain electrode 142b of the opening. 在这些开口中,形成电极150d和电极150e,并且电极150d和电极150e分别与源或漏电极142a和源或漏电极142b接触。 In these openings, an electrode 150d and the electrode 150e, 150e and the electrode 150d and the electrode with the source or drain electrode 142a and the source or drain electrode in contact 142b. 类似于电极150d和电极150e,在位于栅极绝缘层138、保护绝缘层144 和层间绝缘层146中的开口中形成电极150a、电极150b和电极150c,并且电极150a、电极150b和电极150c分别与电极136a、电极136b和电极136c接触。 Electrodes 150d and 150e similar to the electrodes, forming the electrode 150a, the electrode 150b and the electrode 150c on the gate insulating layer 138, the protective insulating layer 146 in the opening of insulating layer 144 and the interlayer layer, and the electrode 150a, the electrode 150b and the electrode 150c, respectively, , the electrode 136b and the electrode 136c in contact with the electrode 136a.

[0096] 这里,氧化物半导体层140优选地是通过去除杂质(诸如,氢)而高度净化的氧化物半导体层。 [0096] Here, the oxide semiconductor layer 140 preferably by removing impurities (such as hydrogen) and highly purified oxide semiconductor layer. 具体地讲,氧化物半导体层140中的氢浓度小于或等于5XIO19原子/cm3,优选地小于或等于5XIO18原子/cm3,或者更优选地小于或等于5XIO17原子/cm3。 Specifically, the hydrogen concentration in the oxide semiconductor layer 140 is less than or equal to 5XIO19 atoms / cm3, preferably less than or equal 5XIO18 atoms / cm3, or more preferably less than or equal 5XIO17 atoms / cm3. 在通过充分减小氢浓度而高度净化的氧化物半导体层140中,载流子浓度小于或等于5X1014/cm3, 优选地小于或等于5XIO1Vcm3。 In the highly purified by sufficiently reducing the hydrogen concentration in the oxide semiconductor layer 140, the carrier concentration is less than or equal to 5X1014 / cm3, preferably less than or equal 5XIO1Vcm3. 以这种方式,通过使用通过充分减小氢浓度而高度净化并且是i型氧化物半导体或者基本上是i型氧化物半导体的氧化物半导体,能够获得具有极有利的截止电流特性的晶体管162。 In this manner, by use of highly purified by sufficiently reducing the hydrogen concentration and an i-type oxide semiconductor or a substantially i-type oxide semiconductor is an oxide semiconductor, a transistor 162 can be obtained having extremely favorable off-current characteristic. 例如,当漏极电压Vd是+IV或+IOV并且栅极电压V8处于-5V到-20V的范围时,截止电流小于或等于IX1(T13A。当使用通过充分减小氢浓度而高度净化的氧化物半导体层140并且减小了晶体管162的截止电流时,能够实现具有新型结构的半导体装置。需要注意的是,通过次级离子质谱法(SIMS)测量氧化物半导体层140中的氢浓度。 For example, when the drain voltage Vd is + IV or + IOV V8 and the gate voltage in the range -5V to -20V, the off current is less than or equal to IX1 (T13A. When used by sufficiently reducing the hydrogen peroxide concentration of highly purified when the semiconductor layer 140 is reduced and the current of the transistor 162, it is possible to realize a semiconductor device having a novel structure. It is noted that the hydrogen concentration in the oxide semiconductor layer 140 is measured by secondary ion mass spectrometry (the SIMS).

[0097] 另外,绝缘层152布置在层间绝缘层146上方。 [0097] Further, the insulating layer 152 is disposed over the interlayer insulating layer 146. 电极154a、电极154b、电极154c 和电极154d布置为嵌入在绝缘层152中。 Electrode 154a, an electrode 154b, an electrode 154c and the electrode 154d are arranged to be embedded in the insulating layer 152. 这里,电极154a与电极150a接触;电极154b与电极150b接触;电极154c与电极150c和150d接触;并且电极154d与电极150e接触。 Here, the contact electrode 154a and the electrode 150a; 150b contact electrode 154b and the electrode; electrode 154c and the electrode 150c and 150d contacts; 154d and the electrode in contact with the electrodes 150e.

[0098] 也就是说,在图2A和2B中表示的半导体装置中,晶体管160的栅电极IlOa经电极130c、136c、150c、154c和150d电连接到晶体管162的源或漏电极142a。 [0098] That is, the semiconductor device shown in FIGS. 2A and 2B, the gate electrode of transistor 160 via IlOa electrodes 130c, 136c, 150c, 154c and 150d is electrically connected to the source or drain electrode of transistor 162 142a.

[0099]〈用于制造半导体装置的方法〉 [0099] <Method for manufacturing a semiconductor device>

[0100] 接下来,将描述用于制造上述半导体装置的方法的例子。 [0100] Next, an example of the method for manufacturing the semiconductor device will be described. 首先,将参照图3A至3H 描述制造在下部的晶体管160的方法,然后将参照图4A至4G和图5A至描述制造在上部的晶体管162的方法。 First, with reference to FIGS. 3A to 3H a method of manufacturing the transistor 160 in the lower portion of the description, the method of the transistor 162 and 4A to 4G and 5A described with reference to FIG manufactured in the upper part.

[0101]〈用于制造在下部的晶体管的方法〉 [0101] <Method for manufacturing the transistor in the lower portion of>

[0102] 首先,准备包含半导体材料的衬底100 (参见图3A)。 [0102] First, a substrate 100 comprises (see FIG. 3A) of the semiconductor material. 作为包含半导体材料的衬底100,能够使用包含硅、碳化硅等的单晶半导体衬底或多晶半导体衬底,包含硅锗等的化合物半导体衬底,SOI衬底等。 As the substrate 100 comprises a semiconductor material, it can be used comprising a single crystal semiconductor substrate of silicon, silicon carbide, and the like or a polycrystalline semiconductor substrate, a silicon germanium or the like comprising a compound semiconductor substrate, the SOI substrate or the like. 这里,描述单晶硅衬底用作包含半导体材料的衬底100的例子。 Here, a single crystal silicon substrate used as an example of the substrate 100 comprises a semiconductor material. 需要注意的是,通常,术语"SOI衬底"表示在其绝缘表面上方具有硅半导体层的半导体衬底。 It is noted that, generally, the term "SOI substrate" indicates an insulating surface over which a semiconductor substrate having a silicon semiconductor layer. 在本说明书中,术语"SOI衬底"还表示在其绝缘表面上方具有使用除硅之外的材料的半导体层的衬底。 In the present specification, the term "SOI substrate" also indicates a substrate having an insulating surface over which a semiconductor layer using a material other than silicon. 换句话说,"SOI衬底"中所包括的半导体层不限于硅半导体层。 In other words, the semiconductor layer "SOI substrate" is not limited to those included in the silicon semiconductor layer. SOI衬底的例子包括在其诸如玻璃衬底的绝缘衬底上方具有半导体层的衬底,在半导体层和绝缘衬底之间具有绝缘层。 Examples of the SOI substrate comprises a substrate over which an insulating substrate such as a glass substrate having a semiconductor layer, an insulating layer between the semiconductor substrate and the insulating layer.

[0103] 在衬底100上方,保护层102用作用于形成元件隔离绝缘层的掩模(参见图3A)。 [0103] over the substrate 100, the protective layer 102 serves as a mask for forming the element isolation insulating layer (see FIG. 3A). 作为保护层102,例如,能够使用利用氧化硅、氮化硅、氧氮化硅等形成的绝缘层。 As the protective layer 102, for example, can be used with the insulating layer of silicon oxide, silicon nitride, silicon oxynitride, or the like. 需要注意的是,给出n型电导的杂质元素或者给出p型电导的杂质元素可在以上步骤之前或之后添加到衬底100,从而控制晶体管的阈值电压。 Note that, given n-type conductivity impurity element or a p-type conductivity is given an impurity element may be added before or after the above step 100 to the substrate, thereby controlling the threshold voltage of the transistor. 作为给出n型电导的杂质,当衬底100中所包含的半导体材料是硅时能够使用磷、砷等。 As the n-type conductivity impurity is given, when the semiconductor material contained in the substrate 100 can be used is silicon, phosphorus, arsenic and the like. 作为给出P型电导的杂质,例如能够使用硼、铝、 镓等。 As the P-type conductivity impurity is given, for example, boron, aluminum, gallium and the like.

[0104] 接下来,使用以上保护层102作为掩模,通过蚀刻去除衬底100的在未被保护层102覆盖的区域(暴露区域)中的部分。 [0104] Next, using the above protective layer 102 as a mask, portions of the substrate 100 in region 102 covered by layer unprotected (exposed region) is removed by etching. 因此,形成分离的半导体区域104(参见图3B)。 Thus, a semiconductor region 104 of the separation (see FIG. 3B). 对于蚀刻,优选地执行干法蚀刻,但能够执行湿法蚀刻。 For the etching, preferably dry etching, but wet etching can be performed. 根据待蚀刻的物体的材料能够合适地选择蚀刻气体和蚀刻剂。 Depending on the material of the object to be etched can be suitably selected etching gas and an etching agent.

[0105] 接下来,形成绝缘层以覆盖半导体区域104并且在与半导体区域104重叠的区域中选择性地去除该绝缘层,由此形成元件隔离绝缘层106 (参见图3B)。 [0105] Next, an insulating layer is formed to cover the semiconductor region 104 and the insulating layer is selectively removed in region 104 overlapping with the semiconductor region, thereby forming the element isolation insulating layer 106 (see FIG. 3B). 使用氧化硅、氮化硅、氧氮化硅等形成绝缘层。 Forming an insulating layer using silicon oxide, silicon nitride, silicon oxynitride and the like. 作为用于去除绝缘层的方法,存在蚀刻和抛光处理(诸如, CMP),并且能够采用它们中的任何一种。 As a method for removing the insulating layer, there are etching and polishing process (such as, the CMP), and can adopt any one of them. 需要注意的是,在形成半导体区域104之后或者在形成元件隔离绝缘层106之后去除保护层102。 It should be noted that the removal of the protective layer 102 or after forming the element isolation insulating layer 106 is formed after the semiconductor region 104.

[0106] 然后,绝缘层形成在半导体区域104上方,并且包含导电材料的层形成在绝缘层上方。 [0106] Then, an insulating layer is formed over the semiconductor region 104, and comprises a layer of conductive material is formed over the insulating layer.

[0107] 绝缘层稍后用作栅极绝缘层并优选地具有通过CVD法、溅射法等获得的使用包含氧化硅、氧氮化硅、氮化硅、氧化铪、氧化铝、氧化钽等的膜的单层结构或叠层结构。 [0107] insulating layer as a gate insulating layer and preferably has later obtained by using a CVD method, a sputtering method or the like including silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, etc. a single layer structure or a stacked structure of a film. 替代地, 可通过经高密度等离子体处理或热氧化处理氧化或氮化半导体区域104的表面获得以上绝缘层。 Alternatively, the insulating layer may be obtained by the above surface oxidation treatment or nitriding the semiconductor region 104 via a high-density plasma treatment or thermal oxidation. 可以使用例如稀有气体(诸如,He、Ar、Kr或Xe)和氧气、氧化氮、氨、氮气、氢气等的组合的混合气体执行高密度等离子体处理。 May be used, for example, a rare gas (such as, He, Ar, Kr, or Xe), and oxygen, nitrogen oxide, ammonia, nitrogen, hydrogen, a mixed gas composition and the like of performing high-density plasma treatment. 对于绝缘层的厚度没有特定的限制,但是厚度例如能够大于或等于Inm并且小于或等于100nm。 No special limitation on the thickness of the insulating layer, but the thickness of, for example, can be greater than or equal to and less than or equal to Inm 100nm.

[0108] 使用金属材料(诸如,铝、铜、钛、钽或钨)能够形成所述包含导电材料的层。 [0108] using a metal material (such as aluminum, copper, titanium, tantalum, or tungsten) capable of forming the layer containing a conductive material. 替代地,使用包含导电材料的半导体材料(诸如,多晶硅)可形成包含导电材料的层。 The semiconductor material (such as polysilicon) Alternatively, using a conductive material may form a layer containing a conductive material. 对用于形成包含导电材料的层的方法也没有特定的限制,并且可应用各种膜形成方法中的任何一种,诸如蒸发法、CVD法、溅射法和旋涂法。 There is no specific limitation on the method for forming a layer comprising a conductive material, and may use any of a variety of film formation methods, such as evaporation method, CVD method, a sputtering method and a spin coating method. 需要注意的是,在这个实施例中,描述使用金属材料形成包含导电材料的层的情况的例子。 Note that, in this embodiment, an example of the case of forming a layer comprising a metal material is described using a conductive material.

[0109] 其后,通过选择性地蚀刻绝缘层和包含导电材料的层,形成栅极绝缘层108a和栅电极IlOa(参见图3C)。 [0109] Subsequently, by selectively etching the insulating layer and a layer containing a conductive material, a gate insulating layer 108a and the gate electrode ILOA (see FIG. 3C).

[0110] 接下来,形成覆盖栅电极IlOa的绝缘层112 (参见图3C)。 [0110] Next, cover the gate electrode IlOa insulating layer 112 (see FIG. 3C) is formed. 磷(P)、砷(As)等随后被添加到半导体区域104,由此形成具有在浅区域的浅结深度的杂质区域114 (参见图3C)。 Phosphorus (P), arsenic (As) and the like are then added to the semiconductor region 104, thereby forming a shallow region having a shallow junction depth of the impurity region 114 (see FIG. 3C). 需要注意的是,虽然在这里添加磷或砷从而形成n沟道晶体管,但在形成p沟道晶体管的情况下可添加诸如硼(B)或铝(Al)的杂质元素。 It is noted that, while phosphorus or arsenic is added here to form an n-channel transistor, but in the case of forming a p-channel transistor may be added such as boron (B) or an impurity element aluminum (Al),. 还需要注意的是,通过形成杂质区域114,在栅极绝缘层l〇8a下方在半导体区域104中形成沟道形成区域116 (参见图3C)。 It is also noted that the 114, a channel is formed in the semiconductor region 104 is formed by impurity regions below the gate insulating layer l〇8a forming region 116 (see FIG. 3C). 这里,能够合适地设置添加的杂质的浓度;在半导体元件高度小型化的情况下,浓度优选地设置为高。 Here, the concentration can be appropriately set adding impurities; in highly miniaturized semiconductor device, the concentration is preferably set high. 另外,替代于这里采用的在形成绝缘层112之后形成杂质区域114的工艺,可采用在形成杂质区域114之后形成绝缘层112的工艺。 Further, instead of forming process employed herein in the impurity region 114 is formed after the insulating layer 112, insulating layer 112 may be employed process after forming impurity regions 114.

[0111] 然后,形成侧壁绝缘层118 (参见图3D)。 [0111] Then, the sidewall insulating layer 118 (see FIG. 3D) is formed. 形成绝缘层以覆盖绝缘层112,然后该绝缘层经受高度各向异性蚀刻,由此能够以自对准方式形成侧壁绝缘层118。 Forming an insulating layer to cover the insulating layer 112, the insulating layer is then subjected to a highly anisotropic etching, whereby a sidewall insulating layer 118 can be formed in a self-aligned manner. 优选地,绝缘层112在此时被部分地蚀刻,从而栅电极IlOa的顶表面和杂质区域114的顶表面露出。 Preferably, the insulating layer 112 is partially etched at this point, so that top surfaces of the gate electrode and the impurity region 114 IlOa exposed.

[0112] 其后,形成绝缘层以覆盖栅电极ll〇a、杂质区域114、侧壁绝缘层118等。 [0112] Thereafter, an insulating layer is formed to cover the gate electrode ll〇a, impurity regions 114, sidewall insulating layers 118 and the like. 磷(P)、 砷(As)等随后被添加到杂质区域114的与绝缘层接触的区域,由此形成高浓度杂质区域120 (参见图3E)。 Phosphorus (P), arsenic (As) and the like is then added to the insulating layer region in contact with the impurity region 114, whereby the high concentration impurity region 120 (see FIG. 3E) is formed. 接下来,去除以上绝缘层并且形成金属层122以覆盖栅电极110a、侧壁绝缘层118、高浓度杂质区域120等(参见图3E)。 Next, the insulating layer is removed and the above metal layer 122 is formed to cover the gate electrode 110a, the sidewall insulating layer 118, a high concentration impurity region 120 and the like (see FIG. 3E). 各种方法(诸如,真空蒸发法、溅射法和旋涂法)中的任何一种方法可用于形成金属层122。 Various methods (such as, a vacuum evaporation method, a sputtering method and a spin coating method) may be any of the methods used for the metal layer 122 is formed. 优选地,使用与半导体区域104中所包含的半导体材料发生反应以形成具有低电阻的金属化合物的金属材料形成金属层122。 Preferably, the semiconductor material used in the semiconductor region 104 included react to form a metal compound of a metal material having low resistance metal layer 122 is formed. 这种金属材料的例子包括钦、组、鹤、镇、钻和销。 Examples of such materials include metal Chin, group, crane, town, drilling and the pin.

[0113] 接下来,执行热处理,由此金属层122与半导体材料发生化学反应。 [0113] Next, heat treatment is performed, whereby the metal layer 122 and the semiconductor material of a chemical reaction. 相应地,形成与高浓度杂质区域120接触的金属化合物区域124(参见图3F)。 Accordingly, a metal compound in contact with the region of the high concentration impurity regions 120 124 (see FIG. 3F). 需要注意的是,在对于栅电极IlOa使用多晶硅的情况下,栅电极IlOa的与金属层122接触的部分也具有金属化合物区域。 Note that, in the case of using polysilicon for the gate electrode IlOa, the metal layer portion in contact with the gate electrode 122 also has a metal compound IlOa region.

[0114] 作为热处理,能够采用利用闪光灯的照射。 [0114] As the heat treatment, irradiation with flash lamp can be employed. 虽然当然可使用其他热处理方法,但优选地使用能够实现极短时间热处理的方法,以便提高金属化合物的形成中的化学反应的可控制性。 Although of course be used other heat treatment process, but is preferably used to achieve extremely short heat treatment methods to increase the controllability of formation of the metal compound in the chemical reaction. 需要注意的是,通过金属材料与半导体材料的反应形成以上金属化合物区域,并且金属化合物区域具有充分增加的电导率。 Note that, the above metal compound is formed by reaction of the metal material region with the semiconductor material, and the metal compound having sufficiently increased conductivity region. 通过形成金属化合物区域,能够充分地减小电阻并且能够提高元件特性。 Region by forming a metal compound, the resistance can be sufficiently reduced and the element characteristics can be improved. 在形成金属化合物区域124之后,去除金属层122。 After the formation of the metal compound region 124, metal layer 122 is removed.

[0115] 形成层间绝缘层126和128以覆盖在以上步骤中形成的部件(参见图3G)。 [0115] forming an interlayer insulating layer 126 and the cover member 128 is formed in the above steps (see FIG. 3G). 使用包含无机绝缘材料(诸如,氧化硅、氧氮化硅、氮化硅、氧化铪、氧化铝或氧化钽)的材料能够形成层间绝缘层126和128。 A material containing an inorganic insulating material (such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, tantalum oxide or aluminum) can be an interlayer insulating layers 126 and 128 are formed. 替代地,能够使用有机绝缘材料,诸如聚酰亚胺或丙烯酸树月旨。 Alternatively, it is possible to use an organic insulating material, such as polyimide or acrylic resin months purpose. 需要注意的是,虽然层间绝缘层126和层间绝缘层128在这里形成两层结构,但层间绝缘层的结构不限于此。 Note that, although the inter-layer insulating layer 126 and the interlayer insulating layer 128 is formed where two-layer structure, but the structure of the interlayer insulating layer is not limited thereto. 还需要注意的是,在形成层间绝缘层128之后,层间绝缘层128的表面优选地经受CMP处理、蚀刻等以便变平。 It is also noted that after forming the interlayer insulating layer 128, the surface of the interlayer insulating layer 128 is preferably subjected to CMP treatment, etching or the like to flatten.

[0116] 其后,在层间绝缘层中形成到达金属化合物区域124的开口,然后在这些开口中形成源或漏电极130a和源或漏电极130b(参见图3H)。 [0116] Thereafter, the opening is formed of a metal compound region 124 in the interlayer insulating layer, and these openings are formed in the source or drain electrode 130a and the source or drain electrode 130b (see FIG. 3H). 例如,源或漏电极130a和源或漏电极130b能够如下形成:通过PVD法、CVD法等在包括这些开口的区域中形成导电层;然后, 通过蚀刻、CMP处理等去除导电层的一部分。 For example, the source or drain electrode 130a and the source or drain electrode 130b can be formed as follows: by a PVD method, CVD method or the like in the region of these openings include a conductive layer is formed; then, by etching, CMP, and other processing portion of conductive layer removed.

[0117] 需要注意的是,在源或漏电极130a和源或漏电极130b通过去除导电层的一部分形成的情况下,优选地对其表面进行处理以使其表面是平的。 [0117] Note that the source or drain electrode and 130b, the surface thereof is preferably treated in a source or drain electrode 130a is formed by removing a part of the case where the conductive layer so that its surface is flat. 例如,钛膜、氮化钛膜等在包括开口的区域中形成为具有小的厚度并且随后钨膜形成为嵌入在开口中的情况下,在其后执行的CMP能够去除钨膜、钛膜、氮化钛膜等的不必要的部分,并提高表面的平整度。 For example, a titanium film, a titanium nitride film is formed to have a small thickness in the opening region comprise a tungsten film is formed and then the case is fitted in the opening, the CMP can be removed in a subsequent execution of the tungsten film, a titanium film, unnecessary portions of the titanium nitride film, and to improve the flatness of the surface. 通过如上所述使包括源或漏电极130a和源或漏电极130b的表面的表面变平,能够在稍后的步骤中形成有利的电极、配线、绝缘层、半导体层等。 As described above comprises that the source or drain electrode 130a and the source or drain electrode 130b of the surface to flatten the surface, the electrodes can be formed advantageously, wiring, an insulating layer, a semiconductor layer or the like in a later step.

[0118] 需要注意的是,虽然仅描述了与金属化合物区域124接触的源或漏电极130a和源或漏电极130b,但在同一步骤中能够形成与栅电极IlOa接触的电极(例如,图2A的电极130c)等。 [0118] It is noted that, while only the source or drain electrode in contact with the metal compound region 124 electrode 130a and the source or drain electrode 130b, but in the same step capable of forming an electrode in contact with the gate electrode ILOA (e.g., FIG. 2A electrodes 130c) and the like. 对于用于源或漏电极130a和源或漏电极130b的材料没有特定的限制,并且能够使用各种导电材料中的任何一种材料。 For a source or drain electrode 130a or drain electrode 130b of the source material and is not particularly limited, and any material can be used in various conductive materials. 例如,能够使用诸如钥、钛、铬、钽、钨、铝、铜、钕或钪的导电材料。 For example, it is possible to use a conductive material such as a key, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium.

[0119] 通过以上过程,形成使用包含导电材料的衬底100形成的晶体管160。 [0119] Through the above process, the transistor 160 is formed using a conductive material, the substrate 100 is formed. 需要注意的是,在执行以上过程之后,也可以形成另外的电极、配线、绝缘层等。 It is noted that, after performing the above process, may be further formed an electrode, a wiring, an insulating layer and the like. 当层间绝缘层和导电层堆叠的多层配线结构用作配线结构时,能够提供高度集成的半导体装置。 When the interlayer insulating layer and the conductive layer are stacked wiring structure as the multilayer wiring structure, a semiconductor device can be highly integrated.

[0120] 〈用于制造在上部的晶体管的方法〉 [0120] <Method for manufacturing the transistor in the upper portion of>

[0121] 然后,参照图4A至4G和图5A至描述制造在层间绝缘层128上方的晶体管162 的过程。 [0121] Then, with reference to FIGS. 4A to 4G and 5A to be described in the manufacturing process of the transistor above the interlayer insulating layer 128 162. 需要注意的是,在表示层间绝缘层128上方的各种电极、晶体管162等的制造过程的图4A至4G和图5A至中,省略了晶体管162下方的晶体管160等。 Note that, in a manufacturing process represents the inter-layer insulating layer over the various electrodes 128, transistor 162, etc. 4A to 4G and 5A, the transistor 160 is omitted below the transistor 162 and the like.

[0122] 首先,绝缘层132形成在层间绝缘层128、源或漏电极130a、源或漏电极130b和电极130c上方(参见图4A)。 [0122] First, an insulating layer 132 is formed over the interlayer insulating layer 130c 128, a source or drain electrode 130a, and the source electrode or drain electrode 130b (see FIG. 4A). 通过PVD法、CVD法等能够形成绝缘层132。 By a PVD method, CVD method, the insulating layer 132 can be formed. 包含无机绝缘材料(诸如,氧化硅、氧氮化硅、氮化硅、氧化铪、氧化铝或氧化钽)的材料能够用于绝缘层132。 Insulating material comprises an inorganic material (such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, tantalum oxide or aluminum) can be used for the insulating layer 132.

[0123] 接下来,在绝缘层132中形成到达源或漏电极130a、源或漏电极130b和电极130c的开口。 [0123] Next, an electrode reaching the source or drain 130a, the source or drain electrode 130b and the electrode 130c of the opening in the insulating layer 132. 此时,在将要形成栅电极136d的区域中形成另一开口。 At this point, another opening is formed in a region to be formed in the gate electrode 136d. 导电层134形成为嵌入在这些开口中(参见图4B)。 Conductive layer 134 is formed to be embedded in the openings (see FIG. 4B). 例如,通过使用掩模的蚀刻能够形成以上开口。 For example, by using the etching mask can be formed more openings. 例如,通过经使用光掩模曝光能够形成掩模。 For example, by using a photomask through the exposure mask can be formed. 对于蚀刻,可执行湿法蚀刻或干法蚀刻,但考虑到精细图案化,优选地执行干法蚀刻。 For the etching, wet etching or perform dry etching, but considering the fine patterning, dry etching is preferably performed. 通过诸如PVD法或CVD法的沉积方法能够形成导电层134。 By a deposition method such as a PVD method or a CVD method conductive layer 134 can be formed. 用于导电层134的材料的例子包括导电材料,诸如钥、钛、铬、钽、钨、铝、铜、钕和钪、这些材料中的任何材料的合金以及包含这些材料中的任何材料的化合物(例如,这些材料中的任何材料的氮化物)。 Examples of the material for the conductive layer 134 comprises a conductive material, such as a key, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, and scandium, alloys of any of these materials as well as the compound of any of these materials contains (e.g., any of these materials in the nitride).

[0124] 具体地讲,例如,导电层134能够如下形成:钛膜在包括开口的区域中通过PVD法形成为具有小的厚度,并且氮化钛膜随后通过CVD法形成为具有小的厚度;然后,钨膜形成为嵌入在开口中。 [0124] Specifically, for example, the conductive layer 134 can be formed as follows: a titanium film is formed to have a small thickness and a titanium nitride film having a small thickness is then formed by CVD method by a PVD method including the opening region; then, a tungsten film is formed to be embedded in the opening. 这里,通过PVD法形成的钛膜具有减少在界面的氧化膜并减小与下部电极(这里,源或漏电极130a、源或漏电极130b和电极130c等)的接触电阻的功能。 Here, the titanium film formed by a PVD method has reduced the oxide film at the interface and decreasing the lower electrode (here, a source or drain electrode 130a, the source electrode or drain electrode 130b, and 130c, etc.) the function of the contact resistance. 另外, 随后形成的氮化钛膜具有阻挡层性质,从而防止导电材料的扩散。 Further, the titanium nitride film is then formed having barrier properties, thereby preventing the diffusion of the conductive material. 替代地,在使用钛、氮化钛等形成阻挡膜之后,可通过镀覆法形成铜膜。 Alternatively, after forming a barrier film of titanium, titanium nitride, copper film can be formed by a plating method.

[0125] 在形成导电层134之后,通过蚀刻、CMP处理等去除导电层134的一部分,从而露出绝缘层132并且形成电极136a、136b和136c以及栅电极136d(参见图4C)。 [0125] After the formation of the conductive layer 134, by etching, CMP, processing part of the conductive layer 134 is removed, thereby exposing the insulating layer 132 and the electrodes 136a, 136b and 136c and the gate electrode 136d (see FIG. 4C). 需要注意的是,当通过去除以上导电层134的一部分形成电极136a、136b和136c以及栅电极136d时, 优选地执行处理从而获得变平的表面。 Note that, when forming the electrodes 136a, 136b and 136c and the gate electrode 136d by removing a portion of the conductive layer 134 is more preferably performed so as to obtain a flattened processing surface. 通过使绝缘层132、电极136a、136b和136c以及栅电极136d的表面变平,能够在稍后的步骤中形成有利的电极、配线、绝缘层、半导体层等。 By the insulating layer 132, the electrodes 136a, 136b and 136c of the gate electrode 136d and the surface becomes flat, the electrode is advantageous, wiring, an insulating layer, a semiconductor layer can be formed in a later step, and the like.

[0126] 其后,形成栅极绝缘层138以覆盖绝缘层132、电极136a、136b和136c以及栅电极136d(参见图4D)。 [0126] Thereafter, a gate insulating layer 138 is formed to cover the insulating layer 132, the electrodes 136a, 136b and 136c and the gate electrode 136d (see FIG. 4D). 通过溅射法、CVD法等能够形成栅极绝缘层138。 By sputtering, CVD method or the like capable of forming a gate insulating layer 138. 栅极绝缘层138优选地包含氧化硅、氮化硅、氮氧化硅、氧氮化硅、氧化铝、氧化铪、氧化钽等。 The gate insulating layer 138 preferably comprises silicon oxide, silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, and tantalum oxide. 需要注意的是,栅极绝缘层138可具有单层结构或叠层结构。 Note that the gate insulating layer 138 may have a single layer structure or a stacked structure. 例如,通过使用硅烷(SiH4)、氧气和氮气作为源气体的等离子体CVD法能够形成氮氧化硅的栅极绝缘层138。 For example, by using silane (of SiH4), oxygen and nitrogen source gas as a plasma CVD method capable of forming a gate insulating layer of silicon oxynitride film 138. 对于栅极绝缘层138的厚度没有特定的限制,但厚度例如能够大于或等于IOnm并且小于或等于500nm。 No special limitation on the thickness of the gate insulating layer 138, for example, the thickness of IOnm and greater than or equal to less than or equal to 500nm. 当采用叠层结构时,优选地通过堆叠具有大于或等于50nm并且小于或等于200nm的厚度的第一栅极绝缘层和位于第一栅极绝缘层上方的具有大于或等于5nm并且小于或等于300nm的厚度的第二栅极绝缘层,形成栅极绝缘层138。 When the stacked structure, preferably by stacking 50nm greater than or equal to 200nm and less than or equal to the thickness of the first gate insulating layer and located above the first gate insulating layer is greater than or equal to and less than or equal to 300nm 5nm the thickness of the second gate insulating layer, a gate insulating layer 138 is formed.

[0127] 需要注意的是,通过去除杂质变为i型氧化物半导体或者基本上i型氧化物半导体的氧化物半导体(高度净化的氧化物半导体)对界面态或界面电荷极为灵敏;因此,当这种氧化物半导体用于氧化物半导体层时,氧化物半导体层和栅极绝缘层之间的界面很重要。 [0127] It is noted that, by removing the impurity becomes i-type oxide semiconductor or a substantially i-type oxide semiconductor is an oxide semiconductor (highly purified oxide semiconductor) is extremely sensitive to the interface state or interface charge; therefore, when when such an oxide semiconductor is used for the oxide semiconductor layer, the interface between the oxide semiconductor layer and the gate insulating layer is important. 换句话说,将要与高度净化的氧化物半导体层接触的栅极绝缘层138需要具有高质量。 In other words, the gate insulating layer to be in contact with the highly purified oxide semiconductor layer 138 is required to have high quality.

[0128] 例如,使用微波(2. 45GHz)的高密度等离子体CVD法是有利的,因为由此能够形成具有高耐受电压的致密的高质量栅极绝缘层138。 [0128] For example, using a microwave (2. 45GHz) high-density plasma CVD method is advantageous, since thereby forming a dense, high-quality gate insulating layer 138 having a high withstand voltage. 这是因为,当高度净化的氧化物半导体层和高质量栅极绝缘层彼此接触时,界面态能够减小并且界面特性能够是有利的。 This is because, when highly purified oxide semiconductor layer and a high-quality gate insulating layer in contact with each other, the interface state can be reduced and interface properties can be advantageous.

[0129] 当然,即使在使用这种高度净化的氧化物半导体层时,也能够采用其他方法(诸如,溅射法或等离子体CVD法),只要能够形成具有良好质量的绝缘层作为栅极绝缘层即可。 [0129] Of course, even when the oxide semiconductor layer is formed using such a highly purified, it is possible to employ other methods (such as a sputtering method or a plasma CVD method), as long as the insulating layer can be formed with good quality as a gate insulating layer can be. 替代地,可应用在形成之后通过热处理修改了其膜质量和界面特性的绝缘层。 Alternatively, the modification may be applied after forming the film quality of the insulating layer and its interface characteristics by heat treatment. 在任何情况下,可接受具有作为栅极绝缘层138的良好质量并且减小栅极绝缘层和氧化物半导体层之间的界面态密度的层,从而形成良好的界面。 In any case, acceptable quality having a good gate insulating layer 138 and reduce the interface state density between the gate insulating layer and the oxide layer of the semiconductor layer, thereby forming a good interface.

[0130] 此外,当在氧化物半导体中包含杂质时,在利用电场强度2X106V/cm的在12小时期间在85°C的偏置温度测试(BT测试)中,通过强电场(B:偏置)和高温(T:温度)切割杂质和氧化物半导体的主要成分之间的组合,并且产生的悬空键导致阈值电压(Vth)的漂移。 [0130] Further, when the impurities contained in the oxide semiconductor, the electric field intensity 2X106V / cm during 12 hours at a temperature bias test of 85 ° C (BT test) by a strong electric field (B: Bias ) and high temperature (T: a combination between a main component of the oxide semiconductor and the impurity cutting temperature), and the dangling bond generated causes the threshold voltage (Vth) shift.

[0131] 另一方面,根据公开的发明的一个实施例,通过如上所述去除氧化物半导体中的杂质(尤其是氢或水)并在栅极绝缘层和氧化物半导体层之间实现良好的界面特性,能够提供即使在BT测试中也稳定的晶体管。 [0131] On the other hand, in accordance with a disclosed embodiment of the invention, and to achieve a good insulating layer between the gate and the oxide semiconductor layer described above, by removing the oxide semiconductor impurities (especially hydrogen or water) interface properties can be provided even in a BT test of a transistor is stable.

[0132] 然后,氧化物半导体层形成在栅极绝缘层138上方并通过诸如使用掩模的蚀刻的方法处理,从而形成具有岛形的氧化物半导体层140 (参见图4E)。 [0132] Then, the oxide semiconductor layer is formed over the gate insulating layer 138 and processing method, such as by using an etching mask, thereby forming the oxide semiconductor layer 140 having an island shape (see FIG. 4E).

[0133] 作为氧化物半导体层,能够应用使用下面材料中的任何材料形成的氧化物半导体层:四成分金属氧化物,诸如In-Sn-Ga-Zn-O;三成分金属氧化物,诸如In-Ga-Zn-0、 In_Sn_Zn_0、In_Al_Zn_0、Sn_Ga_Zn_0、Al-Ga-Zn-O和Sn-Al-Zn-O; _成分金属氧化物, 诸如In-Zn-〇、Sn-Zn-〇、Al-Zn-〇、Zn-Mg-〇、Sn-Mg-O和In-Mg-O;单成分金属氧化物,诸如In-〇、Sn-O和Zn-O;等等。 [0133] As the oxide semiconductor layer can be applied using any of an oxide semiconductor material layer is formed of the following materials: four-component metal oxides, such as In-Sn-Ga-Zn-O; three-component metal oxides such as In -Ga-Zn-0, In_Sn_Zn_0, In_Al_Zn_0, Sn_Ga_Zn_0, Al-Ga-Zn-O and Sn-Al-Zn-O; _ component metal oxides, such as In-Zn-square, Sn-Zn-square, an Al- Zn-square, Zn-Mg-square, Sn-Mg-O and In-Mg-O; single-component metal oxides, such as In-square, Sn-O and Zn-O; and the like. 另外,以上氧化物半导体层可包含SiO2。 Further, the above oxide semiconductor layer may comprise SiO2.

[0134] 作为氧化物半导体层,能够使用由InMO3(Zn0)m(m>0)代表的薄膜。 [0134] As the oxide semiconductor layer, a thin film can be used by the InMO3 (Zn0) m (m> 0) represents. 这里,M代表从Ga、Al、Mn和Co选择的一种或多种金属元素。 Here, M for the Ga, Al, Mn, and Co to select one or more metal elements. 例如,M能够是Ga、Ga和Al、Ga和Mn、Ga和Co等。 Eg, M can be Ga, Ga and Al, Ga and Mn, Ga and Co, and the like. 由包括Ga作为M的InMO3 (Zn0)m(m>0)代表的氧化物半导体膜称为基于In-Ga-Zn-O 的氧化物半导体,并且基于In-Ga-Zn-O的氧化物半导体的薄膜称为基于In-Ga-Zn-O的氧化物半导体膜(基于In-Ga-Zn-O的非晶膜)。 Referred to the oxide semiconductor film includes Ga as a InMO3 M (Zn0) m (m> 0) represented based on In-Ga-Zn-O oxide semiconductor, and based on the In-Ga-Zn-O oxide semiconductor a film based on the oxide semiconductor film is referred to as in-Ga-Zn-O (the amorphous film based on in-Ga-Zn-O's).

[0135] 在这个实施例中,作为氧化物半导体层,利用用于沉积的基于In-Ga-Zn-O的氧化物半导体靶通过溅射法形成非晶氧化物半导体层。 [0135] In this embodiment, as the oxide semiconductor layer, using the amorphous oxide semiconductor layer is formed by a sputtering method for depositing an oxide semiconductor target based on In-Ga-Zn-O's. 需要注意的是,通过把硅添加到非晶氧化物半导体层,能够抑制结晶;因此,使用包含大于或等于2wt. %并且小于或等于IOwt. % 的SioJA靶可形成氧化物半导体层。 Note that, by the addition of silicon to the amorphous oxide semiconductor layer, the crystallization can be suppressed; therefore, comprises greater than or equal to 2wt% and less than or equal to a target IOwt% SioJA may be formed of an oxide semiconductor layer.

[0136] 作为用于通过溅射法形成氧化物半导体层的靶,例如,能够使用包含氧化锌作为其主要成分的金属氧化物靶。 [0136] As a target for an oxide semiconductor layer is formed by a sputtering method, for example, possible to use a metal oxide containing zinc oxide as its main component target. 此外,例如,能够使用包含In、Ga和Zn(In2O3=Ga203:Zn0的成分比=1 :1 :1[摩尔比])等的用于沉积的氧化物半导体靶。 Further, for example, may be used containing In, Ga, and Zn (In2O3 = Ga203: Zn0 composition ratio = 1: 1: 1 [molar ratio]) or the like for the deposited oxide semiconductor target. 另外,可使用包含In、Ga和Zn(In203:Ga203:Zn0 的成分比=1 :1 :2 [摩尔比]或者In203:Ga203:Zn0 的成分比=1 :1 : 4[摩尔比])的用于沉积的氧化物半导体靶。 Further, it may be used containing In, Ga, and Zn (In203: Ga203: component Zn0 ratio = 1: 1: 2 [molar ratio] or In203: Ga203: Zn0 composition ratio = 1: 1: 4 [molar ratio]) of a target for an oxide semiconductor deposited. 用于沉积的氧化物半导体靶的填充率是90% 至100% (包括90%和100%),优选地大于或等于95% (例如,99. 9%)。 Filling rate target for an oxide semiconductor is deposited from 90 to 100% (including 90% and 100%), preferably greater than or equal to 95% (e.g., 99.9%). 使用具有高填充率的用于沉积的氧化物半导体靶形成致密的氧化物半导体层。 A dense oxide semiconductor layer formed using an oxide semiconductor target for deposition having a high filling rate.

[0137] 用于形成氧化物半导体层的气氛优选地是稀有气体(通常为氩气)气氛、氧气气氛或者稀有气体(通常为氩气)和氧气的混合气氛。 Atmosphere preferably [0137] used for forming the oxide semiconductor layer is rare gas (typically argon) atmosphere, an oxygen atmosphere or a rare gas (typically argon) and oxygen mixed atmosphere. 具体地讲,优选地使用高纯度气体,其中,杂质(诸如,氢、水、羟基和氢化物)的浓度减小至近似百万分之几(优选地,十亿分之几)。 Specifically, preferably used high-purity gas in which the concentration of impurities (such as hydrogen, water, a hydroxyl group, and hydride) is reduced to approximately a few parts per million (preferably, parts per billion).

[0138] 在形成氧化物半导体层时,衬底固定在保持于减压状态的处理室中,并且衬底温度高于或等于KKTC并且低于或等于60(TC,优选地高于或等于20(TC并且低于或等于400°C。当在衬底加热的同时形成氧化物半导体层时,氧化物半导体层中所包含的杂质的浓度能够减小。另外,减小了由于溅射导致的损伤。在去除了留在处理室中的水分的同时,弓丨入去除了氢和水分的溅射气体,并且利用金属氧化物作为靶形成氧化物半导体层。为了去除处理室中的剩余水分,优选地使用捕集真空泵。例如,能够使用低温泵、离子泵或者钛升华泵。抽空单元可以是具有冷阱的涡轮泵。从利用低温泵抽空的沉积室去除氢原子、包含氢原子的化合物(诸如,水(H2O))、(优选地,包含碳原子的化合物)等,由此减小在沉积室中形成的氧化物半导体层中所包含的杂质的浓度。 [0138] When the oxide semiconductor layer is formed, the substrate is fixed in a process chamber maintained at a reduced pressure state, and the substrate temperature is higher than or equal to and lower than or equal to KKTC 60 (TC, preferably higher than or equal to 20 (TC and lower than or equal to 400 ° C. when the oxide semiconductor layer is formed while heating the substrate, the concentration of the oxide semiconductor layer contains an impurity can be reduced. Further, since sputtering is reduced due to damage. in addition to the water remaining in the process chamber while the bow to Shu sputtering gas in addition to hydrogen and moisture, and as a target for forming the oxide semiconductor layer is formed using a metal oxide. in order to remove the residual moisture in the treatment chamber, entrapment vacuum pump is preferably used. For example, a cryopump, an ion pump, or a titanium sublimation pump. evacuation unit may be a turbo pump having a cold trap. removing a hydrogen atom from the deposition chamber is evacuated using a cryopump, a compound containing a hydrogen atom ( such as, water (H2O)), (preferably, a compound containing a carbon atom) and the like, thereby reducing the concentration of the oxide semiconductor layer formed in the deposition chamber contained impurities.

[0139] 例如,沉积条件能够设置如下:衬底和靶之间的距离是IOOmm;压力是0. 6Pa;直流(DC)功率是0.5kW;并且气氛是氧气气氛(氧气流量的比例是100%)。 [0139] For example, the deposition conditions can be set as follows: IOOmm distance between the substrate and the target is; the pressure is 0. 6Pa; current (DC) power is 0.5kW; and the atmosphere is an oxygen atmosphere (oxygen flow ratio is 100% ). 优选地,使用脉冲直流(DC)电源,因为能够减少粉状物质(也称为颗粒或粉尘)并且膜厚度能够是均匀的。 Preferably, a pulse direct current (DC) power, can be reduced because the powder substances (also referred to as particles or dust) and the film thickness can be uniform. 氧化物半导体层的厚度大于或等于2nm并且小于或等于200nm,优选地大于或等于5nm并且小于或等于30nm。 The thickness of the oxide semiconductor layer is greater than or equal to 2nm and less than or equal to 200nm, preferably greater than or equal to 5nm and less than or equal to 30nm. 需要注意的是,合适的厚度取决于应用的氧化物半导体材料,并且氧化物半导体层的厚度可根据材料而合适地设置。 Note that, depending on the appropriate thickness of the oxide semiconductor material is applied, and the thickness of the oxide semiconductor layer can be appropriately set depending on the material.

[0140] 需要注意的是,在通过溅射法形成氧化物半导体层之前,优选地通过反溅射去除附着于栅极绝缘层138的表面的粉尘,在反溅射中,引入氩气并产生等离子体。 [0140] Note that before the oxide semiconductor layer is formed by sputtering, preferably by reverse sputtering removing dust adhering to the surface of the gate insulating layer 138, the reverse sputtering, the argon gas is introduced and produce plasma. 这里,反溅射表示一种通过离子撞击待处理的物体的表面提高表面的质量的方法,而一般的溅射是通过离子撞击溅射靶来实现的。 Here, a method represented by reverse sputtering ions strike the surface of the object to be treated to improve the quality of the surface, and typically by sputtering a sputtering ions strike the target to achieve. 用于使离子撞击待处理的物体的表面的方法包括这样的方法:在氩气气氛中在表面上施加高频电压并且在衬底附近产生等离子体。 A method for ion bombardment of the surface of the object to be treated in a method comprising: applying a high frequency voltage to the surface in an argon atmosphere and plasma is generated in the vicinity of the substrate. 需要注意的是,替代于氩气气氛,可使用氮气气氛、氦气气氛、氧气气氛等。 Note that, instead of an argon atmosphere, a nitrogen atmosphere can be used, a helium atmosphere, an oxygen atmosphere.

[0141] 对于氧化物半导体层的蚀刻,可使用干法蚀刻或者湿法蚀刻。 [0141] For the etching of the oxide semiconductor layer, may be dry etching or wet etching. 当然,可采用干法蚀刻和湿法蚀刻的组合。 Of course, be used dry etching and wet etching in combination. 根据材料合适地设置蚀刻条件(蚀刻气体、蚀刻溶液、蚀刻时间、温度等),从而氧化物半导体层能够蚀刻为所希望的形状。 Suitably disposed etching conditions (etching gas, the etching solution, etching time, temperature, etc.) depending on the material, so that the oxide semiconductor layer can be etched into a desired shape.

[0142] 用于干法蚀刻的蚀刻气体的例子是包含氯的气体(基于氯的气体,诸如氯气(Cl2)、三氯化硼(BCl3)、四氯化硅(SiCl4)或者四氯化碳(CCl4))等。 [0142] Examples of the dry etching gas is a gas containing chlorine (chlorine-based gas such as chlorine gas (of Cl2), boron (of BCl3) trichloride, silicon tetrachloride (of SiCl4), or carbon tetrachloride (CCl4)) and so on. 替代地,可使用包含氟的气体(基于氟的气体,诸如四氟化碳(CF4)、六氟化硫(SF6)、三氟化氮(NF3)或者三氟甲烷(CHF3));溴化氢(HBr);氧气(O2);添加诸如氦气(He)或氩气(Ar)的稀有气体的这些气体中的任何气体;等等。 Alternatively, a gas containing fluorine (fluorine-based gas, such as carbon tetrafluoride (of CF4), sulfur hexafluoride (of SF6), nitrogen trifluoride (NF3), or trifluoromethane (CHF3)); bromide hydrogen (of HBr); oxygen (the O2); adding a rare gas such as helium (He) or argon (Ar) gas of any of these gases; and the like.

[0143] 作为干法蚀刻方法,能够使用平行板反应离子蚀刻(RIE)法或者感应耦合等离子体(ICP)蚀刻法。 [0143] As the dry etching method, a parallel plate may be used reactive ion etching (RIE) process or an inductively coupled plasma (ICP) etching method. 为了把层蚀刻为所希望的形状,合适地设置蚀刻条件(施加于线圈形电极的电功率的量、施加于衬底侧的电极的电功率的量、衬底侧的电极的温度等)。 To the layer was etched into a desired shape, suitably disposed etching conditions (the amount of electric power applied to the coil-shaped electrode, the amount of electric power applied to the electrode substrate side, the temperature of the substrate side electrode, etc.).

[0144] 作为用于湿法蚀刻的蚀刻剂,能够使用磷酸、醋酸和硝酸的混合溶液、氨水和过氧化氢混合物(31wt%的过氧化氢溶液:28Wt%的氨水溶液:水=5 :2 :2)等。 [0144] As an etchant used for wet etching, can be used phosphoric acid, acetic acid and a mixed solution of nitric acid, a mixture of ammonia and hydrogen peroxide (31wt% hydrogen peroxide solution: 28 wt% aqueous ammonia: water = 5: 2 : 2) and so on. 替代地,可使用诸如ITOO7N(由KantoChemicalCo.,Inc•生产)等的蚀刻剂。 Alternatively, use of such ITOO7N (a KantoChemicalCo., Inc •) and the like etchant.

[0145] 然后,氧化物半导体层优选地经受第一热处理。 [0145] Then, the oxide semiconductor layer is preferably subjected to a first heat treatment. 通过这种第一热处理,氧化物半导体层能够脱水或者脱氢。 By this first heat treatment, the oxide semiconductor layer can be dehydrated or dehydrogenated. 在高于或等于30(TC并且低于或等于750°C(优选地,高于或等于400°C并且低于衬底的应变点)的温度执行第一热处理。例如,衬底被引入到使用电阻加热元件等的电炉中,并且氧化物半导体层140在一小时期间在450°C的温度在氮气气氛中经受热处理。此时,防止氧化物半导体层140暴露于空气,从而防止水或氢的进入。 Performed at a temperature higher than or equal to 30 (TC and lower than or equal to 750 ° C (preferably, greater than or equal to 400 ° C and lower than the strain point of the substrate) of the first heat treatment. For example, the substrate is introduced into electric resistance heating element or the like, and the oxide semiconductor layer 140 is subjected to a period of one hour at a temperature of 450 ° C heat treatment in a nitrogen atmosphere. at this time, to prevent the oxide semiconductor layer 140 is exposed to the air, so as to prevent water or hydrogen entry.

[0146] 需要注意的是,热处理设备不限于电炉,并且可包括用于通过由介质(诸如,加热气体等)提供的热传导或热辐射加热待处理的物体的装置。 [0146] Note that heat treatment apparatus is not limited to an electric furnace, and may include a device or a conductive object to be treated is heated by heat radiation by the heat provided by the medium (such as a heating gas, etc.) used. 例如,能够使用快速热退火(RTA)设备,诸如气体快速热退火(GRTA)设备或者灯快速热退火(LRTA)设备。 For example, a rapid thermal annealing (RTA) apparatus, such as a gas rapid thermal annealing (a GRTA) device or a lamp rapid thermal annealing (an LRTA) devices. GRTA设备是用于使用高温气体的热处理的设备。 GRTA apparatus is an apparatus for heat treatment using high-temperature gas. 作为气体,使用不会由于热处理而与待处理的物体发生反应的惰性气体,诸如氮气或稀有气体(诸如,氩气)。 As the gas, an inert gas by the heat treatment does not react with the object to be treated, such as nitrogen or a rare gas (such as argon). LRTA设备是用于通过从灯(诸如,卤素灯、金属卤化物灯、氙弧灯、碳弧灯、高压钠灯或者高压汞灯)发出的光的辐射(电磁波)加热待处理的物体的设备。 LRTA apparatus is an apparatus for heating an object to be treated by radiation of light emitted from the lamp (such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, high pressure sodium lamp or high pressure mercury lamp) (electromagnetic wave).

[0147]例如,作为第一热处理,GRTA可如下执行。 [0147] For example, as the first heat treatment, a GRTA may be performed as follows. 衬底被放置在已被加热到650°C至700°C的高温的惰性气体中,加热几分钟,并被从惰性气体中取出。 The substrate is placed has been heated to 650 ° C to 700 ° C high-temperature inert gas, heated for several minutes, and removed from the inert gas. GRTA能够在短时间中实现高温热处理。 GRTA high temperature heat treatment can be realized in a short time. 另外,即使当温度超过衬底的应变点时也可应用这种热处理,因为仅花费很短时间。 Further, even when the temperature exceeds the strain point of the substrate is also applicable when this heat treatment, since it takes only a short time.

[0148] 需要注意的是,优选地在包含氮气或稀有气体(例如,氦气、氖气或氩气)作为其主要成分并且不包含水、氢等的气氛中执行第一热处理。 [0148] Note that, preferably comprising nitrogen or a noble gas (e.g., helium, neon, or argon) as its main component and does not contain water, hydrogen and the like is performed in the first heat treatment. 例如,引入到热处理设备中的氮或稀有气体(例如,氦气、氖气或氩气)的纯度大于或等于6N(99. 9999%),优选地大于或等于7N(99. 99999% )(也就是说,杂质的浓度小于或等于Ippm,优选地,小于或等于0.Ippm)。 For example, introduced into a heat treatment apparatus in nitrogen or a rare gas (e.g., helium, neon, or argon) is greater than or equal to a purity of 6N (99. 9999%), preferably greater than or equal to 7N (99. 99999%) ( That is, the impurity concentration of less than or equal IPPM, preferably less than or equal to 0.Ippm).

[0149]在一些情况下,根据第一热处理的条件或者氧化物半导体层的材料,氧化物半导体层可能结晶化为微晶层或多晶层。 [0149] In some cases, depending on the material of the first heat treatment conditions, or the oxide semiconductor layer, the oxide semiconductor layer may be crystallized into polycrystalline layer or a microcrystalline layer. 例如,氧化物半导体层可结晶化以变为具有大于或等于90%或者大于或等于80%的结晶的程度的微晶氧化物半导体层。 For example, the oxide semiconductor layers may crystallize to become microcrystalline oxide semiconductor layer having a degree of greater than or equal to 90%, or greater than or equal to 80% of the crystalline. 另外,根据第一热处理的条件或者氧化物半导体层的材料,氧化物半导体层可变为不包含结晶成分的非晶氧化物半导体层。 Further, according to the conditions of heat treatment or the material of the first oxide semiconductor layer, the oxide semiconductor layer may be changed to an amorphous oxide semiconductor layer contains no crystalline component.

[0150]氧化物半导体层可变为在非晶氧化物半导体(例如,氧化物半导体层的表面)中混有微晶(具有大于或等于Inm并且小于或等于20nm,典型地,大于或等于2nm并且小于或等于4nm的粒径)的氧化物半导体层。 [0150] In the oxide semiconductor layer may be changed to an amorphous oxide semiconductor (e.g., the surface of the oxide semiconductor layer) mixed with crystallites (greater than or equal to and less than or equal to 20 nm Inm, typically, greater than or equal to 2nm and the oxide semiconductor layer is less than or equal to the particle size 4nm) is.

[0151] 另外,通过在非晶氧化物半导体中布置微晶能够改变氧化物半导体层的电特性。 [0151] Further, by arranging the crystallites in an amorphous oxide semiconductor can change the electrical characteristics of the oxide semiconductor layer. 例如,在利用用于沉积的基于In-Ga-Zn-O的氧化物半导体靶形成氧化物半导体层的情况下,通过形成由具有电各向异性的In2Ga2ZnO^表的晶粒排列的微晶部分能够改变氧化物半导体层的电特性。 For example, in the case where the oxide semiconductor layer is formed on an oxide semiconductor target In-Ga-Zn-O using for deposition, by forming a dielectric anisotropy having In2Ga2ZnO ^ microcrystalline grains table arrangement portion capable of changing the electrical characteristics of the oxide semiconductor layer.

[0152] 更具体地讲,例如,通过把In2Ga2ZnOjAc轴排列为取向沿着垂直于氧化物半导体层的表面的方向,提高在平行于氧化物半导体层的表面的方向上的电导率,由此在垂直于氧化物半导体层的表面的方向上的绝缘性质能够增加。 [0152] More specifically, for example, by In2Ga2ZnOjAc axis arrangement oriented along a direction perpendicular to the surface of the oxide semiconductor layer, to improve the conductivity in the direction parallel to the surface of the oxide semiconductor layer, whereby perpendicular to the direction of the surface of the insulating properties of the oxide semiconductor layer can be increased. 另外,这种微晶部分具有抑制杂质(诸如,水或氢)进入氧化物半导体层的功能。 Further, the suppressing portion microcrystalline impurities (such as water or hydrogen) into the function of the oxide semiconductor layer.

[0153] 需要注意的是,通过由GRTA加热氧化物半导体层的表面能够形成以上包括微晶部分的氧化物半导体层。 [0153] It should be noted that the surface can be formed by heating the oxide semiconductor layer GRTA above the oxide semiconductor layer comprises a microcrystalline portion. 当使用Zn的量小于In或Ga的量的溅射靶时,能够实现更加有利的形成。 When the amount of Zn using In or Ga is less than the amount of the sputtering target can be achieved more favorable form.

[0154] 能够对还未处理成岛形层的氧化物半导体层140执行对氧化物半导体层140执行的第一热处理。 [0154] The first heat treatment can be performed on the oxide semiconductor layer 140 has not yet processed into the island-shaped oxide semiconductor layer 140 performs layer. 在这种情况下,在第一热处理之后,从加热设备取出衬底并且执行光刻步骤。 In this case, after the first heat treatment, the substrate is taken out from the heating apparatus and a photolithography step.

[0155] 需要注意的是,以上热处理能够使氧化物半导体层140脱水或脱氢,因此能够称为脱水处理或脱氢处理。 [0155] Note that the above heat treatment of the oxide semiconductor layer 140 is dehydration or dehydrogenation, it can be referred to as dehydration treatment or dehydrogenation treatment. 例如,在形成氧化物半导体层之后,在源或漏电极堆叠在氧化物半导体层140上方之后,或者在保护绝缘层形成在源或漏电极上方之后,可以在任何时刻执行这种脱水处理或脱氢处理。 For example, after formation of the oxide semiconductor layer, the source or drain electrode is stacked over the oxide semiconductor layer 140 after or in the protective insulating layer is formed after the source or drain electrode over, this dehydration may be performed at any time or de hydrogen treatment. 这种脱水处理或脱氢处理可执行超过一次。 Such dehydration treatment or dehydrogenation treatment may perform more than once.

[0156] 接下来,将源或漏电极142a和源或漏电极142b形成为与氧化物半导体层140接触(参见图4F)。 [0156] Next, the source or drain electrode 142a and the source or drain electrode 142b formed in contact with the oxide semiconductor layer 140 (see FIG. 4F). 源或漏电极142a和源或漏电极142b能够以这种方式形成:形成导电层以覆盖氧化物半导体层140,然后选择性地蚀刻该导电层。 Source or drain electrode 142a and the source or drain electrode 142b can be formed in such a manner: a conductive layer is formed to cover the oxide semiconductor layer 140, and then selectively etching the conductive layer.

[0157] 通过PVD法(诸如,溅射法)、CVD(诸如,等离子体CVD法)能够形成导电层。 [0157] by a PVD method (such as sputtering), CVD (such as a plasma CVD method) capable of forming a conductive layer. 作为导电层的材料,能够使用从铝、铬、铜、钽、钛、钥和钨选择的元素,包含以上元素中的任何元素作为其成分的合金等。 As the material of the conductive layer, it is possible to use elements selected from aluminum, chromium, copper, tantalum, titanium, tungsten and key, comprising any of the above elements as alloying elements in its composition, and the like. 另外,可使用包含从锰、镁、锆、铍和钍选择的一种或多种元素的材料。 Further, use can comprise a material selected from manganese, magnesium, zirconium, beryllium, thorium, and one or more elements. 组合铝和从钛、钽、钨、钥、铬、钕和钪选择的一种或多种元素的材料也可用于导电层的材料。 A combination of aluminum and from one or more of the elements titanium, tantalum, tungsten, keyhole, chromium, neodymium, and scandium may also be a material selected material for the conductive layer.

[0158]替代地,可使用导电金属氧化物形成导电层。 [0158] Alternatively, the conductive layer may be formed using a conductive metal oxide. 作为导电金属氧化物,能够使用氧化铟(In2O3)、氧化锡(SnO2)、氧化锌(ZnO)、氧化铟-氧化锡合金(In2O3-SnO2,在一些情况下缩写入为IT0)、氧化铟-氧化锌合金(In2O3-ZnO)或者包含硅或氧化硅的金属氧化物材料中的任何材料。 As the conductive metal oxide can be indium oxide (In203), tin oxide (of SnO2), zinc oxide (ZnO), indium oxide - tin oxide alloy (In2O3-SnO2, abbreviated in some cases as the IT0), indium oxide - zinc oxide alloy (In2O3-ZnO), or any material containing a metal oxide material such as silicon or silicon oxide.

[0159] 导电层可具有单层结构或者两层或更多层的叠层结构。 [0159] The conductive layer may have a single layer structure or a stacked structure of two or more layers. 例如,能够给出:包含硅的铝膜的单层结构;铝膜和堆叠在其上方的钛膜的两层结构;钛膜、铝膜和钛膜依次堆叠的三层结构等。 For example, it can be given: a single-layer structure of an aluminum film containing silicon; two-layer structure of an aluminum film and a titanium film stacked above it; titanium film, an aluminum film and a titanium film are sequentially stacked in a three-layer structure.

[0160] 这里,紫外线、KrF激光束或者ArF激光束优选地用于形成蚀刻掩模的曝光。 [0160] Here, ultraviolet light, KrF laser beam or ArF laser beam is preferably used to form an etching mask exposure.

[0161] 晶体管的沟道长度(L)由源或漏电极142a的下边缘部分和源或漏电极142b的下边缘部分之间的距离确定。 [0161] transistor channel length (L) of the source or drain electrode 142a and the lower edge portion of the distance between the source or drain electrode 142b of the lower edge portion is determined. 在执行沟道长度(L)小于25nm的图案的曝光的情况下,在几纳米至几十纳米的极远紫外范围(该范围是极短波长)中执行用于制作掩模的曝光。 Exposure for making a mask in the case where the channel length (L) of less than 25nm pattern exposure, extreme ultraviolet in the range of several nanometers to several tens of nanometers (which is a very short wavelength range) is executed. 在使用极远紫外光的曝光中,分辨率高并且聚焦深度大。 Exposure using a far ultraviolet light, a high resolution and large depth of focus. 因此,稍后将要形成的晶体管的沟道长度(L)能够大于或等于IOnm并且小于或等于lOOOnm,由此电路的操作速度能够增加。 Thus, the transistor channel length (L) to be formed later can be greater than or equal to and less than or equal to IOnm lOOOnm, whereby the operation speed of the circuit can be increased. 另外, 晶体管的断态电流极小,这防止了功耗的增加。 Further, off-state current of a transistor is extremely small, which prevents an increase in power consumption.

[0162] 合适地调整层的材料和蚀刻条件,从而在导电层的蚀刻中不去除氧化物半导体层140。 [0162] Suitable conditions and etching a material layer is adjusted so that the oxide semiconductor layer 140 is not removed in the etching of the conductive layer. 需要注意的是,根据材料和蚀刻条件,氧化物半导体层140在一些情况下在这个步骤中被部分地蚀刻以变为具有凹槽(凹陷部分)的氧化物半导体层。 Note that, depending on the material and etching conditions of the oxide semiconductor layer 140 in some cases in this step is partially etched to become an oxide semiconductor layer having a groove (concave portion).

[0163] 氧化物导电层可形成在氧化物半导体层140和源或漏电极层142a之间并且在氧化物半导体层140和源或漏电极层142b之间。 [0163] oxide conductive layer may be formed between the oxide semiconductor layer 140 and the source or drain electrode layer 142a and between the oxide semiconductor layer 140 and the source or drain electrode layer 142b. 氧化物导电层以及用于形成源或漏电极142a 和源或漏电极142b的导电层能够连续地形成(连续沉积)。 Oxide conductive layer for forming a source or drain electrode 142a and the source or drain electrode 142b of the conductive layer can be formed continuously (continuous deposition). 氧化物导电层能够用作源区域或者漏区域。 Oxide conductive layer can function as a source region or a drain region. 通过提供这种氧化物导电层,能够减小源区域和漏区域的电阻并且能够实现晶体管的高速操作。 By providing such an oxide conductive layer can reduce the resistance of the source region and a drain region of the transistor and high speed operation can be realized.

[0164] 为了减少掩模和步骤的数量,可利用使用多色调掩模形成的抗蚀剂掩模执行蚀亥IJ,多色调掩模是曝光掩模,光透射通过该曝光掩模以具有多种强度。 [0164] In order to reduce the number of masks and steps, may be formed using a multi-tone mask using a resist mask etch performed Hai IJ, multi-tone mask is a mask for exposure light is transmitted through the exposure mask having multiple kind of strength. 利用多色调掩模形成的抗蚀剂掩模具有有着多种厚度的形状(阶梯状形状)并且还能够通过磨光而在形状方面改变;因此,抗蚀剂掩模能够用在多个蚀刻步骤中以用于处理成不同图案。 Multi-tone mask is formed using a resist mask having a shape (stepped shape) and can also be changed in shape by polishing with various thicknesses; therefore, the resist mask can be used in a plurality of etching steps to for processing into different patterns. 也就是说,通过一个多色调掩模能够形成与至少两种或更多种不同图案对应的抗蚀剂掩模。 That is, the multi-tone mask through a resist mask can be formed with at least two or more different patterns corresponding to. 因此,曝光掩模的数量能够减少并且对应的光刻步骤的数量也能够减少;由此能够实现工艺的简化。 Thus, the number of light-exposure masks can be reduced and the number of corresponding photolithography steps can also be reduced; whereby the process can be simplified.

[0165] 需要注意的是,在以上步骤之后优选地执行使用气体(诸如,队0、队或41〇的等离子体处理。通过这种等离子体处理,附着于露出的氧化物半导体层的表面的水被去除。替代地,可使用氧气和氩气的混合气体执行等离子体处理。 [0165] Note that, a gas is preferably performed after step (such as 0 teams, team or plasma treatment 41〇 By such plasma treatment, the oxide semiconductor layer is adhered to the exposed surface water is removed. Alternatively, plasma treatment is performed using a mixed gas of oxygen and argon.

[0166] 其后,在不暴露于空气的情况下形成与氧化物半导体层140的一部分接触的保护绝缘层144(参见图4G)。 [0166] Thereafter, a protective insulating layer in contact with the oxide semiconductor layer 140 a portion 144 (see FIG. 4G) without exposure to the atmosphere.

[0167] 通过合适地采用诸如溅射法的方法能够形成保护绝缘层144,通过该方法防止杂质(诸如,水或氢)进入保护绝缘层144。 [0167] By suitably using a method such as a sputtering method capable of forming a protective insulating layer 144 to prevent impurities (such as water or hydrogen) into the protective insulating layer 144 by this method. 保护绝缘层144形成为具有大于或等于Inm的厚度。 The protective insulating layer 144 is formed to have a thickness of greater than or equal Inm. 作为能够用于保护绝缘层144的材料,存在氧化硅、氮化硅、氮氧化硅、氧氮化硅等。 It can be used as the protective insulating layer material 144, the presence of silicon oxide, silicon nitride, silicon oxide, silicon oxynitride and the like. 保护绝缘层144可具有单层结构或叠层结构。 The protective insulating layer 144 may have a single layer structure or a stacked structure. 用于保护绝缘层144的成形的衬底温度优选地高于或等于室温并且低于或等于300°C。 The substrate temperature is preferably used for forming the protective insulating layer 144 is higher than or equal to room temperature and lower than or equal to 300 ° C. 用于保护绝缘层144的形成的气氛优选地是稀有气体(通常为氦气)气氛、氧气气氛或者稀有气体(通常为氦气)和氧气的混合气氛。 Atmosphere is preferably used for forming the protective insulating layer 144 is a rare gas (typically helium) atmosphere, an oxygen atmosphere or a rare gas (typically helium) and a mixed atmosphere of oxygen.

[0168] 如果氢被包含在保护绝缘层144中,则引起氢进入到氧化物半导体层、由氢提取氧化物半导体层中的氧等,并且使氧化物半导体层的背沟道侧的电阻变低,这可形成寄生沟道。 [0168] If hydrogen is contained in the protective insulating layer 144, causing the hydrogen into the oxide semiconductor layer by hydrogen abstraction of the oxide semiconductor layer is oxygen, and the channel resistance of the back side of the oxide semiconductor layer becomes low, which may form a parasitic channel. 因此,很重要地,采用尽可能少地使用氢的形成方法,从而保护绝缘层144尽可能少地包含氢。 Thus, it is important, a formation method using hydrogen as little as possible, thereby protecting the insulating layer 144 containing hydrogen as little as possible.

[0169] 另外,优选地,在去除处理室中的剩余水分的同时形成保护绝缘层144。 [0169] Further, preferably, while removing remaining moisture in the processing chamber 144 for forming the protective insulating layer. 这是为了防止氢、羟基或水分被包含在氧化物半导体层140和保护绝缘层144中。 This is to prevent hydrogen, hydroxy or moisture contained in the oxide semiconductor layer 140 and the protective insulating layer 144.

[0170] 为了去除处理室中的剩余水分,优选地使用捕集真空泵。 [0170] In order to remove the residual moisture in the treatment chamber, an entrapment vacuum pump is preferably used. 例如,优选地使用低温泵、离子泵或者钛升华泵。 For example, preferably a cryopump, an ion pump, or a titanium sublimation pump. 抽空单元可以是具有冷阱的涡轮泵。 Evacuation means may be a turbine pump having a cold trap. 从利用低温泵抽空的沉积室去除氢原子、包含氢原子的化合物(诸如,水(H2O))等,由此减小在沉积室中形成的保护绝缘层144中所包含的杂质的浓度。 Removing a hydrogen atom from the deposition chamber is evacuated using a cryopump, a compound containing a hydrogen atom (such as water (H2O)) and the like, thereby reducing the concentration of the protective insulating layer 144 is formed in the deposition chamber contained impurities.

[0171] 作为在保护绝缘层144的形成中使用的溅射气体,优选地使用杂质(诸如,氢、水、 羟基或氢化物)减少至近似百万分之几(优选地,十亿分之几)的高纯度气体。 [0171] As a sputtering gas used in forming the protective insulating layer 144, an impurity is preferably used (such as hydrogen, water, a hydroxyl group, or hydride) reduced to approximately several parts per million (preferably, parts per billion s) of high-purity gas.

[0172] 然后,优选地在惰性气体气氛或氧气气氛中执行第二热处理(优选地在高于或等于200°C并且低于或等于400°C的温度,例如在高于或等于250°C并且低于或等于350°C的温度)。 [0172] Then, second heat treatment is preferably performed (preferably at higher than or equal to 200 ° C and lower than or equal to the temperature of 400 ° C, for example greater than or equal to 250 ° C in an inert gas atmosphere or an oxygen atmosphere and lower than or equal to the temperature of 350 ° C). 例如,在一小时期间在250°C在氮气气氛中执行第二热处理。 For example, performing a second heat treatment in a nitrogen atmosphere at 250 ° C during one hour. 第二热处理能够减小薄膜晶体管的电特性的变化。 The second heat treatment can reduce the electrical characteristics of the thin film transistor changes.

[0173] 另外,可在空气中在大于或等于1小时并且小于或等于30小时期间在高于或等于KKTC并且低于或等于200°C的温度执行热处理。 [0173] Further, in the air may be greater than or equal to 1 hour and less than or equal to greater than or equal KKTC during 30 hours and a heat treatment performed at a temperature lower than or equal to 200 ° C. 可在固定加热温度执行这种热处理。 This heat treatment may be performed at a fixed heating temperature. 替代地,可反复多次应用下面的温度循环:温度从室温增加至高于或等于KKTC并且低于或等于200°C的温度,然后减小至室温。 Alternatively, the application can be repeated several times following temperature cycle: increasing the temperature to a temperature higher than or equal KKTC and lower than or equal to 200 ° C from room temperature, and then reduced to room temperature. 另外,这种热处理可在保护绝缘层的形成之前在减小的压力下执行。 Further, this heat treatment may be performed under reduced pressure before the formation of the protective insulating layer. 减小的压力能够使热处理时间较短。 Reduced pressure heat treatment time can be made shorter. 需要注意的是,可替代于第二热处理执行这种热处理;替代地,可除了第二热处理之外还在第二热处理之前或之后执行这种热处理。 Note that, alternatively to the second heat treatment is performed such heat treatment; alternatively, such a heat treatment may be performed after or before addition to the second heat treatment is also a second heat treatment.

[0174] 然后,层间绝缘层146形成在保护绝缘层144上方(参见图5A)。 [0174] Then, the interlayer insulating layer 146 is formed over the protective insulating layer 144 (see FIG. 5A). 层间绝缘层146 能够通过PVD法、CVD法等形成。 The interlayer insulating layer 146 can, CVD method or the like is formed by a PVD method. 包含无机绝缘材料(诸如,氧化硅、氧氮化硅、氮化硅、氧化铪、氧化铝或氧化钽)的材料能够用于层间绝缘层146。 Insulating material comprises an inorganic material (such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, tantalum oxide or aluminum) it can be used for the interlayer insulating layer 146. 另外,在形成层间绝缘层146之后,层间绝缘层146的表面优选地经受CMP处理、蚀刻处理等以便变平。 Further, after forming the interlayer insulating layer 146, the surface of the interlayer insulating layer 146 is preferably subjected to CMP treatment, etching treatment for flattening.

[0175] 接下来,在层间绝缘层146、保护绝缘层144和栅极绝缘层138中形成到达电极136a、136b和136c、源或漏电极142a和源或漏电极142b的开口;然后,导电层148形成为嵌入在这些开口中(参见图5B)。 [0175] Next, the interlayer insulating layer 146, the protective 136a, 136b and 136c, the source or drain electrode and the source or drain electrode 142b of the opening to the electrode 142a and the gate insulating layer 144 is formed in the insulating layer 138; Then, a conductive layer 148 is formed to be embedded in the openings (see FIG. 5B). 例如,通过使用掩模的蚀刻能够形成以上开口。 For example, by using the etching mask can be formed more openings. 例如,通过经使用光掩模曝光能够形成掩模。 For example, by using a photomask through the exposure mask can be formed. 对于蚀刻,可执行湿法蚀刻或干法蚀刻,但考虑到精细图案化,优选地执行干法蚀刻。 For the etching, wet etching or perform dry etching, but considering the fine patterning, dry etching is preferably performed. 通过诸如PVD法或CVD法的沉积方法能够形成导电层148。 By a deposition method such as PVD or CVD conductive layer 148 can be formed. 用于导电层148的材料的例子包括导电材料,诸如钥、钛、铬、钽、钨、铝、铜、钕和钪、这些材料中的任何材料的合金以及包含这些材料中的任何材料的化合物(例如,这些材料中的任何材料的氮化物)。 Examples of the material for the conductive layer 148 comprises a conductive material, such as a key, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, and scandium, alloys of any of these materials as well as the compound of any of these materials contains (e.g., any of these materials in the nitride).

[0176] 具体地讲,例如,导电层148能够如下形成:钛膜在包括开口的区域中通过PVD法形成为具有小的厚度并且氮化钛膜随后通过CVD法形成为具有小的厚度;然后,钨膜形成为嵌入在开口中。 [0176] Specifically, for example, the conductive layer 148 can be formed as follows: an opening in a region including a titanium film is formed by a PVD method to have a small thickness and a titanium nitride film is then formed to have a small thickness by the CVD method; and , a tungsten film is formed to be embedded in the opening. 这里,通过PVD法形成的钛膜具有减小在界面的氧化膜并减小与下部电极(这里,电极136a、136b和136c、源或漏电极142a和源或漏电极142b等)的接触电阻的功能。 Here, the titanium film formed by a PVD method has reduced the oxide film at the interface of the lower electrode and reduces (here, the electrodes 136a, 136b and 136c, the source or drain electrode 142a and the source or drain electrode 142b, etc.) of the contact resistance Features. 另外,随后形成的氮化钛膜具有阻挡层性质,从而防止导电材料的扩散。 Further, the titanium nitride film is then formed having barrier properties, thereby preventing the diffusion of the conductive material. 替代地,在使用钛、氮化钛等形成阻挡膜之后,可通过镀覆法形成铜膜。 Alternatively, after forming a barrier film of titanium, titanium nitride, copper film can be formed by a plating method.

[0177] 在形成导电层148之后,通过蚀刻处理、CMP处理等去除导电层148的一部分,从而露出层间绝缘层146并且形成电极150a、150b、150c、150d和150e(参见图5C)。 [0177] After the formation of the conductive layer 148, by etching, the CMP treatment or the like is removed portion of conductive layer 148, thereby exposing the interlayer insulating layer 146 and the electrodes 150a, 150b, 150c, 150d, and 150e (see FIG. 5C). 需要注意的是,当通过去除以上导电层148的一部分形成电极150a、150b、150c、150d和150e时, 优选地执行处理从而获得变平的表面。 Note that when 150a, 150b, 150c, 150d, and when 150e, processing is preferably performed so as to obtain a flattened electrode surface is formed by removing a portion of the conductive layer 148 above. 通过使层间绝缘层146以及电极150a、150b、150c、 150d和150e的表面变平,能够在稍后的步骤中形成有利的电极、配线、绝缘层等。 By making the interlayer insulating layer 146 and the electrodes 150a, 150b, 150c, 150d, and 150e of the flattened surface, electrodes can be formed advantageously, the wiring, the insulating layer or the like in a later step.

[0178] 另外,形成绝缘层152并且在绝缘层152中形成到达电极150a、150b、150c、150d 和150e的开口;然后,导电层形成为嵌入在这些开口中。 [0178] Further, an insulating layer 152 is formed and 150a, 150b, 150c, 150d, and 150e electrode reaches the opening in the insulating layer 152; then, the conductive layer is formed to be embedded in these openings. 其后,通过蚀刻、CMP等去除导电层的一部分,从而露出绝缘层152并且形成电极154a、154b、154c和154d(参见图OT)。 Thereafter, by etching, CMP, and other part of the conductive layer is removed, thereby exposing the insulating layer 152 and the electrodes 154a, 154b, 154c and 154d (see FIG. OT). 这个步骤类似于形成电极150a等的步骤;因此,这里省略详细的描述。 The other steps are similar to electrode 150a is formed; therefore, detailed description thereof is omitted herein.

[0179] 当以上述方式制造晶体管162时,氧化物半导体层140中的氢浓度小于或等于5XIO19原子/cm3并且晶体管162的断态电流小于或等于IX1(T13A。因此,通过采用高度净化的氧化物半导体层140能够获得具有极佳特性的晶体管162,在高度净化的氧化物半导体层140中,充分地减小了氢浓度并且减少了由于缺氧导致的缺陷。另外,能够制造具有极佳特性的半导体装置,该半导体装置包括位于下部的使用除氧化物半导体之外的材料形成的晶体管160和位于上部的使用氧化物半导体形成的晶体管162。 [0179] When the above-described manner for manufacturing the transistor 162, the hydrogen concentration in the oxide semiconductor layer 140 is less than or equal to 5XIO19 atoms / cm3 and the off-state current of the transistor 162 is less than or equal IX1 (T13A. Thus, by using highly purified oxide semiconductor layer 140 of the transistor 162 can be obtained with excellent properties, in highly purified oxide semiconductor layer 140, substantially reducing the hydrogen concentration and reduces defects caused by lack of oxygen. in addition, having excellent characteristics can be manufactured transistor semiconductor device, the semiconductor device comprises a transistor 160 located on a lower portion of a material other than an oxide semiconductor and formed on the upper portion of the formation 162 using an oxide semiconductor.

[0180] 需要注意的是,碳化硅(例如,4H_SiC)是与氧化物半导体相比的半导体材料。 [0180] It should be noted that the silicon carbide (e.g., 4H_SiC) is a semiconductor material in comparison with the oxide semiconductor. 氧化物半导体和4H-SiC具有一些共同的特点。 An oxide semiconductor and 4H-SiC have some common features. 一个例子是载流子密度。 One example is the carrier density. 在室温使用费米-狄拉克(Femi-Dirac)分布,少数载流子的密度在氧化物半导体中被估计为近似l(T7/cm3,该密度与4H-SiC的6. 7XKT1Vcm3-样极低。当比较氧化物半导体的少数载流子密度与硅的本征载流子密度(IjXlOuVcm3)时,容易理解氧化物半导体的少数载流子密度很低。 At room temperature using the Fermi - Dirac (Femi-Dirac) distribution, minority carrier density in the oxide semiconductor is estimated to be approximately l (T7 / cm3, the density of 4H-SiC sample 6. 7XKT1Vcm3- low when the intrinsic carrier density and minority carrier density of an oxide semiconductor silicon comparison (IjXlOuVcm3), readily be understood that a low minority carrier density of an oxide semiconductor.

[0181] 另外,氧化物半导体的能带隙为3.OeV至3. 5eV,并且4H_SiC的能带隙为3. 26eV, 这意味着氧化物半导体和碳化硅都是宽带隙半导体。 [0181] Further, the energy band gap of the oxide semiconductor is 3.OeV to 3. 5eV, and the energy band gap of 4H_SiC 3. 26eV, which means that the oxide semiconductor and silicon carbide is a wide bandgap semiconductor.

[0182] 相比之下,在氧化物半导体和碳化硅之间存在很大差异,即在处理温度方面。 [0182] In contrast, there is a big difference between the oxide semiconductor and silicon carbide, i.e., in terms of the treatment temperature. 在使用碳化硅的半导体处理中通常需要在1500°C至2000°C激活的热处理,从而难以形成碳化硅和使用除碳化硅之外的半导体材料形成的半导体元件的叠层。 In the silicon carbide semiconductor processing typically requires 1500 ° C to 2000 ° C heat activation, making it difficult to form silicon carbide and a semiconductor device using a semiconductor laminated materials other than silicon carbide is formed. 这是因为,半导体衬底、半导体元件等被这种高温损伤。 This is because the semiconductor substrate, a semiconductor element such high temperatures and the like are damaged. 另一方面,能够利用在300°C至500°C(在低于或等于玻璃态转化温度的温度,最大为近似700°C)的热处理形成氧化物半导体;因此,在使用其他半导体材料形成集成电路之后,能够使用氧化物半导体形成半导体元件。 On the other hand, it can be utilized at 300 ° C to 500 ° C (at a temperature below or equal to the glass transition temperature, up to approximately 700 ° C) heat treatment of the oxide semiconductor is formed; Thus, other semiconductor materials used in forming an integrated after the circuit can be a semiconductor element formed using an oxide semiconductor.

[0183] 氧化物半导体相对于碳化硅具有这样的优点:能够使用低耐热衬底,诸如玻璃衬底。 [0183] with respect to the oxide semiconductor has the advantage that the silicon carbide: substrate can be used a low heat, such as a glass substrate. 此外,氧化物半导体还具有这样的优点:与碳化硅相比能够充分地减少能量成本,因为不需要在高温的加热温度。 Further, an oxide semiconductor has further advantages: as compared to silicon carbide can be sufficiently reduced energy costs, since no high temperature heating temperature.

[0184] 需要注意的是,虽然进行了许多关于诸如氧化物半导体的态密度(DOS)的物理性质的研究,但它们未提出充分地减少能隙中的局域态的思想。 [0184] It is noted that, although many studies on the physical properties such as density of states oxide semiconductor (DOS), but they are not made to sufficiently reduce thought localized states in the energy gap. 在公开的发明的一个实施例中,从氧化物半导体去除能够引起局域能级的水或氢,由此制造高度净化的氧化物半导体。 In one embodiment of the disclosed embodiment of the invention, can be removed from the oxide semiconductor due to the local levels of water or hydrogen, thereby producing highly purified oxide semiconductor. 这基于充分地减少局域态的思想并实现了优异工业产品的制造。 This is based on sufficiently reduce the localized states of thought and achieve excellent manufacturing industrial products.

[0185] 需要注意的是,当去除氢、水等时,在一些情况下也去除氧。 [0185] Note that, when removing hydrogen, water and the like, in some cases, also to oxygen. 因此,有利的是,通过把氧提供给由于缺氧产生的金属的悬空键从而减少由于缺氧导致的局域态,进一步净化氧化物半导体(使其成为i型氧化物半导体)。 Thus, advantageously, the oxygen provided by the metal due to dangling bonds anoxia reducing localized state caused by lack of oxygen, the oxide semiconductor further purification (making i-type oxide semiconductor). 例如,由于缺氧导致的局域态能够以下面的方式减少:具有过多氧的氧化膜形成为与沟道形成区域紧密接触;并且执行在200°C至400°C(典型地,近似250°C)的热处理,从而氧被从氧化膜提供给氧化物半导体。 For example, lack of oxygen due to localized states can be reduced in the following manner: an oxide film having excess oxygen is brought into close contact with the channel forming region; and performing at 200 ° C to 400 ° C (typically, approximately 250 ° C) heat treatment, so that oxygen is supplied from the oxide film to the oxide semiconductor.

[0186] 另外,在充分地减少氢、水等的气氛或者氧气气氛中执行并且跟在第二加热处理之后的温度减小步骤中,氧能够被提供给氧化物半导体。 [0186] Further, hydrogen reduction is performed sufficiently, water and the like or an atmosphere with oxygen atmosphere and the temperature is reduced after the second heat treatment step, the oxygen can be supplied to the oxide semiconductor.

[0187] 能够考虑:氧化物半导体的缺陷的因素是在导带以下在0.IeV至0. 2eV由于过多的氢导致的浅能级、由于缺氧导致的深能级等。 [0187] can be considered: factors defect of the oxide semiconductor is a shallow level in the conduction band to 0. 2eV 0.IeV due to excessive hydrogen resulting deep level caused by lack of oxygen and the like. 彻底去除氢并充分地提供氧以便消除这些缺陷的技术思想应该是有效的。 Complete removal of hydrogen and oxygen in order to sufficiently provide the technical idea of ​​eliminating these defects should be effective.

[0188] 需要注意的是,虽然氧化物半导体通常具有n型电导率,但在公开的发明的一个实施例中,通过去除杂质(诸如,水或氢)并提供作为氧化物半导体的成分的氧使氧化物半导体成为i型氧化物半导体。 [0188] It is noted that, although generally an oxide semiconductor having n-type conductivity, in one embodiment of the disclosed embodiment of the invention, by removing impurities (such as water or hydrogen) and oxygen is provided as the component of the oxide semiconductor the oxide semiconductor becomes i-type oxide semiconductor. 从这个方面,不同于通过添加杂质而成为i型硅的硅的情况, 公开的发明的一个实施例包括新的技术思想。 In this regard, unlike the case of silicon becomes i-type silicon by the addition of impurities, an embodiment of the disclosed invention include new technical idea.

[0189] 需要注意的是,使用氧化物半导体形成的晶体管162在这个实施例中是底栅晶体管;然而,本发明的实施例不限于此。 [0189] Note that the transistor 162 is formed using an oxide semiconductor in this embodiment is a bottom gate transistor; however, embodiments of the present invention is not limited thereto. 晶体管162可以是底栅晶体管、顶栅晶体管或者双栅晶体管。 Transistor 162 may be a bottom gate transistor, the top gate transistor or a dual gate transistor. 双栅晶体管表示这样的晶体管:两个栅电极层布置在沟道区域上方和下方并且在其间布置栅极绝缘层。 It refers to a double gate transistor transistor: two gate electrode layers are arranged above and below the channel region and a gate insulating layer disposed therebetween.

[0190] 〈使用氧化物半导体的晶体管的导电机制〉 [0190] <conduction mechanism transistor using an oxide semiconductor>

[0191] 将参照图31、图32、图33A和33B以及图34描述包括氧化物半导体的晶体管的导电机制。 [0191] Referring to FIG 31, FIG 32, FIGS. 33A and 33B and FIG. 34 described mechanism comprises a conductive oxide semiconductor transistor. 需要注意的是,下面的描述为了容易理解而基于理想情况的假设并且不必反映实际情况。 Note that the following description for ease of understanding based on the assumption of ideal case and do not necessarily reflect the actual situation. 还需要注意的是,下面的描述仅是一种考虑并且不影响本发明的有效性。 It is also noted that the following description is only considering and not affect the validity of the present invention.

[0192] 图31是包括氧化物半导体的晶体管(薄膜晶体管)的截面图。 [0192] FIG. 31 is a sectional view of a transistor (thin film transistor) of an oxide semiconductor. 氧化物半导体层(OS)布置在栅电极(GEl)上方并且栅极绝缘层(GI)位于它们之间,并且源电极(S)和漏电极(D)布置在它们上方。 An oxide semiconductor layer (OS) is arranged above the gate electrode (GEL) and a gate insulating layer (GI) situated between them, and the source electrode (S) and drain electrode (D) disposed above them. 提供绝缘层以覆盖源电极(S)和漏电极(D)。 Providing an insulating layer to cover the source electrode (S) and drain electrode (D).

[0193] 图32是图31的A-A'部分的能带图(示意图)。 [0193] FIG 32 FIG 31 is a A-A 'energy band diagrams (schematic) moiety. 在图32中,黑圆圈(•)和白圆圈(〇)分别代表电子和空穴并具有电荷(_q,+q)。 In FIG. 32, black circles (•) and white circles (square) represent electron and a hole and a charge (_q, + q). 在正电压(VD>0)施加于漏电极的情况下,虚线显示没有电压施加于栅电极(\= 0)的情况,并且实线显示正电压施加于栅电极(\>0)的情况。 In the case of a positive voltage (VD> 0) is applied to the drain electrode of the dashed line indicates no voltage is applied to the gate electrode (\ = 0), and the solid line shows the case where a positive voltage is applied to the gate electrode (\> 0). 在没有电压施加于栅电极的情况下,载流子(电子)因为高势垒而不会从电极注入到氧化物半导体侧,从而电流不流动,这意味着截止状态。 In the absence of a voltage applied to the gate electrode, the carriers (electrons) and not because of the high barrier oxide semiconductor are injected from the electrode to the side, so that current does not flow, which means an off state. 另一方面,当正电压施加于栅电极时,势垒降低,因此电流流动,这意味着导通状态。 On the other hand, when a positive voltage is applied to the gate electrode, the potential barrier decreases, so that the current flows, which means the conduction state.

[0194] 图33A和33B是图31的B-B'部分的能带图(示意图)。 [0194] FIGS. 33A and 33B in FIG. 31 is a B-B 'energy band diagrams (schematic) moiety. 图33A表示正电压(Ve>0) 施加于栅电极(GEl)并且载流子(电子)在源电极和漏电极之间流动的导通状态。 33A shows a positive voltage (Ve> 0) applied to the gate electrode (GEL) and the carriers (electrons) in the conduction state between the source and drain electrodes flows. 图33B 表示负电压(\〈0)施加于栅电极(GEl)并且少数载流子不流动的截止状态。 FIG 33B shows the negative voltage (\ <0) is applied to the gate electrode off-state (GEL) and minority carriers does not flow.

[0195] 图34表示真空能级和金属的功函数(ctM)之间的关系以及真空能级和氧化物半导体的电子亲和势(X)之间的关系。 [0195] FIG. 34 shows the relationship between the relationship between the vacuum level and the work function of metal (CTM) as well as the vacuum level and an oxide semiconductor electron affinity (X).

[0196] 在普通温度,金属中的电子退化并且费米能级位于导带中。 [0196] In the normal temperature, the metal and degradation of the electronic Fermi level in the conduction band. 另一方面,常规氧化物半导体是n型半导体,在n型半导体中,费米能级(Ef)离开位于带隙的中间的本征费米能级(Ei)并更靠近导带。 On the other hand, a conventional oxide semiconductor is an n-type semiconductor, the n-type semiconductor, the Fermi level (Ef of) located away from the middle of the band gap of the intrinsic Fermi level (Ei) and closer to the conduction band. 需要注意的是,已知氢的一部分是氧化物半导体中的施主并且是导致氧化物半导体成为n型半导体的一个因素。 Note that it is known that a part of hydrogen in the oxide semiconductor is a donor and the n-type semiconductor element leads to become an oxide semiconductor.

[0197] 另一方面,通过去除作为使氧化物半导体具有n型电导的一个因素的氢以便按照尽可能少地包含不是其主要成分的元素(杂质元素)的方式进行高度净化,使根据公开的发明的一个实施例的氧化物半导体成为本征(i型)氧化物半导体或者基本上本征的氧化物半导体。 [0197] On the other hand, by removing the oxide semiconductor as a factor having n-type conductivity of hydrogen so as less as possible according to the embodiment not comprising elements whose main component (impurity element) is highly purified, so that according to the disclosed invention, a semiconductor oxide of the oxide semiconductor of the present embodiment becomes an intrinsic (i-type) oxide semiconductor or substantially intrinsic. 换句话说,根据公开的发明的一个实施例的氧化物半导体不是通过添加杂质元素而成为i型氧化物半导体的氧化物半导体,而是通过尽可能多地去除杂质(诸如,氢或水)而高度净化的i型(本征)或者几乎i型的氧化物半导体。 In other words, the oxide semiconductor according to one embodiment of the disclosed invention is not to be an i-type oxide semiconductor and the impurity element is added by an oxide semiconductor, but by as much as possible to remove impurities (such as hydrogen or water) highly purified i-type (intrinsic) or substantially i-type oxide semiconductor. 以这种方式,费米能级(Ef) 能够极为接近本征费米能级(Ei)。 In this way, the Fermi level (Ef) can be very close to the intrinsic Fermi level (Ei).

[0198] 据称,氧化物半导体的带隙(Eg)为3. 15eV并且电子亲和势(X)是4. 3V。 [0198] Allegedly, the oxide semiconductor band gap (Eg) of 3. 15eV and electron affinity (X) is 4. 3V. 源电极和漏电极中所包括的钛(Ti)的功函数基本上等于氧化物半导体的电子亲和势(X)。 A source electrode and a drain electrode included in the titanium (Ti) is substantially equal to the work function of an oxide semiconductor electron affinity (X). 在这种情况下,在金属和氧化物半导体之间的界面未形成电子的肖特基势垒。 In this case, the interface between the metal and the oxide semiconductor is not formed electron Schottky barrier.

[0199] 此时,电子在栅极绝缘层和净化的氧化物半导体(在能量方面稳定的氧化物半导体的最下面部分)之间的界面的附近移动,如图33A中所示。 [0199] At this time, the electrons move in the gate insulating layer and purification of the interface between the oxide semiconductor (the lowermost part of the oxide semiconductor is stable in terms of energy) near, as shown in FIG 33A.

[0200] 另外,如图33B中所示,当负电位施加于栅电极(GEl)时,电流的值极为接近零,因为作为少数载流子的空穴基本上为零。 [0200] Further, as shown in FIG. 33B, when a negative potential is applied to the gate electrode (GEL), the current value is very close to zero, because the hole minority carriers is substantially zero.

[0201] 以这种方式,通过进行净化以使得尽可能少地包含除其主要元素之外的元素(即,杂质元素),获得本征(i型)氧化物半导体或者基本上本征的氧化物半导体。 [0201] In this manner, by purification contains as little as possible so that the elements other than main elements (i.e., an impurity element), to obtain an intrinsic (i-type) oxide semiconductor or substantially intrinsic oxide semiconductor. 因此, 氧化物半导体和栅极绝缘层之间的界面的特性变得明显。 Thus, the nature of the interface between the oxide semiconductor and the gate insulating layer becomes apparent. 由于这个原因,栅极绝缘层需要能够与氧化物半导体形成有利的界面。 For this reason, the gate insulating layer can be formed advantageously requires an interface with the oxide semiconductor. 具体地讲,优选地使用例如使用利用VHF频带至微波频带的范围中的电源频率产生的高密度等离子体通过CVD法形成的绝缘层、通过溅射法形成的绝缘层等。 Specifically, for example, it is preferably used to power by using the VHF band frequency range of the microwave band of high-density plasma generated by the insulating layer formed by a CVD method, the insulating layer and the like formed by sputtering.

[0202] 当净化氧化物半导体并且使氧化物半导体和栅极绝缘层之间的界面变得有利时, 在晶体管具有例如IXIO4iIm的沟道宽度(W)和3 的沟道长度(L)的情况下,可实现KT13A或更小的断态电流和0.lV/dec的亚阈值摆幅(S值)(利用IOOnm厚的栅极绝缘层)。 [0202] When the oxide semiconductor and the purification of the interface between the oxide semiconductor and the gate insulating layer becomes advantageous, for example, in the case of a transistor having a channel width IXIO4iIm (W) of 3, and a channel length (L) of the next, or may be implemented KT13A less 0.lV/dec off-state current and subthreshold swing (S value) (IOOnm using the gate insulating layer thickness).

[0203] 如上所述净化氧化物半导体以尽可能少地包含除其主要元素之外的元素(即,杂质元素),从而薄膜晶体管能够以有利的方式工作。 [0203] As described above purifying an oxide semiconductor can operate in an advantageous manner comprise as little as possible elements other than main elements (i.e., an impurity element), so that the thin film transistor.

[0204]〈修改例子〉 [0204] <Modified Example>

[0205] 参照图6、图7A和7B、图8A和8B以及图9A和9B描述半导体装置的结构的修改例子。 6, 7A and modified example 7B, 8A and 8B and 9A and 9B depict a configuration of a semiconductor device [0205] Referring to FIG. 需要注意的是,在下面的修改例子中,晶体管162的结构不同于已经描述的结构。 Note that, in the following modified example, the structure different from the structure of the transistor 162 has been described. 换句话说,晶体管160的结构类似于已经描述的结构。 In other words, a structure similar to the structure of the transistor 160 has been described.

[0206] 在图6中表示的例子中,晶体管162包括位于氧化物半导体层140和源或漏电极142a和源或漏电极142b下方的栅电极136d,源或漏电极142a和源或漏电极142b在氧化物半导体层140的底表面与氧化物半导体层140接触。 [0206] In the example shown in FIG. 6, the transistor 162 includes an oxide semiconductor layer 140 and the source or drain electrode 142a and the source or drain electrode 142b of the gate electrode 136d, the source or drain electrode 142a and the bottom of the source or drain electrode 142b contacting the bottom surface of the oxide semiconductor layer 140 of the oxide semiconductor layer 140. 由于平面结构可对应于截面结构合适地改变,所以在这里仅描述截面结构。 Since the planar structure corresponding to the sectional structure can be appropriately changed, so that only the cross-sectional structure described herein.

[0207] 作为图6中表示的结构和图2A和2B中表示的结构之间的很大差异,存在源或漏电极142a和源或漏电极142b连接到氧化物半导体层140的多个连接位置。 [0207] FIG structure as shown in FIG. 6 2A and 2B big difference between the structures shown in, the presence of the source or drain electrode 142a and the source or drain electrode 142b connected to a plurality of connection locations of the oxide semiconductor layer 140 . 也就是说,在图2A和2B中表示的结构中,源或漏电极142a和源或漏电极142b在氧化物半导体层140 的顶表面与氧化物半导体层140接触;另一方面,在图6中表示的结构中,源或漏电极142a 和源或漏电极142b在氧化物半导体层140的底表面与氧化物半导体层140接触。 That is, the structure shown in FIGS. 2A and 2B, the source or drain electrode 142a and the source or drain electrode 142b contacts the top surface of the oxide semiconductor layer 140, the oxide semiconductor layer 140; on the other hand, in FIG. 6 structure represented by the source or drain electrode 142a and the source or drain electrode 142b contacts the bottom surface of the oxide semiconductor layer 140 of the oxide semiconductor layer 140. 另外,由于这种接触的差异,其他电极、其他绝缘层等的位置改变。 Further, since the difference in position of this contact, the other electrode, an insulation layer, other changes. 关于每个部件的细节,可以参照图2A和2B。 Details regarding each component, can be referred to FIGS. 2A and 2B.

[0208] 具体地讲,半导体装置包括:栅电极136d,布置在层间绝缘层128上方;栅极绝缘层138,布置在栅电极136d上方;源或漏电极142a和源或漏电极142b,布置在栅极绝缘层138上方;和氧化物半导体层140,与源或漏电极142a和源或漏电极142b的顶表面接触。 [0208] Specifically, the semiconductor device comprising: a gate electrode 136d, disposed above the interlayer insulating layer 128; a gate insulating layer 138 disposed over the gate electrode 136d; source or drain electrode 142a and the source or drain electrode 142b, disposed over the gate insulating layer 138; and an oxide semiconductor layer 140 in contact with the source or drain electrode 142a and the source or drain electrode 142b of the top surface.

[0209] 这里,栅电极136d布置为嵌入在绝缘层132中,绝缘层132形成在层间绝缘层128 上方。 [0209] Here, the gate electrode 136d are arranged to be embedded in the insulating layer 132, the insulating layer 132 is formed over the interlayer insulating layer 128. 另外,类似于栅电极136d,电极136a、电极136b和电极136c被形成为分别与源或漏电极130a、源或漏电极130b和电极130c接触。 Further, similar to the gate electrode 136d, the electrode 136a, the electrode 136b and the electrode 136c 130c is formed in contact with the source or drain electrode 130a, and the source electrode or drain electrode 130b.

[0210] 在晶体管162上方,提供保护绝缘层144并且保护绝缘层144与氧化物半导体层140的一部分接触。 [0210] In the above transistor 162, and the protective insulating layer 144 provided in contact with a portion of the protective insulating layer 144 and the oxide semiconductor layer 140. 层间绝缘层146布置在保护绝缘层144上方。 The interlayer insulating layer 146 is disposed over the protective insulating layer 144. 这里,在保护绝缘层144 和层间绝缘层146中,形成到达源或漏电极142a和源或漏电极142b的开口。 Here, in the inter-layer insulating layer 144 and the protective insulating layer 146 is formed reaching the source or drain electrode 142a and the source or drain electrode 142b of the opening. 在这些开口中,电极150d和电极150e被形成为分别与源或漏电极142a和源或漏电极142b接触。 In these openings, the electrodes 150d and 150e are formed in the electrode in contact with the source or drain electrode 142a and the source or drain electrode 142b. 类似于电极150d和电极150e,在栅极绝缘层138、保护绝缘层144和层间绝缘层146中的开口中,电极150a、电极150b和电极150c被形成为分别与电极136a、电极136b和电极136c 接触。 Electrodes 150d and 150e similar to the electrode, the gate insulating layer 138, the protective insulating layer 146 in the openings, the electrode 150a, the electrode 150b and the electrode 150c are formed and the interlayer insulating layer 144 and the electrode layer, respectively 136a, the electrode 136b and the electrode 136c contacts.

[0211] 另外,绝缘层152布置在层间绝缘层146上方。 [0211] Further, the insulating layer 152 is disposed over the interlayer insulating layer 146. 电极154a、电极154b、电极154c 和电极154d布置为嵌入在绝缘层152中。 Electrode 154a, an electrode 154b, an electrode 154c and the electrode 154d are arranged to be embedded in the insulating layer 152. 这里,电极154a与电极150a接触;电极154b与电极150b接触;电极154c与电极150c和150d接触;并且电极154d与电极150e接触。 Here, the contact electrode 154a and the electrode 150a; 150b contact electrode 154b and the electrode; electrode 154c and the electrode 150c and 150d contacts; 154d and the electrode in contact with the electrodes 150e.

[0212] 图7A和7B中的每一个表示栅电极136d布置在氧化物半导体层140上方的例子。 [0212] FIGS. 7A and shows an example of each of the gate electrode 136d is disposed over the oxide semiconductor layer 140 7B. 这里,图7A表示源或漏电极142a和源或漏电极142b在氧化物半导体层140的底表面与氧化物半导体层140接触的例子;并且图7B表示源或漏电极142a和源或漏电极142b在氧化物半导体层140的顶表面与氧化物半导体层140接触的例子。 Here, FIG. 7A shows an example of a source or drain electrode 142a and the source or drain electrode 142b on the bottom surface of the oxide semiconductor layer 140 is in contact with the oxide semiconductor layer 140; and FIG. 7B shows the source or drain electrode 142a and the source or drain electrode 142b in the case of a top surface of the oxide semiconductor layer 140 and the oxide semiconductor layer 140 in contact.

[0213] 图7A和7B的结构在很大程度上不同于图2A和2B以及图6中的结构,差别在于: 栅电极136d布置在氧化物半导体层140上方。 Structure [0213] FIGS. 7A and 7B are largely different from that in FIGS. 2A and 2B and the structure of FIG. 6, the difference lies in: the gate electrode 136d is disposed over the oxide semiconductor layer 140. 另外,图7A中表示的结构和图7B中表示的结构之间的很大差异在于源或漏电极142a和源或漏电极142b与氧化物半导体层140接触的表面,该接触的表面是氧化物半导体层140的顶表面或底表面。 Further, a large difference between the structure and FIG 7B shows a structure shown in FIG. 7A that the source or drain and the source or drain electrode 142a of the surface 140 in contact with the oxide semiconductor electrode layer 142b, the surface is in contact with the oxide the top or bottom surface of the semiconductor layer 140. 另外,由于这些差异,其他电极、其他绝缘层等的位置改变。 Further, since the position of these differences, the other electrodes, other insulating layers and the like change. 关于每个部件的细节,可以参照图2A和2B中表示的结构。 Details regarding each component may 2A and 2B show the structure.

[0214] 具体地讲,在图7A中,半导体装置包括:源或漏电极142a和源或漏电极142b,布置在层间绝缘层128上方;氧化物半导体层140,与源或漏电极142a和源或漏电极142b的顶表面接触;栅极绝缘层138,布置在氧化物半导体层140上方;和栅电极136d,在栅极绝缘层138上方位于与氧化物半导体层140重叠的区域中。 [0214] Specifically, in FIG. 7A, the semiconductor device comprising: a source or drain electrode 142a and the source or drain electrode 142b, is disposed above the interlayer insulating layer 128; an oxide semiconductor layer 140, and source or drain electrode 142a and the source or drain electrode 142b contacts the top surface; a gate insulating layer 138 disposed over the oxide semiconductor layer 140; and a gate electrode 136d, the insulating layer 138 located above the gate region 140 overlaps with the oxide semiconductor layer.

[0215] 在图7B中,半导体装置包括:氧化物半导体层140,布置在层间绝缘层128上方; 源或漏电极142a和源或漏电极142b,布置为与氧化物半导体层140的顶表面接触;栅极绝缘层138,布置在氧化物半导体层140、源或漏电极142a和源或漏电极142b上方;和栅电极136d,在栅极绝缘层138上方位于与氧化物半导体层140重叠的区域中。 [0215] In Figure 7B, a semiconductor device comprising: an oxide semiconductor layer 140 is disposed above the interlayer insulating layer 128; source or drain electrode 142a and the source or drain electrode 142b, and the oxide semiconductor layer is disposed to a top surface 140 of the contacting; a gate insulating layer 138, the oxide semiconductor layer 140 is disposed, the source or drain electrode 142a and the source or drain electrode 142b above; 136d and a gate electrode, over the gate insulating layer 138 is positioned to overlap with the oxide semiconductor layer 140 is area.

[0216] 需要注意的是,在图7A和7B中表示的结构中,在一些情况下能够省略图2A和2B 等中表示的结构所具有的部件(例如,电极150a、电极154a等)。 [0216] Note that, in the structure shown in FIGS. 7A and 7B, in some cases can be represented by the structures 2A and 2B in FIG like member having omitted (e.g., an electrode 150a, an electrode 154a, etc.). 在这种情况下,能够次要地实现制造过程的简化。 In this case, it is possible to simplify the manufacturing process of the secondary. 当然,在图2A和2B等中表示的结构中也能够省略不必要的部件。 Of course, in the structure shown in FIGS. 2A and 2B may be omitted and other unnecessary parts.

[0217] 图8A和8B中的每一个表示元件具有相对较大的尺寸并且栅电极136d布置在氧化物半导体层140下方的结构的例子。 [0217] Each of FIGS. 8A and 8B represent elements having a relatively large size and configuration example of the gate electrode 136d disposed below the oxide semiconductor layer 140. 在这种情况下,配线、电极等不需要被形成为嵌入在绝缘层中,因为表面的平整度或覆盖范围不需要极高。 In this case, the wiring and electrodes need not be formed to be embedded in the insulating layer, since the surface flatness or coverage need not be very high. 例如,栅电极136d等能够以这种方式形成:形成导电层,然后进行图案化。 For example, like the gate electrode 136d can be formed in such a manner: a conductive layer is formed, and then patterned. 需要注意的是,虽然未示出,但能够类似地制造晶体管160。 Note that, although not shown, the transistor 160 can be manufactured similarly.

[0218] 图8A中表示的结构和图8B中表示的结构之间的很大差异在于源或漏电极142a 和源或漏电极142b与氧化物半导体层140接触的表面,该接触的表面是氧化物半导体层140的顶表面或底表面。 [0218] The structure big difference between FIG. 8A and 8B represent that the representation in the source or drain and the source or drain electrode 142a of the surface 140 in contact with the oxide semiconductor electrode layer 142b, the contact surface is oxidized top or bottom surface of the semiconductor layer 140. 另外,由于这种差异,其他电极、其他绝缘层等的位置改变。 Further, since the position of this difference, other electrodes, other insulating layers and the like change. 关于每个部件的细节,可以参照图2A和2B或其它附图中表示的结构。 Details regarding each component may 2A and 2B or other structure represented in the drawings.

[0219] 具体地讲,在图8A中表示的结构中,半导体装置包括:栅电极136d,布置在层间绝缘层128上方;栅极绝缘层138,布置在栅电极136d上方;源或漏电极142a和源或漏电极142b,布置在栅极绝缘层138上方;和氧化物半导体层140,与源或漏电极142a和源或漏电极142b的顶表面接触。 [0219] Specifically, the structure shown in FIG. 8A, a semiconductor device comprising: a gate electrode 136d, disposed above the interlayer insulating layer 128; a gate insulating layer 138 disposed over the gate electrode 136d; source or drain electrode source or drain electrode 142a and 142b, is disposed above the gate insulating layer 138; and an oxide semiconductor layer 140 in contact with the source or drain electrode 142a and the source or drain electrode 142b of the top surface.

[0220] 在图8B中表示的结构中,半导体装置包括:栅电极136d,布置在层间绝缘层128 上方;栅极绝缘层138,布置在栅电极136d上方;氧化物半导体层140,布置在栅极绝缘层138上方以与栅电极136d重叠;以及源或漏电极142a和源或漏电极142b,布置为与氧化物半导体层140的顶表面接触。 [0220] The structure represented in FIG. 8B, the semiconductor device comprising: a gate electrode 136d, disposed above the interlayer insulating layer 128; a gate insulating layer 138 disposed over the gate electrode 136d; the oxide semiconductor layer 140, disposed over the gate insulating layer 138 to overlap with the gate electrode 136d; and a source or drain electrode 142a and the source or drain electrode 142b, disposed in contact with the top surface of the oxide semiconductor layer 140.

[0221] 需要注意的是,在图8A和8B中表示的结构中,在一些情况下也能够省略图2A和2B等中表示的结构所具有的部件。 [0221] Note that, in the structure shown in FIGS. 8A and 8B, in some cases it is possible to have the components and structures in FIGS. 2A and 2B represent the like will be omitted. 在这种情况下,也能够实现制造过程的简化。 In this case, it is possible to simplify the manufacturing process.

[0222] 图9A和9B中的每一个表示元件具有相对较大的尺寸并且栅电极136d布置在氧化物半导体层140上方的结构的例子。 [0222] FIGS. 9A and 9B each element represents a relatively large size and arrangement example of the gate electrode 136d over the oxide semiconductor layer 140. 在这种情况下,配线、电极等也不需要被形成为嵌入在绝缘层中,因为表面的平整度或覆盖范围不需要极高。 In this case, the wiring and electrodes are formed does not need to be embedded in the insulating layer, since the surface flatness or coverage need not be very high. 例如,栅电极136d等能够以这种方式形成:形成导电层,然后进行图案化。 For example, like the gate electrode 136d can be formed in such a manner: a conductive layer is formed, and then patterned. 需要注意的是,虽然未示出,但能够类似地制造晶体管160。 Note that, although not shown, the transistor 160 can be manufactured similarly.

[0223] 图9A中表示的结构和图9B中表示的结构之间的很大差异在于源或漏电极142a 和源或漏电极142b与氧化物半导体层140接触的表面,该接触的表面是氧化物半导体层140的顶表面或底表面。 [0223] significant differences between the structure and the structure represented in FIG. 9A 9B shows that the source or drain and the source or drain electrode 142a of the surface 140 in contact with the oxide semiconductor electrode layer 142b, the contact surface is oxidized top or bottom surface of the semiconductor layer 140. 另外,由于这种差异,其他电极、其他绝缘层等的位置改变。 Further, since the position of this difference, other electrodes, other insulating layers and the like change. 关于每个部件的细节,可以参照图2A和2B或其它附图中表示的结构。 Details regarding each component may 2A and 2B or other structure represented in the drawings.

[0224] 具体地讲,在图9A中,半导体装置包括:源或漏电极142a和源或漏电极142b,布置在层间绝缘层128上方;氧化物半导体层140,与源或漏电极142a和源或漏电极142b的顶表面接触;栅极绝缘层138,布置在源或漏电极142a、源或漏电极142b和氧化物半导体层140上方;和栅电极136d,在栅极绝缘层138上方布置在与氧化物半导体层140重叠的区域中。 [0224] Specifically, in FIG. 9A, the semiconductor device comprising: a source or drain electrode 142a and the source or drain electrode 142b, is disposed above the interlayer insulating layer 128; an oxide semiconductor layer 140, and source or drain electrode 142a and the source or drain electrode 142b contacts the top surface; a gate insulating layer 138, disposed in the electrode 142a or drain electrode 142b source over the source or drain, and the oxide semiconductor layer 140; 136d and a gate electrode disposed above the gate insulating layer 138 overlapping with the oxide semiconductor layer 140 region.

[0225] 在图9B中,半导体装置包括:氧化物半导体层140,布置在层间绝缘层128上方; 源或漏电极142a和源或漏电极142b,布置为与氧化物半导体层140的顶表面接触;栅极绝缘层138,布置在源或漏电极142a、源或漏电极142b和氧化物半导体层140上方;和栅电极136d,在栅极绝缘层138上方布置在与氧化物半导体层140重叠的区域中。 [0225] In Figure 9B, the semiconductor device comprising: an oxide semiconductor layer 140 is disposed above the interlayer insulating layer 128; source or drain electrode 142a and the source or drain electrode 142b, and the oxide semiconductor layer is disposed to a top surface 140 of the contacting; a gate insulating layer 138, disposed in the source or drain electrode 142a, 142b and the source or drain electrode over the oxide semiconductor layer 140; and a gate electrode 136d, the gate insulating layer 138 over the oxide semiconductor layer 140 is arranged to overlap area.

[0226] 需要注意的是,在图9A和9B中表示的结构中,在一些情况下也能够省略图2A和2B等中表示的结构所具有的部件。 [0226] Note that, in the structure shown in FIGS. 9A and 9B, it is possible in some cases has a structure member shown in Figures 2A and 2B and the like will be omitted. 在这种情况下,也能够实现制造过程的简化。 In this case, it is possible to simplify the manufacturing process.

[0227] 如上所述,根据公开的发明的一个实施例,实现了具有新型结构的半导体装置。 [0227] As described above, according to one embodiment of the disclosed embodiments of the invention, to achieve a semiconductor device having a novel structure. 虽然晶体管160和晶体管162在这个实施例中是堆叠的,但半导体装置的结构不限于此。 While the transistor 160 and transistor 162 in this embodiment is a stacked embodiment, but the structure of the semiconductor device is not limited thereto. 另夕卜,虽然描述了晶体管160的沟道长度方向和晶体管162的沟道长度方向彼此垂直的例子, 但晶体管160和162的位置不限于此。 Another Bu Xi, while another described example of a vertical direction of a channel length of the transistor channel length direction of the transistor 160 and 162, the position of the transistors 160 and 162 are not limited thereto. 另外,晶体管160和162可布置为彼此重叠。 Further, the transistors 160 and 162 may be arranged to overlap each other.

[0228] 需要注意的是,虽然在这个实施例中为了容易理解而描述了每最小存储单元(一位)的半导体装置,但半导体装置的结构不限于此。 [0228] It should be noted that although in this embodiment, for ease of understanding to describe each minimum memory cell (a) a semiconductor device, the structure of the semiconductor device is not limited thereto. 通过合适地连接多个半导体装置能够形成更发达的半导体装置。 By suitably connecting a plurality of semiconductor devices can be formed a semiconductor device further developed. 例如,通过使用多个半导体装置可制作NAND类型或NOR类型半导体装置。 For example, by using a plurality of semiconductor devices can be fabricated NOR type or NAND type semiconductor device. 配线的结构不限于图1中表示的配线的结构并且能够合适地改变。 FIG wiring structure is not limited to the structure represented in wiring and can be suitably changed.

[0229] 在根据这个实施例的半导体装置中,晶体管162的小断态电流特性使数据能够保存极长时间。 [0229] In the semiconductor device according to this embodiment, a small off-state current characteristics of the transistor 162 is extremely long to enable data storage. 换句话说,不需要在DRAM等中需要的刷新操作;因此,能够抑制功耗。 In other words, no refresh operation of the DRAM or the like is required; thus, power consumption can be suppressed. 另外, 该半导体装置能够基本上用作非易失性半导体装置。 Further, the semiconductor device can be used as a substantially non-volatile semiconductor device.

[0230] 由于通过晶体管162的开关操作写入数据,所以不需要高电压并且在半导体装置中元件不会劣化。 [0230] Since the write data through the switching operation of the transistor 162, so no high voltage element and in the semiconductor device is not deteriorated. 另外,因为通过使晶体管导通或截止来写入或擦除数据,所以半导体装置能够容易地工作于高速。 Further, since the transistor by turning on or off to write or erase data, the semiconductor device can easily operate at high speeds. 另外,存在这样的优点:不需要用于擦除数据的擦除操作,擦除操作是闪速存储器等中的必要操作。 Further, there is an advantage: no erase operation for erasing data, an erase operation is necessary for operation of the flash memory, and the like.

[0231]另外,使用除氧化物半导体之外的材料形成的晶体管能够与使用氧化物半导体形成的晶体管相比工作于高得多的速度,并因此实现存储内容的高速读取。 [0231] Further, a transistor using a material other than an oxide semiconductor capable of forming a transistor formed using an oxide semiconductor and work as compared to the much higher speed, and thus achieving high-speed reading stored content.

[0232] 在这个实施例中描述的结构、方法等能够合适地与任何其它实施例中的结构、方法等组合。 [0232] In this Example described structure, a method can be suitably combined with any structure of the other embodiments, a method.

[0233] [实施例2] [0233] [Example 2]

[0234] 在这个实施例中,描述根据本发明实施例的半导体装置的电路结构和操作。 [0234] In this embodiment, description of the circuit configuration of a semiconductor device according to the embodiment and operate in accordance with the present invention.

[0235] 半导体装置中所包括的存储元件(以下,也称为存储单元)的电路图的例子表示在图10中。 Examples of a circuit diagram of the memory element [0235] The semiconductor device included (hereinafter, also referred to as storage means) 10 is shown in FIG. 图10中表示的存储单元200是多值存储单元并包括源极线SL、位线BL、第一信号线S1、第二信号线S2、字线WL、晶体管201、晶体管202、晶体管203和电容器205。 FIG storage unit 10 is represented by a multi-value storage unit 200 and includes a source line SL, bit lines BL, a first signal line S1, the second signal line S2, the word line WL, transistor 201, transistor 202, transistor 203 and a capacitor 205. 使用除氧化物半导体之外的材料形成晶体管201和203,并且使用氧化物半导体形成晶体管202。 In addition to using a material for forming an oxide semiconductor transistors 201 and 203, and transistor 202 is formed using an oxide semiconductor.

[0236] 这里,晶体管201的栅电极电连接到晶体管202的源电极和漏电极中的一个。 [0236] Here, the gate electrode of the transistor 201 is connected to a source electrode and a drain electrode of the transistor 202. 另夕卜,源极线SL电连接到晶体管201的源电极,并且晶体管203的源电极电连接到晶体管201 的漏电极。 Another Bu Xi, a source line SL connected to the source electrode of the transistor 201 and the source electrode of transistor 203 is connected to the drain electrode of the transistor 201. 位线BL电连接到晶体管203的漏电极,并且第一信号线Sl电连接到晶体管202 的源电极和漏电极中的另一个。 The bit line BL is electrically connected to the drain electrode of transistor 203, and the first signal line Sl is electrically connected to the other of the source electrode and the drain electrode of the transistor 202. 第二信号线S2电连接到晶体管202的栅电极,并且字线WL 电连接到晶体管203的栅电极。 A second signal line S2 is electrically connected to a gate electrode of the transistor 202, and the word line WL is electrically connected to a gate electrode of the transistor 203. 另外,电容器205的一个电极电连接到晶体管201的栅电极以及所述晶体管202的源电极和漏电极中的一个。 Further, the capacitor electrode 205 is electrically connected to the gate electrode of the transistor 201 and a source electrode of the transistor 202 and a drain electrode. 为电容器205的另一个电极提供预定电位,例如GND。 Providing a predetermined potential to the other electrode of the capacitor 205, for example GND.

[0237] 接下来,描述图10中表示的存储单元200的操作。 [0237] Next, the operation storage unit 10 shown in FIG 200. 描述存储单元200是四值存储单元的情况。 The storage unit 200 is described in the case of four-value memory cells. 存储单元200的四种状态是数据"00b"、"01b"、"10b"和"11b",并且在四种状态下的节点A的电位分别是VwVwVltl和Vn (VcitlWV1ZV11)。 Four states of the data storage unit 200 is "00b", "01b", "10b" and "11b", the potential of the node A and the four states are VwVwVltl and Vn (VcitlWV1ZV11).

[0238]当对存储单元200执行写入时,源极线SL设置为0 [V],字线WL设置为0 [V],位线BL设置为0 [V],并且第二信号线S2设置为2 [V]。 [0238] When writing is performed to the memory cell 200, the source line SL is set to 0 [V], the word line WL is set to 0 [V], the bit line BL is set to 0 [V], and the second signal line S2 is set to 2 [V]. 当执行数据"00b"的写入时,第一信号线Sl设置为VTO[V]。 When data "00b" is written, is set to a first signal line Sl VTO [V]. 当执行数据"01b"的写入时,第一信号线Sl设置为Vc^V]。 When data "01b" is written, is set to a first signal line Sl Vc ^ V]. 当执行数据"l〇b"的写入时,第一信号线Sl设置为V1(I[V]。当执行数据"lib"的写入时,第一信号线Sl设置为V11 [V]。此时,晶体管203处于截止状态并且晶体管202处于导通状态。需要注意的是,在写入的末尾,在第一信号线Sl的电位改变之前,第二信号线S2设置为0 [V], 从而晶体管202截止。 When data "l〇b" writing, the first signal line Sl is set to V1 (I [V]. When data "lib" is written, is set to a first signal line Sl V11 [V]. at this time, the transistor 203 is in an off state and the transistor 202 in the on state. Note that, at the end of writing, prior to changing the potential of the first signal line Sl and the second signal line S2 is set to 0 [V], so that the transistor 202 is turned off.

[0239] 结果,在写入数据"0013"、"0113"、"1013"或"1113"之后,连接到晶体管201的栅电极的节点(以下,称为节点A)的电位分别为近似VdVhVdVhVjV]或Vn[V]。 [0239] As a result, the data "0013", "0113", "1013" or after "1113", the node connected to the gate electrode of the transistor 201 (hereinafter referred to as node A) are approximately the potential VdVhVdVhVjV] or Vn [V]. 电荷根据第一信号线Sl的电位而积聚在节点A中,并且由于晶体管202的截止电流极小或者基本上为〇,所以晶体管201的栅电极的电位长时间保留。 The potential of the electric charges accumulated in the first signal line Sl node A, and since the current of the transistor 202 is extremely small or substantially square, the transistor 201 gate electrode potential retention time.

[0240] 当执行存储单元200的读取时,首先,位线BL预充电至Vpe [V]。 [0240] When reading the memory cell 200 is performed, first, the bit line BL is precharged to Vpe [V]. 然后,源极线SL 设置为Vs,ead[V],字线WL设置为2V,第二信号线S2设置为0V,并且第一信号线Sl设置为0 [V]。 Then, the source line SL is set to Vs, ead [V], the word line WL is set to 2V, the second signal line S2 is set to 0V, and the first signal line Sl is set to 0 [V]. 此时,晶体管203处于导通状态并且晶体管202处于截止状态。 At this time, the transistor 203 in the ON state and the transistor 202 is turned off.

[0241] 结果,电流从源极线SL流至位线BL,并且位线BL充电至由(节点A的电位)-(晶体管201的阈值电压Vth)代表的电位。 [0241] As a result, a current flows from the source line SL to the bit line BL, and the bit line BL is charged to the (potential of the node A) is represented by - (transistor 201 threshold voltage Vth) represented potential. 因此,位线BL的电位变为分别与数据"00b"、"01b"、 "10b"和"lib"对应的Vtll-Vtl^Vltl-Vth和Vn-Vth。 Thus, the potential of the bit line BL and the data are changed to "00b", "01b", "10b" and "lib" corresponding Vtll-Vtl ^ Vltl-Vth and Vn-Vth. 由于位线的与数据对应的电位彼此不同,所以连接到位线BL的读取电路能够读出数据"00b"、"01b"、"10b"和"lib"。 Since the potential corresponding to the data bit lines different from each other, the bit line BL connected to a reading circuit capable of reading data "00b", "01b", "10b" and "lib".

[0242] 包括mXn位的存储容量的根据本发明实施例的半导体装置的方框电路图表示在图11中。 [0242] a block circuit diagram of a semiconductor device according to an embodiment of the present invention comprises a storage capacity of mXn bit 11 is shown in FIG.

[0243] 根据本发明实施例的半导体装置包括:m个字线WL;m个第二信号线S2 ;n个位线BL;n个第一信号线SI;n个源极线SL;存储单元阵列210,包括按照m个单元(行)乘n个单元(列)(m和n都是自然数)的矩阵布置的多个存储单元200 (1,1)至200 (m,n);和外围电路,诸如读取电路211、第一信号线驱动器电路212、用于第二信号线和字线的驱动器电路213和电位产生电路214。 [0243] The semiconductor device according to an embodiment of the present invention comprises: m word lines WL; m second signal line S2; n-bit lines BL; n of first signal lines SI; n source lines SL; storage unit array 210, comprises a plurality of memory cells according to the units of m (rows) by n units (columns) (m and n are natural numbers) 200 arranged in a matrix (1, 1) to 200 (m, n); and a peripheral circuit, such as a read circuit 211, a first signal line driver circuit 212, circuit 214 generates a driver circuit 213 and the potential of the second signal lines and word lines. 作为其他外围电路,可提供刷新电路等。 Examples of the other peripheral circuits, refresh circuit may be provided.

[0244] 考虑每个存储单元,例如存储单元200 (i,j)(这里,i是大于或等于1并且小于或等于m的整数,j是大于或等于1并且小于或等于n的整数)。 [0244] Consider each memory cell, for example, the storage unit 200 (i, j) (where, i is greater than or equal to 1 and less than or equal to the integer m, j is greater than or equal to 1 and less than or equal to the integer n). 存储单元200 (i,j)连接到位线BL(j)、第一信号线SI(j)、源极线SL(j)、字线WL⑴和第二信号线S2⑴。 The storage unit 200 (i, j) connected to bit lines BL (j), a first signal line SI (j), the source line SL (j), the word line and the second signal line WL⑴ S2⑴. 另外,位线BL(I)至BL(n)和源极线SL⑴至SL(n)连接到读取电路211。 Further, the bit line BL (I) to BL (n) and the source line SL⑴ to SL (n) is connected to the read circuit 211. 第一信号线Sl⑴至SI(n) 连接到第一信号线驱动器电路212。 A first signal line Sl⑴ to SI (n) is connected to a first signal line driver circuit 212. 字线WL(I)至WL(m)和第二信号线S2(l)至S2(m)连接到用于第二信号线和字线的驱动器电路213。 Word lines WL (I) to WL (m) and the second signal line S2 (l) to S2 (m) are connected to the driver circuit for a second signal line 213 and word lines.

[0245] 用于第二信号线和字线的驱动器电路213的例子表示在图12中。 [0245] Examples of the second signal line driver circuit and the word line 213 shown in FIG. 12. 用于第二信号线和字线的驱动器电路213包括解码器215。 A driver circuit for a second signal line and a word line 213 includes a decoder 215. 解码器215经开关连接到第二信号线S2和字线WL。 Decoder 215 is connected via a switch S2 to the second signal line and a word line WL. 另外,第二信号线S2和字线WL经开关连接到GND(地电位)。 Further, the second signal line S2 and the word line WL is connected via a switch to GND (ground potential). 这些开关由读使能信号(RE信号)或者写使能信号(WE信号)控制。 These switches by the read enable signal (RE signal) or a write enable signal (WE) to control. 地址信号ADR从外部输入到解码器215。 ADR an address signal externally input to the decoder 215.

[0246]当地址信号ADR输入到用于第二信号线和字线的驱动器电路213时,由该地址指定的行(以下,也称为选择的行)被断言(激活)并且其它行(以下,也称为非选择的行) 被去断言(去激活)。 [0246] When the address signal ADR is input to the second circuit for driving signal lines 213 and word lines, designated by the address lines (hereinafter also referred to as selection lines) is asserted (active) and the other row (hereinafter , also known as non-selected row) is de-asserted (deactivated). 另外,当断言RE信号时,字线WL连接到解码器215的输出,并且当去断言RE信号时,字线WL连接到GND。 Further, when signal RE is asserted, the word line WL is connected to the output of the decoder 215, and when the RE signal is de-asserted, the word line WL connected to GND. 当断言WE信号时,第二信号线S2连接到解码器215 的输出,并且当去断言WE信号时,第二信号线S2连接到GND。 When asserted WE signal, the second signal line S2 is connected to the output of the decoder 215 and de-asserted when the WE signal, the second signal line S2 is connected to GND.

[0247] 第一信号线驱动器电路212的例子表示在图13中。 [0247] The first signal line driver circuit 212 shown in FIG. 13 example. 第一信号线驱动器电路212 包括复用器(MUXl)。 A first signal line driver circuit 212 includes a multiplexer (MUXl). DI和写入电位Vcic^Vc^Vltl和Vn输入到复用器(MUXl)。 DI and write potential Vcic ^ Vc ^ Vltl and Vn is input to the multiplexer (MUXl). 复用器的输出端子经开关连接到第一信号线S1。 The multiplexer output terminal via a switch connected to the first signal line S1. 另外,第一信号线Sl经开关连接到GND。 Further, the first signal line via the switch Sl is connected to GND. 这些开关由写入使能信号(WE信号)控制。 The switch consists of a write enable signal (WE) to control.

[0248] 当DI输入到第一信号线驱动器电路212时,复用器(MUXl)根据DI的值从写入电位Vcic^I、Vlt^PVn选择写入电位Vw。 [0248] When DI 212 is input to the first signal line driver circuit, a multiplexer (MUXl) writing potential Vw write potential Vcic ^ I, Vlt ^ PVn from selected according to the value of DI. 复用器(MUXl)的行为显示在表1中。 Behavior multiplexer (MUXl) are shown in Table 1. 当断言WE信号时,选择的写入电位Vw施加于第一信号线S1。 When the WE signal is asserted, the selected writing potential Vw is applied to the first signal line S1. 当去断言WE信号时,OV施加于第一信号线Sl(第一信号线Sl连接到GND)。 When the WE signal is de-asserted, OV is applied to the first signal line Sl (the first signal line Sl is connected to the GND).

[0249] [表1] [0249] [Table 1]

Figure CN104600074AD00271

[0251] 读取电路211的例子表示在图14中。 Examples of [0251] the read circuit 211 shown in FIG. 14. 读取电路211包括多个感测放大器电路、逻辑电路219等。 The reading circuit 211 comprises a plurality of sense amplifier circuits, logic circuit 219 and the like. 每个感测放大器电路的一个输入端子经开关连接到位线BL或配线Vp。 Each input terminal of the switch via a sense amplifier circuit connected to the bit line BL or wiring Vp. . 参考电位VrafJPVMf2中的任何一个输入到每个感测放大器电路的另一个输入端子。 Another reference potential VrafJPVMf2 any input to a sense amplifier circuit for each input terminal. 每个感测放大器电路的输出端子连接到逻辑电路219的输入端子。 The output terminal of each sense amplifier circuit is connected to the input terminal 219 of the logic circuit. 需要注意的是,这些开关由读使能信号(RE信号)控制。 Note that these switches by the read enable signal (RE) to control.

[0252]通过设置每个参考电位VMfQ、UPVMf2的值以满足VM-Vtl^UVtll-VthUVltl -Vth〈VMf2〈Vn-Vth,能够读出存储单元的状态作为3位数字信号。 [0252] By providing each of the reference potential VMfQ, UPVMf2 value to satisfy VM-Vtl ^ UVtll-VthUVltl -Vth <VMf2 <Vn-Vth, state of the memory cell can be read as a 3 bit digital signals. 例如,在数据"00b"的情况下,位线BL的电位是Vcici-Vtht5这里,位线的电位小于参考电位VMf(l、VMfl和VMf2中的任何一个;因此,感测放大器电路的每个输出SA_0UT0、SA_0UT1和SA_0UT2变为"0"。类似地,在数据"〇lb"的情况下,位线BL的电位是Vtll-Vth,从而感测放大器电路的输出SA_0UT0、SA_0UT1 和SA_0UT2分别变为和"0"。在数据"10b"的情况下,位线BL的电位是Vltl-Vth, 由此感测放大器电路的输出SA_0UT0、SA_0UT1和SA_0UT2分别变为和"0"。在数据"lib"的情况下,位线BL的电位是V11-Vth,从而感测放大器电路的输出SA_0UT0、SA_ OUTl和SA_0UT2分别变为和"1"。其后,使用在表2中的逻辑表中显示的逻辑电路219,从读取电路211产生并输出2位数据D0。 For example, in the case where the data "00b", the potential of the bit line BL is Vcici-Vtht5 Here, the potential of the bit line is less than the reference potential VMF (any one of l, VMfl and VMf2; therefore, each sense amplifier circuit output SA_0UT0, SA_0UT1 SA_0UT2 and becomes "0." Similarly, in the case where the data "〇lb", the potential of the bit line BL is Vtll-Vth, so that the output of the sense amplifier circuit SA_0UT0, SA_0UT1 were changed and SA_0UT2 and "0." in the case of the data "10b", the potential of the bit line BL is Vltl-Vth, thereby the output of the sense amplifier circuit SA_0UT0, SA_0UT1 and SA_0UT2 were changed, and "0." in the data "lib" under the circumstances, the potential of the bit line BL is V11-Vth, so that the output of the sense amplifier circuit SA_0UT0, SA_ OUTl and SA_0UT2 were changed and "1." Thereafter, the logic used in the logic shown in table 2 table circuit 219, read circuit 211 generates and outputs the 2-bit data D0.

[0253][表2] [0253] [Table 2]

Figure CN104600074AD00272

[0255] 需要注意的是,在这里表示的读取电路211中,当去断言RE信号时,源极线SL连接到GND并且OV施加于源极线SL。 [0255] Note that, in the reading circuit 211 shown here, when the RE signal is de-asserted, the source line SL is connected to the GND and OV applied to the source line SL. 同时,电位Vpe [V]施加于位线BL和连接到位线BL的感测放大器电路的端子。 Meanwhile, the potential Vpe [V] is applied to the bit line BL and the terminal connected to the bit line sense amplifier circuit of the BL. 当断言RE信号时,VSMad[V]施加于源极线SL,由此反映数据的电位被充电至位线BL。 When the RE signal is asserted, VSMad [V] is applied to the source line SL, thereby reflecting the data is charged to the potential of the bit line BL. 然后,执行读取。 Then, read. 需要注意的是,电位Vp。 It should be noted that the potential Vp. 设置为低于Vcitl-Vtht5另外,Vs Mad设置为高于vn-vth。 Further provided, Vs Mad set higher than vn-vth below Vcitl-Vtht5.

[0256] 需要注意的是,在读取中比较的"位线BL的电位"包括通过开关连接到位线BL的感测放大器电路的输入端子的节点的电位。 [0256] Note that, in the comparison of reading "the potential of the bit line BL 'includes the input terminal potential of the node of the sense amplifier circuit connected to the bit line BL via the switch. 也就是说,在读取电路中比较的电位不必完全与位线BL的电位相同。 That is, in comparison to the potential of the read circuit need not be completely the same as the potential of the bit line BL.

[0257] 电位产生电路214的例子表示在图15中。 [0257] Examples of potential generating circuit 214 shown in FIG. 15. 在电位产生电路214中,通过电阻在Vdd 和GND之间分割电位,由此能够获得所希望的电位。 Potential generating circuit 214 by resistance division between Vdd and the GND potential, thereby to obtain a desired potential. 然后,通过模拟缓冲器220输出产生的电位。 Then, generated by the analog buffer output 220 potential. 以这种方式,产生写入电位Vcic^I、Vltl和Vn以及参考电位V_、Vrefl和Vref2。 In this way, a writing potential Vcic ^ I, Vltl Vn and a reference potential, and V_, Vrefl and Vref2. 需要注意的是,¥(|(|〈1_〈¥ (11〈¥#1〈¥1(|〈¥#2〈¥11的结构表示在图21中;然而,电位关系不限于此。 通过调整电阻器和参考电位所连接到的节点,能够合适地产生所需的电位。另外,可使用与V_、UPVMf2不同的电位产生电路产生VQQ、VQ1、Vltl和Vn。 Note that, ¥ (| (| <1_ <¥ (11 <¥ # 1 <¥ 1 (| <¥ # 2 <¥. 11 structure is shown in FIG. 21; however, by adjusting the potential relation is not limited thereto. and a node of the resistor is connected to a reference potential, it is possible to suitably produce the desired potential. in addition, the use V_, different UPVMf2 potential generation circuit generates VQQ, VQ1, Vltl and Vn of.

[0258] 图17表示差分感测放大器作为感测放大器电路的例子。 [0258] FIG. 17 shows an example of the differential sense amplifier as the sense amplifier circuit. 差分感测放大器包括输入端子Vin⑴和Vin㈠以及输出端子Vtjut,并放大Vin⑴和Vin㈠之差。 Differential sense amplifier comprising an input terminal and an output terminal Vin⑴ and Vin㈠ Vtjut, and amplifies the difference Vin⑴ and Vin㈠. Vtju^Vin⑴〉Vin(_) 时是近似高输出并且在Vin(+) <Vin(_)时是近似低输出。 Vtju ^ Vin⑴> Vin when (_) are approximate and a high output when Vin (+) <Vin (_) is approximately low output.

[0259] 图18表示锁存感测放大器作为感测放大器电路的例子。 [0259] As an example of the sense amplifier circuit of FIG. 18 showing the latch of the sense amplifier. 锁存感测放大器包括输入-输出端子Vl和V2以及控制信号Sp和Sn的输入端子。 Latch sense amplifier comprising an input - output terminals Vl and V2 and the input terminal of the control signal Sp and Sn. 首先,停止把信号Sp设置为高并且把信号Sn设置为低的电源。 First, the stop signal Sp is set to high and the signal Sn is set low power. 接下来,把待比较的电位施加于Vl和V2。 Next, the potential applied to be compared to the Vl and V2. 其后,当提供把信号Sp设置为低并且把信号Sn设置为高的电源时,在提供该电源之前的电位是V1>V2的情况下,Vl变为高输出并且V2变为低输出。 Thereafter, when providing the time signal Sp is set to low and the signal Sn is set to a high power supply potential of the power supply before providing the case of V1> V2 is, Vl and V2 becomes a high output to a low output. 当提供该电源之前的电位是V1〈V2时,Vl变为低输出并且V2变为高输出。 When the potential of the power supply is provided before V1 <V2 when, Vl and V2 output goes low the output goes high. 以这种方式,放大Vl和V2之间的电位差。 In this way, amplifying the potential difference between the Vl and V2.

[0260] 图16A表示写入操作的时序图的例子。 [0260] FIG. 16A shows an example of a timing chart of the write operation. 执行把数据"10b"写入到存储单元的情况表示在图16A中的时序图中。 Implementation of the data "10b" is written to the memory cell a sequence diagram in FIG. 16A. 选择的第二信号线S2早于第一信号线Sl变为0V。 A second signal line S2 is selected earlier than the first signal line Sl becomes 0V. 在写入时间段期间,第一信号线Sl的电位变为Vltl。 During the writing period, the potential of the first signal line Sl becomes Vltl. 需要注意的是,字线WL、位线BL和源极线SL具有0V。 Note that the word line WL, bit line BL and source line SL having 0V. 另外,图16B表示读取操作的时序图的例子。 Further, FIG. 16B shows an example of the read operation timing chart. 从存储单元执行数据"10b"的读取的情况表示在图16B中的时序图中。 Where data read "10b" of a sequence from the storage unit in FIG. 16B in FIG. 当断言选择的字线WL并且源极线SL具有Vs _d[V]时, 位线BL被充电至与存储单元的数据"10b"对应的V1(l-Vth[V]。结果,SA_0UT0、SA_0UT1和SA_0UT2分别变为和"0"。需要注意的是,第一信号线SI和第二信号线S2都具有OV0 When asserted the selected word line WL and the source line SL having a Vs _d [V], the bit line BL is charged data to the memory cell "10b" corresponding to V1 (l-Vth [V]. The results, SA_0UT0, SA_0UT1 and SA_0UT2 were changed, and "0." Note that the first signal line SI and the second signal line S2 have OV0

[0261]这里,描述特定工作电位(电压)的例子。 [0261] Here, a specific operating potential (voltage) is an example. 例如,能够获得下面各项:晶体管201 的阈值电压为近似〇. 3V,电源电压Vdd是2V,Vn是I. 6V,V1(|是I. 2V,VC11是0. 8V,V⑷是0V, Vreftl是0• 3V,Vrefl是0• 7V,并且Vref2是LIV。例如,电位Vp。优选地是0V。 For example, the following can be obtained: the threshold voltage of the transistor 201 is approximately square 3V, the power supply voltage Vdd is 2V, Vn is I. 6V, V1 (| is I. 2V, VC11 is 0. 8V, V⑷ is 0V, Vreftl. is 0 • 3V, Vrefl is 0 • 7V, and Vref2 is LIV. For example, the potential Vp. preferably 0V.

[0262] 另外,在这个实施例中,第一信号线Sl沿位线BL方向(列方向)布置并且第二信号线S2沿字线WL方向(行方向)布置;然而,本发明的一个实施例不限于此。 [0262] Further, in this embodiment, the first signal line Sl is disposed along the bit line BL direction (column direction) and the second signal line S2 are arranged along the word line WL direction (row direction); however, an embodiment of the present invention. embodiment is not limited thereto. 例如,第一信号线Sl可沿字线WL方向(行方向)布置并且第二信号线S2可沿位线BL方向(列方向)布置。 For example, the first signal line Sl may be arranged along the word line WL direction (row direction) and the second signal line S2 along the bit line BL direction (column direction). 在这种情况下,可合适地布置第一信号线Sl所连接到的驱动器电路和第二信号线S2所连接到的驱动器电路。 In this case, it may be suitably disposed a first signal line Sl is connected to the driver circuit and the second signal line S2 is connected to the driver circuit.

[0263] 在这个实施例中,描述了四值存储单元的操作,也就是说,在一个存储单元中执行四种不同状态中的任何一种状态的写入和读取的情况。 [0263] In this embodiment, the operation is described four of the memory cell, that is, the implementation of the writing and reading the state of any one of four different states in one memory cell. 然而,通过合适地改变电路结构,能够执行n值存储单元的操作,也就是说,任意n种不同状态(n是大于或等于2的整数)中的任何一种状态的写入和读取。 However, by suitably changing the circuit configuration, capable of performing the operations of the memory cell n, that is, writing and reading the state of any arbitrary n different states (n is an integer greater than or equal to 2) was added.

[0264] 例如,在八值存储单元中,存储容量变为两值存储单元的三倍。 [0264] For example, in the eight-value storage unit, the storage capacity becomes two to three times the value of the memory cell. 当执行写入时,准备确定节点A的电位的八种写入电位并且产生八种状态。 When writing is performed, the potential of the node A is determined to prepare eight writing potential and generates eight states. 当执行读时,准备能够用于区分这八种状态的七种参考电位。 When performing a read, this preparation can be used to distinguish eight states seven reference potential. 提供一个感测放大器并且执行七次比较,从而能够读出数据。 A sense amplifier and comparison performed seven times, so that data can be read. 另外,通过反馈比较的结果,比较次数可减少至三次。 Further, by comparing the results of the feedback, the number of comparisons may be reduced to three.

[0265] 通常,在2k值存储单元(k是大于或等于1的整数)中,存储容量是两值存储单元的k倍。 [0265] Generally, in the value storage unit 2k (k is an integer equal to or greater than 1), the storage capacity of two times the value of k memory cells. 当执行写入时,准备确定节点A的电位的2k种写入电位并且产生2k种状态。 When writing is performed, 2k kinds of writing potential ready determination node A and the potential of generating 2k states. 当执行读取时,可准备能够用于区分这2k种状态的2k-l种参考电位。 When reading is performed, it can be used to prepare 2k-l distinguish types of reference potential states of 2k. 提供一个感测放大器并且执行2k-l次比较,从而能够读取数据。 A sense amplifier and performs comparisons 2k-l, so that data can be read. 另外,通过反馈比较的结果,比较次数可减少至k次。 Further, the results of the comparison by the feedback, the number of comparisons can be reduced to k times. 在用于驱动源极线SL的读取方法中,通过提供2k-l个感测放大器能够在一次比较中读取数据。 In the reading method for driving a source line SL, the data can be read by providing a comparison 2k-l sense amplifiers. 另外,能够提供多个感测放大器并且多次执行比较。 Further, it is possible to provide a plurality of sense amplifiers and a comparison is performed a plurality of times.

[0266] 因为晶体管202的断态电流特性,根据这个实施例的半导体装置能够把数据保留很长时间。 [0266] Because the off-state current characteristics of the transistor 202, the semiconductor device according to an embodiment of the data can be retained for a long time. 也就是说,不需要在DRAM等中需要的刷新操作,从而能够抑制功耗。 That is, without the need for DRAM refresh operation or the like, so that power consumption can be suppressed. 另外,这个实施例的半导体装置能够用作基本上非易失性的存储装置。 Further, the semiconductor device of this embodiment can be used as a substantially non-volatile storage device.

[0267] 由于通过晶体管202的开关操作执行写入数据等,所以不需要高电压并且不存在元件的劣化的问题。 [0267] Since the data writing operation performed by the switching transistor 202, and the like, a high voltage is not required and no problem of deterioration of the element is present. 另外,因为通过使晶体管导通或截止来执行写入和擦除数据,所以能够容易地实现高速操作。 Further, since the transistor by turning on or off to perform write and erase data, high-speed operation can be easily realized. 另外,通过控制输入到晶体管的电位,能够执行数据的直接重写入。 Further, by controlling the potentials input to the transistor, directly to the rewritten data can be performed. 因此,不需要擦除操作(擦除操作是闪速存储器等中的必需操作),并且能够防止由于擦除操作导致的操作速度的减小。 Thus, no erase operation (erase operation in a flash memory or the like necessary for operation), and since the erasing operation can be prevented due to reduced operation speed.

[0268] 此外,使用除氧化物半导体材料之外的材料的晶体管能够工作于足够高的速度, 因此,通过使用该晶体管,能够以高速读取存储内容。 [0268] Further, using a material other than an oxide semiconductor material transistor can operate in a sufficiently high speed, and therefore, by using the transistor, the content can be read at a high speed memory.

[0269] 根据这个实施例的半导体装置是多值半导体装置,从而能够增加每面积的存储容量。 [0269] The semiconductor device according to this embodiment of the semiconductor device is multi-value, thereby increasing the storage capacity per area. 因此,半导体装置的尺寸能够减小并且半导体装置能够高度集成。 Thus, the size of the semiconductor device can be reduced and the semiconductor device can be highly integrated. 另外,在执行写入操作时变为浮动状态的节点的电位能够被直接控制;因此,能够以高准确性容易地控制阈值电压,这是多值存储元件所需要的情况。 Further, the potential at the time of writing becomes a floating state can be directly controlled node; Accordingly, high accuracy is possible to easily control the threshold voltage, which is multi-value storage element is needed. 因此,多值存储元件要求的写入数据之后的状态的核实能够省略,并且在这种情况下,写入数据所需的时间能够缩短。 Thus, after verification of the state of multi-value write data storage elements required can be omitted, and in this case, the time required to write data can be shortened.

[0270] [实施例3] [0270] [Example 3]

[0271] 在这个实施例中,描述根据本发明实施例的半导体装置的电路结构和操作。 [0271] In this embodiment, description of the circuit configuration of a semiconductor device according to the embodiment and operate in accordance with the present invention.

[0272] 在这个实施例中,利用图10中表示的存储单元的电路结构描述执行与实施例2的读取操作不同的读取操作的情况。 [0272] In this embodiment, the circuit configuration using the memory cell shown in FIG. 10 and described embodiment performs the read operation different from Example 2 in the case of a read operation. 需要注意的是,在一些情况下,在图10中不包括电容器205。 Note that, in some cases, does not include a capacitor 205 in FIG. 10. 存储元件是多值存储元件,并且在这个实施例中描述四值存储单元。 Storage element is a multi-value memory element, and four-value memory cells described in this embodiment. 存储单元200的四种状态是数据"〇〇b"、"01b"、" 10b"和" 11b",并且在四种状态下的节点A的电位分别是HVic^V11(WV1ZV11)0 Four states of the data storage unit 200 is "〇〇b", "01b", "10b" and "11b", the potential of the node A and the four states are HVic ^ V11 (WV1ZV11) 0

[0273] 在对存储单元200执行写入的情况下,源极线SL设置为0[V],字线WL设置为0 [V],位线BL设置为0 [V],并且第二信号线S2设置为2 [V]。 [0273] In the case where the storage unit 200 performs writing, the source line SL is set to 0 [V], the word line WL is set to 0 [V], the bit line BL is set to 0 [V], and the second signal line S2 is set to 2 [V]. 在写入数据"00b"的情况下, 第一信号线Sl设置为VtlJV]。 In the case of writing data "00b", the first signal lines Sl to VtlJV]. 在写入数据"01b"的情况下,第一信号线Sl设置为Vtll [V]。 In the case of writing data "01b", the first signal lines Sl to Vtll [V]. 在写入数据"l〇b"的情况下,第一信号线Sl设置为Vltl [V]。 In the case of writing data "l〇b", the first signal lines Sl to Vltl [V]. 在写入数据"lib"的情况下, 第一信号线Sl设置为V11 [V]。 In the case of writing data "lib", the first signal lines Sl to V11 [V]. 此时,晶体管203处于截止状态并且晶体管202处于导通状态。 At this time, the transistor 203 is in an off state and the transistor 202 in a conducting state. 需要注意的是,在写入的末尾,在第一信号线SI的电位改变之前,第二信号线S2设置为O[V],从而晶体管202截止。 Note that, at the end of writing, prior to changing the potential of the first signal line SI and the second signal line S2 is set to O [V], so that the transistor 202 is turned off.

[0274] 结果,在写入数据"0013"、"0113"、"1013"或"1113"之后,连接到晶体管201的栅电极的节点(以下,称为节点A)的电位分别为近似VdVhVdVhVjV]或Vn[V]。 [0274] As a result, the data "0013", "0113", "1013" or after "1113", the node connected to the gate electrode of the transistor 201 (hereinafter referred to as node A) are approximately the potential VdVhVdVhVjV] or Vn [V]. 电荷根据第一信号线Sl的电位而积聚在节点A中,并且由于晶体管202的截止电流极小或者基本上为〇,所以晶体管201的栅电极的电位长时间保留。 The potential of the electric charges accumulated in the first signal line Sl node A, and since the current of the transistor 202 is extremely small or substantially square, the transistor 201 gate electrode potential retention time.

[0275] 接下来,在执行存储单元200的读取的情况下,源极线SL设置为0V,字线WL设置为VDD,第二信号线S2设置为0V,第一信号线Sl设置为0V,并且连接到位线BL的读取电路211处于操作状态。 [0275] Next, in the case of reading the memory cell 200 is performed, the source line SL is set to 0V, the word line WL is set to the VDD, the second signal line S2 is set to 0V, a first signal line is set to 0V Sl and a reading circuit connected to the bit line BL is in the operating state 211. 此时,晶体管203处于导通状态并且晶体管202处于截止状态。 At this time, the transistor 203 in the ON state and the transistor 202 is turned off.

[0276] 结果,根据存储单元200的状态确定存储单元200的有效电阻值。 [0276] As a result, determining the effective resistance value storage unit 200 according to the state of the memory cell 200. 当节点A的电位增加时,有效电阻值减小。 When the potential of the node A increases, the effective resistance value decreases. 读取电路能够根据电阻值之差读出数据"00b"、"01b"、"10b" 和"lib"。 The read circuit is capable of "00b", "01b", "10b" and "lib" The difference between the resistance values ​​of the read data. 需要注意的是,在除节点A的电位为最低值的数据"00b"之外的数据的情况下, 优选地,晶体管201处于导通状态。 Note that, in the case where data other than the potential of the node A is the minimum value "00b" of data, preferably, the transistor 201 in the ON state.

[0277] 图19表示包括mXn位的存储容量的根据本发明实施例的半导体装置的其他例子的方框电路图。 [0277] FIG. 19 shows a block circuit diagram showing another example comprising a semiconductor device according to an embodiment of the present invention, the storage capacity of mXn bits.

[0278] 图19中表示的半导体装置包括:m个字线WL;m个第二信号线S2 ;n个位线BL;n 个第一信号线SI;存储单元阵列210,在存储单元阵列210中按照m个单元(行)乘n个单元(列)(m和n是自然数)的矩阵布置多个存储单元200 (1,1)至200 (m,n);和外围电路, 诸如读取电路221、第一信号线驱动器电路212、用于第二信号线和字线的驱动器电路213 和电位广生电路214。 The semiconductor device [0278] 19 represented comprises: m word lines WL; m second signal line S2; n-bit lines BL; n the SI of first signal lines; the memory cell array 210, memory cell array 210 in accordance with the m units (rows) by n matrix of cells (columns) (m and n are natural numbers) arranged in a plurality of memory cells 200 (1, 1) to 200 (m, n); and a peripheral circuit, such as a read circuit 221, a first signal line driver circuit 212, a driver circuit 213 and the potential of the second signal line and the word line circuit 214 Kwong Sang. 作为其他外围电路,可提供刷新电路等。 Examples of the other peripheral circuits, refresh circuit may be provided.

[0279] 考虑每个存储单元,例如存储单元200 (i,j)(这里,i是大于或等于1并且小于或等于m的整数,j是大于或等于1并且小于或等于n的整数)。 [0279] Consider each memory cell, for example, the storage unit 200 (i, j) (where, i is greater than or equal to 1 and less than or equal to the integer m, j is greater than or equal to 1 and less than or equal to the integer n). 存储单元200 (i,j)连接到位线BL(j)、第一信号线SI(j)、字线WL⑴、第二信号线S2⑴和源配线。 The storage unit 200 (i, j) connected to bit lines BL (j), a first signal line SI (j), the word line WL⑴, a second signal line and the source line S2⑴. 另外,位线BL⑴ 至BL(n)连接到读取电路221,第一信号线Sl(I)至SI(n)连接到第一信号线驱动器电路212,字线WL(I)至WL(m)和第二信号线S2(l)至S2(m)连接到用于第二信号线和字线的驱动器电路213。 Further, BL⑴ to the bit lines BL (n) is connected to a read circuit 221, a first signal line Sl (I) to SI (n) is connected to a first signal line driver circuit 212, the word line WL (I) to WL (m ) and the second signal line S2 (l) to S2 (m) are connected to the driver circuit for a second signal line 213 and word lines.

[0280] 需要注意的是,例如,电位产生电路214、用于第二信号线和字信号线的驱动器电路213和第一信号线驱动器电路212可以与图15、图12和图13的结构相同。 [0280] Note that, for example, the potential generation circuit 214, a driver circuit 213 for the second signal line and the word line signal and the first signal line driver circuit 212 in FIG. 15 may be the same as the structure of FIGS. 12 and 13 .

[0281] 图20表示读取电路221的例子。 [0281] FIG. 20 shows an example of the read circuit 221. 读取电路221包括:感测放大器电路,参考单元22,逻辑电路219,复用器(MUX2),双稳态多谐振荡器电路FFO、FFl和FF2,偏置电路223等。 The reading circuit 221 comprises: a sense amplifier circuit, the reference cell 22, a logic circuit 219, a multiplexer (MUX2 are), the flip-flop circuit FFO, FFl and FF2, a bias circuit 223 and the like. 参考单元225包括晶体管216、晶体管217和晶体管218。 Reference cell 225 includes a transistor 216, transistor 217 and transistor 218. 参考单元225中所包括的晶体管216、晶体管217和晶体管218分别对应于存储单元中所包括的晶体管201、晶体管202和晶体管203,并形成与存储单元相同的电路结构。 Transistor 225 included in the reference cell 216, a transistor 217 and a transistor corresponding to transistor 218 in the storage unit 201 included, transistor 202 and transistor 203, and the memory cell is formed of the same circuit configuration. 优选地,使用除氧化物半导体之外的材料形成晶体管216和晶体管218,并且使用氧化物半导体形成晶体管217。 Preferably, a material other than an oxide semiconductor transistor 216 and the transistor 218 is formed, and transistor 217 is formed using an oxide semiconductor. 另外,在存储单元包括电容器205的情况下,优选地,参考单元225也包括电容器。 Further, in a case where the memory cell comprises a capacitor 205, preferably, the reference unit 225 also includes a capacitor. 偏置电路223的两个输出端子分别经开关连接到位线BL和参考单元225中所包括的晶体管218的漏电极。 The bias circuit 223 via a switch the two output terminals are connected to bit line BL and the drain of the transistor 225 included in the reference cell 218 electrodes. 另外,偏置电路223的输出端子连接到感测放大器电路的输入端子。 Further, the output terminal of the bias circuit 223 is connected to an input terminal of the sense amplifier circuit. 感测放大器电路的输出端子连接到双稳态多谐振荡器电路FF0、FF1和FF2。 An output terminal of the sense amplifier circuit is connected to the flip-flop circuits FF0, FF1 and FF2. 双稳态多谐振荡器电路FF0、FF1和FF2的输出端子连接到逻辑电路219的输入端子。 Flip-flop circuits FF0, FF1 and FF2 the output terminal is connected to an input terminal 219 of the logic circuit. 信号REO、REl和RE2,参考电位V,efQ、Vrefl和V,ef2 和GND输入到复用器(MUX2)。 Signal REO, REl and RE2, reference potential V, efQ, Vrefl and V, ef2 GND and input to a multiplexer (MUX2). 复用器(MUX2)的输出端子连接到参考单元225中所包括的晶体管217的源电极和漏电极之一。 Multiplexer (MUX2 are) an output terminal connected to the source electrode of one of the reference unit 225 comprises a transistor 217 as a drain electrode and a. 位线BL和参考单元225中所包括的晶体管218的漏电极经开关连接到配线Vp。 The drain bit line BL and the reference cell 225 included in the transistor 218 is connected to the source line via the switch Vp. . 需要注意的是,这些开关由信号FA控制。 Note that these switches are controlled by signal FA.

[0282] 读取电路221具有这样的结构:在该结构中,执行存储单元的电导与参考单元225 的电导的比较。 [0282] Read circuit 221 has a structure: In this structure, the conductivity of the memory cell which performs the comparison of the conductivity of the reference cell 225. 这种结构包括一个感测放大器电路。 This structure includes a sense amplifier circuit. 在这种结构中,执行三次比较以便读出四种状态。 In this structure, the comparison performed three times to read the four states. 换句话说,在三种参考电位中的每一种参考电位的情况下执行存储单元的电导与参考单元225的电导的比较。 In other words, execution of the case where the conductance of the memory cell of each of the three reference potential of the reference potential in comparison with a reference conductivity cell 225. 这三次比较由信号RE0、RE1、RE2和FA控制。 These three are compared by the signal RE0, RE1, RE2 and FA control. 复用器(1^乂2)根据信号1^0、1«1和1«2的值选择三种参考电位1_、¥#1和^# 2和6冊中的任何一种。 A multiplexer (1 qe ^ 2) ^ selected in accordance with a signal value of 0, «1 and 1« 2 three reference potential 1_, ¥ # 1 ^ # and 2 and any one of the six. 复用器(MUX2)的性能表示在表3中。 Multiplexer (MUX2 are) performance shown in Table 3. 双稳态多谐振荡器电路FFO、FFl和FF2分别由信号REO、REl和RE2控制,并存储感测放大器的输出信号SA_0UT的值。 The value of the flip-flop circuit FFO, FFl and FF2 respectively, by signal REO, REl and RE2 control, and stores the output signal of the sense amplifier of SA_0UT.

[0283][表3] [0283] [Table 3]

Figure CN104600074AD00311

[0285] 参考电位的值被确定为¥(|(|〈1_〈¥ (11〈¥#1〈¥1(|〈¥#2〈¥11。因此,根据这三次比较的结果能够读出四种状态。在数据"〇〇b"的情况下,双稳态多谐振荡器电路FFO、FFl和FF2的值是和"0"。在数据"01b"的情况下,双稳态多谐振荡器电路FFO、FFl和FF2的值是和"0"。在数据"10b"的情况下,双稳态多谐振荡器电路FFO、FFl和FF2的值是和"0"。在数据"lib"的情况下,双稳态多谐振荡器电路FFO、FFl和FF2的值是和"1"。以这种方式,能够读出存储单元的状态作为3位数字信号。其后,通过使用在表2中的逻辑值表中表示的逻辑电路219,从读取电路产生并输出2位数据D0。 [0285] value of the reference potential is determined to be ¥ (| (| <1_ <¥ (11 <¥ # 1 <¥ 1 (|. <¥ # 2 <¥ 11 Thus, the results of these three comparisons can be read out four states. in the case of the data "〇〇b", the flip-flop circuit FFO, FFl and FF2 is the value and "0". in the case of the data "01b", the flip-flop circuit FFO, FFl and FF2 is the value and "0." in the case of the data "10b", the flip-flop circuit FFO, FFl and FF2 is the value and "0." in the data "lib" under the circumstances, the flip-flop circuit FFO, FFl and FF2 is the value and state "1". in this way, the memory cell can be read out as a three-bit digital signals. Thereafter, by using the table logic circuit 2 represents the logical value table 219, generates and outputs 2-bit data D0 is read from the circuit.

[0286] 需要注意的是,在图20中表示的读取电路中,当去断言RE信号时,位线BL和参考单元225连接到配线Vp。 [0286] Note that, in the reading circuit shown in FIG. 20, when the RE signal de-asserted, the bit line BL and the reference cell 225 is connected to the line Vp. ,从而执行预充电。 , Thereby performing the precharge. 当断言RE信号时,建立位线BL和偏置电路223 之间以及参考单元225和偏置电路223之间的电连接。 When the RE signal is asserted, and the bit line BL is established between the bias circuit 223 and the reference cells 225 and the electrical connection between the bias circuit 223 is connected.

[0287] 需要注意的是,并非必须执行预充电。 [0287] Note that the precharge need not be performed. 在这个电路中,优选地,产生输入到感测放大器电路的两个信号的电路具有几乎相同的结构。 In this circuit, preferably, the signal generating circuit of two inputs to the sense amplifier circuit having almost the same structure. 例如,优选地,参考单元225中的晶体管的结构与存储单元中的对应晶体管的结构相同。 For example, preferably, the same as the structure corresponding to the structure of the memory cell transistor in the reference cell 225 in the transistor. 优选地,偏置电路223中的对应晶体管和开关具有相同的结构。 Preferably, the corresponding switching transistor and the bias circuit 223 have the same structure.

[0288] 写入操作的时序图与图16A相同。 [0288] The timing diagrams of the write operation of FIG. 16A. 读取操作的时序图的例子显示在图21中。 Examples of a timing chart of the read operation is shown in FIG. 21. 图21显示在从存储单元读出数据"10b"的情况下的时序图。 Figure 21 shows a timing chart in the case of "10b" is read out from the memory cell. 在分别断言信号RE0、RE1和RE2 的情况下,¥_、¥#1和¥#2输入到复用器_乂2)的输出1^2_0^'。 Respectively assert a signal RE0, RE1, and the case of RE2, ¥ _, ¥ # 1 and # 2 is input to the multiplexer ¥ _ qe 2) output 2_0 ^ 1 ^ '. 在每一情况的前半部分,信号FA被断言并且预定电位被施加于参考单元225中所包括的晶体管的节点B。 In the first half of each case, the FA signal is asserted and a predetermined potential is applied to the node 225 included in the reference cell transistor B. 在每一情况的后半部分,信号FA被去断言,预定电位被保留在参考单元225中所包括的晶体管的节点B,并且参考单元225中所包括的晶体管218的漏电极连接到偏置电路223。 In the second half of each case, FA signal is de-asserted, the predetermined potential of the node B is retained in the reference unit 225 included in the transistor, and a drain unit 225 included in the reference transistor 218 is connected to the bias circuit 223. 然后, 感测放大器电路中的比较的结果存储在每个双稳态多谐振荡器电路FF0、FF1和FF2中。 Then, sense amplifier circuit of the comparison result is stored in each flip-flop circuits FF0, FF1 and FF2. 在存储单元的数据是"l〇b"的情况下,双稳态多谐振荡器电路FF0、FF1和FF2的值是" 1"、" 1" 和"0"。 Data in the memory cell is "l〇b", the flip-flop circuits FF0, FF1 and FF2, value is "1", "1" and "0." 需要注意的是,第一信号线Sl和第二信号线S2都具有0V。 Note that the first signal line Sl and the second signal line S2 have 0V.

[0289] 接下来,描述与图20中表示的读取电路不同的读取电路和用于读取的方法。 [0289] Next, different read circuit shown in FIG. 20 and a reading circuit for reading methods.

[0290] 图28表示读取电路222作为例子。 [0290] FIG. 28 shows a reading circuit 222 as an example. 读取电路222包括:感测放大器电路、多个参考单元(参考单元225a、参考单元225b和参考单元225c)、逻辑电路219、双稳态多谐振荡器电路FFO、FFl和FF2、偏置电路223等。 The reading circuit 222 comprises: a sense amplifier circuit, a plurality of reference cells (reference cells 225a, 225b reference cell and the reference cell 225c), the logic circuit 219, flip-flop circuits FFO, FFl and FF2, the bias circuit 223 and so on.

[0291] 参考单元225a、225b和225c中的每一个包括晶体管216、晶体管217和晶体管218。 [0291] Referring units 225a, 225b and 225c each include a transistor 216, transistor 217 and transistor 218. 晶体管216、217和218分别对应于晶体管201、202和203,并形成与存储单元200的电路结构相同的电路结构。 Transistors 216, 217 and 218 respectively correspond to the transistors 201, 202 and 203, and forms a circuit configuration storage unit 200 of the same circuit configuration. 优选地,使用除氧化物半导体之外的材料形成晶体管216和晶体管218,并且使用氧化物半导体形成晶体管217。 Preferably, a material other than an oxide semiconductor transistor 216 and the transistor 218 is formed, and transistor 217 is formed using an oxide semiconductor. 另外,在存储单元包括电容器205的情况下,优选地,每个参考单元也包括电容器。 Further, in a case where the memory cell comprises a capacitor 205, preferably, each of the reference cell also includes a capacitor. 偏置电路223的两个输出端子分别经开关连接到位线BL和多个参考单元中所包括的晶体管218的漏电极。 The bias circuit 223 via the two output terminals of each switching transistor drain connected to bit line BL and a plurality of reference cells 218 included in the electrode. 另外,偏置电路223的输出端子连接到感测放大器电路的输入端子。 Further, the output terminal of the bias circuit 223 is connected to an input terminal of the sense amplifier circuit. 感测放大器电路的输出端子连接到双稳态多谐振荡器电路FF0、FF1和FF2。 An output terminal of the sense amplifier circuit is connected to the flip-flop circuits FF0, FF1 and FF2. 双稳态多谐振荡器电路FF0、FF1和FF2的输出端子连接到逻辑电路219的输入端子。 Flip-flop circuits FF0, FF1 and FF2 the output terminal is connected to an input terminal 219 of the logic circuit. 位线BL和多个参考单元中所包括的晶体管218的漏电极经开关连接到配线Vp。 Drain of transistor 218 the bit line BL and a plurality of reference cells included in the wiring connected to the electrode via the switch Vp. . 需要注意的是,这些开关由读使能信号(RE信号)控制。 Note that these switches by the read enable signal (RE) to control.

[0292] 读取电路222具有这样的结构:在该结构中,执行存储单元的电导与多个参考单元的电导的比较。 [0292] Read circuit 222 has a structure: In this structure, the conductivity of the memory cell which performs the comparison of the conductance of the plurality of reference cells. 这种结构包括一个感测放大器电路。 This structure includes a sense amplifier circuit. 在这种结构中,执行三次比较以便读出四种状态。 In this structure, the comparison performed three times to read the four states. 也就是说,读取电路222具有这样的结构:在该结构中,执行存储单元的电导与三个参考单元中的每一个参考单元的电导的比较。 That is, the read circuit 222 has a structure: In this structure, the conductance of conductance comparison performed with three reference memory cell units each of a reference cell. 这三次比较由信号RE0、RE1、RE2控制。 These three are compared by the signal RE0, RE1, RE2 control. V_、UPVMf2输入到三个参考单元的各自晶体管216的栅电极。 V_, UPVMf2 three reference cell is inputted to the gate electrode of each transistor 216. 在读取之前,断言信号FA,所有晶体管217导通,并且执行对参考单元的写入。 Prior to reading, the FA signal is asserted, all the transistor 217 is turned on, and performs writing to reference cell. 在读取操作之前,可执行一次对参考单元的写入。 Before the read operation, the write-once-executable reference cell. 当然,当执行几次读取时,可执行一次写入,或者每次执行读取时,可执行一次写入。 Of course, when reading performed several times, perform the write-once, or performed each time reading, the write-once-executable. 另外,双稳态多谐振荡器电路FF0、FF1和FF2由信号RE0、RE1和RE2控制,并存储感测放大器的输出信号SA_0UT的值。 Further, the flip-flop circuits FF0, FF1 and FF2 by the signals RE0, RE1 and RE2 control, and storing the output signal SA_0UT sense amplifier.

[0293] 参考电位的值被确定为^〈^。 [0293] value is determined as a reference potential ^ <^. 〈^〈^^、〈^'、。 <^ <^^ <^ ',. 因此^据这三次比较的结果能够读出四种状态。 ^ It is therefore the result of the comparison of these three can be read four states. 在数据"〇〇b"的情况下,双稳态多谐振荡器电路FFO、FFl和FF2的值是和"0"。 In the case of the data "〇〇b", the flip-flop circuit FFO, FFl and FF2 is the value and "0." 在数据"01b"的情况下,双稳态多谐振荡器电路FFO、FFl和FF2的值是和"0"。 In the case of the data "01b", the flip-flop circuit FFO, FFl and FF2 is the value and "0." 在数据"10b"的情况下,双稳态多谐振荡器电路FFO、FFl和FF2的值是和"0"。 In the case of the data "10b", the flip-flop circuit FFO, FFl and FF2 is the value and "0." 在数据"lib"的情况下,双稳态多谐振荡器电路FFO、FFl和FF2的值是和"1"。 In the case of the data "lib", the flip-flop circuit FFO, FFl and FF2, value and the "1." 以这种方式,能够读出存储单元的状态作为3位数字信号。 In this manner, the state of the memory cell can be read as a 3 bit digital signals. 其后,通过使用在表2中的逻辑值表中表示的逻辑电路219,从读取电路产生并输出2位数据D0。 Thereafter, 219 generates and outputs 2-bit data D0 is read from the circuit by a logic circuit using a logic value table shown in the Table 2.

[0294] 需要注意的是,在图28中表不的读取电路中,当去断目RE彳目号时,位线BL和参考单元225连接到配线Vp。 [0294] Note that, not the table reading circuit 28 in FIG, when the left foot to head off RE mesh number, the bit line BL and the reference cell 225 is connected to the line Vp. ,从而执行预充电。 , Thereby performing the precharge. 当断言RE信号时,建立位线BL和偏置电路223 之间以及多个参考单元和偏置电路223之间的电连接。 When the RE signal is asserted, to establish electrical connections between the bit line BL and a plurality of bias circuit 223 and bias circuit 223 and the reference cell.

[0295] 需要注意的是,并非必须执行预充电。 [0295] Note that the precharge need not be performed. 在这个电路中,优选地,产生输入到感测放大器的信号的电路具有几乎相同的结构。 In this circuit, preferably, the signal generating circuit is input to the sense amplifier has almost the same structure. 例如,优选地,参考单元中的晶体管的结构与存储单元中的对应晶体管的结构相同。 For example, preferably, the same as the structure corresponding to the structure of the memory cell transistor in the reference cell transistor is. 优选地,偏置电路223中的对应晶体管和开关具有相同的结构。 Preferably, the corresponding switching transistor and the bias circuit 223 have the same structure.

[0296] 写入操作的时序图与图16A相同。 [0296] The timing diagrams of the write operation of FIG. 16A. 读操作的时序图的例子显示在图29中。 Examples of the read operation timing chart shown in FIG. 29. 图29 显示在从存储单元读出数据"l〇b"的情况下的时序图。 29 shows a timing chart in a case where data is read from the memory cell "l〇b" a. 在分别断言信号RE0、RE1和RE2的情况下,参考单元225a、参考单元225b和参考单元225c被选择并连接到偏置电路223。 Respectively assert a signal RE0, RE1 and RE2 case, the reference cells 225a, 225b and a reference cell is selected and the reference cell 225c is connected to the bias circuit 223. 然后,感测放大器电路中的比较的结果存储在每个双稳态多谐振荡器电路FF0、FF1和FF2中。 Then, sense amplifier circuit of the comparison result is stored in each flip-flop circuits FF0, FF1 and FF2. 在存储单元的数据是"l〇b"的情况下,双稳态多谐振荡器电路FFO、FFl和FF2的值是"1"、 "1"和"0"。 Data in the memory cell is "l〇b", the flip-flop circuit FFO, FFl and FF2 value is "1", "1" and "0." 需要注意的是,第一信号线Sl和第二信号线S2都具有0V。 Note that the first signal line Sl and the second signal line S2 have 0V.

[0297] 描述特定工作电位(电压)的例子。 [0297] Examples of describing particular operating potential (voltage). 例如,能够获得下面各项:晶体管201的阈值电压为近似〇. 3V,电源电位Vdd是2V,Vn是I. 6V,V1Q是I. 2V,V01是0. 8V,VQQ是0V,Vref。 For example, the following can be obtained: the threshold voltage of the transistor 201 is approximately square 3V, the power supply potential Vdd is 2V, Vn is I. 6V, V1Q is I. 2V, V01 is 0. 8V, VQQ is 0V, Vref.. 是0. 6V,VMfl是I. 0V,并且VMf2是I. 4V。 Is 0. 6V, VMfl is I. 0V, and is VMf2 I. 4V. 例如,电位Vp。 For example, the potential Vp. 优选地是0V。 Preferably 0V.

[0298] 虽然在这个实施例中第一信号线Sl沿位线BL方向(列方向)布置并且第二信号线S2沿字线WL方向(行方向)布置,但本发明的实施例不限于此。 [0298] Although the first signal line Sl along the bit line BL direction (column direction) in this embodiment and the second signal line S2 along the word line WL direction (row direction), but the embodiment of the present invention is not limited thereto . 例如,第一信号线Sl可沿字线WL方向(行方向)布置并且第二信号线S2可沿位线BL方向(列方向)布置。 For example, the first signal line Sl may be arranged along the word line WL direction (row direction) and the second signal line S2 along the bit line BL direction (column direction). 在这种情况下,可合适地布置第一信号线Sl所连接到的驱动器电路和第二信号线S2所连接到的驱动器电路。 In this case, it may be suitably disposed a first signal line Sl is connected to the driver circuit and the second signal line S2 is connected to the driver circuit.

[0299] 在这个实施例中,描述了四值存储单元的操作,也就是说,在一个存储单元中执行四种不同状态中的任何一种状态的写入和读取的情况。 [0299] In this embodiment, the operation is described four of the memory cell, that is, the implementation of the writing and reading the state of any one of four different states in one memory cell. 然而,通过合适地改变电路结构,能够执行n值存储单元的写入和读取,也就是说,任意n种不同状态(n是2或更大的整数) 中的任何一种状态的写入和读取。 Any write status, however, by suitably changing the circuit configuration, capable of performing write and read of the memory cell n, i.e., n different arbitrary state (n is an integer of 2 or more) of and read.

[0300] 例如,八值存储单元的存储容量是两值存储单元的存储容量的三倍。 [0300] For example, the storage capacity of eight-value memory cell is two to three times the storage capacity of the memory cell. 当执行写入时,准备确定节点A的电位的八种写入电位并且产生八种状态。 When writing is performed, the potential of the node A is determined to prepare eight writing potential and generates eight states. 当执行读取时,准备能够用于区分这八种状态的七种参考电位。 When reading is performed, it can be used to prepare seven kinds of reference potential to distinguish between the eight states. 当执行读取时,提供一个感测放大器并且执行七次比较,从而能够读出数据。 When reading is performed, a sense amplifier and comparison performed seven times, so that data can be read. 另外,通过反馈比较的结果,比较次数可减少至三次。 Further, by comparing the results of the feedback, the number of comparisons may be reduced to three. 在驱动源极线SL的读取方法中,当提供七个感测放大器时,能够通过执行一次比较读出数据。 In the driving method of reading the source line SL, when the sense amplifier to provide seven, can be read out by performing a comparison. 另外,能够采用提供多个感测放大器并且多次执行比较的结构。 Further, it is possible to provide a plurality of sense amplifiers employed and the structure of the comparison performed a plurality of times.

[0301] 通常,2k值存储单元(k是1或更大的整数)的存储容量是两值存储单元的存储容量的k倍。 [0301] Generally, 2k value storage unit (k is an integer of 1 or more) k storage capacity is two times the storage capacity of the memory cell. 当执行写入时,准备确定节点A的电位的2k种写入电位并且产生2k种状态。 When writing is performed, 2k kinds of writing potential ready determination node A and the potential of generating 2k states. 当执行读取时,优选地准备能够用于区分这2k种状态的2k-l种参考电位。 When reading is performed, it can be preferably prepared for 2k-l distinguish types of reference potential states of 2k. 提供一个感测放大器并且通过执行2k-l次比较能够读出数据。 A sense amplifier and by performing 2k-l comparisons data can be read. 另外,通过反馈比较的结果,比较次数可减少至k次。 Further, the results of the comparison by the feedback, the number of comparisons can be reduced to k times. 在驱动源极线SL的读取方法中,通过提供2k-l个感测放大器,能够通过执行一次比较执行读取。 In the driving method of reading the source line SL by providing 2k-l sense amplifiers, a comparison can be performed by performing a read. 另外,能够采用提供多个感测放大器并且多次执行比较的结构。 Further, it is possible to provide a plurality of sense amplifiers employed and the structure of the comparison performed a plurality of times.

[0302] 在根据这个实施例的半导体装置中,因为晶体管202的低截止电流特性,数据能够保留极长时间。 [0302] In the semiconductor device according to this embodiment, since the low off current characteristics of the transistor 202, the data retention can be extremely long. 换句话说,不需要在DRAM等中需要的刷新操作,从而能够抑制功耗。 In other words, no DRAM requires the refresh operation or the like, so that power consumption can be suppressed. 另夕卜,根据这个实施例的半导体装置能够用作基本上非易失性的存储装置。 Another Bu Xi, the semiconductor device according to the embodiment can be used as a substantially non-volatile storage device.

[0303] 另外,通过晶体管202的开关操作执行数据的写入等;因此,不需要高电压并且不存在元件的劣化的问题。 [0303] Further, the write operation by the switching transistor 202 performs data and the like; thus, no high-voltage problems and deterioration of the element does not exist. 另外,通过使晶体管导通或截止来执行数据的写入和擦除;因此, 能够容易地获得高速操作。 Further, the transistor is turned on or off to perform writing and erasing data; thus, it is possible to easily obtain high-speed operation. 通过控制输入到晶体管的电位,能够执行数据的直接重写入。 By controlling the input to the potential of the transistor directly rewritten data can be performed. 因此,不需要擦除操作(擦除操作是在闪速存储器等中需要的操作),从而能够抑制由于擦除操作导致的操作速度的减小。 Thus, no erase operation (erase operation is an operation required in flash memory, etc.), it is possible to suppress a decrease in operation since the erase operation speed caused.

[0304] 另外,使用除氧化物半导体之外的材料形成的晶体管能够工作于足够高的速度, 因此,通过使用该晶体管,能够以高速读出存储内容。 [0304] Further, using a material other than an oxide semiconductor can operate in a transistor formed sufficiently high speed, and therefore, by using the transistor, at a high speed read out the stored content.

[0305] 由于根据这个实施例的半导体装置是多值半导体,所以能够增加每单位面积的存储容量。 [0305] Since the semiconductor device according to this embodiment is a semiconductor multi-valued, it is possible to increase the storage capacity per unit area. 因此,能够实现半导体装置的小型化及其高度集成。 Accordingly, the semiconductor device can be miniaturized and highly integrated. 另外,当执行写入时,将要处于浮动状态的节点的电位能够被直接控制;因此,能够容易地执行多值存储元件中所需的具有高准确性的阈值电压的控制。 Further potential of the node, when writing is performed, to be in a floating state can be controlled directly; therefore, it is possible to easily perform control of the desired multi-value storage element has a threshold voltage higher accuracy. 因此,多值存储元件中要求的写入之后的状态的断言能够省略;因此,在这种情况下,写入所需的时间能够缩短。 Accordingly, the asserted state after writing multi-value memory element requirements can be omitted; thus, in this case, the time required for writing can be shortened.

[0306] [实施例4] [0306] [Example 4]

[0307] 在这个实施例中,描述与实施例2和实施例3不同的半导体装置的电路结构和操作作为例子。 [0307] In this embodiment, description and Examples 2 and 3 a circuit configuration of a semiconductor device according to a different embodiment of example and operation.

[0308] 图22表示半导体装置中所包括的存储单元的电路图的例子。 [0308] FIG. 22 shows an example circuit diagram showing a memory cell of a semiconductor device included. 图22中表示的存储单元240包括源极线SL、位线BL、第一信号线S1、第二信号线S2、字线WL、晶体管201、晶体管202和电容器204。 Figure 22 shows the storage unit 240 includes a source line SL, bit lines BL, a first signal line S1, the second signal line S2, the word line WL, transistor 201, transistor 202 and capacitor 204. 使用除氧化物半导体之外的材料形成晶体管201,并且使用氧化物半导体形成晶体管202。 In addition to using a material for forming an oxide semiconductor transistor 201, and transistor 202 is formed using an oxide semiconductor.

[0309] 这里,晶体管201的栅电极、晶体管202的源电极和漏电极中的一个以及电容器204的电极中的一个彼此电连接。 [0309] Here, the gate electrode of the transistor 201, the source electrode and the drain electrode of the transistor 202 and a capacitor 204 is in an electrically connected to each other. 另外,源极线SL和晶体管201的源电极彼此电连接。 Further, the source line SL and a source electrode of the transistor 201 are electrically connected to each other. 位线BL和晶体管201的漏电极彼此电连接。 Bit line BL and the drain of the transistor 201 is electrically connected to each other. 第一信号线Sl和晶体管202的源电极和漏电极中的另一个彼此电连接。 Another power source and drain electrodes from each other a first signal line Sl and the transistor 202 is connected. 第二信号线S2和晶体管202的栅电极彼此电连接。 A second signal line S2 and the gate electrode of transistor 202 is electrically connected to each other. 字线WL和电容器204的另一个电极彼此电连接。 Word line WL and the other electrode of the capacitor 204 is electrically connected to each other.

[0310] 接下来,描述图22中表示的存储单元240的操作。 [0310] Next, the operation storage unit 22 shown in FIG 240. 这里,采用四值存储单元。 Here, four-value storage unit. 存储单元240的四种状态是数据"00b"、"01b"、"10b"和"11b",并且在四种状态下的节点A 的电位分别是VQQ、Vtll、Vltl和Vn (VQQ〈Wc^V11)。 The storage unit 240 is data of four states "00b", "01b", "10b" and "11b", the potential of the node A and the four states are VQQ, Vtll, Vltl and Vn (VQQ <Wc ^ V11).

[0311] 在执行对存储单元240的写入的情况下,源极线SL设置为0[V],字线WL设置为0 [V],位线BL设置为0 [V],并且第二信号线S2设置为Vdd[V]。 [0311] In the case of performing the writing to the memory cell 240, the source line SL is set to 0 [V], the word line WL is set to 0 [V], the bit line BL is set to 0 [V], and the second a signal line S2 is set to Vdd [V]. 在写入数据"00b"的情况下, 第一信号线Sl设置为VtlJV]。 In the case of writing data "00b", the first signal lines Sl to VtlJV]. 当写入数据"01b"的情况下,第一信号线Sl设置为Vtll [V]。 In the case where the write data is "01b", the first signal lines Sl to Vtll [V]. 当写入数据"l〇b"的情况下,第一信号线Sl设置为Vltl [V]。 In the case where the data "l〇b", the first signal lines Sl to Vltl [V]. 当写入数据"lib"的情况下, 第一信号线Sl设置为V11 [V]。 In the case where the write data "lib", the first signal lines Sl to V11 [V]. 此时,晶体管201处于截止状态并且晶体管202处于导通状态。 At this time, the transistor 201 is in an off state and the transistor 202 in a conducting state. 需要注意的是,在写入的末尾,在第一信号线Sl的电位改变之前,第二信号线S2设置为0 [V],从而晶体管202截止。 Note that, at the end of writing, prior to changing the potential of the first signal line Sl and the second signal line S2 is set to 0 [V], so that the transistor 202 is turned off.

[0312] 结果,在写入数据"0013"、"0113"、"1013"或"1113"(字线孔的电位设置为(^)之后, 连接到晶体管201的栅电极的节点(以下,称为节点A)的电位分别为近似LjVhVtV]、 V1(I[V]或Vn[V]。电荷根据第一信号线SI的电位而积聚在节点A中,并且由于晶体管202 的截止电流极小或者近似为〇,所以晶体管201的栅电极的电位长时间保留。 After [0312] As a result, the data "0013", "0113", "1013" or "1113" (the potential of the word line set aperture (^), the node connected to the gate electrode of transistor 201 (hereinafter referred to node a) are approximately the potential LjVhVtV], V1 (I [V] or Vn [V]. charges accumulated in the potential of the node a according to the first signal line SI, and since the current of the transistor 202 is extremely small, or is approximately square, the potential of the gate electrode of transistor 201 is retained for a long time.

[0313] 接下来,在执行存储单元240的读取的情况下,源极线SL设置为0V,第二信号线S2设置为0V,第一信号线Sl设置为0V,并且连接到位线BL的读取电路处于操作状态。 [0313] Next, in the case of reading the memory execution unit 240, the source line SL is set to 0V, the second signal line S2 is set to 0V, a first signal line Sl set to 0V, and connected to the bit line BL reading circuit in operation. 此时,晶体管202处于截止状态。 At this time, the transistor 202 is turned off.

[0314] 字线WL设置为Vi[V]。 [0314] Word line WL is set to Vi [V]. 存储单元240的节点A的电位取决于字线WL的电位。 A potential of the memory cell node 240 depends on the potential of the word line WL. 当字线WL的电位增加时,存储单元240的节点A的电位增加。 When the potential of the word line WL increases, the potential of the node A of the storage unit 240 is increased. 例如,在四种不同状态下施加于存储单元的字线WL的电位从低电位变为高电位,数据"lib"的存储单元的晶体管201首先导通,然后,数据"l〇b"的存储单元、数据"01b"的存储单元和数据"00b"的存储单元按照这种次序导通。 For example, in four different states is applied to the word line WL of the memory cell from the low potential to the potential of the high voltage transistors, the data "lib" in the storage unit 201 is turned on first, and then, data "l〇b 'storage unit, the data "01b" and the memory cell data "00b" of the memory cell is turned on in this order. 换句话说,通过合适地选择字线WL的电位,能够区分存储单元的状态(也就是,存储单元中所包括的数据)。 In other words, by suitably selecting the potential of the word line WL, the memory cell can distinguish the state (i.e., the storage unit included in the data). 通过合适地选择字线WL的电位,晶体管201处于导通状态的存储单元处于低电阻状态,并且晶体管201处于截止状态的存储单元处于高电阻状态;因此,当由读取电路区分电阻状态时,能够读出数据"00b"、"01b"、"10b"*"llb"。 By suitably selecting the potential of the word line WL, the memory cell transistor 201 in the ON state in the low resistance state, and the transistor 201 in an off state of the memory cell in a high resistance state; therefore, when the resistance state distinguished by the reading circuit, able to read data "00b", "01b", "10b" * "llb".

[0315] 图23表示包括mXn位的存储容量的根据本发明实施例的半导体装置的其他例子的方框电路图。 [0315] FIG. 23 shows a block circuit diagram showing a storage capacity comprises mXn bit according to another example embodiment of the semiconductor device according to the present invention.

[0316] 图23中表示的半导体装置包括:m个字线WL;m个第二信号线S2 ;n个位线BL;n 个第一信号线SI;存储单元阵列210,存储单元阵列210中,按照m个单元(行)乘n个单元(列)(m和n是自然数)的矩阵布置多个存储单元240 (1,1)至240 (m,n);和外围电路, 诸如读取电路231、第一信号线驱动器电路212、用于第二信号线和字线的驱动器电路233 和电位广生电路214。 The semiconductor device of [0316] FIG. 23 represent include: m word lines WL; m second signal line S2; n-bit lines BL; n the SI of first signal lines; the memory cell array 210, the memory cell array 210 , by means of n (columns) (m and n are natural numbers) according to the m units (rows) a plurality of memory cells 240 arranged in a matrix (1, 1) to 240 (m, n); and a peripheral circuit, such as a read circuit 231, a first signal line driver circuit 212, a driver circuit 233 and the potential of the second signal line and the word line circuit 214 Kwong Sang. 作为其他外围电路,可提供刷新电路等。 Examples of the other peripheral circuits, refresh circuit may be provided.

[0317] 考虑每个存储单元,例如存储单元240 (i,j)(这里,i是大于或等于1并且小于或等于m的整数,j是大于或等于1并且小于或等于n的整数)。 [0317] Consider each memory cell, for example, the storage unit 240 (i, j) (where, i is greater than or equal to 1 and less than or equal to the integer m, j is greater than or equal to 1 and less than or equal to the integer n). 存储单元240 (i,j)连接到位线BL(j)、第一信号线SI(j)、字线WL(i)、第二信号线S2(i)和源极线SL。 The storage unit 240 (i, j) connected to bit lines BL (j), a first signal line SI (j), the word line WL (i), the second signal line S2 (i) and the source line SL. 另外,位线BL(I)至BL(n)连接到读取电路231,第一信号线Sl(I)至SI(n)连接到第一信号线驱动器电路212,字线WL⑴至WL(m)和第二信号线S2⑴至S2(m)连接到用于第二信号线S2和字线WL的驱动器电路233。 Further, the bit line BL (I) to BL (n) is connected to a read circuit 231, a first signal line Sl (I) to SI (n) is connected to a first signal line driver circuit 212, the word lines WL⑴ to WL (m ) and a second signal line to S2⑴ S2 (m) are connected to the driver circuit and a second signal line S2 233 word lines WL.

[0318] 需要注意的是,图13和图15中表示的结构能够分别用于第一信号线驱动器电路212和电位产生电路214的结构。 [0318] Note that the structure shown in FIGS. 15 and 13, respectively, can be a first signal line driver circuit 212 and the potential generation circuit 214 configuration.

[0319] 图24表示读取电路的例子。 [0319] FIG. 24 shows an example of the reading circuit. 读取电路包括:感测放大器电路、双稳态多谐振荡器电路、偏置电路224等。 The reading circuit comprising: a sense amplifier circuit, a bistable multivibrator circuit, the bias circuit 224 and the like. 偏置电路224经开关连接到位线BL。 The bias circuit 224 via a switch connected to the bit line BL. 另外,偏置电路224连接到感测放大器电路的输入端子。 Further, the bias circuit 224 is connected to the input terminal of the sense amplifier circuit. 参考电位t输入到感测放大器电路的其他输入端子。 T the reference potential input to the other input terminal of the sense amplifier circuit. 感测放大器电路的输出端子连接到双稳态多谐振荡器电路FR)和FFl的输入端子。 An output terminal of the sense amplifier circuit is connected to the input terminal of the flip-flop circuit oscillator FR) and the FFl. 需要注意的是, 开关由读使能信号(RE信号)控制。 It is noted that the switch from the read enable signal (RE) to control. 该读取电路能够通过读出连接到位线BL的指定存储单元的电导读出数据。 The circuit can be read by reading out the specified data is read electrically connected to bit lines BL of the memory cell. 需要注意的是,存储单元的电导的读取表示存储单元中所包括的晶体管201的导通或截止状态的读取。 Note that the conductance reading means to read the memory cell turned on or off state of the memory cell transistor 201 is included.

[0320] 图24中表示的读取电路包括一个感测放大器,并执行两次比较以便区分四种状态。 Read circuit [0320] FIG. 24 shows a sense amplifier comprises, and perform two comparisons to distinguish four states. 这两次比较由信号REO和REl控制。 Comparison of these two signals is controlled by the REO and REl. 双稳态多谐振荡器电路FFO和FFl分别由信号REO和REl控制,并存储感测放大器电路的输出信号的值。 Flip-flop circuits FFl and FFO respectively, by control signals REl and REO, and storing the output signal of the sense amplifier circuit. 从读取电路输出双稳态多谐振荡器电路FR)的输出D0[1]和双稳态多谐振荡器电路FFl的输出D0[0]。 FR flip-flop circuit from the read circuit output) output D0 [1] and the flip-flop circuit FFl output D0 [0].

[0321] 需要注意的是,在示出的读取电路中,当去断言RE信号时,位线BL连接到配线Vpe 并且执行预充电。 [0321] Note that, in the reading circuit shown, when the RE signal de-asserted, the bit line BL is connected to the wiring Vpe and precharge is performed. 当断言RE信号时,建立位线BL和偏置电路224之间的电连接。 When the RE signal is asserted, an electrical connection between the bit line BL and the bias circuit 224. 需要注意的是,并非必须执行预充电。 It should be noted that not must perform a pre-charging.

[0322] 图25表示用于第二信号线S2和字线WL的驱动器电路233作为其他例子。 [0322] FIG. 25 shows a second circuit for driving the signal line S2 and the word line WL 233 as another example.

[0323] 在图25中表示的用于第二信号线S2和字线WL的驱动器电路233中,当输入地址信号ADR时,由该地址指定的行(选择的行)被断言,并且其它行(非选择的行)被去断言。 [0323] shown in FIG. 25 for a second signal line S2 and the word line WL of the driver circuit 233, when the input address signal ADR, the address specified by the row (selected row) is asserted, and the other row (non-selected row) is de-asserted. 当断言WE信号时,第二信号线S2连接到解码器输出,并且当去断言WE信号时,第二信号线S2连接到GND。 When asserted WE signal, the second signal line S2 is connected to the decoder output, and when de-asserted WE signal, the second signal line S2 is connected to GND. 选择的行中的字线WL连接到复用器(MUX3)的输出Vj,并且非选择的行中的字线WL连接到GND。 Row word line WL selected row word line WL is connected to a multiplexer (MUX3) output Vj, and the non-selected is connected to GND. 复用器(MUX3)响应于信号REO、REl和DO的值选择三种参考电位1_、1抓和¥#2中的任何一种或者6冊。 A multiplexer (MUX3) in response to a signal REO, and DO values ​​REl choice of three reference potential 1_, any one of a grasping and a ¥ # 2 or 6 in. 复用器(1^乂3)的行为显示在表4中。 Behavior multiplexer (1 ^ qe 3) shown in Table 4.

[0324][表4] [0324] [Table 4]

Figure CN104600074AD00361

[0326] 描述这三种参考电位VMfQ、UPVMf2 (VMfQ〈VMfl〈VMf2)。 [0326] described with reference to the three potential VMfQ, UPVMf2 (VMfQ <VMfl <VMf2). 在选择U乍为字线WL 的电位的情况下,选择使数据"〇〇b"的存储单元的晶体管201截止并且使数据"01b"的存储单元的晶体管201导通的电位作为V,ef(l。另外,在选择Vrefl作为字线WL的电位的情况下,选择使数据"〇lb"的存储单元的晶体管201截止并且使数据"10b"的存储单元的晶体管201导通的电位作为V,efl。另外,在选择V,ef2作为字线WL的电位的情况下,选择使数据"l〇b"的存储单元的晶体管201截止并且使数据"lib"的存储单元的晶体管201导通的电位作为VMf2。 In the case of selecting the U at first as the potential of the word line WL of the memory cell transistor selected data "〇〇b" 201 is turned off and the potential of the conductive memory cell 201 data "01b" as a transistor V, ef ( l. Further, in the case of selecting a word line WL Vrefl potential, selected so that the data "〇lb" memory cell transistor 201 is turned off and the data "10b" of the memory cell 201 is turned on as a transistor potential V, case efl. Further, the choice V, ef2 as the potential of the word line WL, so that the data selection "l〇b" memory cell transistor 201 is turned off and the data "lib" in the memory cell 201 is turned potential of transistor as VMf2.

[0327] 在读取电路中,通过两次比较执行读取。 [0327] In the reading circuit, the reading is performed by comparing the two. 使用VMfl执行第一比较。 Use VMfl execution first comparison. 当由于利用VMfl 的比较导致双稳态多谐振荡器电路FR)的值是"0"时使用VMf(l执行第二比较,或者当由于利用VMfl的比较导致双稳态多谐振荡器电路FFO的值是"1"时使用Vref2执行第二比较。按照以上方式,通过两次比较能够读出四种状态。 When using VMf VMfl since the comparison results of the flip-flop circuit FR) value is "0" (L performing a second comparison, when the oscillator circuit or FFO VMfl since the comparison results of the flip-flop the value Vref2 is performed using the second comparative "1". in the above manner, two comparisons can be read by four states.

[0328] 写入操作的时序图与图16A相同。 [0328] The timing diagrams of the write operation of FIG. 16A. 读取操作的时序图的例子显示在图26中。 Examples of a timing chart of the read operation is shown in FIG. 26. 图26显示在从存储单元读出数据"10b"的情况下的时序图。 Figure 26 shows a timing chart in the case of "10b" is read out from the memory cell. 在断言信号REO和REl的情况下,VMfjPVMf2输入到选择的各字线WL,并且感测放大器中的比较结果存储在双稳态多谐振荡器电路FR)和FFl中。 In the case of the assert signals REl and REO, VMfjPVMf2 inputted to each of the selected word line WL, and the sense of the comparison result stored in the sense amplifier flip-flop circuit FR), and in FFl. 在存储单元的数据是"10b"的情况下,双稳态多谐振荡器电路FR)和FFl的值是"1"和"0"。 Data in the case where the memory cell is "10b", the value of the flip-flop circuit FR) and FFl is "1" and "0." 需要注意的是,第一信号线Sl和第二信号线S2具有0V。 Note that the first signal line Sl and the second signal line S2 having 0V.

[0329] 描述特定工作电位(电压)的例子。 [0329] Examples of describing particular operating potential (voltage). 例如,晶体管201的阈值电压Vth为2. 2V。 For example, the transistor 201 threshold voltage Vth is 2. 2V. 节点A的电位取决于字线WL和节点A之间的电容Cl以及晶体管202的栅电容C2,并且在这里,例如,当晶体管202处于截止状态时C1/C2>>1,并且当晶体管202处于导通状态时Cl/ C2 = 1。 The potential of the node A depends on the capacitance Cl between the word line WL and the node A 202 and the transistor gate capacitance C2, and here, for example, when the transistor 202 in an off state C1 / C2 >> 1, and when the transistor 202 is when conducting state Cl / C2 = 1. 图27显示在源极线SL具有OV的情况下节点A的电位和字线WL的电位之间的关系。 Figure 27 shows the relationship between the word line and the potential of the node A in the case of a OV source line SL WL potential. 从图27,发现:在执行写入的情况下,参考电位V_、Vrefl和V 尤选地分别是0. 8V、 I. 2V和2. 0V,数据"00b"的节点A的电位是0V,数据"01b"的节点A的电位是0. 8V,数据"10b"的节点A的电位是I. 2V,并且数据"lib"的节点A的电位是I. 6V。 From FIG 27, it was found: in a case where writing is performed, a reference potential V_, Vrefl and optionally V are in particular 0. 8V, I. ​​2V and 2. 0V, potential of the data "00b" of the node A is 0V, potential of the data "01b" of the node a is 0. 8V, the potential of the data "10b" of the node a is I. 2V, and the potential of the data "lib" node a is I. 6V.

[0330] 需要注意的是,在写入之后的晶体管201的节点A的电位(字线WL的电位是0V) 优选地低于或等于晶体管201的阈值电压。 [0330] Note that, after writing the potential of the transistor 201 of the node A (the potential of the word line WL is 0V) is preferably lower than or equal to the threshold voltage of transistor 201.

[0331] 虽然这个实施例采用了第一信号线Sl沿位线BL方向(列方向)布置并且第二信号线S2沿字线WL方向(行方向)布置的结构,但本发明的一个实施例不限于此。 [0331] Although this embodiment employs the first signal line Sl along the bit line BL direction (column direction) and the second signal line S2 are arranged along the word line WL direction (row direction) structure, but an embodiment of the present invention is not limited thereto. 例如,第一信号线Sl可沿字线WL方向(行方向)布置并且第二信号线S2可沿位线BL方向(列方向)布置。 For example, the first signal line Sl may be arranged along the word line WL direction (row direction) and the second signal line S2 along the bit line BL direction (column direction). 在这种情况下,可合适地布置第一信号线Sl所连接到的驱动器电路和第二信号线S2所连接到的驱动器电路。 In this case, it may be suitably disposed a first signal line Sl is connected to the driver circuit and the second signal line S2 is connected to the driver circuit.

[0332] 在这个实施例中,描述了四值存储单元的操作,也就是说,对一个存储单元执行四种不同状态中的任何一种状态的写入和读取的情况。 [0332] In this embodiment, the operation is described four of the memory cell, that is, the implementation of the writing and reading the state of any one of four different states of a memory cell. 通过合适地改变电路结构,能够执行n 值存储单元的写入和读取,也就是,任意n种不同状态(n是2或更大的整数)中的任何一种状态的写入和读取。 By suitably changing the circuit configuration, the n value storage unit perform writing and reading, i.e., any of n different states (n is an integer of 2 or more) in any one state of the writing and reading .

[0333] 例如,八值存储单元的存储容量是两值存储单元的存储容量的三倍。 [0333] For example, the storage capacity of eight-value memory cell is two to three times the storage capacity of the memory cell. 当执行写入时,准备确定节点A的电位的八种写入电位并且产生八种状态。 When writing is performed, the potential of the node A is determined to prepare eight writing potential and generates eight states. 当执行读取时,准备能够用于区分这八种状态的七种参考电位。 When reading is performed, it can be used to prepare seven kinds of reference potential to distinguish between the eight states. 当执行读取时,提供一个感测放大器并且执行七次比较,从而能够读出数据。 When reading is performed, a sense amplifier and comparison performed seven times, so that data can be read. 另外,通过反馈比较的结果,比较次数能够减少至三次。 Further, by comparing the results of the feedback, the number of comparisons can be reduced to three. 在驱动源极线SL的读取方法中,当提供七个感测放大器时,能够通过执行一次比较读出数据。 In the driving method of reading the source line SL, when the sense amplifier to provide seven, can be read out by performing a comparison. 另外, 能够采用提供多个感测放大器并且多次执行比较的结构。 Further, it is possible to provide a plurality of sense amplifiers employed and the structure of the comparison performed a plurality of times.

[0334] 通常,2k值存储单元(k是1或更大的整数)的存储容量是两值存储单元的存储容量的k倍。 [0334] Generally, 2k value storage unit (k is an integer of 1 or more) k storage capacity is two times the storage capacity of the memory cell. 当执行写入时,准备确定节点A的电位的2k种写入电位并且产生2k种状态。 When writing is performed, 2k kinds of writing potential ready determination node A and the potential of generating 2k states. 当执行读取时,优选地准备能够用于区分这2k种状态的2k-l种参考电位。 When reading is performed, it can be preferably prepared for 2k-l distinguish types of reference potential states of 2k. 提供一个感测放大器并且通过执行2k-l次比较能够读出数据。 A sense amplifier and by performing 2k-l comparisons data can be read. 另外,通过反馈比较的结果,比较次数能够减少至k次。 Further, by comparing the results of the feedback, the number of comparisons can be reduced to k times. 在驱动源极线SL的读取方法中,通过提供2k-l个感测放大器,能够通过执行一次比较执行读取。 In the driving method of reading the source line SL by providing 2k-l sense amplifiers, a comparison can be performed by performing a read. 另外,能够采用提供多个感测放大器并且多次执行比较的结构。 Further, it is possible to provide a plurality of sense amplifiers employed and the structure of the comparison performed a plurality of times.

[0335] 在根据这个实施例的半导体装置中,因为晶体管202的低截止电流特性,数据能够保留极长时间。 [0335] In the semiconductor device according to this embodiment, since the low off current characteristics of the transistor 202, the data retention can be extremely long. 换句话说,不需要在DRAM等中需要的刷新操作,从而能够抑制功耗。 In other words, no DRAM requires the refresh operation or the like, so that power consumption can be suppressed. 另夕卜,根据这个实施例的半导体装置能够用作基本上非易失性的存储装置。 Another Bu Xi, the semiconductor device according to the embodiment can be used as a substantially non-volatile storage device.

[0336] 另外,通过晶体管202的开关操作执行数据的写入等;因此,不需要高电压并且不存在元件的劣化的问题。 [0336] Further, the write operation by the switching transistor 202 performs data and the like; thus, no high-voltage problems and deterioration of the element does not exist. 另外,通过使晶体管导通或截止来执行数据的写入和擦除;因此, 能够容易地获得高速操作。 Further, the transistor is turned on or off to perform writing and erasing data; thus, it is possible to easily obtain high-speed operation. 通过控制输入到晶体管的电位,能够执行数据的直接重写入。 By controlling the input to the potential of the transistor directly rewritten data can be performed. 因此,不需要擦除操作(擦除操作是在闪速存储器等中需要的操作),从而能够抑制由于擦除操作导致的操作速度的减小。 Thus, no erase operation (erase operation is an operation required in flash memory, etc.), it is possible to suppress a decrease in operation since the erase operation speed caused.

[0337] 另外,使用除氧化物半导体之外的材料形成的晶体管能够工作于足够高的速度, 因此,通过使用该晶体管,能够以高速读出存储内容。 [0337] Further, using a material other than an oxide semiconductor can operate in a transistor formed sufficiently high speed, and therefore, by using the transistor, at a high speed read out the stored content.

[0338] 由于根据这个实施例的半导体装置是多值半导体,所以能够增加每单位面积的存储容量。 [0338] Since the semiconductor device according to this embodiment is a semiconductor multi-valued, it is possible to increase the storage capacity per unit area. 因此,能够实现半导体装置的小型化及其高度集成。 Accordingly, the semiconductor device can be miniaturized and highly integrated. 另外,当执行写入时,将要处于浮动状态的节点的电位能够被直接控制;因此,能够容易地执行多值存储元件中所需的具有高准确性的阈值电压的控制。 Further potential of the node, when writing is performed, to be in a floating state can be controlled directly; therefore, it is possible to easily perform control of the desired multi-value storage element has a threshold voltage higher accuracy. 因此,多值存储元件中要求的写入之后的状态的断言能够省略;因此,在这种情况下,写入所需的时间能够缩短。 Accordingly, the asserted state after writing multi-value memory element requirements can be omitted; thus, in this case, the time required for writing can be shortened.

[0339] [实施例5] [0339] [Example 5]

[0340] 在这个实施例中,参照图30A至30F描述安装根据以上实施例获得的半导体装置的电子设备的例子。 [0340] In this embodiment, with reference to the above described electronic apparatus mounting a semiconductor device according to the embodiment obtained in Examples 30A to 30F embodiment FIG. 根据以上实施例获得的半导体装置即使在没有电源的情况下也能够保留数据。 Even in the absence of power semiconductor device capable of retaining data was obtained according to the above embodiment. 不会引起由于写入和擦除导致的劣化。 Since the writing and erasing does not cause deterioration caused. 因此,其操作速度高。 Thus, its high operating speed. 因此,通过使用该半导体装置,能够提供具有新型结构的电子设备。 Thus, by using the semiconductor device, it is possible to provide an electronic device having a novel structure. 需要注意的是,根据以上实施例的半导体装置集成并安装于电路板等以便安装在电子设备上。 Note that the integration and the like is mounted on a circuit board mounted on the electronic apparatus for a semiconductor device according to the above embodiment.

[0341] 图30A表示膝上型个人计算机,该膝上型个人计算机包括根据以上实施例的半导体装置并包括主体301、壳体302、显示部分303、键盘304等。 [0341] FIG. 30A shows a laptop personal computer, a laptop personal computer which includes a main body 301 and includes a device according to the above embodiment of semiconductor, the housing 302, a display portion 303, a keyboard 304 and the like. 当把根据本发明实施例的半导体装置应用于该膝上型个人计算机时,即使在没有电源的情况下也能够保留数据。 When the semiconductor device according to embodiments of the present invention is applied to a laptop personal computer, even in the absence of power capable of retaining data. 另外, 不会引起由于写入和擦除导致的劣化。 Further, without causing deterioration caused due to the writing and erasing. 另外,其操作速度高。 In addition, its high operating speed. 因此,优选地把根据本发明实施例的半导体装置应用于膝上型个人计算机。 Thus, a semiconductor device of the preferred embodiment of the present invention is applied to a laptop personal computer.

[0342] 图30B表示便携式信息终端(PDA),该PDA包括根据以上实施例的半导体装置并具有包括显示部分313、外部接口315、操作按钮314等的主体311。 [0342] FIG. 30B shows a portable information terminal (PDA), a semiconductor device of this embodiment includes a PDA according to the above embodiment and includes a display portion 313 having an external interface 315, an operation button 314 of the body 311 and the like. 另外,包括触摸笔312作为用于操作的配件。 Further, as the accessory 312 including a touch pen for operation. 当把根据本发明实施例的半导体装置应用于PDA时,即使在没有电源的情况下也能够保留数据。 When the semiconductor device according to an embodiment of the present invention is applied to PDA, even in the absence of power capable of retaining data. 另外,不会引起由于写入和擦除导致的劣化。 Further, without causing deterioration caused due to the writing and erasing. 另外,其操作速度高。 In addition, its high operating speed. 因此,优选地把根据本发明实施例的半导体装置应用于PDA。 Thus, a semiconductor device of the preferred embodiment of the present invention is applied to the PDA.

[0343] 图30C表示电子书阅读器320作为包括根据以上实施例的半导体装置的电子纸的例子。 [0343] FIG. 30C showing an electronic book reader 320 as an example of electronic paper embodiment of a semiconductor device comprising the above embodiment. 电子书阅读器320包括两个壳体,即壳体321和壳体323。 E-book reader 320 includes two housings, a housing 321 and housing 323. 壳体321和壳体323利用铰链337组合,从而电子书阅读器320能够利用铰链337作为轴线打开和闭合。 Housing 321 and the housing 323 in combination with a hinge 337, so that e-book reader 320 using a hinge 337 can be opened and closed as an axis. 根据这种结构,能够像纸书一样使用电子书阅读器320。 According to such a configuration, it is possible to use as a paper book e-book reader 320. 当把根据本发明实施例的半导体装置应用于该电子纸时,即使在没有电源的情况下也能够保留数据。 When the semiconductor device according to an embodiment of the present invention is applied to the electronic paper, even in the absence of power capable of retaining data. 另外,不会引起由于写入和擦除导致的劣化。 Further, without causing deterioration caused due to the writing and erasing. 另外,其操作速度高。 In addition, its high operating speed. 因此,优选地把根据本发明实施例的半导体装置应用于电子纸。 Thus, a semiconductor device of the preferred embodiment of the present invention is applied to an electronic paper.

[0344]显示部分325被包括在壳体321中并且显示部分327被包括在壳体323中。 [0344] The display section 325 is included in housing 321 and the display section 327 is included in the housing 323. 显示部分325和显示部分327可显示一页,或者可显示不同页。 A display portion 325 and the display portion 327 may display one, or may display different pages. 当显示部分325和327显示不同页时,例如,位于右侧的显示部分(在图30C中的显示部分325)能够显示文本,并且位于左侧的显示部分(在图30C中的显示部分327)能够显示图形。 When the display portion 325 and 327 display a different page, for example, on the right display portion (the display portion 325 in FIG. 30C) can display text and a display portion located on the left side (shown in FIG. 30C, 327) It can display graphics.

[0345] 图30C表示壳体321具有操作按钮等的例子。 [0345] FIG. 30C showing an example of a housing 321 having an operation button or the like. 例如,壳体321具有电源按钮331、 操作键333、扬声器335等。 For example, the housing 321 has a power button 331, operation keys 333, a speaker 335 and the like. 利用操作键333能够翻页。 333 pages can be turned with the operation key. 需要注意的是,键盘、定点装置等也可以布置在壳体的表面上,显示部分布置在该壳体上。 Note that a keyboard, a pointing device or the like may be disposed on a surface of the housing, a display portion disposed on the housing. 另外,外部连接端子(耳机端子、 USB端子、能够连接到诸如AC适配器和USB线缆等的各种线缆的端子)、记录介质插入部分等可布置在壳体的背面或侧面上。 Further, (terminal earphone terminal, a USB terminal, such as an AC adapter can be connected to a USB cable or the like and a variety of cables) connected to the external terminals, a recording medium insertion portion or the like or may be disposed on the back surface side of the housing. 另外,电子书阅读器320可具有电子字典的功能。 In addition, e-book reader 320 may have the function of an electronic dictionary.

[0346] 电子书阅读器320可构造为以无线方式发送和接收数据。 [0346] e-book reader 320 may be configured to transmit and receive data wirelessly. 通过无线通信,能够从电子书服务器购买并下载所希望的书数据等。 Through wireless communication, e-books can be purchased from the server and download the desired book data and so on.

[0347] 需要注意的是,电子纸能够应用于能够显示数据的任何领域中的电子设备。 [0347] It should be noted that the electronic paper can be applied to any field data can be displayed in the electronic device. 例如, 除了电子书阅读器之外,电子纸还能够用于车辆(诸如,火车)中的海报、广告,各种卡(诸如,信用卡)中的显示等。 For example, in addition to e-book reader, electronic paper can also be used for vehicles (such as trains) in posters, advertising, all kinds of cards (such as credit cards) in the display.

[0348] 图30D表不包括根据以上实施例的半导体装置的移动电话。 [0348] FIG. 30D table does not include a mobile phone semiconductor device according to the above embodiment. 移动电话包括两个壳体,即壳体340和壳体341。 Mobile phone includes two housings, a housing 340 and housing 341. 壳体341包括:显示面板342、扬声器343、麦克风344、定点装置346、照相机镜头347、外部连接端子348等。 Housing 341 comprising: a display panel 342, a speaker 343, a microphone 344, a pointing device 346, a camera lens 347, an external connection terminal 348 and the like. 壳体341包括用于对移动电话充电的太阳能电池349、外部存储插槽350等。 Housing 341 for charging the mobile phone includes a solar cell 349, an external memory slot 350 and the like. 另外,在壳体341中包括天线。 Further, the housing 341 includes an antenna. 当把根据本发明实施例的半导体装置应用于移动电话时,即使在没有电源的情况下也能够保留数据。 When the semiconductor device according to embodiments of the present invention is applied to a mobile telephone, even in a case without power supply capable of retaining data. 另外,不会引起由于写入和擦除导致的劣化。 Further, without causing deterioration caused due to the writing and erasing. 另外,其操作速度高。 In addition, its high operating speed. 因此,优选地把根据本发明实施例的半导体装置应用于该移动电话。 Thus, a semiconductor device of the preferred embodiment of the present invention is applied to the mobile phone.

[0349]显示面板342具有触摸面板功能。 [0349] The display panel 342 has a touch panel function. 显示为图像的多个操作键345在图30D中由虚线表示。 A plurality of operation keys is displayed as an image 345 represented by a dotted line in FIG. 30D. 需要注意的是,移动电话包括升压电路,该升压电路用于把从太阳能电池349输出的电压升高到每个电路所需的电压。 Note that the mobile phone includes a boosting circuit, the boosting circuit for converting the output voltage from the solar cell 349 is raised to a voltage required in each circuit. 另外,除了以上结构之外,可采用这样的结构:在该结构中,包括非接触式IC芯片、小的记录装置等。 Further, in addition to the above configuration, such a configuration may be employed: In this structure, comprising a non-contact IC chip, a small recording apparatus or the like.

[0350]显示面板342的显示方向根据使用模式而合适地改变。 [0350] direction of the display panel 342 and appropriately changed based on usage patterns. 另外,照相机镜头347布置在与显示面板342相同的表面上,因此它能够用作可视电话。 Further, the camera lens 347 is disposed on the same surface of the display panel 342, so it can be used as a videophone. 扬声器343和麦克风344 能够用于可视电话、记录、重放等,而不局限于语言通信。 A speaker 343 and a microphone 344 can be used for videophone, recording, reproducing and the like, without being limited to speech communication. 此外,在壳体340和341如图30D 中所示展开的状态下的壳体340和341能够滑动,从而一个壳体重叠在另一个壳体上方; 因此,移动电话的尺寸能够减小,这使得移动电话适合携带。 Further, as shown in an expanded housing 340 and the housing 341 in the state shown in FIG 30D 340 and 341 can slide so that one above the other housing overlaps the housing; therefore, the size of the mobile phone can be reduced, which so that the mobile phone suitable for carrying.

[0351] 外部连接端子348能够连接到诸如AC适配器或USB线缆等的各种线缆,这能够实现充电和数据通信。 [0351] The external connection terminals 348 can be connected to various cables such as an AC adapter or USB cable or the like, which enables charging and data communication. 此外,通过把记录介质插入到外部存储插槽350中,移动电话能够进行存储和移动大容量的数据。 Further, by the recording medium inserted into the external memory slot 350, a mobile phone capable of data storage and movement of a large capacity. 另外,除了以上功能之外,可提供红外通信功能、电视接收功能等。 Further, in addition to the above functions, it can provide an infrared communication function, a television reception function.

[0352] 图30E表示包括根据以上实施例的半导体装置的数字照相机。 [0352] FIG. 30E indicates a digital camera comprising a semiconductor device according to the above embodiment. 该数字照相机包括主体361、显示部分(A)367、目镜363、操作开关364、显示部分(B)365、电池366等。 The digital camera includes a main body 361, a display portion (A) 367, an eyepiece 363, an operation switch 364, a display portion (B) 365, the battery 366 and the like. 当把根据本发明实施例的半导体装置应用于该数字照相机时,即使在没有电源的情况下也能够保留数据。 When the semiconductor device according to an embodiment of the present invention is applied to the digital camera, even in the absence of power capable of retaining data. 另外,不会引起由于写入和擦除导致的劣化。 Further, without causing deterioration caused due to the writing and erasing. 另外,其操作速度高。 In addition, its high operating speed. 因此,优选地把根据本发明实施例的半导体装置应用于数字照相机。 Thus, a semiconductor device of the preferred embodiment of the present invention is applied to a digital camera.

[0353] 图30F表示包括根据以上实施例的半导体装置的电视机。 [0353] FIG. 30F showing a television comprising the semiconductor device according to the above embodiment. 在电视机370中,显示部分373被包括在壳体371中。 In the television 370, the display portion 373 is included in the housing 371. 显示部分373能够显示图像。 The display section 373 can display an image. 这里,壳体371由台座375 支撑。 Here, the housing 371 is supported by a stand 375.

[0354] 电视机370能够由壳体371的操作开关或者单独的遥控器380操作。 [0354] 380 TV 370 can operate the operation switch 371 by the housing or a separate remote controller. 频道和音量能够由遥控器380的操作键379控制,从而能够控制显示部分373上显示的图像。 Channels and volume can be controlled by the remote controller 379 an operation key 380, so that the image on the display portion 373 can control the display. 另外,遥控器380可具有用于显示从遥控器380输出的数据的显示部分377。 Further, the remote controller 380 may have a display 380 from the data output from the remote controller display section 377. 当把根据本发明实施例的半导体装置应用于电视机时,即使在没有电源的情况下也能够保留数据。 When the semiconductor device according to embodiments of the present invention is applied to a television, even in the absence of power capable of retaining data. 另外,不会引起由于写入和擦除导致的劣化。 Further, without causing deterioration caused due to the writing and erasing. 另外,其操作速度高。 In addition, its high operating speed. 因此,优选地把根据本发明实施例的半导体装置应用于电视机。 Accordingly, the preferred embodiment of a semiconductor device according to the present invention applied to a television.

[0355] 需要注意的是,电视机370优选地具有接收器、调制解调器等。 [0355] Note that the television set 370 preferably has a receiver, a modem and the like. 利用接收器,能够接收一般电视广播。 Using the receiver, a general television broadcast can be received. 另外,当电视机370经调制解调器通过有线或无线连接连接到通信网络时,能够执行单向(从发射器到接收器)或双向(发射器和接收器之间、接收器之间,等等)数据通信。 Further, when connected to the TV 370 via a communication network by wired or wireless modem connection, can be one-way (from a transmitter to a receiver) or (between the receiver between transmitter and receiver, and the like) two-way data communication.

[0356] 在这个实施例中描述的方法和结构能够合适地与其它实施例中描述的任何方法和结构组合。 [0356] In this embodiment, the methods and structures described herein can suitably be any other combination methods and structures described in the embodiments.

[0357] 本申请基于2009年11月6日提交给日本专利局的序列号为2009-255448的日本专利申请,该专利申请的全部内容通过引用包含于此。 [0357] The present application is based on 6 November 2009 submitted to the serial number of the Japanese Patent Office Japanese Patent Application 2009-255448, the entire disclosure of which is hereby incorporated by reference. 标号解释100 :衬底;102 :保护层;104 :半导体区域;106 :元件隔离绝缘层;108a:栅极绝缘层;IlOa:栅电极;112 :绝缘层;114 :杂质区域;116 :沟道形成区域;118 :侦彳壁绝缘层;120 :高浓度杂质区域;122 :金属层;124 :金属化合物区域;126 :层间绝缘层;128 :层间绝缘层; 130a:源或漏电极;130b:源或漏电极;130c:电极;132 :绝缘层;134 :导电层;136a:电极; 136b:电极;136c:电极;136d:栅电极;138 :栅极绝缘层;140 :氧化物半导体层;142a:源或漏电极;142b:源或漏电极;144 :保护绝缘层;146 :层间绝缘层;148 :导电层;150a:电极;150b:电极;150c:电极;150d:电极;150e:电极;152 :绝缘层;154a:电极;154b:电极;154c:电极;154d:电极;160 :晶体管;162 :晶体管;200 :存储单元;201 :晶体管;202 : 晶体管;203 :晶体管;204 :电容器;205 :电容器;210 :存储单元阵列;211 :读取电路;212 : 信 Reference numeral 100 explained: a substrate; 102: protection layer; 104: semiconductor region; 106: element isolation insulating layer; 108a: gate insulating layer; ILOA: a gate electrode; 112: insulating layer; 114: impurity region; 116: channel forming region; 118: wall insulating layer investigation left foot; 120: high-concentration impurity region; 122: a metal layer; 124: metal compound region; 126: interlayer insulating layer; 128: interlayer insulating layer; 130a: source or drain electrode; 130b: source or drain electrode; 130c: an electrode; 132: insulating layer; 134: conductive layer; 136a: an electrode; 136b: an electrode; 136c: an electrode; 136d: gate electrode; 138: a gate insulating layer; 140: an oxide semiconductor layer; 142a: source or drain electrode; 142b: source or drain electrode; 144: protective insulating layer; 146: interlayer insulating layer; 148: conductive layer; 150a: an electrode; 150b: an electrode; 150c: an electrode; 150 d: an electrode; 150e: an electrode; 152: insulating layer; 154a: an electrode; 154b: an electrode; 154c: an electrode; 154d: an electrode; 160: transistor; 162: transistor; 200: storage unit; 201: transistor; 202: transistor; 203: transistor; 204: a capacitor; 205: a capacitor; 210: a memory cell array; 211: reading circuit; 212: letter 线驱动器电路;213 :驱动器电路;214 :电势产生电路;215 :解码器;216 :晶体管;217 : 晶体管;218 :晶体管;219 :逻辑电路;220 :|旲拟缓冲器;221 :读取电路;222 :读取电路; 223 :偏置电路;224 :偏置电路;225 :参考单元;225a:参考单元;225b:参考单元;225c:参考单元;231 :读取电路;232 :读取电路;233 :驱动器电路;240 :存储单元;301 :主体;302 : 壳体;303 :显示部分;304 :键盘;311 :主体;312 :触摸笔;313 :显示部分;314 :操作按钮; 315 :外部接口;320 :电子书阅读器;321 :壳体;323 :壳体;325 :显示部分;327 :显示部分; 331 :电源按钮;333 :操作键;335 :扬声器;337 :铰链单元;340 :壳体;341 :壳体;342 :显示面板;343 :扬声器;344 :麦克风;345 :操作键;346 :定点装置;347 :照相机镜头;348 : 外部连接端子;349 :太阳能电池;350 :外部存储插槽;361 :主体;363 :目镜;3 Line driver circuit; 213: driver circuit; 214: potential generating circuit; 215: a decoder; 216: transistor; 217: transistor; 218: transistor; 219: a logic circuit; 220: | Dae quasi buffer; 221: reading circuit ; 222: reading circuit; 223: bias circuit; 224: bias circuit; 225: reference cell; 225a: reference cell; 225b: reference cell; 225c: reference cell; 231: reading circuit; 232: reading circuit ; 233: driver circuit; 240: storage unit; 301: body; 302: a housing; 303: display portion; 304: keyboard; 311: body; 312: touch pen; 313: display portion; 314: an operation button; 315: an external interface; 320: e-book reader; 321: housing; 323: housing; 325: display portion; 327: display portion; 331: power button; 333: operation key; 335: speaker; 337: hinge unit; 340 : a housing; 341: housing; 342: display panel; 343: speaker; 344: microphone; 345: operation key; 346: pointing means; 347: camera lens; 348: external connection terminal; 349: solar cell; 350: external storage slots; 361: body; 363: eyepiece; 3 64 :操作开关;365 :显示部分B;366 :电池;367 :显示部分A;370 :电视机;371 :壳体;373 :显示部分; 375 :台座;377 :显示部分;379 :操作键;和380 :遥控器。 64: an operation switch; 365: display portion B; 366: battery; 367: display portion A; 370: TV; 371: housing; 373: display portion; 375: pedestal; 377: display portion; 379: operation key; and 380: the remote control.

Claims (9)

1. 一种用于驱动半导体装置的方法,包括: 第一线; 第二线; 存储单元; 第一电路,电连接到所述第一线;W及第二电路,电连接到所述第二线, 所述方法包括写入步骤和读取步骤,所述写入步骤包括如下步骤: 选择多个写入电位中的一个;W及将所述多个写入电位中的所述一个输出到所述第一线,W及所述读取步骤包括如下步骤: 将所述第二线的电位与多个参考电位进行比较, 其中所述存储单元包括: 第一晶体管,包括第一栅极、第一源极和第一漏极; 第二晶体管,包括第二栅极、第二源极和第二漏极;W及第H晶体管,包括第H栅极、第H源极和第H漏极, 其中所述第二晶体管包括氧化物半导体层, 其中所述第一栅极W及所述第二源极和所述第二漏极中的一个彼此电连接, 其中所述第一漏极和所述第H源极彼此电连接, 其中所述第二线和所述第H漏 1. A method for driving a semiconductor device, comprising: a first line; second line; memory cell; a first circuit electrically connected to the first line; and W is a second circuit electrically connected to the second line , said method comprising the step of reading and writing step, writing step comprises the steps of: selecting a plurality of write potentials; W is and the potential of the plurality of write to one of the output said first line, W, and said reading step comprises the steps of: the potential of the second line is compared with a plurality of reference potential, wherein the storage unit comprises: a first transistor including a first gate, a first a first source electrode and the drain electrode; a second transistor including a second gate, a second source and a second drain electrode; W is H and a second transistor including a first gate electrode H, H of the source and the drain of H, wherein said second transistor includes an oxide semiconductor layer, wherein the first gate and the second W and the second source electrode a drain electrically connected to each other, wherein the first drain and the H said first source electrically connected to each other, wherein said second drain line and the H 极彼此电连接,W及其中所述第一线W及所述第二源极和所述第二漏极中的另一个彼此电连接。 Electrically connected to each other, and the second source electrode to another wire W W and wherein the first and second drain connected to each other electrically.
2. -种用于驱动半导体装置的方法,包括: 第一线; 第二线; 存储单元; 第一电路,电连接到所述第一线;W及第二电路,电连接到所述第二线, 所述方法包括写入步骤和读取步骤,所述写入步骤包括如下步骤: 选择多个写入电位中的一个;W及将所述多个写入电位中的所述一个输出到所述第一线,W及所述读取步骤包括如下步骤: 将所述第二线的电位与多个参考电位进行比较, 其中所述存储单元包括: 第一晶体管,包括第一栅极、第一源极和第一漏极; 第二晶体管,包括第二栅极、第二源极和第二漏极;和电容器, 其中所述第二晶体管包括氧化物半导体层, 其中所述第一栅极W及所述第二源极和所述第二漏极中的一个彼此电连接, 其中所述第一栅极W及所述电容器的一个电极彼此电连接, 其中所述第二线和所述第一漏极彼此电连接,W及其中所 2. - A method for driving a semiconductor device types, comprising: a first line; second line; memory cell; a first circuit electrically connected to the first line; and W is a second circuit electrically connected to the second line , said method comprising the step of reading and writing step, writing step comprises the steps of: selecting a plurality of write potentials; W is and the potential of the plurality of write to one of the output said first line, W, and said reading step comprises the steps of: the potential of the second line is compared with a plurality of reference potential, wherein the storage unit comprises: a first transistor including a first gate, a first a first source electrode and the drain electrode; a second transistor including a second gate, a second source and a second drain electrode; and a capacitor, wherein the second transistor includes an oxide semiconductor layer, wherein the first gate W, and the second source and a drain of said second electrically connected to each other, wherein the first gate electrode of a W and the capacitor electrically connected to each other, wherein said first and said second line a drain electrode electrically connected to each other, W and as 第一线w及所述第二源极和所述第二漏极中的另一个彼此电连接。 And the second source line w other of the first and the second drain electrode are electrically connected to each other.
3. -种用于驱动半导体装置的方法,包括: 第一线; 第二线; 第H线; 多个存储单元,彼此并联电连接在所述第二线和所述第H线之间; 第一电路,电连接到所述第一线;W及第二电路,电连接到所述第二线, 所述方法包括写入步骤和读取步骤,所述写入步骤包括如下步骤: 选择多个写入电位中的一个;W及将所述多个写入电位中的所述一个输出到所述第一线,W及所述读取步骤包括如下步骤: 将所述第二线的电位与多个参考电位进行比较, 其中所述多个存储单元中的一个包括: 第一晶体管,包括第一栅极、第一源极和第一漏极; 第二晶体管,包括第二栅极、第二源极和第二漏极;W及电容器, 其中所述第二晶体管包括氧化物半导体层, 其中所述第一栅极W及所述第二源极和所述第二漏极中的一个彼此电连接, 其中所述第一栅极W及所述电容器的一 3. The - method for driving a semiconductor device, comprising: a first line; second line; of H line; a plurality of memory cells, electrically connected in parallel with each other between the second line and the H line; first circuit electrically connected to the first line; and W is a second circuit electrically connected to the second line, the method comprising the step of reading and writing step, writing step comprises the steps of: selecting a plurality of write the potential of a; and W is the potential of the plurality of writes to said first output line, W, and said reading step comprises the steps of: the potential of the second line and a plurality of comparing the reference potential, wherein said plurality of storage means comprises: a first transistor including a first gate, a first source and a first drain electrode; a second transistor including a second gate, a second source and a second drain; W and a capacitor, wherein the second transistor includes an oxide semiconductor layer, wherein the first gate and the second source W and a drain of said second electrically to each other a connector, wherein the first gate and the capacitor W 电极彼此电连接, 其中所述第二线和所述第一漏极彼此电连接,W及其中所述第一线W及所述第二源极和所述第二漏极中的另一个彼此电连接。 Electrodes electrically connected to each other, wherein said second line and the first drain electrode electrically connected to each other electrically from each other and wherein the first wire W W and the second source electrode and the drain electrode of the second connection.
4. 如权利要求1所述的方法,其中所述半导体装置还包括电容器,所述电容器电连接到所述第一栅极。 4. The method according to claim 1, wherein said semiconductor device further comprising a capacitor electrically connected to the first gate.
5. 如权利要求1-3中任意一项所述的方法,其中所述氧化物半导体层包括In、Ga和Zn。 5. A method as claimed in any one of claims, wherein the oxide semiconductor layer including In, Ga and Zn.
6. 如权利要求1-3中任意一项所述的方法,其中所述氧化物半导体层包括In2Ga2化07 的晶体。 6. A method as claimed in claim 1 to 3 of any one of, wherein the oxide semiconductor layer 07 comprises In2Ga2 of crystals.
7. 如权利要求1-3中任意一项所述的方法,其中所述氧化物半导体层中的氨浓度小于或等于5X 1019原子/cm3。 7. A method as claimed in any one of claims, wherein the ammonia concentration in the oxide semiconductor layer is less than or equal to 5X 1019 atoms / cm3.
8. 如权利要求1-3中任意一项所述的方法,其中所述第二晶体管的截止电流小于或等于1X10-13A。 8. A method as claimed in claim 1 to 3 of any one of, wherein off-state current of the second transistor is less than or equal to 1X10-13A.
9. 如权利要求1-3中任意一项所述的方法,所述半导体装置还包括第H电路, 所述方法进一步包括: 产生所述多个写入电位并将其提供给所述第一电路;W及产生所述多个参考电位并将其提供给所述第二电路。 The method of any one of claims 1 to 3 as claimed in claim 9, said semiconductor device further includes a first circuit H, the method further comprising: generating the plurality of write potential supplied to the first and circuit; and W is generating said plurality of reference potential and to said second circuit.
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