CN104581172A - Hardware structure for realizing SVC macroblock-level algorithm - Google Patents
Hardware structure for realizing SVC macroblock-level algorithm Download PDFInfo
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Abstract
The embodiment of the invention provides a hardware structure for realizing an SVC macroblock-level algorithm, and aims at improving the encoding efficiency. The hardware structure comprises a memory, an arbitration module, a data reading module, a prediction module and a data sending module, wherein the data reading module, the prediction module and the data sending module realize access to the memory through the arbitration module; the memory saves base layer data, and the data reading module, the prediction module and the data sending module access the memory simultaneously or non-simultaneously; the arbitration module is used for judging the reading and writing priority of the data reading module, the prediction module and the data sending module to the memory; the prediction module is used for carrying out luminance sampling interpolation operation and chroma sampling interpolation operation on the data read from the memory by the data reading module to obtain luminance and chroma prediction values; SAD of the prediction values with the luminance information of the current frame is calculated, and finally the prediction values are saved in the memory.
Description
Technical field
The present invention relates to SVAC standard, particularly a kind of hardware configuration realizing SVC macro-block level algorithm in SVAC standard.
Technical background
In existing coding and decoding video, SVC is many to be realized by software algorithm, is seldom realized by hardware, does not make full use of the performance of hardware, makes coding inefficiency.
Summary of the invention
In view of this, the embodiment of the present invention provides a kind of hardware configuration realizing SVC macro-block level algorithm, to improve code efficiency.
In order to achieve the above object, a kind of hardware configuration realizing SVC macro-block level algorithm that the embodiment of the present invention provides, comprising: memory, arbitration modules, read data module, prediction module, transmission data module; Wherein said read data module, prediction module, transmission data module realize the access to storing by described arbitration modules;
Base layer data preserved by described memory, described read data module, prediction module, transmission data module simultaneously or different time reference to storage;
Described arbitration modules is for judging that read data module, prediction module, transmission data module are to the read-write priority of memory;
Described prediction module, carries out luma samples interpolation arithmetic and chroma samples difference operation to the data that read data module reads from memory, obtains brightness and colorimetric prediction value; Calculate the SAD with the monochrome information of present frame; Predicted value is saved in memory the most at last.
This hardware structure implementation is based upon in SVAC standard base, by taking hardware encoding language to realize SVC macro-block level coding on FPGA, effectively can improve code efficiency.
Accompanying drawing explanation
Fig. 1 is a kind of hardware configuration schematic diagram realizing SVC macro-block level algorithm in the embodiment of the present invention.
Fig. 2 shows the priority orders that in one embodiment of the invention, arbitration modules judges.
Fig. 3 shows the structural representation of prediction module in one embodiment of the invention.
Figure 4 shows that the schematic flow sheet of luma prediction and colorimetric prediction serial process in one embodiment of the invention.
Figure 5 shows that the schematic flow sheet of luma prediction and colorimetric prediction parallel processing in one embodiment of the invention.
Embodiment
For making the object, technical solutions and advantages of the present invention clearly, below in conjunction with accompanying drawing, the present invention is described in further detail.
Fig. 1 is a kind of hardware configuration schematic diagram realizing SVC macro-block level algorithm in the embodiment of the present invention.As shown in Figure 1, this hardware configuration comprises: memory, arbitration (Arbitrate) module, read data (Read Data) module, prediction (Prediction) module, transmission data (Send Data) module.
Wherein, base layer data preserved by memory, read data module, prediction module, transmission data module need simultaneously or different time reference to storage to obtain corresponding data, or by the deposit data after process in memory.In an embodiment of the present invention, memory can take SRAM (Static Random Access Memory) to realize.
Arbitration modules is for judging that read data module, prediction module, transmission data module are to the read-write priority of memory.Fig. 2 shows the priority orders that in one embodiment of the invention, arbitration modules judges.As shown in Figure 2, concrete priority is: read data priority, higher than transmission data priority, sends the priority of data priority higher than prediction module.
Read data module, obtains base layer data (Read Data) from Busife module, is saved in memory after judging priority by arbitration modules.
Prediction module, carries out luma samples difference operation (Luma up sample) and chroma samples difference operation (Chroma up sample) to the data that read data module reads from memory, obtains brightness and colorimetric prediction value; Calculate the SAD with the monochrome information of present frame; Predicted value is saved in memory the most at last.
Fig. 3 shows the structural representation of prediction module in one embodiment of the invention.As shown in Figure 3, prediction module comprises:
Luma prediction subelement, carries out luma samples difference operation for the data read from memory read data module, obtains luma prediction value.
Colorimetric prediction subelement, carries out chroma samples difference operation for the data read from memory read data module, obtains colorimetric prediction value.
SAD subelement, for calculating the SAD of the monochrome information of luma prediction value and present frame.In an embodiment of the present invention, by the data of shared predicted value, amount of calculation can be reduced.
In prediction module, due to the connecting between macro block, decrease associated hardware resource by shared related data (comprising adjacent data, results of intermediate calculations).
In an embodiment of the present invention, before luma prediction subelement carries out up-sampling interpolation arithmetic to Primary layer brightness data, the block that can be divided into 4 4*4 carries out, make processing mode identical with colourity, thus minimizing register memory space, the effective hardware resource reduced shared by design.Now, prediction module comprises division submodule further, for brightness data being divided into the block of 4*4.
In an embodiment of the present invention, prediction module is before the data read from memory read data module carry out luma samples difference operation (Luma up sample) and chroma samples difference operation (Chroma up sample), further border extended is carried out to the data that read data module reads from memory, make to become normal data matrix model, and then luma samples difference operation and chroma samples difference operation are carried out to canonical matrix model.In this case, prediction module comprises data processing subelement further, carries out border extended for the data read from memory read data module, makes to become normal data matrix model.In an embodiment of the present invention, the partial data of canonical matrix model directly can be used in the middle of next pending model, reduce the workload again from memory of data.
In one embodiment, predicted value result can also be given Mode Decision Module carry out decision-making by sending data module by prediction module.
In an embodiment of the present invention, when the serial process of brightness in the enough SVC of timeticks, colourity, luma prediction subelement and the serial of colorimetric prediction subelement in prediction module.Figure 4 shows that the schematic flow sheet of luma prediction and colorimetric prediction serial process in one embodiment of the invention.In the diagram, after first up-sampling interpolation arithmetic being carried out to Primary layer brightness data, then up-sampling interpolation arithmetic is carried out to Primary layer chroma data.
In an embodiment of the present invention, when timeticks is nervous or need SVC to accelerate computing, the mode of luma prediction and colorimetric prediction parallel processing can be taked, i.e. luma prediction subelement and the concurrent working of colorimetric prediction subelement in prediction module.Figure 5 shows that the schematic flow sheet of luma prediction and colorimetric prediction parallel processing.In Figure 5, when memory designs for single port, consider that except sequencing, when carrying out up-sampling interpolation arithmetic, brightness and colourity can be carried out simultaneously except needing when reading and store data from memory.Take the mode of luma prediction and colorimetric prediction parallel processing greatly can shorten treatment cycle.
In an embodiment of the present invention, prediction module can support parallel or serial process scheme simultaneously.Now, prediction module comprises a control port further, with according to global design requirement, selects parallel or serial process scheme.
Send data module, the predicted value finally obtained is passed to correlation module (TFE) and carry out mode decision.
In an embodiment of the present invention, described hardware configuration is realized by FPGA (Field-Programmable Gate Array), and memory both can be the built-in memory of FPGA in this case, also can be external memory.
In an embodiment of the present invention, described hardware configuration can also be by Implementation of Embedded System, or is realized by other feasible hardware modes.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment done, equivalent replacement etc., all should be included within protection scope of the present invention.
Claims (9)
1. realize a hardware configuration for SVC macro-block level algorithm, it is characterized in that, comprising: memory, arbitration modules, read data module, prediction module, transmission data module; Wherein said read data module, prediction module, transmission data module realize the access to storing by described arbitration modules;
Base layer data preserved by described memory, described read data module, prediction module, transmission data module simultaneously or different time reference to storage;
Described arbitration modules is for judging that read data module, prediction module, transmission data module are to the read-write priority of memory;
Described prediction module, carries out luma samples interpolation arithmetic and chroma samples difference operation to the data that read data module reads from memory, obtains brightness and colorimetric prediction value; Calculate the SAD with the monochrome information of present frame; Predicted value is saved in memory the most at last.
2. hardware configuration as claimed in claim 1, it is characterized in that, described prediction module comprises:
Luma prediction subelement, carries out luma samples difference operation for the data read from memory read data module, obtains luma prediction value;
Colorimetric prediction subelement, carries out chroma samples difference operation for the data read from memory read data module, obtains colorimetric prediction value;
SAD subelement, for calculating the SAD of the monochrome information of luma prediction value and present frame.
3. hardware configuration as claimed in claim 2, it is characterized in that, described prediction module comprises further:
Divide submodule, for brightness data being divided into the block of 4*4.
4. hardware configuration as claimed in claim 2 or claim 3, it is characterized in that, described prediction module comprises further:
Data processing subelement, carries out border extended for the data read from memory read data module, makes to become normal data matrix model.
5. hardware configuration as claimed in claim 2 or claim 3, is characterized in that, described luma prediction subelement and described colorimetric prediction subelement walk abreast or work in series.
6. as claimed in claim 2 or claim 3 hardware configuration, it is characterized in that, described prediction module comprises a control port further, walks abreast or work in series with described colorimetric prediction subelement to control described luma prediction subelement.
7. the hardware configuration as described in claim 1,2 or 3, is characterized in that, the priority orders that described arbitration modules judges higher than transmission data priority, sends the priority of data priority higher than prediction module as: read data priority.
8. the hardware configuration as described in claim 1,2 or 3, is characterized in that, described in be stored as static random access memories.
9. the hardware configuration as described in claim 1,2 or 3, is characterized in that, described hardware configuration is realized by FPGA.
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Application publication date: 20150429 |