CN104576507A - Three-dimensional packaging method on basis of silicon through hole technology - Google Patents
Three-dimensional packaging method on basis of silicon through hole technology Download PDFInfo
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- CN104576507A CN104576507A CN201310504865.7A CN201310504865A CN104576507A CN 104576507 A CN104576507 A CN 104576507A CN 201310504865 A CN201310504865 A CN 201310504865A CN 104576507 A CN104576507 A CN 104576507A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/7688—Filling of holes, grooves or trenches, e.g. vias, with conductive material by deposition over sacrificial masking layer, e.g. lift-off
Abstract
The invention relates to a three-dimensional packaging method on the basis of a silicon through hole technology. The three-dimensional packaging method comprises the following steps: providing a wafer; forming a through hole on the front side of the wafer; filling the through hole with a sacrificial layer; after filling the through hole with the sacrificial layer, forming a semiconductor device on the front side of the wafer; forming an interlayer dielectric layer covering the front side of the wafer, the sacrificial layer and the semiconductor device; forming an opening for enabling the sacrificial layer to be exposed out in the interlayer dielectric layer; removing the sacrificial layer which is positioned below the opening and in the through hole; filling the through hole and the opening with metal to form a conductive plug. According to the technical scheme adopted by the invention, not only is electrical conductivity of the conductive plug improved, but also a manufacturing process of the semiconductor device is prevented from being polluted by the metal in the conductive plug, and further, the electrical performance of a packaging structure is improved.
Description
Technical field
The present invention relates to field of semiconductor package, particularly relate to a kind of three-dimension packaging method based on silicon through hole technology.
Background technology
Silicon through hole (Through Silicon Via, be called for short TSV) technology is a kind of realization between chip and chip, between wafer and wafer or the interconnection technique of line conduction between wafer and chip.Encapsulate bonding and use the superimposing technique of salient point different from IC in the past, silicon through hole technology can make that chip is maximum in the density that three-dimensional is stacking, overall dimension is minimum.
The order in whole three-dimension packaging flow process is produced on according to silicon through hole, three-dimension packaging method based on silicon through hole technology is divided into three kinds, is respectively the three-dimension packaging method of the three-dimension packaging method of first through hole technology (via first), the three-dimension packaging method of middle through hole technology (via middle), rear through hole technology (via last).Wherein, the three-dimension packaging method of existing first through hole technology comprises: in wafer, form through hole, and filled conductive material in through hole, to form conductive plunger; After forming conductive plunger, wafer is formed semiconductor device and metal interconnect structure, and described metal interconnect structure is electrically connected with conductive plunger.
Require without metallic pollution when wafer makes semiconductor device, in order to the making preventing the electric conducting material of filling in described through hole from can affect Subsequent semiconductor device, the electric conducting material of filling in described through hole is polysilicon, instead of metal.But, because the electric conductivity of polysilicon is not good, the electric property of encapsulating structure thus can be affected.
Summary of the invention
The problem to be solved in the present invention is: in the three-dimension packaging method of existing first through hole technology, and the electric conducting material electric conductivity of filling in the through hole of wafer is not good, have impact on the electric property of encapsulating structure.
For solving the problem, the invention provides a kind of three-dimension packaging method based on silicon through hole technology, comprising:
Wafer is provided;
Through hole is formed in described wafer frontside;
Sacrifice layer is filled in described through hole;
Fill sacrifice layer in described through hole after, form semiconductor device in described wafer frontside;
Form the interlayer dielectric layer covered on described wafer frontside, sacrifice layer and semiconductor device;
The opening exposing described sacrifice layer is formed in described interlayer dielectric layer;
Remove below described opening, be positioned at the sacrifice layer of described through hole;
Full metal is filled, to form conductive plunger in described through hole and opening.
Optionally, described metal is copper.
Optionally, the material of described sacrifice layer is amorphous carbon.
Optionally, before described wafer frontside forms semiconductor device, also comprise: form the etching barrier layer covering described sacrifice layer.
Optionally, the material of described etching barrier layer is silica.
Optionally, fill sacrifice layer in described through hole before, also comprise: on the bottom and sidewall of described through hole, form insulating barrier.
Optionally, the material of described insulating barrier is silica, formation method is thermal oxidation process.
Present invention also offers the another kind of three-dimension packaging method based on silicon through hole technology, comprising:
Wafer is provided;
Through hole is formed in described wafer frontside;
Sacrifice layer is filled in described through hole;
After filling described sacrifice layer, form semiconductor device in described wafer frontside;
Form the interlayer dielectric layer covered on described wafer frontside, sacrifice layer and semiconductor device;
After forming described interlayer dielectric layer, from wafer described in thinning back side of silicon wafer, until expose described sacrifice layer;
Remove the sacrifice layer being positioned at described through hole;
Metal is filled, to form conductive plunger in described through hole.
Optionally, described metal is copper.
Optionally, the material of described sacrifice layer is amorphous carbon.
Optionally, before described wafer frontside forms semiconductor device, also comprise: form the etching barrier layer covering described sacrifice layer.
Optionally, the material of described etching barrier layer is silica.
Optionally, fill sacrifice layer in described through hole before, also comprise: on the bottom and sidewall of described through hole, form insulating barrier.
Optionally, the material of described insulating barrier is silica, formation method is thermal oxidation process.
Compared with prior art, technical scheme of the present invention has the following advantages:
The technical program is after wafer frontside forms through hole, first in through hole, fill sacrifice layer, then semiconductor device is formed in wafer frontside, after forming semiconductor device, the sacrifice layer be filled in through hole is replaced with metal to form conductive plunger, both improve the electric conductivity of conductive plunger, the manufacture craft that turn avoid the metal pair semiconductor device in conductive plunger pollutes, and then improves the electric property of encapsulating structure.
Further, fill sacrifice layer in through hole before, thermal oxidation process is utilized to form in the bottom of through hole and sidewall the insulating barrier that the measured material of matter is silica.
Accompanying drawing explanation
Fig. 1 to Fig. 7 be in the first embodiment of the present invention encapsulating structure in the cross-sectional view of each production phase;
Fig. 8 to Figure 12 be in the second embodiment of the present invention encapsulating structure in the cross-sectional view of each production phase.
Embodiment
As previously mentioned, in the three-dimension packaging method of existing first through hole technology, the electric conducting material electric conductivity of filling in the through hole of wafer is not good, have impact on the electric property of encapsulating structure.
Compared to polysilicon, the electric conductivity of metal is better.But if fill metal first direct in the through hole of wafer, this metal is easy to pollute the manufacturing process of Subsequent semiconductor device, and then have impact on the electric property of encapsulating structure.
In order to solve this problem, the invention provides a kind of three-dimension packaging method based on silicon through hole technology of improvement, the method is after wafer frontside forms through hole, first in through hole, fill sacrifice layer, then semiconductor device is formed in wafer frontside, after forming semiconductor device, the sacrifice layer be filled in through hole is replaced with metal to form conductive plunger, both improve the electric conductivity of conductive plunger, the manufacturing process that turn avoid the metal pair semiconductor device in conductive plunger pollutes, and then improves the electric property of encapsulating structure.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
First embodiment
As shown in Figure 1, wafer 100 is provided.Wafer 100 is bare silicon wafer, has front S1 and back side S2, and the front S1 of wafer 100 is for the formation of semiconductor device.
In the present embodiment, wafer 100 is Silicon Wafer.
Continue with reference to shown in Fig. 1, form through hole 101 at wafer frontside S1, the degree of depth of through hole 101 is less than the thickness of wafer 100.
In the present embodiment, the formation method of through hole 101 comprises: above wafer frontside S1, form graphical photoresist layer (not shown), the position of this graphical photoresist layer definition through hole 101; With this graphical photoresist layer for mask etches, to form through hole 101 in wafer 100; Then, this graphical photoresist layer is removed.
In a particular embodiment, described lithographic method can be dark reactive ion etching (Deep ReactiveIon Etching is called for short DRIE).In other embodiments, the method for Laser drill also can be utilized in wafer 100 to form through hole 101.
Continue, with reference to shown in Fig. 1, insulating barrier 110 to be formed on the bottom and sidewall of through hole 101.
In the present embodiment, the material of insulating barrier 110 is silica, and the formation method of insulating barrier 110 is thermal oxidation process.In other embodiments, chemical gaseous phase depositing process also can be utilized to form insulating barrier 110.Compared to the insulating barrier 110 that additive method is formed, insulating barrier 110 better quality that thermal oxidation process is formed.
As shown in Figure 2, in through hole 101, sacrifice layer 120 is filled.
In the present embodiment, the material of sacrifice layer 120 is amorphous carbon (amorphous carbon).The method of filling sacrifice layer 120 in through hole 101 comprises: formed and cover wafer frontside S1 and the sacrificial material layer of filling full through hole 101; Carry out back carving to this sacrificial material layer, to remove the sacrificial material layer covered on wafer frontside S1, and make the sub-fraction of through hole 101 not be sacrificed layer 120 to fill up.
In the present embodiment, the formation method of amorphous carbon layer is plasma activated chemical vapour deposition (PECVD).
Continue, with reference to shown in Fig. 2, to form the etching barrier layer 130 covered on sacrifice layer 120.
In the present embodiment, the material of etching barrier layer 130 is silica.The formation method of etching barrier layer 130 comprises: form the protects material layer covered on wafer frontside S1 and sacrifice layer 120, the formation method of this protects material layer is plasma activated chemical vapour deposition (PECVD); Carry out cmp to this protects material layer, until remove the protects material layer covered on wafer frontside S1, remaining protects material layer forms the etching barrier layer 130 being positioned at groove.
In other embodiments, etching barrier layer 130 can not be filled in groove yet, as long as make etching barrier layer 130 cover above sacrifice layer 120.
As shown in Figure 3, semiconductor device 140 is formed at wafer frontside S1.
Semiconductor device 140 is included in all devices for being formed in semiconductor front end technique (FEOL).In the present embodiment, semiconductor device 140 is MOSFET.In other embodiments, described semiconductor device can also comprise the element of other types, as resistance, electric capacity, inductance, MEMS etc.
In semiconductor device 140 manufacturing process, etching barrier layer 130 can prevent sacrifice layer 120 to be etched.
Continue, with reference to shown in Fig. 3, to form the interlayer dielectric layer 150 covered on wafer frontside S1, etching barrier layer 130 and semiconductor device 140.
Interlayer dielectric layer 150 can be formed by stacking by one deck dielectric layer or multilayer dielectricity layer.In the present embodiment, the material of interlayer dielectric layer 150 is silica.
Continue, with reference to shown in Fig. 3, in interlayer dielectric layer 150, to form the conductive plunger 160 be electrically connected with semiconductor device 140.
As shown in Figure 4, in interlayer dielectric layer 150, form the opening 151 exposing sacrifice layer 120.
In the present embodiment, the formation method of opening 151 comprises: on interlayer dielectric layer 150, form graphical photoresist layer, the position of this graphical photoresist layer definition opening 151; With this graphical photoresist layer for mask etches, to remove interlayer dielectric layer 150 above sacrifice layer 120 and etching barrier layer 130(as shown in Figure 3); Then, this graphical photoresist layer is removed.
Continue, with reference to shown in Fig. 4, to remove the sacrifice layer 120 in through hole 101.
In the present embodiment, ashing (ashing) method is utilized to remove sacrifice layer 120.The gas that described ashing method adopts comprises oxygen.
The material of sacrifice layer 120 is agraphitic carbon, the chemical property of amorphous carbon is highly stable, can not react with other layers of wafer 100, is also easy to remove totally, therefore, in the making processing procedure of encapsulating structure, introduce sacrifice layer 120 to impact the electric property of encapsulating structure.
As shown in Figure 5, in through hole 101 and opening 151, fill metal, to form conductive plunger 170.
In the present embodiment, the formation method of conductive plunger 170 comprises: formed and cover interlayer dielectric layer 150 and the metal material layer of filling vias 101 and opening 151, the formation method of this metal material layer can be physical vapour deposition (PVD) or plating; Carry out cmp to this metal material layer, to remove the metal material layer covered on interlayer dielectric layer 150, the remaining metal material layer being filled in through hole 101 and opening 151 forms conductive plunger 170.
In the three-dimension packaging method of existing first through hole technology, the electric conducting material be filled in through hole is polysilicon, and in the technical program, the electric conducting material be filled in through hole is metal, electric conductivity due to metal is better than the electric conductivity of polysilicon, therefore, the electric property of the encapsulating structure utilizing the technical program to be formed improves.In addition, fill metal in through hole before, because the semiconductor device on wafer completes, thus avoiding metal can pollute the manufacture craft of semiconductor device.
In the present embodiment, the metal be filled in through hole 101 and opening 151 is copper.Electric conductivity and the hot property of copper are all better than polysilicon, are conducive to the electric property improving encapsulating structure.In this case, before fill described metal material layer in through hole 101 and opening 151, also comprise: form the diffusion impervious layer (not shown), the metal seed layer (not shown) be positioned on this diffusion impervious layer that cover on interlayer dielectric layer 150, the bottom of through hole 101 and sidewall, opening 151 sidewall.
As shown in Figure 6, interlayer dielectric layer 150 forms metal interconnect structure 180.Metal interconnect structure 180 comprises interconnection line and the conductive plunger (mark) of electrical connection.Metal interconnect structure 180 can be layer of metal interconnection structure or multilevel metal interconnection structure.Metal interconnect structure 180 is electrically connected with conductive plunger 170.
As shown in Figure 7 (in figure, dotted portion represents removed part in wafer thinning process), from wafer rear S2 thinned wafer 100, until wafer 100 reaches predetermined thickness.
When thinned wafer 100, first at wafer frontside adhesive silicon wafer carrier (carrier wafer), then wafer rear S2 is ground, after wafer 100 is thinned to predetermined thickness, this wafer carrier and wafer separate are opened.
Second embodiment
Difference between second embodiment and the first embodiment is: in a second embodiment,
Shown in composition graphs 3 and Fig. 8, after filling sacrifice layer 120 and form etching barrier layer 130 in through hole 101, form semiconductor device 140 at wafer frontside S1; Then, the interlayer dielectric layer 150 covering wafer frontside S1, semiconductor device 140 and etching barrier layer 130 is formed; Then, in interlayer dielectric layer 150, form the conductive plunger 160 be electrically connected with semiconductor device 140; Then, interlayer dielectric layer 150 forms metal interconnect structure 180;
As shown in Figure 9 (in figure, dotted portion represents removed part in wafer thinning process), from wafer rear S2 thinned wafer 100, until expose sacrifice layer 120, when thinned wafer 100, first at wafer frontside adhesive silicon wafer carrier (carrier wafer), then wafer rear S2 is ground, until wafer 100 is thinned to predetermined thickness;
As shown in Figure 10, the sacrifice layer 120 in removal through hole 101 and etching barrier layer 130(are as shown in Figure 9);
As shown in figure 11, remove the interlayer dielectric layer 150 below through hole 101, to form opening 151 in interlayer dielectric layer 150;
As shown in figure 12, in opening 151 and through hole 101, fill metal, to form conductive plunger 170, conductive plunger 170 is electrically connected with metal interconnect structure 180, after forming conductive plunger 170, wafer carrier and wafer 100 is separated.
In the present invention, each embodiment adopts laddering literary style, and emphasis describes the difference with previous embodiment, and the same section in each embodiment can with reference to previous embodiment.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (14)
1. based on a three-dimension packaging method for silicon through hole technology, it is characterized in that, comprising:
Wafer is provided;
Through hole is formed in described wafer frontside;
Sacrifice layer is filled in described through hole;
Fill sacrifice layer in described through hole after, form semiconductor device in described wafer frontside;
Form the interlayer dielectric layer covered on described wafer frontside, sacrifice layer and semiconductor device;
The opening exposing described sacrifice layer is formed in described interlayer dielectric layer;
Remove below described opening, be positioned at the sacrifice layer of described through hole;
Full metal is filled, to form conductive plunger in described through hole and opening.
2. three-dimension packaging method according to claim 1, is characterized in that, described metal is copper.
3. three-dimension packaging method according to claim 1, is characterized in that, the material of described sacrifice layer is amorphous carbon.
4. three-dimension packaging method according to claim 1, is characterized in that, before described wafer frontside forms semiconductor device, also comprises: form the etching barrier layer covering described sacrifice layer.
5. three-dimension packaging method according to claim 4, is characterized in that, the material of described etching barrier layer is silica.
6. three-dimension packaging method according to claim 1, is characterized in that, before filling sacrifice layer, also comprises: on the bottom and sidewall of described through hole, form insulating barrier in described through hole.
7. three-dimension packaging method according to claim 6, is characterized in that, the material of described insulating barrier is silica, formation method is thermal oxidation process.
8. based on a three-dimension packaging method for silicon through hole technology, it is characterized in that, comprising:
Wafer is provided;
Through hole is formed in described wafer frontside;
Sacrifice layer is filled in described through hole;
After filling described sacrifice layer, form semiconductor device in described wafer frontside;
Form the interlayer dielectric layer covered on described wafer frontside, sacrifice layer and semiconductor device;
After forming described interlayer dielectric layer, from wafer described in thinning back side of silicon wafer, until expose described sacrifice layer;
Remove the sacrifice layer being positioned at described through hole;
Metal is filled, to form conductive plunger in described through hole.
9. three-dimension packaging method according to claim 8, is characterized in that, described metal is copper.
10. three-dimension packaging method according to claim 8, is characterized in that, the material of described sacrifice layer is amorphous carbon.
11. three-dimension packaging methods according to claim 8, is characterized in that, before described wafer frontside forms semiconductor device, also comprise: form the etching barrier layer covering described sacrifice layer.
12. three-dimension packaging methods according to claim 11, is characterized in that, the material of described etching barrier layer is silica.
13. three-dimension packaging methods according to claim 8, is characterized in that, before filling sacrifice layer, also comprise: on the bottom and sidewall of described through hole, form insulating barrier in described through hole.
14. three-dimension packaging methods according to claim 13, is characterized in that, the material of described insulating barrier is silica, formation method is thermal oxidation process.
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| CN201310504865.7A CN104576507B (en) | 2013-10-23 | 2013-10-23 | Three-dimension packaging method based on silicon hole technology |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2023272785A1 (en) * | 2021-07-01 | 2023-01-05 | 长鑫存储技术有限公司 | Semiconductor device and manufacturing method therefor |
| US11955383B2 (en) | 2021-07-01 | 2024-04-09 | Changxin Memory Technologies, Inc. | Semiconductor device and manufacturing method thereof |
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| CN102832161A (en) * | 2011-06-13 | 2012-12-19 | 中芯国际集成电路制造(上海)有限公司 | Method for forming through-silicon-via |
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| US20120315753A1 (en) * | 2011-06-07 | 2012-12-13 | International Business Machines Corporation | Method of forming a through-silicon via utilizing a metal contact pad in a back-end-of-line wiring level to fill the through-silicon via |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2023272785A1 (en) * | 2021-07-01 | 2023-01-05 | 长鑫存储技术有限公司 | Semiconductor device and manufacturing method therefor |
| US11955383B2 (en) | 2021-07-01 | 2024-04-09 | Changxin Memory Technologies, Inc. | Semiconductor device and manufacturing method thereof |
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