CN104572529A - Efficient bus arbitration system applicable to heterogeneous multi-core DSP - Google Patents

Efficient bus arbitration system applicable to heterogeneous multi-core DSP Download PDF

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Publication number
CN104572529A
CN104572529A CN201510065701.8A CN201510065701A CN104572529A CN 104572529 A CN104572529 A CN 104572529A CN 201510065701 A CN201510065701 A CN 201510065701A CN 104572529 A CN104572529 A CN 104572529A
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China
Prior art keywords
designated lane
request
token ring
bus
srio
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CN201510065701.8A
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张永照
童元满
李仁刚
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浪潮电子信息产业股份有限公司
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Priority to CN201510065701.8A priority Critical patent/CN104572529A/en
Publication of CN104572529A publication Critical patent/CN104572529A/en

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    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/32Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer
    • G06F13/34Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer with priority control
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163Interprocessor communication
    • G06F15/167Interprocessor communication using a common memory, e.g. mailbox
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163Interprocessor communication
    • G06F15/17Interprocessor communication using an input/output type connection, e.g. channel, I/O port

Abstract

The invention relates to an efficient bus arbitration system applicable to a heterogeneous multi-core DSP. According to the efficient bus arbitration system applicable to the heterogeneous multi-core DSP, different bus arbitration strategies are designed respectively according to reading-writing functions of different equipment, and a special bus is distributed for the equipment; reading-writing separation operation is adopted so that the parallelism of reading-writing operation is realized; and an efficient bus arbitration mechanism is established so that data high-speed and block-free transmission of EDMA is realized.

Description

A kind of efficient bus arbitration system being suitable for heterogeneous polynuclear DSP

Technical field

The present invention relates to heterogeneous polynuclear technical field, particularly a kind of efficient bus arbitration system being suitable for heterogeneous polynuclear DSP.

Background technology

Based in the heterogeneous polynuclear dsp system of 4 multinuclear digital signal processor DSP cores and 1 instruction set computer RISC core, there are 4 DSP internal memory (Cache/RAM) DSP0 ~ DSP3, shared storage SSRAM, Double Data Rate synchronous DRAM DDR(DDR3 controller), serial Rapid IO SRIO, external memory interface EMIF16, universal input/output GPIO, Inter-Integrated Circuit I2C, multichannel buffer serial port McBSP, multiple channel audio access interface McASP, other external components multiple such as graphic-image matching SAD and the peripheral hardware control register that can store mapping.Wherein, DSP internal memory DSP0 ~ DSP3, shared storage SSRAM, DDR3 controller are fast equipment, support 128bit operation; All the other are slow devices, support 32bit operation.

In the heterogeneous polynuclear dsp system containing central processing unit (CPU), there is the data transmission in peripherals, sheet between storage, DSP core and between DSP core and RISC core, the read-write requests of these equipment room data transmission produces by corresponding data channel.Data mutual is mainly realized by each data channel.The data channel of multi-nuclear DSP system comprises SMC and forwards CPU request msg passage, the extendible processor architecture of ET/SPARC() designated lane, SRIO check from machine write operation designated lane, SRIO answer two EDMA general channels (EDMA general channels 1 and EDMA general channels 2) from machine-readable operation designated lane, each DSP.

The invention provides a kind of efficient bus arbitration system being suitable for multi-core DSP, under the management of EDMA, can provide between the interior storage of all peripherals, sheet, DSP core and between DSP core and RISC core, carry out choke free high-speed data exchange.

Summary of the invention

The present invention, in order to make up the defect of prior art, provides a kind of efficient bus arbitration system being suitable for heterogeneous polynuclear DSP efficiently, flexibly.

The present invention is achieved through the following technical solutions:

A kind of efficient bus arbitration system being suitable for heterogeneous polynuclear DSP, it is characterized in that: comprise the SSRAM private bus for shared storage SSRAM distributes, for the DDR3 private bus that DDR3 controller distributes, for the peripheral hardware control register configuration bus that the peripheral hardware control register of each DSP core distributes, for external memory interface EMIF16, multichannel buffer serial port McBSP, multiple channel audio access interface McASP, universal input/output GPIO, the slow devices bus of Inter-Integrated Circuit I2C and the configuration of other external components and be DSP0/DSP1/DSP2/DSP3 L2 private bus corresponding to DSP0/DSP1/DSP2/DSP3 Memory Allocation, totally 8 buses, wherein slow devices bus and peripheral hardware control register configuration bus support that 32bit operates bit wide, and all the other buses support that 128bit operates bit wide, described SSRAM private bus, DDR3 private bus, the resolving strategy that slow devices bus and L2 private bus adopt identical fixed priority and token ring to take turns phase inversion to be combined, and peripheral hardware control register configuration bus adopts simple arbitrate mechanism, namely token ring wheel turns arbitration.

Described L2 private bus has 6 one-level request sources and 17 sub-request sources of secondary, and wherein the priority of one-level request source forwards CPU request msg passage, ET/SPARC designated lane, SRIO from machine designated lane, SRIO host-specific passage, EDMA general channels 1 and EDMA general channels 2 from the high extremely low SMC that is followed successively by;

Wherein, SMC forwards CPU request msg passage and can forward the access that DSP0/DSP1/DSP2/DSP3 tetra-DSP check storage space; SRIO has two from machine designated lane, is respectively SRIO0 from machine designated lane and SRIO1 from machine designated lane; SRIO host-specific passage has two, is respectively SRIO0 host-specific passage and SRIO1 host-specific passage; EDMA general channels 1 has four, comprises DSP0/DSP1/DSP2/DSP3 EDMA general channels 1; EDMA general channels 2 has four, comprises DSP0/DSP1/DSP2/DSP3 EDMA general channels 2.

The request source of described peripheral hardware control register configuration bus is EDMA general channels 1 and the EDMA general channels 2 of corresponding DSP core, ET/SPARC designated lane and EDMA general channels 1 and EDMA general channels 2 both can send read request and also can send write request, when read-write requests is concurrent, preferential with write request; Described SRIO host-specific passage is divided into SRIO main frame to send designated lane and SRIO main frame receives designated lane, SRIO main frame sends the request that designated lane can only send read register, SRIO main frame receives designated lane can only send the request writing register, and described SRIO is the same with SRIO host-specific passage with service condition from the division of machine designated lane.

On described L2 private bus, SMC forwards the arbitration that CPU request msg passage, EDMA general channels 1 and EDMA general channels 2 all relate to four DSP cores, adopts identical token ring wheel to turn strategy; The token ring priority being encoded to 4 ' b0001 is followed successively by DSP0, DSP1, DSP2, DSP3 from high to low, the token ring priority being encoded to 4 ' b0010 is followed successively by DSP1, DSP2, DSP3, DSP0 from high to low, the token ring priority being encoded to 4 ' b0100 is followed successively by DSP2, DSP3, DSP0, DSP1 from high to low, and the token ring priority being encoded to 4 ' b1000 is followed successively by DSP3, DSP0, DSP1, DSP2 from high to low; When corresponding four cores all have request to arrive, token ring 4 ' b0001,4 ' b0010,4 ' b0100,4 ' b1000 circulate successively to take turns from top to bottom in order and turn;

On described L2 private bus, from machine, to send token ring priority that designated lane is encoded to 2 ' b10 be SRIO0 to SRIO sends designated lane from machine and be better than SRIO1 and send designated lane from machine, and to be SRIO1 send designated lane from machine to the token ring priority being encoded to 2 ' b01 is better than SRIO0 and sends designated lane from machine; The token ring priority that SRIO main frame transmission designated lane is encoded to 2 ' b10 is that SRIO0 main frame transmission designated lane is better than SRIO1 main frame transmission designated lane, and the token ring priority being encoded to 2 ' b01 is that SRIO1 main frame transmission designated lane is better than SRIO0 main frame transmission designated lane; Token ring 2 ' b10,2 ' b10 circulate successively to take turns from top to bottom in order and turn.

The passage that described peripheral hardware control register configuration bus token ring rotational order is corresponding is followed successively by ET/SPARC designated lane from top to bottom, SRIO0 sends designated lane from machine, SRIO0 receives designated lane from machine, SRIO1 sends designated lane from machine, SRIO1 receives designated lane from machine, SRIO0 main frame sends designated lane, SRIO0 main frame receives designated lane, SRIO1 main frame sends designated lane, SRIO1 main frame receives designated lane, the EDMA general channels 1 of corresponding DSP core and EDMA general channels 2, and in order successively circulation wheel turn.

Under each token ring coding, normally can only receive the request of limit priority, if do not have highest priority request to arrive, the redirect carrying out token ring that the request medium priority that token ring arrives according to residue is the highest, will directly jump to the token ring that this request is highest priority request; It is son request all full 16 requests of complete or continuous transmission that described token ring wheel turns the condition switched.

The invention has the beneficial effects as follows: this is suitable for the efficient bus arbitration system of heterogeneous polynuclear DSP, according to the functional characteristics of distinct device read-write, devise different bus arbitration policy respectively, for equipment distributes special bus, and adopt read and write abruption to operate to realize the parallel of read-write operation, establish efficient bus arbitration mechanism, ensure that EDMA realizes data high-speed without blocking transmission.

Accompanying drawing explanation

Accompanying drawing 1 is invention bus arbitration system schematic diagram.

Accompanying drawing 2 is taken turns for invention L2 private bus arbitration-SMC-token ring order and is turned schematic diagram.

Accompanying drawing 3 is arbitrated unordered wheel of-SMC-token ring for invention L2 private bus and is turned schematic diagram.

Accompanying drawing 4 is arbitrated-SRIO for invention L2 private bus and is turned tactful schematic diagram from the preferential step cone of machine designated lane.

Accompanying drawing 5 is arbitrated-SRIO host-specific Path First step cone for invention L2 private bus and is turned tactful schematic diagram.

Accompanying drawing 6 is token ring wheel turn tactful schematic diagram in invention Pbus.

Embodiment

Below in conjunction with accompanying drawing, the present invention will be described in detail.

As shown in Figure 1, this is suitable for the efficient bus arbitration system of heterogeneous polynuclear DSP, comprise the SSRAM private bus for shared storage SSRAM distributes, for the DDR3 private bus that DDR3 controller distributes, for the peripheral hardware control register configuration bus that the peripheral hardware control register of each DSP core distributes, for external memory interface EMIF16, multichannel buffer serial port McBSP, multiple channel audio access interface McASP, universal input/output GPIO, the slow devices bus of Inter-Integrated Circuit I2C and the configuration of other external components and be DSP0/DSP1/DSP2/DSP3 L2 private bus corresponding to DSP0/DSP1/DSP2/DSP3 Memory Allocation, totally 8 buses, wherein slow devices bus and peripheral hardware control register configuration bus support that 32bit operates bit wide, and all the other buses support that 128bit operates bit wide, described SSRAM private bus, DDR3 private bus, the resolving strategy that slow devices bus and L2 private bus adopt identical fixed priority and token ring to take turns phase inversion to be combined, and peripheral hardware control register configuration bus, i.e. Pbus bus, adopts simple arbitrate mechanism, and namely token ring wheel turns arbitration.

As shown in table 1, described L2 private bus has 6 one-level request sources and 17 sub-request sources of secondary, and wherein the priority of one-level request source forwards CPU request msg passage, ET/SPARC designated lane, SRIO from machine designated lane, SRIO host-specific passage, EDMA general channels 1 and EDMA general channels 2 from the high extremely low SMC that is followed successively by;

Wherein, SMC forwards CPU request msg passage and can forward the access that DSP0/DSP1/DSP2/DSP3 tetra-DSP check storage space; SRIO has two from machine designated lane, is respectively SRIO0 from machine designated lane and SRIO1 from machine designated lane; SRIO host-specific passage has two, is respectively SRIO0 host-specific passage and SRIO1 host-specific passage; EDMA general channels 1 has four, comprises DSP0/DSP1/DSP2/DSP3 EDMA general channels 1; EDMA general channels 2 has four, comprises DSP0/DSP1/DSP2/DSP3 EDMA general channels 2.

In addition, cause low priority request to die of hunger the appearance of situation for avoiding occurring high priority requests source to continue for a long time to have request to arrive, in table 1, also define the every one-level of the fixed priority retainable time.

Table 1 L2 private bus arbitration-channel priorities

The request source of described peripheral hardware control register configuration bus is EDMA general channels 1 and the EDMA general channels 2 of corresponding DSP core, ET/SPARC designated lane and EDMA general channels 1 and EDMA general channels 2 both can send read request and also can send write request, when read-write requests is concurrent, preferential with write request; Described SRIO host-specific passage is divided into SRIO main frame to send designated lane and SRIO main frame receives designated lane, SRIO main frame sends the request that designated lane can only send read register, SRIO main frame receives designated lane can only send the request writing register, and described SRIO is the same with SRIO host-specific passage with service condition from the division of machine designated lane.

On described L2 private bus, SMC forwards the arbitration that CPU request msg passage, EDMA general channels 1 and EDMA general channels 2 all relate to four DSP cores, adopts identical token ring wheel to turn strategy.As shown in table 2, the token ring priority being encoded to 4 ' b0001 is followed successively by DSP0, DSP1, DSP2, DSP3 from high to low, the token ring priority being encoded to 4 ' b0010 is followed successively by DSP1, DSP2, DSP3, DSP0 from high to low, the token ring priority being encoded to 4 ' b0100 is followed successively by DSP2, DSP3, DSP0, DSP1 from high to low, and the token ring priority being encoded to 4 ' b1000 is followed successively by DSP3, DSP0, DSP1, DSP2 from high to low; When corresponding four cores all have request to arrive, token ring 4 ' b0001,4 ' b0010,4 ' b0100,4 ' b1000 circulate successively to take turns from top to bottom in order and turn.Table 3 is L2 private bus arbitration-bus request source code.

Table 2 L2 private bus arbitration-token ring wheel turns priority

Table 3 L2 private bus arbitration-bus request source code

As shown in Figure 4, on described L2 private bus, from machine, to send token ring priority that designated lane is encoded to 2 ' b10 be SRIO0 to SRIO sends designated lane from machine and be better than SRIO1 and send designated lane from machine, and to be SRIO1 send designated lane from machine to the token ring priority being encoded to 2 ' b01 is better than SRIO0 and sends designated lane from machine.As shown in Figure 5, the token ring priority that SRIO main frame transmission designated lane is encoded to 2 ' b10 is that SRIO0 main frame transmission designated lane is better than SRIO1 main frame transmission designated lane, and the token ring priority being encoded to 2 ' b01 is that SRIO1 main frame transmission designated lane is better than SRIO0 main frame transmission designated lane.Described token ring 2 ' b10,2 ' b10 circulate successively to take turns from top to bottom all in order and turn.

Described peripheral hardware control register configuration bus request source coding and corresponding token ring coding are with the request that can send in table 4, and token ring wheel turns strategy and sees Fig. 6.The passage that token ring rotational order is corresponding is followed successively by ET/SPARC designated lane from top to bottom, SRIO0 sends designated lane from machine, SRIO0 receives designated lane from machine, SRIO1 sends designated lane from machine, SRIO1 receives designated lane from machine, SRIO0 main frame sends designated lane, SRIO0 main frame receives designated lane, SRIO1 main frame sends designated lane, SRIO1 main frame receives designated lane, the EDMA general channels 1 of corresponding DSP core and EDMA general channels 2, and in order successively circulation wheel turn.

The request that table 4 Pbus request source coding and token ring are encoded and can be sent

Under each token ring coding, normally can only receive the request of limit priority, if do not have highest priority request to arrive, the redirect carrying out token ring that the request medium priority that token ring arrives according to residue is the highest, will directly jump to the token ring that this request is highest priority request; It is son request all full 16 requests of complete or continuous transmission that described token ring wheel turns the condition switched.

SMC forwards the request that DSP0, DSP1, DSP2 access DSP3 L2 private bus, and meanwhile, in DSP0, DSP1, the general channels 2 of EDMA general channels 1 and DSP1, DSP2 also sends the request of access DSP3 L2 private bus.All access to DSP3 L2 private bus address space all need the arbitration through fast equipment bus DSP3 L2 private bus.L2 private bus receives the request from different pieces of information passage simultaneously, first by according to L2 private bus-channel priorities, priority judgement is carried out to different data channel, SMC forwards CPU request of access priority higher than EDMA general channels, the request that first treatment S MC data channel is sent by L2 private bus.Now, there are two kinds of situations in the EDMA general channels acquisition L2 private bus right to use: after (1) SMC data channel obtains L2 private bus 256 clock period of the right to use; (2) all requests of SMC data channel all complete within 256 clock period, and EDMA general channels will obtain the L2 private bus right to use at once.

There are 3 son requests in SMC data channel, comes from DSP0, DSP1 and DSP2 respectively, after SMC data channel obtains the L2 private bus right to use, turns according to L2 private bus-token ring wheel the process that priority carries out son request.During initial work, have the request from DSP0, determine priforsmc=4 ' b0001, sub-Request Priority is followed successively by from high to low: DSP0, DSP1, DSP2, determines that the request of DSP0 obtains the L2 private bus right to use.The condition that priforsmc wheel turns is: DSP0 request all full 16 requests of complete or continuous transmission, priforsmc=4 ' b0010, sub-Request Priority is followed successively by from high to low: DSP1, DSP2, DSP3, DSP0, determines that DSP1 obtains the L2 private bus right to use.Priforsmc continues wheel by same way and turns, until the request of all SMC data channel completes or the SMC data channel acquisition L2 private bus right to use reaches 256 clock period.

Claims (6)

1. one kind is suitable for the efficient bus arbitration system of heterogeneous polynuclear DSP, it is characterized in that: comprise the SSRAM private bus for shared storage SSRAM distributes, for the DDR3 private bus that DDR3 controller distributes, for the peripheral hardware control register configuration bus that the peripheral hardware control register of each DSP core distributes, for external memory interface EMIF16, multichannel buffer serial port McBSP, multiple channel audio access interface McASP, universal input/output GPIO, the slow devices bus of Inter-Integrated Circuit I2C and the configuration of other external components and be DSP0/DSP1/DSP2/DSP3 L2 private bus corresponding to DSP0/DSP1/DSP2/DSP3 Memory Allocation, totally 8 buses, wherein slow devices bus and peripheral hardware control register configuration bus support that 32bit operates bit wide, and all the other buses support that 128bit operates bit wide, described SSRAM private bus, DDR3 private bus, the resolving strategy that slow devices bus and L2 private bus adopt identical fixed priority and token ring to take turns phase inversion to be combined, and peripheral hardware control register configuration bus adopts simple arbitrate mechanism, namely token ring wheel turns arbitration.
2. the efficient bus arbitration system being suitable for heterogeneous polynuclear DSP according to claim 1, it is characterized in that: described L2 private bus has 6 one-level request sources and 17 sub-request sources of secondary, wherein the priority of one-level request source forwards CPU request msg passage, ET/SPARC designated lane, SRIO from machine designated lane, SRIO host-specific passage, EDMA general channels 1 and EDMA general channels 2 from the high extremely low SMC that is followed successively by;
Wherein, SMC forwards CPU request msg passage and can forward the access that DSP0/DSP1/DSP2/DSP3 tetra-DSP check storage space; SRIO has two from machine designated lane, is respectively SRIO0 from machine designated lane and SRIO1 from machine designated lane; SRIO host-specific passage has two, is respectively SRIO0 host-specific passage and SRIO1 host-specific passage; EDMA general channels 1 has four, comprises DSP0/DSP1/DSP2/DSP3 EDMA general channels 1; EDMA general channels 2 has four, comprises DSP0/DSP1/DSP2/DSP3 EDMA general channels 2.
3. the efficient bus arbitration system being suitable for heterogeneous polynuclear DSP according to claim 1, it is characterized in that: the request source of described peripheral hardware control register configuration bus is EDMA general channels 1 and the EDMA general channels 2 of corresponding DSP core, ET/SPARC designated lane and EDMA general channels 1 and EDMA general channels 2 both can send read request and also can send write request, when read-write requests is concurrent, preferential with write request; Described SRIO host-specific passage is divided into SRIO main frame to send designated lane and SRIO main frame receives designated lane, SRIO main frame sends the request that designated lane can only send read register, SRIO main frame receives designated lane can only send the request writing register, and described SRIO is the same with SRIO host-specific passage with service condition from the division of machine designated lane.
4. the efficient bus arbitration system being suitable for heterogeneous polynuclear DSP according to claim 1 or 2 or 3, it is characterized in that: on described L2 private bus, SMC forwards the arbitration that CPU request msg passage, EDMA general channels 1 and EDMA general channels 2 all relate to four DSP cores, adopt identical token ring wheel to turn strategy; The token ring priority being encoded to 4 ' b0001 is followed successively by DSP0, DSP1, DSP2, DSP3 from high to low, the token ring priority being encoded to 4 ' b0010 is followed successively by DSP1, DSP2, DSP3, DSP0 from high to low, the token ring priority being encoded to 4 ' b0100 is followed successively by DSP2, DSP3, DSP0, DSP1 from high to low, and the token ring priority being encoded to 4 ' b1000 is followed successively by DSP3, DSP0, DSP1, DSP2 from high to low; When corresponding four cores all have request to arrive, token ring 4 ' b0001,4 ' b0010,4 ' b0100,4 ' b1000 circulate successively to take turns from top to bottom in order and turn;
On described L2 private bus, from machine, to send token ring priority that designated lane is encoded to 2 ' b10 be SRIO0 to SRIO sends designated lane from machine and be better than SRIO1 and send designated lane from machine, and to be SRIO1 send designated lane from machine to the token ring priority being encoded to 2 ' b01 is better than SRIO0 and sends designated lane from machine; The token ring priority that SRIO main frame transmission designated lane is encoded to 2 ' b10 is that SRIO0 main frame transmission designated lane is better than SRIO1 main frame transmission designated lane, and the token ring priority being encoded to 2 ' b01 is that SRIO1 main frame transmission designated lane is better than SRIO0 main frame transmission designated lane; Token ring 2 ' b10,2 ' b10 circulate successively to take turns from top to bottom in order and turn.
5. the efficient bus arbitration system being suitable for heterogeneous polynuclear DSP according to claim 1 or 3, it is characterized in that: the passage that described peripheral hardware control register configuration bus token ring rotational order is corresponding is followed successively by ET/SPARC designated lane from top to bottom, SRIO0 sends designated lane from machine, SRIO0 receives designated lane from machine, SRIO1 sends designated lane from machine, SRIO1 receives designated lane from machine, SRIO0 main frame sends designated lane, SRIO0 main frame receives designated lane, SRIO1 main frame sends designated lane, SRIO1 main frame receives designated lane, the EDMA general channels 1 of corresponding DSP core and EDMA general channels 2, and the wheel that circulates successively in order turns.
6. the efficient bus arbitration system being suitable for heterogeneous polynuclear DSP according to claim 4 or 5, it is characterized in that: under each token ring coding, normally can only receive the request of limit priority, if do not have highest priority request to arrive, the redirect carrying out token ring that the request medium priority that token ring arrives according to residue is the highest, will directly jump to the token ring that this request is highest priority request; It is son request all full 16 requests of complete or continuous transmission that described token ring wheel turns the condition switched.
CN201510065701.8A 2015-02-09 2015-02-09 Efficient bus arbitration system applicable to heterogeneous multi-core DSP CN104572529A (en)

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CN106844250A (en) * 2017-02-14 2017-06-13 山东师范大学 The bus arbiter and referee method of a kind of mixed scheduling
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