CN104538293B - Preparation of Gold to achieve the array electrode structure on the target chip structure - Google Patents

Preparation of Gold to achieve the array electrode structure on the target chip structure Download PDF

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CN104538293B
CN104538293B CN 201410842796 CN201410842796A CN104538293B CN 104538293 B CN104538293 B CN 104538293B CN 201410842796 CN201410842796 CN 201410842796 CN 201410842796 A CN201410842796 A CN 201410842796A CN 104538293 B CN104538293 B CN 104538293B
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structure
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electrode
array
chip
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CN104538293A (en )
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朱荣
宗仙丽
郭霄亮
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清华大学
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Abstract

本发明提供一种在芯片结构的目标电极上实现金纳米阵列结构制备方法,其中,该方法包括:在基底的上表面形成包括多个电极的芯片结构,所述多个电极包括:目标电极和非目标电极;按照预设第一时间和预设第一温度,利用预配置的化学溶液和第一电场控制方法,在所述目标电极上形成ZnO纳米阵列结构;按照预设第二时间和预设第二温度,利用预配置的化学镀金溶液和第二电场控制方法,在所形成ZnO纳米阵列结构上进行镀金,形成金纳米阵列结构。 The present invention provides a method implemented on the target electrode array chip structure gold structure production method, wherein the method comprises: forming a chip structure comprises a plurality of electrodes on the surface of the substrate, the plurality of electrodes comprises: an electrode and a target non-target electrodes; a first preset time and a preset first temperature, with a chemical solution and a first electric field control method for pre-configured, a ZnO nano-array electrode structure on said target; a second preset time and pre a second set temperature, using a gold plating solution and a second pre-configured field control method, gold plating on the formed ZnO nano-array structure, the array structure formed of gold. 上述方法能够增加目标电极的表面积、且该方法工艺简便易行、易批量、效率高、可靠性好、成本低。 The above-described method can increase the surface area of ​​the target electrode, which process is simple and easy volume, high efficiency, reliability, and low cost.

Description

在芯片结构的目标电极上实现金纳米阵列结构制备方法 Preparation of Gold to achieve the array electrode structure on the target chip structure

技术领域 FIELD

[0001] 本发明涉及微芯片制造工艺技术领域,尤其涉及一种在芯片结构的目标电极上实现金纳米阵列结构制备方法。 [0001] The present invention relates to a microchip manufacturing technology, and more particularly relates to a method for preparing gold array structure implemented on the target electrode chip structure.

背景技术 Background technique

[0002] 目前,纳机电系统因其超高频率、高品质因数、低能耗、高灵敏度等特性而具有非常广泛的应用前景。 [0002] Currently, ultra-high frequency NEMS because, a high quality factor, low power consumption, high sensitivity characteristic having a very broad application prospects. 纳机电系统的关键技术之一是纳米结构在宏观或微观结构中的局部构造技术。 One of the key technologies NEMS nanostructures is macroscopic or microscopic structure of the local construction techniques. 实现纳米材料大规模阵列式的选择性生长对纳米技术的实际应用来说具有非常重要的意义。 Selective growth to achieve large scale array of nanomaterials has very important significance for practical application of nanotechnology.

[0003] 氧化锌ZnO纳米材料在室温下的禁带宽度为3.37eV,具有低介电常数、高化学稳定性以及很好的光电和压电性质,具有广阔的应用前景,因此,ZnO纳米材料被广泛地应用在各类纳机电器件的研究中。 [0003] The band gap of zinc oxide nano ZnO at room temperature of 3.37eV, a low dielectric constant, high chemical stability, and good optical and piezoelectric properties, has broad application prospects, and therefore, nano ZnO It is widely used in various types of research nanoelectromechanical devices.

[0004] 在ZnO纳米材料的生长中,传统的气相合成法,如化学气相沉积(Chemical Vapor Deposition,简称CVD)法,过程温度较高(>600°C),一般的微机电结构、集成微电子结构或某些基材(如聚合物Polymer)无法承受高温,因而气相合成法难以与微结构兼容,无法实现ZnO纳米材料大规模阵列式的局部位置上的选择性生长;湿化学法(Wet Chemical Method) 可以实现在较低的温度(<l〇〇°C)下合成ZnO纳米材料,但为了实现ZnO纳米材料阵列在局部位置上的选择性生长,往往需利用种子层及复杂的加工工艺形成的模板,工艺步骤繁琐且不易控制,更难以与微结构相集成。 [0004] In the growth of ZnO nano-material, the conventional vapor phase synthesis method, such as chemical vapor deposition (Chemical Vapor Deposition, referred to as CVD) method, a higher process temperature (> 600 ° C), generally microelectromechanical structure, integrated micro electronic structure or some substrates (e.g., polymeric polymer) can not withstand high temperatures, and thus is difficult to be compatible with synthesis gas microstructure, can not be achieved on a large scale array selectively localized growth of nano ZnO position; wet chemical method (wet Chemical Method) may be implemented at a lower temperature (<l〇〇 ° C) for the synthesis of nano ZnO, but in order to achieve selective growth in the local position on the array of nano ZnO, using the seed layer and often takes a complicated process the template formation process step complicated and difficult to control, and even more difficult to integrate microstructures.

[0005] 在芯片结构的目标电极上生长ZnO纳米结构可以增大电极的表面积,但由于ZnO为一种半导体材料,其导电性较差,限制其在诸多方面的应用。 [0005] ZnO nanostructure growth can increase the electrode surface area, but since ZnO is a semiconductor material having poor conductivity, which limits the application in many ways on the target electrode chip structure. 电镀是一种利用电解原理在某些导电结构表面上镀上一薄层金属或合金的过程,是利用电解作用使导电结构表面附着一层金属膜从而改变原结构表面特性的工艺。 Principle by electrolytic plating is a plating structure on some of the conductive surface of a thin layer of metal or alloy processes, electrolysis using the conductive film is a metal structure attached to the surface to change the surface characteristics of the process of the original structure. 但常规电镀用于形成表面膜,而不能形成凹凸的纳米结构。 However, conventional electroplating for forming the surface film, the unevenness can not be formed nanostructures.

[0006] 鉴于此,如何利用ZnO纳米阵列结构制备能够增加目标电极的表面积、工艺简便易行、易批量、高效率、高可靠性、低成本、低温的金纳米阵列结构成为当前需要解决的技术问题。 [0006] In view of this, how to use the ZnO nano-array structure capable of increasing the surface area of ​​the target electrode process is simple, easy-volume, high efficiency, high reliability, low cost, low temperature technology has become the current gold array structure to be solved problem.

发明内容 SUMMARY

[0007] 针对现有技术中的缺陷,本发明提供一种利用ZnO纳米阵列生长与电镀组合在芯片结构的目标电极表面实现金纳米阵列结构制备的方法。 [0007] For the prior art drawbacks, the present invention provides a method for preparing an array of gold plating structure is grown on a combination of the target electrode surface of the chip using a structure ZnO nano-arrays. 利用电场辅助的湿化学生长方法制备ZnO纳米阵列结构,并在ZnO纳米阵列上镀金,在较低的温度(<l〇〇°C)下实现在目标电极上的金纳米阵列结构的选择性制备,能够增加目标电极的表面积、且该方法工艺简便易行、易批量、效率高、可靠性好、成本低。 An electric field-assisted wet chemical growth process of ZnO nano-array structure, and plated on the ZnO nano-arrays, the array structure of the selective preparation of gold on the target electrode is achieved at relatively low temperatures (<l〇〇 ° C) for possible to increase the surface area of ​​the target electrode and which process is simple, easy-volume, high efficiency, reliability, and low cost.

[0008] 本发明提供一种在芯片结构的目标电极上实现金纳米阵列结构制备方法,包括: [0008] The present invention provides a method of fabricating an array of gold structure implemented on the target electrode chip structure, comprising:

[0009] 在基底的上表面形成包括多个电极的芯片结构,所述多个电极包括:目标电极和非目标电极; [0009] The structure comprises a plurality of chip electrodes formed on a surface of the substrate, the plurality of electrodes comprises: non-target electrode and the target electrodes;

[0010]按照预设第一时间和预设第一温度,利用预配置的化学溶液和第一电场控制方法,在所述目标电极上形成ZnO纳米阵列结构; [0010] The first preset time and a preset first temperature, a first chemical solution and a method of controlling an electric field using the pre-configured, a ZnO nano-array electrode structure on said target;

[0011]按照预设第二时间和预设第二温度,利用预配置的化学镀金溶液和第二电场控制方法,在所形成的ZnO纳米阵列结构上进行镀金,形成金纳米阵列结构。 [0011] a second preset time and the second predetermined temperature, the gold plating solution and a second pre-configured control method using an electric field, gold plating on the ZnO nano-array structure is formed, an array structure is formed of gold.

[0012]可选地,所述预设第一时间为0 • 5〜48小时,所述预设第二时间为〇. 5〜5分钟,所述预设第一温度为100°C以下,所述预设第二温度为常温,所述预配置的化学溶液为硝酸锌和乌洛托品复合水溶液,所述预配置的化学镀金溶液为亚硫酸盐镀金溶液。 [0012] Alternatively, the first predetermined time is 0 • 5~48 hours, the second predetermined time is square. 5~5 minutes, the preset first temperature is below 100 ° C, the second predetermined temperature is room temperature, the chemical solution is a preconfigured zinc nitrate and an aqueous solution of hexamine complex, a gold plating solution preconfigured sulfite gold plating solution.

[0013]可选地,所述按照预设第一时间和预设第一温度,利用预配置的化学溶液和第一电场控制方法在所述目标电极上形成ZnO纳米阵列结构,包括: [0013] Alternatively, the first preset time and a preset first temperature, with a chemical solution and a first electric field control method for a ZnO nano preconfigured array structure on the target electrode, comprising:

[00M]按照预设第一温度,将所述芯片结构浸没在预配置的化学溶液中; [00M] according to a preset first temperature, the structure of the chip was immersed in a chemical solution preconfigured;

[0015] 在将所述芯片结构浸没的同时,按照预设第一时间,利用第一电场控制方法在所述目标电极上形成ZnO纳米阵列结构; [0015] In the structure of the chip while submerged, a ZnO nano-array electrode structure on the target according to a preset first time, using the method of controlling the first electric field;

[0016] 在所述芯片结构浸没结束后,将形成有ZnO纳米阵列结构的芯片结构依次进行清洗和烘干。 [0016] After the immersion end of the chip structure, formed of ZnO nano-structure array chip structure sequentially cleaning and drying.

[0017] 可选地,所述第一电场控制方法为直流控制法,所述在将所述芯片结构浸没的同时,按照预设第一时间,利用第一电场控制方法在所述目标电极上形成ZnO纳米阵列结构, 包括: [0017] Alternatively, the first electric field control method for controlling a DC method, the chip while the submerged structure, the first preset time, using a first method of controlling an electric field on the target electrode a ZnO nano-structure array, comprising:

[0018] 在将所述芯片结构浸没的同时,按照预设第一时间,在所述目标电极上施加直流电压VI,在所述全部或一部分非目标电极上施加直流电压V2,在目标电极上形成垂直生长的ZnO纳米阵列结构,其中V1<V2; [0018] In the structure of the chip while submerged, the first preset time, DC voltage VI is applied on the target electrode, DC voltage V2 is applied to the whole or part of the non-target electrode, a target electrode a ZnO nano-array structure perpendicular to the growth, where V1 <V2;

[0019] 或, [0019] or,

[0020] 所述第一电场控制方法为直流交流混合控制法,所述在将所述芯片结构浸没的同时,按照预设第一时间,利用第一电场控制方法在所述目标电极上形成ZnO纳米阵列结构, 包括: [0020] The first DC-AC electric field control method for the hybrid control method of the chip while in the submerged structure, the first preset time, ZnO is formed on the target electrode by the method of the first field control nano-structure array, comprising:

[0021] 在将所述芯片结构浸没的同时,按照预设第一时间,在所述目标电极上施加直流电压V3和交流电压V5,在所述全部或一部分非目标电极上施加直流电压V4,在目标电极上形成杂乱生长的ZnO纳米阵列结构,其中V3<V4。 [0021] In the structure of the chip while submerged, the first preset time, applying a DC voltage an AC voltage V3 and V5 on the target electrode, applying a DC voltage V4 on all or a portion of the non-target electrodes, disorderly array structure formed ZnO nano grown on the target electrode, wherein V3 <V4.

[0022] 可选地,所述第一电场控制方法为直流控制法,所述在将所述芯片结构浸没的同时,按照预设第一时间,利用第一电场控制方法在所述目标电极上形成Zn0纳米阵列结构, 还包括: [0022] Alternatively, the first electric field control method for controlling a DC method, the chip while the submerged structure, the first preset time, using a first method of controlling an electric field on the target electrode Zn0 nano-array structure is formed, further comprising:

[0023] 所述芯片结构的基底下表面还包括底电极; [0023] The lower surface of the chip substrate structure further includes a bottom electrode;

[0024] 在将所述芯片结构浸没的同时,按照预设第一时间,在所述目标电极上施加直流电压VI,在所述全部或一部分非目标电极上施加直流电压V2,在所述底电极上施加直流电压V8,在目标电极上形成垂直生长的ZnO纳米阵列结构,其中V1<V8<V2; [0024] In the structure of the chip while submerged, the first preset time, DC voltage VI is applied on the target electrode, DC voltage V2 is applied over all or a portion of the non-target electrodes, the bottom DC voltage is applied to the electrodes V8, a ZnO nano-array structure vertically grown on the target electrode, where V1 <V8 <V2;

[0025] 或, [0025] or,

[0026] 所述第一电场控制方法为直流交流混合控制法,所述在将所述芯片结构浸没的同时,按照预设第一时间,利用第一电场控制方法在所述目标电极上形成Zn0纳米阵列结构, 还包括: [0026] The first DC-AC electric field control method for the hybrid control method of the chip while in the submerged structure, the first preset time, using a first method of controlling an electric field formed on the target electrode Zn0 nano-array structure, further comprising:

[0027] 所述芯片结构的基底下表面还包括底电极; [0027] The lower surface of the chip substrate structure further includes a bottom electrode;

[0028] 在将所述芯片结构浸没的同时,按照预设第一时间,在所述目标电极上施加直流电压V3和交流电压V5,在所述全部或一部分非目标电极上施加直流电压V4,在所述底电极上施加直流电压V9,在目标电极上形成杂乱生长的ZnO纳米阵列结构,其中V3<V9〈V4。 [0028] In the structure of the chip while submerged, the first preset time, applying a DC voltage an AC voltage V3 and V5 on the target electrode, applying a DC voltage V4 on all or a portion of the non-target electrodes, applied to the bottom electrode DC voltage V9, a ZnO nano-array structure grown clutter in the target electrode, wherein V3 <V9 <V4.

[0029]可选地,所述底电极的材料为:掺杂的单晶硅或金属。 [0029] Alternatively, the bottom electrode is a material: doped monocrystalline silicon or metal.

[0030]可选地,所述按照预设第二时间和预设第二温度,利用预配置的化学镀金溶液和第二电场控制方法,在所形成的ZnO纳米阵列结构上进行镀金,包括: [0030] Alternatively, the second preset time and the second predetermined temperature, using the electroless gold plating solution and a second pre-configured field control method, gold plating on the ZnO nano-array structure is formed, comprising:

[0031]按照预设第二温度,将烘千后的形成有ZnO纳米阵列结构的芯片结构浸没在预配置的化学镀金溶液中,或者,在预设第二温度下将预配置的化学镀金溶液滴加在烘干后的形成有ZnO纳米阵列结构的芯片结构的表面; [0031] according to a preset second temperature, formed after drying ZnO nano structures one thousand the chip array structure immersed in the electroless gold plating solution preconfigured, or at a second predetermined temperature preconfigured gold plating solution dropped after drying is formed with a surface of the ZnO nano-structure array chip structure;

[0032]按照预设第二时间,利用第二电场控制方法在所述预配置的化学镀金溶液中在所形成的ZnO纳米阵列结构上进行镀金,形成金纳米阵列结构; [0032] a second preset time, gold plating on the ZnO nano-array structure formed in the gold plating solution preconfigured, the array structure formed by the second gold field control method;

[0033]在镀金结束后,将形成有金纳米阵列结构的芯片结构取出,依次进行清洗和烘干。 [0033] After the end of the gold, the gold chip structure formed array structure is taken out, sequentially cleaning and drying. [0034]可选地,所述按照预设第二时间,利用第二电场控制方法在所述预配置的化学镀金溶液中在所形成的ZnO纳米阵列结构上进行镀金,包括: [0034] Alternatively, the second preset time, gold plating on the ZnO nano-array structure formed in the gold plating solution of the pre-configured, including the use of a second control method of an electric field:

[0035]按照预设第二时间,在形成有Zn0纳米阵列结构目标电极上施加直流电压V6,在全部或一部分非目标电极上施加直流电压V7,其中V6〈V7。 [0035] a second preset time, the DC voltage V6 is applied is formed on the target electrode array structure Zn0 nanometers, applying a DC voltage V7 on all or a portion of non-target electrodes, wherein V6 <V7.

[0036] 可选地,所述目标电极的材料为:络/金层、或钦/金层、或鹤/金层。 [0036] Alternatively, the electrode material is a target: network / gold layers, or Chin / gold layer, or a crane / gold layer.

[0037] 可选地,所述基底的材料为:二氧化硅、或氮化硅、或聚合物。 [0037] Alternatively, the material of the substrate is: silicon dioxide, or silicon nitride, or a polymer.

[0038]由上述技术方案可知,本发明的在芯片结构的目标电极上实现金纳米阵列结构制备方法,基于电场辅助的湿化学生长方法,在低温下(<10(rc)实现Zn0纳米阵列在目标电极上白^择性生长,在宏/微结构中可以有效地集成纳米材料,满足低温、低成本、易批量的特点,简便易行,利用ZnO纳米阵列,在目标电极上制备出金纳米阵列结构,并极大增大了目标电极的表面积,工艺简便、效率高、可靠性好。 [0038] From the above technical solution, the gold array structure production method of the present invention is implemented on the target electrode chip structure, the field-assisted wet chemical growth method based on at low temperatures (<10 (rc) implemented in Zn0 nanoarray white target electrode ^ selective growth, nanomaterials can be effectively integrated in macro / micro structure to meet the low temperature, low cost, easy-volume characteristics, easy, using ZnO nano-arrays prepared on the target gold electrode array structure, and greatly increases the surface area of ​​the target electrode, the process is simple, high efficiency and good reliability.

附图说明 BRIEF DESCRIPTION

[0039]图1为本发明第一实施例提供的在芯片结构的目标电极上进行金纳米阵列结构制备方法的流程示意图; [0039] Fig 1 a schematic flowchart of a method for preparing a gold electrode array structure of the target structure in the chip according to a first embodiment of the present invention;

[_] _为本_第二实肺_第五实施纖働—种在麵社麵形成的包括多个电极(目标电极和非目标电极)的芯片结构的示意图; _1]图3为本划脂二实顧轉五实脑提働在臟目标电社形麵直生长的ZnO纳米阵列结构的直流控制法示意图; _]、图4为本发明第二实施例和第五实脑提供的一种利臟雜制法在臓目标电极上形成的垂直生长的ZnO纳米阵列结构的示意图; [_] _ Present _ _ a fifth embodiment of the second solid lung fiber Dong - a schematic view of a plurality of electrodes (target and non-target electrode electrode) chip structure formed in the surface of the seed club face; _1] FIG. 3 is a plan a schematic view of two solid lipid DC control method Gu transfected five solid growth in the brain provide a linear Dong dirty Kodensha target surface shape of the ZnO nano-array structure; _], FIG. 4 of the present invention, the second embodiment and the fifth embodiment provides a real brain Lee species schematic configuration of a vertical array of nano ZnO grown method Zang formed on the target electrode dirty heteroaryl;

[00/!^,52i发明第二实施例和第五实施例提供的在臓目标电极上形成杂乱生长的ZnO纳米阵列结构的直流交流混合控制法示意图; 明第二实赫_第五麵體供的—种利醜流交魏合挪法在所述目标电极上形成的杂乱生长的Zn0纳米阵列结构的示意图; _5]图7为本发明第三实施例和第六实施例提供的另一种在基底的上麵形成多个电极(目标电极和非目标电极)、在基底下表面形成底电极的芯片结构的示意图; ! [00 / ^, 52i invention, DC-AC schematic configuration of a ZnO nano-arrays clutter grown hybrid control method Zang formed on the target electrode and the second embodiment of the fifth embodiment provides; Ming He second solid body fifth surface _ for - the kind of interest ugly schematic configuration of an array of nano-Zn0 Wei moved together was formed on the target electrode cross-flow growth clutter; _5] FIG. 7 another embodiment of the third embodiment and the sixth embodiment of the present invention provides forming a plurality of kinds of electrodes (target and non-target electrode electrode) on top of the substrate, a schematic configuration of a chip surface of the bottom electrode is formed at a substrate;

[0046]图8为本发明第三实施例和第六实施例提供的在所述目标电极上形成垂直生长的ZnO纳米阵列结构的直流控制法示意图; [0046] Figure 8 is a schematic diagram of a DC control method of the ZnO nano array structure formed vertically grown on the target electrode in the sixth embodiment and a third embodiment provided by the embodiment of the invention;

[0047]图9为本发明第三实施例和第六实施例提供的在所述目标电极上形成杂乱生长的ZnO纳米阵列结构的直流交流混合控制法示意图; [0047] Figure 9 a schematic view of a third embodiment of a ZnO nano-array structure DC clutter grown on the target and a sixth electrode in Example embodiments provide an AC hybrid control method of the present invention;

[0048]图1〇为本发明第四实施例提供的在所形成的ZnO纳米阵列结构上进行镀金的示意图; [0048] The schematic diagram of FIG. 1〇 gold plating on ZnO nano-structure array formed according to a fourth embodiment of the invention;

[0049]图11为本发明第四实施例提供的完成镀金后得到的金纳米阵列结构的示意图; [0050]图12为本发明第二实施例提供的一种在芯片结构的目标电极上形成ZnO纳米阵列结构制备方法的流程示意图; [0049] FIG 11 a schematic view of an array of gold plated structure obtained after the completion of a fourth embodiment of the invention is provided; one second embodiment provides the target electrode is formed on the chip structure [0050] 12 of the present invention, FIG. preparation process of a schematic structure of an array of nano ZnO;

[0051]图I3为本发明第三实施例提供的另一种在芯片结构的目标电极上形成ZnO纳米阵列结构制备方法的流程示意图; [0051] FIG I3 present third embodiment provides a process preparing an array of ZnO nanorods schematic diagram of another configuration formed on the target electrode chip structure of the present invention;

[0052]图14为本发明第四实施例提供的一种在芯片结构的目标电极上实现金纳米阵列结构制备方法的流程示意图; [0052] FIG 14 provides flow diagram of an embodiment method for preparing an array of gold implementation structures on the target electrode chip structure of the fourth embodiment of the invention;

[0053]图15为本发明第五实施例提供的一种在芯片结构的目标电极上实现金纳米阵列结构制备方法的流程示意图; [0053] FIG 15 provides flow diagram of an embodiment method for preparing an array of gold implementation structure in the target chip electrode structure according to a fifth embodiment of the present invention;

[0054]图le为本发明第六实施例提供的另一种在芯片结构的目标电极上实现金纳米阵列结构制备方法的流程示意图; [0054] FIG. Le sixth embodiment of the present embodiment provides a schematic diagram of another realization of gold preparation process of array structures on the target electrode chip structure of the present invention;

[0055] 附图标记: [0055] The reference numerals:

[0056] 1、基底;2、目标电极;3、非目标电极;4、预配置的化学溶液;5、垂直生长的ZnO纳米阵列结构;6、杂乱生长的ZnO纳米阵列结构;7、底电极;8、预配置的化学镀金溶液;9、金纳米阵列结构。 [0056] 1 substrate; 2, target electrodes; 3, non-target electrode; 4, preconfigured chemical solution; 5, the vertical growth of the ZnO nano-array structure; 6, messy grown ZnO nano-array structure; 7, the bottom electrode ; 8 preconfigured gold plating solution; 9, gold array structure.

具体实施方式 detailed description

[0057]为使本发明实施例的目的、技术方案和优点更加清楚,下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整的描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。 [0057] In order that the invention object, technical solutions, and advantages of the embodiments more clearly, the following the present invention in the accompanying drawings, technical solutions of embodiments of the present invention will be clearly and fully described, obviously, the described the examples are merely part of embodiments of the present invention rather than all embodiments. 基于本发明的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他的实施例,都属于本发明保护的范围。 Based on the embodiments of the present invention, all other embodiments to those of ordinary skill in the art without any creative effort shall fall within the scope of the present invention. [0058] 第一实施例 [0058] First embodiment

[0059]图1示出了本发明第一实施例提供的在芯片结构的目标电极上实现金纳米阵列结构制备方法的流程示意图,如图1所示,本实施例的金纳米阵列结构制备方法如下所述。 [0059] FIG. 1 shows a schematic flow diagram of the present invention to achieve a method for fabricating an array of gold structures on the target electrode chip structure according to a first embodiment, shown in Figure 1, the gold array structure production method of this embodiment below. [0060] 101、在基底的上表面形成包括多个电极的芯片结构,所述多个电极包括:目标电极和非目标电极。 [0060] 101, includes a plurality of electrodes forming a chip structure on a surface of the substrate, the plurality of electrodes comprises: a target electrode and a non-target electrodes.

[0061] 102、按照预设第一时间和预设第一温度,利用预配置的化学溶液和第一电场控制方法,在所述目标电极上形成ZnO纳米阵列结构(纳米线或纳米棒)。 [0061] 102, the first preset time and a preset first temperature, a first chemical solution and a method of controlling an electric field using the pre-configured, a ZnO nano-array structure (nanowires or nanorods) on the target electrode.

[0062] 1〇3、按照预设第二时间和预设第二温度,利用预配置的化学镀金溶液和第二电场控制方法,在所形成的ZnO纳米阵列结构上进行镀金,在目标电极上形成金纳米阵列结构。 [0062] 1〇3, a second preset time and the second predetermined temperature, using the electroless gold plating solution and a second pre-configured field control method, gold plating on the ZnO nano-structure array formed on the target electrode array structure is formed of gold. [0063]本实施例的在芯片结构的目标电极上实现金纳米阵列结构制备方法,基于电场辅助的湿化学生长方法,在低温下(<100°C)实现ZnO纳米阵列在目标电极上的选择性生长,在宏/微结构中可以有效地集成纳米材料,满足低温、低成本、易批量的特点,简便易行,利用ZnO纳米阵列,在目标电极上制备出金纳米阵列结构,并极大增大了目标电极的表面艺简便、效率高、可靠性好。 [0063] Example embodiment of the present method of preparing an array of gold on the target electrode structure to achieve chip structure, the field-assisted wet chemical growth method based on at low temperatures (<100 ° C) selected to achieve an array of ZnO on the target electrode growth, nanomaterials can be effectively integrated in macro / micro structure to meet the low temperature, low cost, easy-volume characteristics, easy, using ZnO nano-arrays prepared gold electrode array structure on the target, and greatly increasing the target electrode surfaces arts simple, high efficiency and reliability.

[0064] 第二实施例 [0064] Second Embodiment

[0065]图12=出了本发明第二实施例提供的一种在目标电极上形成Zn0纳米阵列结构制备方法的流程示意图,如图12所示,本实施例的在目标电极上形成Zn〇纳米阵列结构制备方法如下所述。 [0065] FIG. 12 = a second flow diagram of an embodiment of the present invention provides a method of preparing Zn0 nano-structure array formed on the target electrode 12, the present embodiment is formed on the target electrode Zn〇 nano-structure array preparation method described below.

[0066] 20^、在基底上表面形成包括多个电极(目标电极和非目标电极)的芯片结构,如图2所示,图2示出了一种在基底的上表面形成的包括多个电极(目标电极和非目标电极)的芯片结构的示意图。 [0066] 20 ^, the chip surface structure comprises a plurality of electrodes (target and non-target electrode electrode) on the substrate, as shown in FIG 2 FIG. 2 shows a method of forming on a surface of the substrate comprises a plurality of a schematic structure of an electrode chip (target and non-target electrode electrode).

[0067]优选地,目标电极的材料为:铬/金层、或铁/金层、或鹤/金层,其中,铬、钦、销为金的粘附层,用于增强电极(目标电极和非目标电极)与基底的粘附性。 [0067] Preferably, the material of the target electrode is: Cr / Au layer, or iron / gold layer, or a crane / gold layer, wherein the chromium, Chin, pin gold adhesive layer, for enhancing the electrode (the target electrode and non-target electrode) adhesion to the substrate.

[0068]优选地,本发明实施例的基底的材料为:二氧化硅、或氮化硅、或聚合物。 [0068] Preferably, the base material of the embodiment of the present invention are: silicon dioxide, or silicon nitride, or a polymer.

[0069]可理解的是,本步骤可以采用加工工艺,如可选用光刻、刻蚀或剥离工艺在基底的上表面形成包括多个电极的芯片结构。 [0069] appreciated that the present processing steps may be employed, such as the choice of photolithography, etching or lift-off process of forming a chip structure comprises a plurality of electrodes on the surface of the substrate.

[0070] 202、按照预设第一时间和预设第一温度,利用预配置的化学溶液和第一电场控制方法,在所述目标电极上形成ZnO纳米阵列结构。 [0070] 202, the first preset time and a preset first temperature, a first chemical solution and a method of controlling an electric field using the pre-configured, ZnO nano-array structure is formed on the target electrode.

[0071]其中,所述预设第一时间为0 • 5〜48小时,所述预设第一温度为100 °c以下,所述预配置的化学溶液为硝酸锌和乌洛托品复合水溶液。 [0071] wherein said first predetermined time is 0 • 5~48 hours, the predetermined first temperature is 100 ° c or less, the chemical solution is a preconfigured zinc nitrate and an aqueous solution of hexamine complex .

[0072]可理解的是,所述预设第一时间是根据需要制备的纳米线或纳米棒的长度来设定的,例如,3〜10小时可以制备出3〜10微米长的纳米线或纳米棒; [0072] appreciated that the first predetermined time is set in accordance with desired to prepare nanowires or nanorods of length, for example, can be prepared 3~10 3~10 hours microns long, or nanowires Nano stave;

[0073] 应说明的是,第一电场控制方法可以为直流控制法或直流交流混合控制法。 [0073] It should be noted that the first AC electric field control method may control the mixing process or method of controlling a DC current. 图3- 图4为利用第一电场控制法在所述目标电极上形成ZnO纳米阵列结构的示意图。 Figure 3 - FIG. 4 is a schematic of the ZnO nano-array structure using the method of controlling the first electric field formed on the target electrode.

[0074] 在具体应用中,上述步骤可以包括图中未示出的步骤: [0074] In particular applications, the above step may include steps not shown in the figure:

[0075] 2021、按照预设第一温度,将所述芯片结构浸没在预配置的化学溶液中。 [0075] 2021, according to a preset first temperature, the chip is immersed in a pre-configured structure in a chemical solution.

[0076] 2022、在将所述芯片结构浸没的同时,按照预设第一时间,利用第一电场控制方法在所述目标电极上形成ZnO纳米阵列结构。 [0076] 2022, the chip structure while submerged, a first preset time, a ZnO nano-array electrode structure on the target field using the first control method.

[0077] 举例来说,若本步骤的第一电场控制方法为直流控制法,则上述步骤2022可以具体为步骤2022a: [0077] For example, if the first step of the present method of controlling an electric field to a DC control method, the above-described step 2022 may specifically steps 2022a:

[0078] 2022a、如图3所示,在将所述芯片结构浸没的同时,按照预设第一时间,在所述目标电极上施加直流电压VI,在所述全部或一部分非目标电极上施加直流电压V2,在目标电极上形成垂直生长的ZnO纳米阵列结构,如图4,其中V1<V2。 [0078] 2022a, as shown in FIG chip while the submerged structure, the first preset time, DC voltage VI is applied on the target electrode 3, applied to all or a portion of the non-target electrode DC voltage V2, the target electrode is formed on the ZnO nano-array structure perpendicular to the growth, as shown in FIG 4, where V1 <V2.

[0079] 举例来说,若本步骤的第一电场控制方法为直流交流混合控制法,则上述步骤2022可以具体为步骤2022b: [0079] For example, if the electric field control method according to the first step is mixed AC and DC control method, the above-described step of step 2022 may specifically 2022b:

[0080] 2022b、如图5所示,在将所述芯片结构浸没的同时,按照预设第一时间,在所述目标电极上施加直流电压V3和交流电压V5,在所述全部或一部分非目标电极上一部分施加直流电压V4,在目标电极上形成杂乱生长的ZnO纳米阵列结构,如图6,其中V3<V4。 [0080] 2022b, as shown in FIG chip while the submerged structure, the first preset time, applying a DC voltage an AC voltage V3 and V5 on the target electrode 5, all or a portion of the non- applying a DC voltage on the target portion of the electrode V4, a ZnO nano disorderly array structure grown on a target electrode 6, wherein V3 <V4.

[0081] 203、在所述芯片结构浸没结束后,将形成有Zn0纳米阵列结构的芯片结构依次进行清洗和烘干。 [0081] 203, the die structure after immersion end, formed with a Zn0 nanoarrays array structure sequentially cleaning and drying.

[0082]可理解的是,在进行清洗和烘干之后,可实现在芯片目标电极上ZnO纳米阵列结构的生长。 [0082] understood that, after performing washing and drying, the growth of ZnO nano-arrays may be implemented on a chip configuration target electrodes. 利用直流控制法在所述目标电极上形成ZnO纳米阵列结构为垂直生长的,如图4所示;利用直流交流混合控制法在所述目标电极上形成ZnO纳米阵列结构为杂乱生长的,如图6所示。 ZnO nano-arrays are formed vertically grown structure, shown in Figure 4 on the target electrode by a DC control method; AC hybrid control method using a DC ZnO nano-array structure is formed on the target electrode clutter growth, as FIG 6.

[0083]利用本实施例所述方法可在芯片结构的目标电极上形成ZnO纳米阵列结构。 [0083] With the present embodiment of the method may be formed ZnO nano-array electrode structure on the target chip structure.

[0084] 第三实施例 [0084] Third embodiment

[0085]图13示出了本发明第三实施例提供的另一种在芯片结构的目标电极上形成Zn0纳米阵列结构制备方法的流程示意图,如图13所示,本实施例的在芯片目标电极上形成Zn0纳米阵列结构制备方法如下所述。 [0085] FIG 13 shows a third embodiment of the present invention to provide a nano-array structure schematic flow diagram Zn0 Another method for preparing the target electrode is formed on a chip structure shown in Figure 13, in certain embodiments the chip of the present embodiment Zn0 method of preparing nano-array structure is formed on the electrode as described below. 采用第二实施例所述方法,ZnO纳米阵列结构在未加电的非目标电极和基底上会有少量生长。 Using the second embodiment of the method, ZnO nano-array structure on the non-target non-power electrode and a small amount of growth substrate. 为了抑制ZnO纳米材料在非目标电极和基底上的生长,精确控制ZnO纳米阵列结构在目标电极上的定位生长,在芯片结构中增加底电极以进行第三电场的控制。 In order to inhibit the growth of ZnO material on a non-target electrode and the substrate, precise control of ZnO nano array structure on the target electrode positioned in the growth, increase in the chip bottom electrode structure for controlling the third field.

[0086] 301、图7示出了一种在基底的上表面形成多个电极(目标电极和非目标电极)和下表面形成底电极的芯片结构的示意图。 [0086] 301, FIG. 7 shows a schematic diagram of forming a plurality of electrodes (target and non-target electrode electrode) is formed on a surface of a substrate chip structure of the bottom electrode and a lower surface.

[0087]可选地,目标电极的材料为:铬/金层、或钛/金层、或钨/金层,其中,铬、钛、钨为金的粘附层,用于增强电极(目标电极和非目标电极)与基底的粘附性。 [0087] Alternatively, the material of the target electrode is: Cr / Au layer, or a titanium / gold layer, or a tungsten / gold layers, wherein, chromium, titanium, tungsten, gold adhesive layer, for enhancing the electrode (target electrode and an electrode non-target) adhesion to the substrate.

[00SS]可选地,本发明实施例的中间层(即基底)的材料为:二氧化硅、或氮化硅、或聚合物。 Materials [00SS] Alternatively, the intermediate layer according to embodiments of the present invention (i.e., substrate) is: silicon dioxide, or silicon nitride, or a polymer. 底电极的材料优选为:掺杂的单晶硅或金属。 The bottom electrode material is preferably: doped monocrystalline silicon or metal.

[0089]可理解的是,本步骤可以采用加工工艺,如可选用热氧化、刻蚀或剥离工艺,在底电极上形成中间绝缘基底层并制作目标电极和非目标电极。 [0089] appreciated that the present processing steps may be employed, such as the choice of thermal oxidation, etching or lift-off process, forming an intermediate electrode insulating base layer on the bottom electrode and the target and non-target produced electrode.

[0090] 302、按照预设第三时间和预设第三温度,利用预配置的化学溶液和第三电场控制方法,在所述目标电极上形成ZnO纳米阵列结构。 [0090] 302, a third time and a preset third predetermined temperature, the electric field control, and a third chemical solution method using pre-configured, ZnO nano-array structure is formed on the target electrode.

[0091] 其中,所述预设第三时间为0 •5〜48小时,所述预设第三温度为100 °C以下,所述预配置的化学溶液为硝酸锌和乌洛托品复合水溶液。 [0091] wherein said third predetermined time is 0 • 5~48 hours, the predetermined third temperature is below 100 ° C, the chemical solution is a preconfigured zinc nitrate and an aqueous solution of hexamine complex .

[0092]可理解的是,所述预设第三时间是根据需要制备的纳米线或纳米棒的长度来设定的,例如,3〜10小时可以制备出3〜10微米长的纳米线或纳米棒; [0092] appreciated that the third predetermined time is set based on nanowires or nanorods prepared required length, for example, it can be prepared 3~10 3~10 hours microns long, or nanowires Nano stave;

[0093] 应说明的是,第三电场控制方法可以为直流控制法或直流交流混合控制法。 [0093] It should be noted that the third alternating electric field control method may control the mixing process or method for the DC control current. 图8-图9为利用第三电场控制法在所述目标电极上形成ZnO纳米阵列结构的示意图。 8-9 is a schematic structure ZnO nano-arrays are formed on the target electrode by the electric field of the third control method.

[0094] 在具体应用中,上述步骤可以包括图中未示出的步骤: [0094] In particular applications, the above step may include steps not shown in the figure:

[0095] 3021、按照预设第三温度,将所述芯片结构浸没在预配置的化学溶液中。 [0095] 3021, according to a third preset temperature, the structure of the chip was immersed in a chemical solution preconfigured.

[0096] 3022、在将所述芯片结构浸没的同时,按照预设第三时间,利用第三电场控制方法在所述目标电极上形成ZnO纳米阵列结构。 [0096] 3022, the chip structure while submerged, the third preset time, the electric field control by the third method of forming an array of ZnO nano structure on the target electrode.

[0097] 举例来说,若本步骤的第三电场控制方法为直流控制法,则上述步骤3022可以具体为步骤3022a: [0097] For example, if the third step of the present method of controlling an electric field to a DC control method, the above-described step of step 3022 may specifically 3022a:

[0098] 3022a、如图8所示,在将所述芯片结构浸没的同时,按照预设第三时间,在所述目标电极上施加直流电压VI,在所述全部或一部分非目标电极上施加直流电压V2,在所述底电极上施加直流电压V8,在目标电极上形成垂直生长的ZnO纳米阵列结构,其中VI <V8<V2。 [0098] 3022a, as shown in FIG chip while the submerged structure, the third preset time, DC voltage VI is applied on the target electrode 8 applied to all or a portion of the non-target electrode DC voltage V2, is applied on the bottom electrode DC voltage V8, a ZnO nano-array structure vertically grown on the target electrode, where VI <V8 <V2. [0099] 举例来说,若本步骤的第三电场控制方法为直流交流混合控制法,则上述步骤3022可以具体为步骤3022b: [0099] For example, if the electric field control method according to the third step is mixed AC and DC control method, the above-described step of step 3022 may specifically 3022b:

[0100] 3022b、如图9所示,在将所述芯片结构浸没的同时,按照预设第三时间,在所述目标电极上施加直流电压V3和交流电压V5,在所述全部或一部分非目标电极上一部分施加直流电压V4,在所述底电极上施加直流电压V9,其中在目标电极上形成杂乱生长的ZnO纳米阵列结构,其中V3<V9<V4。 [0100] 3022b, as shown, the chip structure while submerged, the third preset time, applying a DC voltage an AC voltage V3 and V5 on the target electrode 9, all or a portion of the non- is applied to the electrode portion of the target DC voltage V4, V9 DC voltage is applied on the bottom electrode, wherein the array structure formed ZnO nano clutter grown on the target electrode, wherein V3 <V9 <V4.

[0101] 303、在所述芯片结构浸没结束后,将形成有ZnO纳米阵列结构的芯片结构依次进行清洗和供千。 [0101] 303, after the immersion end chip structure, formed of ZnO nanoarrays array structure for sequentially cleaning and thousands.

[0102] 可理解的是,在进行清洗和烘干之后,可实现在目标电极上ZnO纳米阵列结构的生长。 [0102] understood that, after performing washing and drying, the growth of ZnO nano-arrays may be implemented on the target electrode structure. 利用直流控制法在所述目标电极上形成ZnO纳米阵列结构为垂直生长的;利用直流交流混合控制法在所述目标电极上形成ZnO纳米阵列结构为杂乱生长的。 It is formed on the target electrode array structure of ZnO nano vertically grown using a direct current control method; AC hybrid control method by a DC ZnO nano-array structure is formed on the target electrode clutter growth.

[0103] 利用本实施例所述方法可精确地在芯片结构的目标电极上形成ZnO纳米阵列结构。 [0103] With the present embodiment of the method may be precisely formed ZnO nano-array electrode structure on the target chip structure.

[0104] 第四实施例 [0104] Fourth embodiment

[0105]图14示出了本发明第四实施例提供的一种在芯片结构的目标电极上进行金纳米阵列结构制备方法的流程示意图,如图14所示,本实施例的金纳米阵列结构制备方法如下所述。 [0105] FIG. 14 shows a flow diagram of a fourth embodiment of the present invention provides a method for preparing an array of gold electrode structure on the target chip structure, as shown in FIG. 14, the gold array structure according to the present embodiment prepared as described below.

[0106] 401、在芯片目标电极上形成ZnO纳米阵列结构。 [0106] 401, a ZnO nano-array electrode structure on the chip target.

[0107] 402、按照预设第二时间和预设第二温度,利用预配置的化学镀金溶液和第二电场控制方法,在所形成的ZnO纳米阵列结构上进行镀金,形成金纳米阵列结构。 [0107] 402, a second preset time and the second predetermined temperature, the gold plating solution and a second pre-configured control method using an electric field, gold plating on the ZnO nano-array structure is formed, an array structure is formed of gold.

[0108]其中,所述预设第二时间为0.5〜5分钟,所述预设第二温度为常温,所述预配置的化学镀金溶液为:亚硫酸盐镀金溶液。 [0108] wherein said second predetermined time is 0.5~5 minutes, the preset second temperature is room temperature, the pre-configured as gold plating solution: sulfite gold plating solution.

[0109]可理解的是,完成本步骤后得到的金纳米阵列结构如图11所示。 [0109] appreciated that the completion of this step to give gold array structure shown in Fig.

[0110] 在具体应用中,上述步骤402可以包括图14中未示出的步骤4021-4023: [0110] In a particular application, the step 402 may include the steps 4021-4023 in FIG. 14, not shown:

[0111] 4021、按照预设第二温度,将烘干后的形成有ZnO纳米阵列结构的芯片结构浸没在预配置的化学镀金溶液中,或者,在预设第二温度下将预配置的化学镀金溶液滴加在烘干后的形成有ZnO纳米阵列结构的芯片结构的表面。 [0111] 4021, according to the chemical preset second temperature, formed after drying has a chip structure of the ZnO nano-array structure immersed in the electroless gold plating solution preconfigured, or pre-arranged in a preset second temperature gold plating solution was added dropwise formed after drying the surface of the ZnO nanoarrays array structure.

[0112] 4022、按照预设第二时间,利用第二电场控制方法在所述预配置的化学镀金溶液中在所形成的ZnO纳米阵列结构上进行镀金,如图1〇所示。 [0112] 4022, the second preset time, gold plating on the ZnO nano-structure array formed in electroless gold plating solution in the pre-configuration, as shown in FIG 1〇 control method using the second electric field.

[0113] 在具体应用中,上述步骤4022可以具体为: [0113] In a particular application, the step 4022 may specifically be:

[0114]按照预设第二时间,在形成有Zn0纳米阵列结构目标电极上施加直流电压V6,在全部或一部分非目标电极上施加直流电压V7,在目标电极上形成金纳米阵列结构,其中V6< V7〇 [0114] a second preset time, the DC voltage V6 is applied is formed on the target electrode array structure nano Zn0, DC voltage is applied on all or a portion of non-target electrodes V7, gold is formed on the target electrode array structure, wherein V6 <V7〇

[0115] 4023、在镀金结束后,将得到的形成有金纳米阵列结构的芯片取出,依次进行清洗和烘干。 [0115] 4023, after the gold plating is formed, the resulting array structure of the chip gold extraction, cleaning and drying successively.

[0116]可理解的是,在进行清洗和烘干之后,可在目标电极上形成金纳米阵列结构。 [0116] understood that, after performing cleaning and drying, the gold may be formed on the target electrode array structure.

[0117]应说明的是,在ZnO纳米阵列结构(纳米线或纳米棒)上实施镀金的过程中,“zn〇纳米阵列结构在镀金液中的溶解”与“镀金成形”两种作用同时发生,需要合理控制电镀的速率,才能最终形成理想的金纳米阵列结构。 [0117] It should be noted that the process of gold plating on the ZnO nano-structure array (nanowires or nanorods), the "dissolution zn〇 array structure in nano gold plating solution" and "gilt molding" two actions occur simultaneously , a logical control the rate of plating of gold in order to ultimately form the desired array structure.

[0118]本实施例的在芯片结构的目标电极上进行金纳米阵列结构制备方法,基于电场辅助的湿化学生长方法,在低温下(<100°C)实现ZnO纳米阵列在目标电极上的选择性生长,在宏/微结构中可以有效地集成纳米材料,满足低温、低成本、易批量的特点,简便易行,利用选择性生长的ZnO纳米阵列,在目标电极上制备出金纳米阵列结构,并极大增大了目标电极的表面积,工艺简便、效率高、可靠性好。 [0118] Example embodiments of the present preparation process the target structures on a gold electrode array chip structure, the field-assisted wet chemical growth method based on at low temperatures (<100 ° C) selected to achieve a target of ZnO on the electrode array growth can be effectively integrated in a macro / micro structure nanomaterials meet low-temperature, low cost, easy-volume characteristics, easy, using the selective growth of ZnO nano-arrays prepared gold electrode array structure on the target and greatly increases the surface area of ​​the target electrode, the process is simple, high efficiency, good reliability.

[0119] 第五实施例 [0119] Fifth Example

[0120] 图15示出了本发明第五实施例提供的一种在芯片结构的目标电极上进行金纳米阵列结构制备方法的流程示意图,如图15所示,本实施例的金纳米阵列结构制备方法如下所述。 [0120] FIG. 15 shows a flow diagram of a fifth embodiment of the present invention provides a method of gold prepared array structure on the target electrode chip structure, shown in Figure 15, the present embodiment is gold array structure prepared as described below.

[0121] 501、采用微加工工艺在二氧化硅基底上形成包括铬/金目标微电极和铬/金非目标微电极的芯片结构,如图2所示。 [0121] 501, micro-chip structure including forming process Cr / Au electrode and the target micro Cr / Au non-target microelectrodes on a silica substrate, as shown in FIG.

[0122] 举例来说,本步骤的微加工工艺可以包括:光刻、刻蚀或剥离等。 [0122] For example, the present process micro-step may comprise: photolithography such as etching or peeling.

[0123] 可理解的是,铬为金的粘附层,用于增强电极(目标电极和非目标电极)与Si02基底的粘附性。 [0123] understood that the gold chromium adhesion layer for enhancing the adhesion of the electrodes (target and non-target electrode electrode) Si02 substrate.

[0124] 502、按照70〜90°C的持续温度,将所述芯片结构浸没在预配置的硝酸锌和乌洛托品复合水溶液中,其中,硝酸锌水溶液的配置浓度为0.01〜〇.〇4mol/L,乌洛托品水溶液的配置浓度为〇. 01〜〇. 04m〇l/L。 [0124] 502, in accordance with the continuous temperature of 70~90 ° C, the structure of the chip was immersed in a pre-configured and zinc nitrate aqueous solution of hexamine complex, wherein the concentration of zinc nitrate aqueous solution is arranged to 0.01~〇.〇 4mol / L, the concentration of hexamine solution is arranged square. 01~〇. 04m〇l / L.

[0125] 503、在将所述芯片结构浸没的同时,按照0.5〜4小时的持续时间,在所述目标电极上施加大小为-IV〜-0 • IV的直流电压VI,在所述全部或一部分非目标电极上施加大小为0V的直流电压V2,形成垂直生长的ZnO纳米阵列结构,其中V1<V2,如图3及图4所示;或者,在将所述芯片结构浸没的同时,按照0.5〜4小时的持续时间,在所述目标电极上施加大小为-IV〜-0.1V的直流电压V3和大小为O.lVpp〜0.5VPP、频率为1MHz的正弦交流电压V5,在所述全部或一部分非目标电极上施加大小为0V的直流电压V4,形成杂乱生长的ZnO纳米阵列结构,其中V3〈V4,如图5及图6所示。 [0125] 503, while the chip submerged structure according to the duration of 0.5~4 hours applying a DC voltage VI size -IV~-0 • IV on said target electrode, in all or applying a non-target portion of the electrode size of a DC voltage V2 0V, a ZnO nano-array structure perpendicular to the growth, where V1 <V2, as shown in FIG. 3 and FIG. 4; or the chip structure while submerged, in accordance with 0.5~4 hours duration, the magnitude of the applied DC voltage V3 and size -IV~-0.1V is O.lVpp~0.5VPP, a frequency of the sinusoidal AC voltage V5 1MHz, and all the electrodes on the target or applied to the electrode portion of the non-target DC voltage V4 0V size of a ZnO nano-array structure grown messy, wherein V3 <V4, as shown in FIG 5 and FIG 6.

[0126] 504、在所述芯片结构浸没结束后,将形成有ZnO纳米阵列结构的芯片结构依次进行清洗和烘干。 [0126] 504, after the immersion end chip structure, nano-structure formed with a chip array structure sequentially cleaning and drying ZnO.

[0127] 可理解的是,在进行清洗和烘干之后,可实现在目标电极上ZnO纳米阵列结构的生长(垂直生长或杂乱生长)。 [0127] understood that, after performing washing and drying, the growth of ZnO nano-arrays may be implemented on the target electrode structure (vertical growth growth or scrambled).

[0128] 505、在室温下,将烘千后的形成有ZnO纳米阵列结构的芯片结构浸没在预配置的pH值为6.5〜7.5的亚硫酸盐镀金溶液中,或者,在室温下将预配置的pH值为6.5〜7.5的亚硫酸盐镀金溶液滴加在烘干后的形成有ZnO纳米阵列结构的芯片结构的表面。 [0128] 505, at room temperature, after drying the formed one thousand chip structure of ZnO nano-array structure immersed in the pre-configured pH value of 6.5~7.5 sulfite gold plating solution, or the pre-configured at room temperature a pH of 6.5~7.5 sulfite formed in the gold plating solution was added dropwise after drying ZnO nanoarrays surface of the array structure.

[0129] 506、按照0_5〜5分钟的持续时间,在形成有ZnO纳米阵列结构的目标电极上施加大小为-1.5V〜-0.5V的直流电压V6,非目标电极施加大小为0V的直流电压V7。 [0129] 506, according to a duration 0_5~5 minutes, with a DC voltage is applied is formed in a size of V6 -1.5V~-0.5V on the target electrode array structure of nano ZnO, non-target electrodes applying a DC voltage of 0V size V7.

[0130] 507、在镀金结束后,将形成有金纳米阵列结构的芯片取出,依次进行清洗和烘干。 [0130] 507, after the gold plating, the gold formed on a chip array structure is taken out, sequentially cleaning and drying.

[0131]可理解的是,在进行清洗和烘干之后,可在目标电极上形成金纳米阵列结构。 [0131] understood that, after performing cleaning and drying, the gold may be formed on the target electrode array structure.

[0132] 在本实施例中,采用直流控制法生长ZnO纳米阵列并进行镀金后所形成金纳米阵列结构纵向尺寸(凹凸幅度)小且致密,采用直流交流混合控制法生长ZnO纳米阵列并进行镀金后所形成的金纳米阵列结构纵向尺寸(凹凸幅度)大且稀疏。 [0132] In the present embodiment, after the growth of ZnO nano-arrays using direct current control method and the gold plated array structure formed by the longitudinal dimension (uneven amplitude) is small and dense, DC AC hybrid control method of ZnO nano-arrays and plated gold longitudinal dimension array after the formed structure (unevenness amplitude) is large and sparse.

[0133] 本实施例的在芯片结构的目标电极上进行金纳米阵列结构制备方法,基于电场辅助的湿化学生长方法,在低温下(<1〇〇°C)实现ZnO纳米阵列在目标电极上的选择性生长,在宏/微结构中可以有效地集成纳米材料,满足低温、低成本、易批量的特点,简便易行,利用选择性生长的ZnO纳米阵列,在目标电极上制备出金纳米阵列结构,并极大增大了目标电极的表面积,工艺简便、效率高、可靠性好。 [0133] Preparation of gold electrode array structure present on the target chip structure in the embodiment is performed, the field-assisted wet chemical growth method based on, at a low temperature (<1〇〇 ° C) to achieve the target of ZnO electrode array selective growth can be effectively integrated in a macro / micro structure nanomaterials meet low-temperature, low cost, easy-volume characteristics, easy, using the selective growth of ZnO nano-arrays prepared on a gold target electrode array structure, and greatly increases the surface area of ​​the target electrode, the process is simple, high efficiency and good reliability.

[0134] 第六实施例 [0134] Sixth Example

[0135] 图16示出了本发明第六实施例提供的另一种在芯片结构的目标电极上进行金纳米阵列结构制备方法的流程示意图,如图16所示,本实施例的金纳米阵列结构制备方法如下所述。 [0135] FIG. 16 shows a schematic diagram of another process for preparing an array of gold electrode structure on the target chip configuration of a sixth embodiment of the present invention provides, as shown in Figure 16, the present embodiment is an array of gold the structure was prepared as follows.

[0136] 601、采用微加工工艺在掺杂的低阻单晶硅底电极上形成二氧化硅基底,并在二氧化硅基底上形成包括铬/金目标微电极和铬/金非目标微电极的芯片结构,7所示。 [0136] 601, using micromachining on a substrate formed of silica low resistance silicon single crystal doped bottom electrode, and forming a non-target micro electrode comprises chromium / gold microelectrodes and certain chromium / gold on silica substrate chip structure shown in FIG.

[0137] 举例来说,本步骤的微加工工艺可以包括:热氧化、光刻、刻蚀或剥离等。 [0137] For example, the present process micro-step may comprise: a thermal oxidation, photolithography, etching, peeling, or the like.

[0138] 可理解的是,铬为金的粘附层,用于增强目标电极和非目标电极与Si02基底的粘附性。 [0138] understood that the gold chromium adhesion layer for enhancing the adhesion of the target and non-target electrode and the electrode substrate Si02.

[0139] 602、按照70〜90°C的持续温度,将所述芯片结构浸没在预配置的硝酸锌和乌洛托品复合水溶液中,其中,硝酸锌水溶液的配置浓度为〇.〇1〜〇.〇4mol/L,乌洛托品水溶液的配置浓度为0.01〜0.04m〇l/L。 [0139] 602, in accordance with the continuous temperature of 70~90 ° C, the structure of the chip was immersed in a pre-configured and zinc nitrate aqueous solution of hexamine complex, wherein the concentration of zinc nitrate aqueous solution is arranged to 〇.〇1~ 〇.〇4mol / L, the concentration of hexamine solution is arranged 0.01~0.04m〇l / L.

[0140] 603、在将所述芯片结构浸没的同时,按照0.5〜4小时的持续时间,在所述目标电极上施加大小为0.3V的直流电压VI,在所述全部或一部分非目标电极上施加大小为0V的直流电压V2,在所述底电极上施加大小为-0.3V〜0V的直流电压V8,在目标电极上形成垂直生长的ZnO纳米阵列结构,其中VI <V8〈V2,如图8所示;或者,在将所述芯片结构浸没的同时,按照0.5〜4小时的持续时间,在所述目标电极上施加大小为-IV〜-0 • 3V的直流电压V3和0. lVpp〜0 • 5Vpp、频率为1MHz的正弦交流电压V5,在所述全部或一部分非目标电极上施加大小为0V的直流电压V4,在所述底电极上施加大小为-0.3V〜0V的直流电压V9,其中在目标电极上形成杂乱生长的ZnO纳米阵列结构,其中V3<V9<V4,如图9所示。 [0140] 603, while the chip submerged structure according to the duration of 0.5~4 hours applying a DC voltage 0.3V size VI on the target electrode, on all or a portion of the non-target electrode magnitude of the applied DC voltage V2 0V is applied ZnO nano-size array structure of a DC voltage V8 -0.3V~0V, vertical growth is formed on the target electrode on the bottom electrode, wherein VI <V8 <V2, FIG. 8; or, in the chip structure while submerged, according to the duration of 0.5~4 hours, the magnitude of the applied DC voltage V3 -IV~-0 • 3V and 0. lVpp~ on the target electrode 0 • 5Vpp, frequency sinusoidal AC voltage V5 1MHz, the magnitude of the applied DC voltage V4 0V on all or a portion of the non-target electrode, applying a DC voltage V9 of -0.3V~0V size on the bottom electrode wherein the target electrode is formed on the ZnO nano-array structure grown messy, wherein V3 <V9 <V4, shown in Figure 9.

[0141] 604、在所述芯片结构浸没结束后,将形成有ZnO纳米阵列结构的芯片结构依次进行清洗和烘干。 [0141] 604, after the immersion end chip structure, nano-structure formed with a chip array structure sequentially cleaning and drying ZnO.

[0142] 可理解的是,在进行清洗和烘干之后,可实现在目标电极上ZnO纳米阵列结构的生长(垂直生长或杂乱生长)。 [0142] understood that, after performing washing and drying, the growth of ZnO nano-arrays may be implemented on the target electrode structure (vertical growth growth or scrambled).

[0143] 605、在室温下,将烘干后的形成有ZnO纳米阵列结构的芯片结构浸没在预配置的pH值为6.5〜7.5的亚硫酸盐镀金溶液中,或者,在室温下将预配置的pH值为6 • 5〜7.5的亚硫酸盐镀金溶液滴加在烘干后的形成有ZnO纳米阵列结构的芯片结构的表面。 [0143] 605, at room temperature, after drying the formed structure has a chip array structure of nano ZnO immersed in a pH value of 6.5~7.5 preconfigured sulfite gold plating solution, or the pre-configured at room temperature a pH of 6 • 5~7.5 sulfite formed in the gold plating solution was added dropwise after drying ZnO nanoarrays surface of the array structure.

[0144] 606、按照0.5〜5分钟的持续时间,在形成有ZnO纳米阵列结构的目标电极上施加大小为-1.5V〜-0.5V的直流电压V6,非目标电极施加大小为0V的直流电压V7,在目标电极上形成金纳米阵列结构。 [0144] 606, in accordance with the duration of 0.5~5 minutes, with a DC voltage is applied is formed in a size of V6 -1.5V~-0.5V on the target electrode array structure of nano ZnO, non-target electrodes applying a DC voltage of 0V size V7, gold is formed on the target electrode array structure.

[0145] 607、在镀金结束后,将形成有金纳米阵列结构的芯片取出,依次进行清洗和烘干。 [0145] 607, after the gold plating, the gold formed on a chip array structure is taken out, sequentially cleaning and drying.

[0146] 可理解的是,在进行清洗和烘干之后,可在目标电极上形成金纳米阵列结构。 [0146] understood that, after performing cleaning and drying, the gold may be formed on the target electrode array structure.

[0147] 在本实施例中,采用直流控制法生长ZnO纳米阵列并进行镀金后所形成金纳米阵列结构纵向尺寸(凹凸幅度)小且致密,采用直流交流混合控制法生长ZnO纳米阵列并进行镀金后所形成的金纳米阵列结构纵向尺寸(凹凸幅度)大且稀疏。 [0147] In the present embodiment, after the growth of ZnO nano-arrays using direct current control method and the gold plated array structure formed by the longitudinal dimension (uneven amplitude) is small and dense, DC AC hybrid control method of ZnO nano-arrays and plated gold longitudinal dimension array after the formed structure (unevenness amplitude) is large and sparse.

[0148] 本实施例的在芯片结构的目标电极上进行金纳米阵列结构制备方法,基于电场辅助的湿化学生长方法,在低温下(<l〇〇°C)实现ZnO纳米阵列在目标电极上的选择性生长,在歹量的“,简^^ 选择性生长的ZnO纳米在目标电极上制备出金纳米阵列结构,并极大增大了目标电极的表面积,工艺简便、效率咼、可靠性好。 [0148] Example embodiments of the present preparation process the target structures on a gold electrode array chip structure, the field-assisted wet chemical growth method based on at low temperatures (<l〇〇 ° C) to achieve the target of ZnO electrode array selective growth, ", ZnO nano Jane ^^ prepared selectively grown on the target amount of bad the gold electrode array structure, and greatly increases the surface area of ​​the target electrode, the process is simple, 咼 efficiency, reliability it is good.

[0149]最后应说明的是:以上各实施例仅用以说明本发明的技术方案,而非对其限制;尽管参照前述各实施例对本发明进行了详细的说明,本领域的普通技术人员应当理解:其依然可以对前述各实施例所记载的技术方案进行修改,或者对其中部分或者全部技术特征进行等同替换;而这些修改或者替换,并不使相应技术方案的本质脱离本发明权利要求所限定的范围。 [0149] Finally, it should be noted that: the above embodiments only describe the technical solutions in embodiments of the present invention, rather than limiting;. Although the embodiments of the present invention has been described in detail, those of ordinary skill in the art should appreciated: that they may still technical solutions described in the foregoing modified embodiment, or to some or all of the technical features equivalents; as such modifications or replacements do not cause the essence of corresponding technical solutions to depart from the claims of the invention defined range.

Claims (10)

  1. 1. 一种在芯片结构的目标电极表面上实现纯金纳米阵列结构制备方法,其特征在于, 包括: 在基底的上表面形成包括多个电极的芯片结构,所述多个电极包括:目标电极和非目标电极; 按照预设第一时间和预设第一温度,利用预配置的化学溶液和第一电场控制方法,在所述目标电极上形成ZnO纳米阵列结构; 按照预设第二时间和预设第二温度,利用预配置的化学镀金溶液和第二电场控制方法,在所形成的ZnO纳米阵列结构上进行镀金,在镀金过程中,ZnO纳米阵列结构的溶解与镀金成形两种作用同时发生,最终形成纯金纳米阵列结构。 A method of fabricating an array of Pure gold structures on the target surface of the chip electrode structure, comprising: forming a chip structure including a plurality of electrodes on the surface of the substrate, the plurality of electrodes comprises: a target electrode and non-target electrode; a first preset time and a preset first temperature, with a chemical solution and a first electric field control method for pre-configured, a ZnO nano-array electrode structure on said target; a second preset time and preset second temperature, using the electroless gold plating solution and a second pre-configured field control method, gold plating on the ZnO nano-array structure formed in the gold plating process, and the metal plating is dissolved array structure formed ZnO nano two functions simultaneously , eventually forming an array structure of pure gold.
  2. 2. 根据权利要求1所述的方法,其特征在于,所述预设第一时间为0.5〜48小时,所述预设第二时间为0.5〜5分钟,所述预设第一温度为100°C以下,所述预设第二温度为常温,所述预配置的化学溶液为硝酸锌和乌洛托品复合水溶液,所述预配置的化学镀金溶液为:亚硫酸盐镀金溶液。 2. The method according to claim 1, wherein said first predetermined time is 0.5~48 hours, the second predetermined time is 0.5~5 minutes, the predetermined first temperature is 100 ° C below the preset second temperature is room temperature, the chemical solution is a preconfigured zinc nitrate and an aqueous solution of hexamine complex, the pre-configured as gold plating solution: sulfite gold plating solution.
  3. 3. 根据权利要求1所述的方法,其特征在于,所述按照预设第一时间和预设第一温度, 利用预配置的化学溶液和第一电场控制方法在所述目标电极上形成ZnO纳米阵列结构,包括: 按照预设第一温度,将所述芯片结构浸没在预配置的化学溶液中; 在将所述芯片结构浸没的同时,按照预设第一时间,利用第一电场控制方法在所述目标电极上形成ZnO纳米阵列结构; 在所述芯片结构浸没结束后,将形成有ZnO纳米阵列结构的芯片结构依次进行清洗和烘干。 3. The method according to claim 1, characterized in that said first preset time and a preset first temperature, with a chemical solution and a first electric field control method for a ZnO preconfigured on the target electrode nano-structure array, comprising: according to a preset first temperature, the structure of the chip was immersed in a chemical solution preconfigured; the chip structure while submerged, the first preset time, the electric field control by using a first method ZnO nano-array structure is formed on the target electrode; after said immersion end chip structure, formed of ZnO nano-structure array chip structure sequentially cleaning and drying.
  4. 4. 根据权利要求3所述的方法,其特征在于,所述第一电场控制方法为直流控制法,所述在将所述芯片结构浸没的同时,按照预设第一时间,利用第一电场控制方法在所述目标电极上形成ZnO纳米阵列结构,包括: 在将所述芯片结构浸没的同时,按照预设第一时间,在所述目标电极上施加直流电压VI,在所述全部或一部分非目标电极上施加直流电压V2,在目标电极上形成垂直生长的ZnO 纳米阵列结构,其中V1<V2; 或, 所述第一电场控制方法为直流交流混合控制法,所述在将所述芯片结构浸没的同时, 按照预设第一时间,利用第一电场控制方法在所述目标电极上形成ZnO纳米阵列结构,包括: 在将所述芯片结构浸没的同时,按照预设第一时间,在所述目标电极上施加直流电压V3和交流电压V5,在所述全部或一部分非目标电极上施加直流电压V4,在目标电极上形成 4. The method according to claim 3, wherein said first electric field control method for controlling a DC method, the chip while the submerged structure, the first preset time, with the first field control method for a ZnO nano-array electrode structure on the target, comprising: the chip structure while submerged, the first preset time, DC voltage VI is applied on the target electrode, all or part of the ZnO nano-array structure on the DC voltage V2 is applied to the non-target electrodes, are formed on the vertical growth of the target electrode, where V1 <V2; or, the first electric field control method for the AC and DC hybrid control method of the chip in the while submerged structure, the first preset time, using a first electric field control method for a ZnO nano-array electrode structure on the target, comprising: the chip structure while submerged, the first preset time, the applying a DC voltage an AC voltage V3 and V5 on the target electrode, applying a DC voltage V4 on all or a portion of the non-target electrode is formed on the target electrode 杂乱生长的ZnO纳米阵列结构,其中V3<V4。 Growth of ZnO nano messy array structure, wherein V3 <V4.
  5. 5. 根据权利要求3所述的方法,其特征在于,所述第一电场控制方法为直流控制法,所述在将所述芯片结构浸没的同时,按照预设第一时间,利用第一电场控制方法在所述目标电极上形成ZnO纳米阵列结构,还包括: 所述芯片结构的基底下表面还包括底电极; 在将所述芯片结构浸没的同时,按照预设第一时间,在所述目标电极上施加直流电压VI,在所述全部或一部分非目标电极上施加直流电压V2,在所述底电极上施加直流电压V8, 在目标电极上形成垂直生长的ZnO纳米阵列结构,其中V1<V8<V2; 或, 所述第一电场控制方法为直流交流混合控制法,所述在将所述芯片结构浸没的同时, 按照预设第一时间,利用第一电场控制方法在所述目标电极上形成ZnO纳米阵列结构,还包括: 所述芯片结构的基底下表面还包括底电极; 在将所述芯片结构浸没的同时,按照预设 5. The method according to claim 3, wherein said first electric field control method for controlling a DC method, the chip while the submerged structure, the first preset time, with the first field control method for a ZnO nano-array electrode structure on the target, further comprising: a lower surface of the chip substrate further includes a bottom electrode structure; the chip structure while submerged, the first preset time, the a DC voltage is applied to the target electrodes Vl, DC voltage V2 is applied over all or a portion of the non-target electrode, applying a DC voltage on the bottom electrode V8, a ZnO nano-array structure vertically grown on the target electrode, where V1 < V8 <V2; or, the first electric field control method for the AC and DC hybrid control method of the chip while in the submerged structure, the first preset time, using a first method of controlling an electric field at the target electrode ZnO nano-array structure is formed, further comprising: a lower substrate of the chip surface structure further includes a bottom electrode; the chip structure while submerged, according to a preset 第一时间,在所述目标电极上施加直流电压V3和交流电压V5,在所述全部或一部分非目标电极上施加直流电压V4,在所述底电极上施加直流电压V9,在目标电极上形成杂乱生长的ZnO纳米阵列结构,其中V3<V9<V4。 A first time, the electrode is applied on the target DC voltage and AC voltage V5 V3, V4 DC voltage is applied on all or a portion of the non-target electrode, applying a DC voltage V9 on the bottom electrode, are formed on the target electrode growth of ZnO nano messy array structure, wherein V3 <V9 <V4.
  6. 6. 根据权利要求5所述的方法,其特征在于,所述底电极的材料为:掺杂的单晶硅或金属。 6. The method as claimed in claim 5, wherein said bottom electrode is a material: doped monocrystalline silicon or metal.
  7. 7. 根据权利要求1所述的方法,其特征在于,所述按照预设第二时间和预设第二温度, 利用预配置的化学镀金溶液和第二电场控制方法,在所形成的ZnO纳米阵列结构上进行镀金,包括: 按照预设第二温度,将烘干后的形成有ZnO纳米阵列结构的芯片结构浸没在预配置的化学镀金溶液中,或者,在预设第二温度下将预配置的化学镀金溶液滴加在烘干后的形成有ZnO纳米阵列结构的芯片结构的表面; 按照预设第二时间,利用第二电场控制方法在所述预配置的化学镀金溶液中在所形成的ZnO纳米阵列结构上进行镀金,形成金纳米阵列结构; 在镀金结束后,将形成有金纳米阵列结构的芯片结构取出,依次进行清洗和烘干。 7. The method according to claim 1, wherein said second preset time and the second predetermined temperature, using the electroless gold plating solution and a second pre-configured field control method, ZnO in the formed nano gold plating on the array structure, comprising: according to a preset second temperature, after drying the formed ZnO nano structure of the chip array structure immersed in the electroless gold plating solution of the pre-configured, or, at a predetermined temperature to a second pre- configuration gold plating solution was added dropwise formed after drying of the surface nano-structure array chip structure of ZnO; a second preset time, a second electric field control method utilizes electroless gold plating solution in the pre-formed configuration in ZnO nano-arrays for the plated structure, array structure formed of gold; after gold plating, the gold array structure formed with a chip architecture removed sequentially cleaning and drying.
  8. 8. 根据权利要求7所述的方法,其特征在于,所述按照预设第二时间,利用第二电场控制方法在所述预配置的化学镀金溶液中在所形成的ZnO纳米阵列结构上进行镀金,包括: 按照预设第二时间,在形成有Zn〇纳米阵列结构目标电极上施加直流电压ve,在全部或一部分非目标电极上施加直流电压V7,其中V6<V7。 8. The method according to claim 7, wherein said second preset time, performed on the ZnO nano-array structure formed in the gold plating solution preconfigured by a second method of controlling an electric field gold, comprising: a second preset time, formed on a DC voltage is applied Zn〇 ve nano target electrode array structure, applying a DC voltage V7 on all or a portion of non-target electrodes, wherein V6 <V7.
  9. 9.根据权利要求1所述的方法,其特征在于,所述目标电极的材料为:铬/金层、或钛/金层、或鹤/金层。 9. The method according to claim 1, characterized in that the material of the target electrode is: Cr / Au layer, or a titanium / gold layer, or a crane / gold layer.
  10. 10.根据权利要求1所述的方法,其特征在于,所述基底的材料为:二氧化硅、或氮化硅、 或聚合物。 10. The method according to claim 1, characterized in that the material of the substrate is: silicon dioxide, or silicon nitride, or a polymer.
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CN102730630A (en) * 2012-07-03 2012-10-17 清华大学 Method for manufacturing ZnO nano structure and nano ultraviolet sensor
CN103779400A (en) * 2013-06-09 2014-05-07 国家纳米科学中心 Composite electrode and preparation method thereof

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CN101308108A (en) * 2007-05-15 2008-11-19 清华大学 Preparation method of sensor embodying one-dimensional nano material sensitive element
CN102730630A (en) * 2012-07-03 2012-10-17 清华大学 Method for manufacturing ZnO nano structure and nano ultraviolet sensor
CN103779400A (en) * 2013-06-09 2014-05-07 国家纳米科学中心 Composite electrode and preparation method thereof

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