CN104515918B - The implementation method of multistage triggering based on multi-stage pipeline structure - Google Patents

The implementation method of multistage triggering based on multi-stage pipeline structure Download PDF

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Publication number
CN104515918B
CN104515918B CN201410705346.1A CN201410705346A CN104515918B CN 104515918 B CN104515918 B CN 104515918B CN 201410705346 A CN201410705346 A CN 201410705346A CN 104515918 B CN104515918 B CN 104515918B
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China
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circuit
triggering
trigger
detection
stage
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CN201410705346.1A
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Chinese (zh)
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CN104515918A (en
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常路
殷晔
郑义
安佰岳
王石记
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北京航天测控技术有限公司
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Abstract

The present invention provides a kind of implementation method of the multistage triggering based on multi-stage pipeline structure, and each trigger element circuit is realized by three stage pipeline structures, is loading trigger condition circuit, detection trigger ready circuit, detection trigger circuit respectively.Streamline is spread out by three trigger element circuits, realizes in complicated multistage triggering and judges dead band without triggering.The present invention is breached judges dead-zone technique without triggering, perfect complex conditions trigger in triggering turn function.The device can be realized by FPGA simultaneously, it is not necessary to increase peripheral circuit, it is not necessary to develop asic chip, can be reduced cost and be shortened the construction cycle.

Description

The implementation method of multistage triggering based on multi-stage pipeline structure

Technical field

The invention belongs to T & M field, it is related to a kind of realization of the multistage triggering based on multi-stage pipeline structure Method.

Background technology

Trigger Function is the essential function of T & M instrument including logic analyser, and instrument, which passes through, to be touched Hair can fix a breakdown.In present engineering survey, the triggering of single type can not meet the requirement of various senior measurements.Example Such as, protocal analysis needs multistage different types of triggering to meet successively, could capture the signal needed.Relative to single-stage triggering, Complicated multistage triggering includes triggering and redirected, the function such as branch's triggering.When different types of triggering is redirected, if it is big to redirect the time In a trigger clock cycle, effectively triggering may be missed, and triggering occurred and judged dead band, cause entirely to trigger deterministic process mistake Lose.It is very necessary so ensureing that whole process judges dead band without triggering.

At present, realize that the device of complicated multistage triggering is realized usually using ASIC.But these ASIC are set by test measurement Standby manufacturer, which develops and is only used for it, tests measuring apparatus, and do not meet the needs of the market sale.Meanwhile, the cost realized using ASIC Height, the cycle is long.

The content of the invention

The present invention provides a kind of implementation method of the multistage triggering based on multi-stage pipeline structure, can not only detect Polytype triggering, and be not in that triggering judges dead band when triggering not at the same level is redirected.

The present invention is achieved through the following technical solutions:

A kind of implementation method of the multistage triggering based on multi-stage pipeline structure, designs a trigger element electricity first Road, realizes certain one-level triggering in multistage triggering, wherein described trigger element circuit is realized by three stage pipeline structures; Then, each trigger element circuit is copied as into tri- parts of A, B, C, three stage pipeline structures expansion composition is judged without triggering Dead-zone circuit;Judge that dead-zone circuit is made up of three trigger element circuits without triggering, in moment T, the A circuit realirations first order is touched Power Generation Road, the detection-phase in pipeline organization, B circuit realirations second level triggers circuit, in pipeline organization Ready phase, C circuit realiration third level triggers circuits, the load phase in pipeline organization;Now, no triggering judges dead The state of area's circuit is detection first order triggering, after the first order, which is triggered, to be responded, and it is next that no triggering judges that dead-zone circuit enters Clock cycle, the moment is T+1, and B circuit realirations second level triggers circuit, the detection-phase in pipeline organization, C circuits are real Existing third level triggers circuit, the ready phase in pipeline organization, A circuit realiration fourth stage triggers circuits, in flowing water Load phase in cable architecture, now, no triggering judge that the state of dead-zone circuit is the triggering of the detection second level;First order triggering inspection Survey and the time interval of second level detection trigger is an operating clock cycle, do not trigger and judge dead band;Without dead-zone circuit according to Secondary detection third level triggering, fourth stage triggering;Until multistage triggering terminates;So far realize and judge that the complexity in dead band is multistage without triggering Triggering.

The three wherein described stages are specifically realized using following methods:First stage is loading trigger condition circuit, is used for Trigger condition is obtained from instruction cache unit, instruction cache unit is realized by RAM on FPGA pieces, trigger condition not at the same level It is stored in the different address of instruction cache unit, loading trigger condition circuit is referred to by sending request to instruction cache unit Order, obtains corresponding trigger condition;Second stage is detection trigger ready circuit, for trigger condition to be configured to triggering electricity Road, makes triggers circuit enter detection trigger ready state;Phase III is detection trigger circuit, for being carried out to trigger source signal Detection, and produce triggering response signal.

Each at least one clock cycle of stage circuit operating time, trigger element circuit in wherein described three phases At least three clock cycle.

Beneficial effects of the present invention:

The present invention is breached judges dead-zone technique without triggering, perfect complex conditions trigger in triggering turn function.Together When the device need to only be realized by FPGA, it is not necessary to develop asic chip, can reduce cost and shorten the construction cycle.

Brief description of the drawings

Fig. 1 is trigger element circuit diagram of the present invention;

Fig. 2 judges that circuit is realized in dead band for the present invention without triggering.

Embodiment

The invention will be described further below in conjunction with the accompanying drawings.

The present invention realizes a kind of complexity multistage that dead band is judged without triggering of multi-stage pipeline structure based on FPGA The device of triggering, specific implementation process is as follows:

First, a trigger element circuit is designed, the circuit can realize certain one-level triggering in multistage triggering.Trigger element Circuit is realized by three stage pipeline structures.As shown in figure 1,1 is trigger element circuit, certain in multistage triggering can be achieved One-level is triggered;2 be trigger condition loaded circuit;3 be instruction cache unit, for caching trigger condition;4 be that detection trigger is ready Circuit;5 detection trigger circuits.Wherein 2,4,5 be the three phases of trigger element circuit pipeline structure.

First stage is loading trigger condition circuit (abbreviation loaded circuit), and this circuit realiration is from instruction cache unit Obtain the process of trigger condition.Instruction cache unit realizes that trigger condition not at the same level is stored in instruction by RAM on FPGA pieces In the different address of buffer unit.Loaded circuit obtains corresponding triggering bar by sending request instruction to instruction cache unit Part.The work of loaded circuit is a clock cycle.Second stage is detection trigger ready circuit (abbreviation ready circuit), this electricity Road, which is realized, configures trigger condition to triggers circuit, triggers circuit is entered detection trigger ready state.Phase III is tactile Hair detection circuit (referred to as detection circuit), this circuit realiration produces triggering response letter to the detection process of trigger source signal Number.Each stage circuit operating time is at least one clock cycle, so trigger element circuit at least needs 3 clock weeks Phase.

Then, each trigger element circuit is copied as into tri- parts of A, B, C, spreads out three stage pipeline structures, constituted Judge dead-zone circuit without triggering (referred to as without dead-zone circuit).As shown in Fig. 21 is the shape that dead-zone circuit is judged without triggering at T moment State;2 be the state that dead-zone circuit is judged without triggering at T+1 moment;3 be trigger element circuit, it is no triggering judge dead-zone circuit by Three trigger element circuit compositions.In moment T, A circuit realiration first order triggers circuits, the detection in pipeline organization Stage, B circuit realirations second level triggers circuit, the ready phase in pipeline organization, C circuit realirations third level triggering electricity Road, the load phase in pipeline organization.Now, the state of no dead-zone circuit is detection first order triggering.Work as the first order After triggering response, circuit enters next clock cycle, and the moment is T+1, B circuit realirations second level triggers circuit, in flowing water Detection-phase in cable architecture, C circuit realiration third level triggers circuits, the ready phase in pipeline organization, A circuits are real Existing fourth stage triggers circuit, the load phase in pipeline organization.Now, the state of no dead-zone circuit is the detection second level Triggering.The time interval of first order detection trigger and second level detection trigger is an operating clock cycle, does not trigger judgement Dead band.Detect that the third level triggers successively without dead-zone circuit, fourth stage triggering etc..Until multistage triggering terminates.Therefore, no dead band Circuit can be realized judges the multistage triggering of the complexity in dead band without triggering.

Claims (2)

1. a kind of implementation method of the multistage triggering based on multi-stage pipeline structure, it is characterised in that:One is designed first to touch Element circuit is sent out, certain one-level triggering in multistage triggering is realized, wherein described trigger element circuit passes through three stage pipelines Structure is realized;Then, each trigger element circuit is copied as into tri- parts of A, B, C, makes three stage pipeline structures expansion composition Judge dead-zone circuit without triggering;Judge that dead-zone circuit is made up of three trigger element circuits without triggering, in moment T, A circuits are real Existing first order triggers circuit, the detection-phase in pipeline organization, B circuit realirations second level triggers circuit, in flowing water Ready phase in cable architecture, C circuit realiration third level triggers circuits, the load phase in pipeline organization;Now, nothing Triggering judges that the state of dead-zone circuit is detection first order triggering, and after the first order, which is triggered, to be responded, no triggering judges dead-zone circuit Into next clock cycle, the moment is T+1, B circuit realirations second level triggers circuit, the detection rank in pipeline organization Section, C circuit realiration third level triggers circuits, the ready phase in pipeline organization, A circuit realirations fourth stage triggering electricity Road, the load phase in pipeline organization, now, no triggering judge that the state of dead-zone circuit is the triggering of the detection second level; The time interval of first order detection trigger and second level detection trigger is an operating clock cycle, does not trigger and judges dead band; Detect that the third level triggers successively without dead-zone circuit, fourth stage triggering;Until multistage triggering terminates;So far realize and judge dead without triggering The multistage triggering of complexity in area;
The three described stages are specifically realized using following methods:First stage is loading trigger condition circuit, for slow from instruction Trigger condition is obtained in memory cell, instruction cache unit realizes that trigger condition not at the same level is stored in finger by RAM on FPGA pieces Make in the different address of buffer unit, loading trigger condition circuit obtains phase by sending request instruction to instruction cache unit The trigger condition answered;Second stage is detection trigger ready circuit, for trigger condition to be configured to triggers circuit, makes triggering electricity Road enters detection trigger ready state;Phase III is detection trigger circuit, for being detected to trigger source signal, and is produced Trigger response signal.
2. a kind of implementation method of multistage triggering based on multi-stage pipeline structure as claimed in claim 1, its feature exists In:Each at least one clock cycle of stage circuit operating time in wherein described three phases, trigger element circuit is at least For three clock cycle.
CN201410705346.1A 2014-11-27 2014-11-27 The implementation method of multistage triggering based on multi-stage pipeline structure CN104515918B (en)

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CN103631316A (en) * 2012-08-21 2014-03-12 安捷伦科技有限公司 Multilevel triggering system used for outputting complicated trigger signals
CN103869120A (en) * 2012-12-13 2014-06-18 北京普源精电科技有限公司 Oscilloscope with fine equivalent triggering function and method for fine equivalent triggering
CN103969483A (en) * 2014-04-24 2014-08-06 中国电子科技集团公司第四十一研究所 Digital triggering system of oscilloscope

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US20030110430A1 (en) * 2001-12-10 2003-06-12 International Business Machines Corporation Method and system for use of a field programmable gate array (FPGA) function within an application specific integrated circuit (ASIC) to enable creation of a debugger client within the ASIC
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CN101526559A (en) * 2008-03-04 2009-09-09 特克特朗尼克公司 Pre-trigger and post-trigger acquisition for a no dead time acquisition system
CN103631316A (en) * 2012-08-21 2014-03-12 安捷伦科技有限公司 Multilevel triggering system used for outputting complicated trigger signals
CN103869120A (en) * 2012-12-13 2014-06-18 北京普源精电科技有限公司 Oscilloscope with fine equivalent triggering function and method for fine equivalent triggering
CN103969483A (en) * 2014-04-24 2014-08-06 中国电子科技集团公司第四十一研究所 Digital triggering system of oscilloscope

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