CN104506456A - Method for limiting packet loss at entry of exchanger - Google Patents
Method for limiting packet loss at entry of exchanger Download PDFInfo
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- CN104506456A CN104506456A CN201410848425.8A CN201410848425A CN104506456A CN 104506456 A CN104506456 A CN 104506456A CN 201410848425 A CN201410848425 A CN 201410848425A CN 104506456 A CN104506456 A CN 104506456A
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- switch
- packet loss
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- exchanger
- entry
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Abstract
The invention provides a method for limiting packet loss at an entry of an exchanger. The method comprises the steps of: 1, setting the minimum value of a buffer memory space at the entry of the exchanger; 2, setting the minimum value of buffer memory control at an exit of the exchanger; and 3, setting a domain value of a configuration register at the exit of the exchanger as 0. By the method, a problem that when the speed of multiple broadcast entering messages in the exchanger is higher than the speed of the multiple broadcast getting out of the exchanger, the following messages are lost at the entry, and packet loss at the entry can be avoided by setting the minimum values of the buffer memory spaces at the entry and the exit and the domain value of the configuration register at the exit.
Description
Technical field
The present invention relates to the method field solving switch packet loss, especially relate to a kind of method solving switch entrance packet loss.
Background technology
Along with Ethernet switch is applied and the raising of network transmission speed more and more widely, the speed that message enters switch is more and more faster, measures also increasing; Time when the speed that message enters switch is very fast, speed that is outlet is very slow, exchange opportunity abandons the follow-up message entered at entrance, the higher message of priority even occurs can not normal storage forward and situation about being dropped in porch, this will affect user and normally use switch.
Summary of the invention
The technical problem that the present invention need solve is to provide the method for the high restriction switch entrance packet loss of a kind of efficiency.
In order to solve the above problems, the present invention devises a kind of method limiting switch entrance packet loss, and it comprises the following steps: step 1: the minimum arranging the spatial cache of switch entrance; Step 2: the minimum that the buffer control of switch outlet is set; Step 3: the value arranging the territory of the configuration register of switch outlet is 0.
Improve further as the present invention, the minimum of the spatial cache of described switch entrance is set to 5 ~ 6K.
Improve further as the present invention, the minimum of the buffer control of described switch outlet is set to 4 ~ 5K.
Improve further as the present invention, the minimum of the minimum of the spatial cache of described switch entrance and the spatial cache of described switch entrance is equal.
Improve further as the present invention, this method also comprises: step 4: dispatched the forwarding and drop policy that realize message by QoS.
The present invention can solve when the speed of multicast message that enter switch is too fast and from speed export away too slowly thus cause abandoning the follow-up problem entering message at entrance, by the minimum of spatial cache of both inlet porting and outlet and the value in territory of the configuration register of outlet, to ensure in porch not packet loss.
Embodiment
Technical scheme of the present invention is understood better in order to make relevant technical staff in the field, below in conjunction with execution mode, technical scheme in embodiment of the present invention is clearly and completely described, obviously, described execution mode is only the present invention's part execution mode, instead of whole execution modes.
The present invention is directed to the problem of existing switch at entrance packet loss, a kind of method limiting switch entrance packet loss is provided.During when occurring the speed of the multicast message entering switch too fast from the situation that the speed exported away is too slow, the present invention ensures that message can not be dropped in porch, but forwarding and the drop policy of message is realized by QoS (Quality of Service, service quality) scheduling.
The present invention limits the method for switch entrance packet loss, arrange the minimum of the minimum of the spatial cache of switch entrance and the buffer control of switch outlet, and the value in the territory of the configuration register of switch outlet.In the present embodiment, the minimum of the spatial cache of switch entrance is set to 5 ~ 6K, the minimum of the buffer control of switch outlet is set to 4 ~ 5K, and the value in the territory of the configuration register of switch outlet is set to 0.More optimizedly, the minimum of the spatial cache of the minimum of the spatial cache of switch entrance and described switch entrance is arranged close to equal.
In the buffer memory of the exchange chip of switch, have divide a part of space be used for buffer inlet and outlet process business datum, the spatial cache that inlet porting of the present invention is corresponding with both outlets, the spatial cache controlling entrance and exit reaches balance, the value of adding the territory of the configuration register exported by switch is set to 0, namely can be controlled in the porch not packet loss of switch.
The present invention ensure when occurring the speed of the multicast message entering switch too fast from the situation that the speed exported away is too slow time, can not dropping packets in porch, and the forwarding of message and drop policy are dispatched by QoS, low or the unessential message of such as priority realizes abandoning by the scheduling of QoS, and the normal forwarding of message realization that priority is higher, can not go out be dropped at entrance.
The present invention can solve when the speed of message that enter switch is too fast and from speed export away too slowly thus cause abandoning the follow-up problem entering message at entrance, by the minimum of spatial cache of both inlet porting and outlet and the value in territory of the configuration register of outlet, to ensure in porch not packet loss.
Below only have expressed one embodiment of the present invention, it describes comparatively concrete and detailed, but therefore can not be interpreted as the restriction to the scope of the claims of the present invention.It should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection range of patent of the present invention should be as the criterion with claims.
Claims (5)
1. limit a method for switch entrance packet loss, it is characterized in that, the method comprises the following steps:
Step 1: the minimum that the spatial cache of switch entrance is set;
Step 2: the minimum that the buffer control of switch outlet is set;
Step 3: the value arranging the territory of the configuration register of switch outlet is 0.
2. the method for restriction switch entrance packet loss according to claim 1, it is characterized in that, the minimum of the spatial cache of described switch entrance is set to 5 ~ 6K.
3. the method for restriction switch entrance packet loss according to claim 1 and 2, is characterized in that, the minimum of the buffer control of described switch outlet is set to 4 ~ 5K.
4. the method for restriction switch entrance packet loss according to claim 1, is characterized in that, the minimum of the minimum of the spatial cache of described switch entrance and the spatial cache of described switch entrance is equal.
5. the method for restriction switch entrance packet loss according to claim 1, it is characterized in that, the method also comprises:
Step 4: dispatched the forwarding and drop policy that realize message by QoS.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410848425.8A CN104506456A (en) | 2014-12-26 | 2014-12-26 | Method for limiting packet loss at entry of exchanger |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410848425.8A CN104506456A (en) | 2014-12-26 | 2014-12-26 | Method for limiting packet loss at entry of exchanger |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104506456A true CN104506456A (en) | 2015-04-08 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410848425.8A Pending CN104506456A (en) | 2014-12-26 | 2014-12-26 | Method for limiting packet loss at entry of exchanger |
Country Status (1)
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| CN (1) | CN104506456A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106656870A (en) * | 2015-10-28 | 2017-05-10 | 中国科学院声学研究所 | Two-layer switch storage method based on storage port |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020089926A1 (en) * | 2001-01-06 | 2002-07-11 | Kloth Axel K. | Method and apparatus for lossless switchover in a redundant switch fabric |
| CN1287560C (en) * | 1998-06-16 | 2006-11-29 | 阿尔卡塔尔公司 | Digital traffic switch with credit-based buffer control |
| US7817470B2 (en) * | 2006-11-27 | 2010-10-19 | Mosaid Technologies Incorporated | Non-volatile memory serial core architecture |
| CN102025631A (en) * | 2010-12-15 | 2011-04-20 | 中兴通讯股份有限公司 | Method and exchanger for dynamically adjusting outlet port cache |
| CN203608225U (en) * | 2013-11-21 | 2014-05-21 | 浙江宇视科技有限公司 | Cache-optimized switch suitable for monitoring |
-
2014
- 2014-12-26 CN CN201410848425.8A patent/CN104506456A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1287560C (en) * | 1998-06-16 | 2006-11-29 | 阿尔卡塔尔公司 | Digital traffic switch with credit-based buffer control |
| US20020089926A1 (en) * | 2001-01-06 | 2002-07-11 | Kloth Axel K. | Method and apparatus for lossless switchover in a redundant switch fabric |
| US7817470B2 (en) * | 2006-11-27 | 2010-10-19 | Mosaid Technologies Incorporated | Non-volatile memory serial core architecture |
| CN102025631A (en) * | 2010-12-15 | 2011-04-20 | 中兴通讯股份有限公司 | Method and exchanger for dynamically adjusting outlet port cache |
| CN203608225U (en) * | 2013-11-21 | 2014-05-21 | 浙江宇视科技有限公司 | Cache-optimized switch suitable for monitoring |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106656870A (en) * | 2015-10-28 | 2017-05-10 | 中国科学院声学研究所 | Two-layer switch storage method based on storage port |
| CN106656870B (en) * | 2015-10-28 | 2020-04-17 | 中国科学院声学研究所 | Storage port-based two-layer switch storage method |
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| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20150408 |
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| RJ01 | Rejection of invention patent application after publication |